A multi-objective optimization soft error hardening method based on Bayesian optimization theory

Abstract

The present invention belongs to the technical field of semiconductors and integrated circuits, and specifically relates to a multi-objective optimization soft error hardening method based on Bayesian optimization theory. The hardening method includes three processes: the information acquisition process acquires basic information such as the area, power consumption, and soft error rate of flip-flops in the circuit; the data dimensionality reduction process clusters, sorts, and performs real-number encoding on the flip-flops in the circuit according to the acquired information. The optimization and hardening process is based on Bayesian optimization theory. By using a surrogate model to simulate the performance of circuit replacement hardening, the acquisition function is used to select the next sampling evaluation point, and multi-objective optimization is solved. After iteration, the best compromise of area, power consumption, and soft error rate is obtained, and the final replacement hardening scheme is given; the method of the present invention has scalability, high efficiency, and universality, and can be used to guide soft error tolerance replacement hardening of various high-reliability structures such as triple modular redundancy (TMR), and can adapt to circuit hardening designs with multiple scenarios and requirements.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors and integrated circuits, and in particular relates to a multi-objective optimization soft error reinforcement method in integrated circuits based on Bayesian optimization theory. Background Art

[0002] With the rapid development of technologies such as artificial intelligence and the Internet of Things, the scientific and technological level in the aerospace field has made great breakthroughs. The 6G integrated space-air and ground communication system with low-orbit satellites as a key component has received widespread attention. However, the harsh radiation environment in space can easily cause electronic systems to malfunction or even fail. At the same time, as the feature size of semiconductors continues to shrink and the operating voltage continues to decrease, the impact of radiation particle bombardment on integrated circuits is increasing, and the probability of soft errors is also increasing.

[0003] When devices in a circuit are bombarded by high-energy particles, additional charges will be generated and move under the action of the electric field, which will generate abnormal operating currents, which may cause problems such as logic state errors and functional disorders in the circuit. This non-permanent error is called a soft error. For electronic systems in radiation environments or with high reliability requirements (such as spacecraft, autonomous driving tools, etc.), it is particularly important to carry out hardening designs that tolerate soft errors.

[0004] The main idea of ​​current circuit-level reinforcement is redundant replacement, that is, replacing standard units with high-reliability devices with the same functions to improve the circuit's soft error tolerance. For example, the triple module redundancy (TMR) structure copies the circuit to be reinforced into three copies and uses the filtering function of the majority voter to improve the reliability of the circuit. It is often used for circuit device replacement reinforcement. However, while the redundant replacement method improves the circuit's soft error tolerance, it often also brings about huge area and power consumption losses. Therefore, it is very important to design a flexible and efficient replacement reinforcement method that balances indicators such as area, power consumption, and soft error rate, optimizes them, and provides the optimal replacement reinforcement solution. Summary of the invention

[0005] The purpose of the present invention is to provide a flexible and efficient circuit replacement reinforcement method, which balances indicators such as area, power consumption, and soft error rate to adapt to various design conditions and provide designers with the best replacement reinforcement solution.

[0006] The present invention provides a multi-objective optimization soft error reinforcement method based on Bayesian optimization theory, which includes three processes: circuit information acquisition, data dimension reduction and optimization reinforcement; wherein:

[0007] Circuit information acquisition process: obtain basic information including the area, power consumption and soft error rate of the trigger in the circuit;

[0008] Data dimensionality reduction process: Cluster, sort, and perform real-number encoding on the flip-flops in the circuit based on the acquired information to reduce the complexity of the data;

[0009] Optimization and hardening process: Based on the Bayesian optimization theory, use the Bayesian neural network BNN as a surrogate model to simulate the impact of replacing some flip-flops in the circuit with high-reliability structured flip-flops on the area, power consumption, and soft error rate metrics of the circuit's flip-flops. Use the acquisition function to select the next sampling evaluation point and perform multi-objective optimization to solve. After multiple iterations until certain conditions are met, obtain the best trade-off of area, power consumption, and soft error rate, and give the final replacement and hardening plan to replace the flip-flops in the circuit with corresponding high-reliability structured flip-flops.

[0010] In the present invention, the circuit information acquisition process specifically includes the following steps:

[0011] (1) Perform logic synthesis on the circuit file to obtain the basic information of the initial circuit, including the circuit netlist, area, and power consumption;

[0012] (2) According to the circuit netlist, regard the entire initial circuit as a directed acyclic graph G = <V, E>. The vertices V in the directed graph G include the input and output terminals of the circuit, the input and output terminals of all flip-flops in the circuit, and logic gates. The directed edges in the directed graph G include all the connections in the circuit;

[0013] (3) Based on the directed acyclic graph and the established soft error physical model, calculate the soft error rate values of each flip-flop in the initial circuit;

[0014] (4) Replace the flip-flops in the circuit netlist obtained after logic synthesis with high-reliability structured flip-flops with the same function one by one, and based on the analysis of logic synthesis and the soft error physical model, calculate and obtain the basic information of the corresponding circuit after replacing one flip-flop, including the area, power consumption, and soft error rate of the flip-flop;

[0015] (5) The circuit information acquisition process ends.

[0016] In the present invention, the high-reliability structured flip-flop is a flip-flop strengthened by structures such as triple modular redundancy (TMR).

[0017] In the present invention, during the data dimensionality reduction process, when clustering the flip-flops, by analyzing the impact of each flip-flop after hardening on the area, power consumption, and soft error rate metrics of the circuit, identify the potential patterns of the data, and use the corresponding clustering algorithm to perform clustering operations on the flip-flops; the clustering algorithms include the k-means clustering algorithm and the affinity propagation clustering algorithm.

[0018] In the present invention, during the data dimensionality reduction process, the Euclidean distance among the area, power consumption, and soft error rate metrics of each flip-flop is used as the similarity, and in combination with the superiority and inferiority of the flip-flop performance and the weight settings of each metric by the designer, the flip-flops in each cluster after clustering are sorted; the following is the specific process of sorting the flip-flops within the cluster:

[0019] ① Define the key coefficient of each flip-flop, denoted as F:

[0020] F = -W Area ·Area - W Power ·Power + W SER ·SER

[0021] Where W Area 、W Power 、W SER are the weights of the area, power consumption, and soft error rate metrics of the flip-flop respectively; calculate the key coefficient F of each flip-flop within the cluster;

[0022] ② Initialize an empty list, the length of the list is the same as the number of flip-flops within the cluster. According to the key coefficients of each flip-flop, select the flip-flop with the largest key coefficient F as the head of the list, and the flip-flop with the smallest key coefficient F as the tail of the list;

[0023] ③ Based on the head and tail of the list, traverse all the remaining flip-flops in the cluster, find the flip-flop that is closest (i.e., most similar) to the current head and tail of the list, place it near the head or tail of the list, and use it as the new head or tail of the list to update the list, and only update one point in each round;

[0024] ④ Repeat operation ③ until all the flip-flops within the cluster fill the entire list, and the sorting is completed;

[0025] In the present invention, during the data dimensionality reduction process, the sorted flip-flops in each cluster are encoded in real numbers. The flip-flops to be replaced with high-reliability structures are denoted as "1", and the flip-flops not to be replaced are denoted as "0". The reinforcement result is encoded, and the number of "1"s in the "1", "0" sequence after reinforcement, that is, the number of flip-flops reinforced in the sequence, is used as the encoding result, and the binary reinforcement scheme is converted into a decimal encoding result to ensure continuous changes.

[0026] In the present invention, during the optimization and reinforcement process, the lower confidence bound is selected as the acquisition function to select the next sampling and evaluation point, and the acquisition function is extended into three parts, corresponding to the three design metrics of area, power consumption, and soft error rate respectively.

[0027] In the present invention, during the optimization and strengthening process, the second-generation non-dominated sorting genetic algorithm NSGA-II is used as a multi-objective optimization algorithm to perform multi-objective optimization on the acquisition function, obtain the Pareto solution set, and select the next sampling and evaluation point from it; the actual multi-objective optimization problem is written as:

[0028]

[0029] where X = (x1, x2,..., x k ) T , X is a K-dimensional vector, K is the number of clusters after data dimensionality reduction by the clustering step, and x i is the real number encoding result of each cluster.

[0030] Compared with the existing circuit optimization and strengthening technologies, the advantages of the present invention are reflected in three aspects:

[0031] First, scalability. The present invention adopts a preprocessing method of input data dimensionality reduction, reducing the dimension of the data to be processed from exponential to power. Compared with the existing circuit optimization and strengthening technologies, it greatly reduces the complexity of the input data, which is beneficial to improving the speed and efficiency of subsequent optimization and strengthening processing, making the present invention applicable to the multi-objective optimization and soft error tolerance strengthening design of large-scale circuits;

[0032] Second, high efficiency. When the present invention performs multi-objective optimization to obtain the optimal replacement solution set, based on the Bayesian optimization theory, it abandons the cumbersome way of solving the visualization function and instead adopts an efficient black-box function optimization method. Compared with the existing circuit optimization and strengthening technologies, the present invention greatly reduces the complexity of the optimization solution, and the solution process is more efficient and simple;

[0033] Third, versatility. The present invention can provide a flexible and general replacement and strengthening scheme, which is not limited to the replacement and strengthening structure used in the design and strengthening, and can be used to guide the soft error tolerance replacement and strengthening of various highly reliable structures such as triple modular redundancy TMR. Compared with the existing circuit optimization and strengthening technologies, the present invention can adapt to circuit designs with multiple scenarios and requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a flowchart of the multi-objective optimization circuit strengthening method based on the Bayesian optimization theory according to the present invention.

[0035] Figure 2 is a trigger and truth table strengthened by the TMR structure.

[0036] Figure 3 is the clustering result of the intermediate trigger after strengthening the 32-bit Booth multiplier as the target circuit by the present invention.

[0037] Figure 4 This is an example of the trigger sorting during the data dimensionality reduction process of the present invention.

[0038] Figure 5 This is an example of the real number encoding of the trigger during the data dimensionality reduction process of the present invention.

[0039] Figure 6 This is the network structure diagram with a 32-bit Booth multiplier as the target circuit and a BNN selected as the surrogate model.

[0040] Figure 7 This is the final Pareto front output after the target circuit of the 32-bit Booth multiplier is strengthened by the present invention.

[0041] Figure 8 This is the final circuit replacement and strengthening solution output after the target circuit of the 32-bit Booth multiplier is strengthened by the present invention. Detailed implementation manners

[0042] The present invention will be further described in detail below in conjunction with embodiments.

[0043] Embodiment 1

[0044] A multi-objective optimization circuit strengthening method based on Bayesian optimization theory includes three processes, as Figure 1 shown. They are respectively the circuit acquisition and reading process, the data dimensionality reduction process, and the optimization and strengthening process.

[0045] In this embodiment, it is implemented based on the Python language. The circuit to be replaced and strengthened is a 32-bit Booth multiplier, and the high-reliability device selected is a trigger with a TMR structure. Its circuit structure and truth table are as Figure 2 shown. The basic information of the circuit is obtained based on the 28-nm CMOS bulk silicon process.

[0046] In this embodiment, the circuit information acquisition process specifically includes the following steps:

[0047] (1) Taking the synthesis tool Design Compiler as an example, perform logic synthesis on the 32-bit Booth multiplier to be strengthened, and obtain the netlist file, area, power consumption, etc. information of the multiplier circuit;

[0048] (2) According to the circuit netlist, regard the entire Booth multiplier circuit as a directed acyclic graph G = <V, E>. The vertices V in the directed graph G include the input and output terminals of the circuit, the input and output terminals of all the triggers in the circuit, and the logic gates. The directed edges in the directed graph G include all the connections in the circuit.

[0049] (3) Based on the directed acyclic graph and the established soft error physical model, using the open-source software BFIT, calculate the soft error rate values of each flip-flop in the Booth multiplier circuit;

[0050] (4) Replace the flip-flops in the multiplier circuit netlist obtained after synthesis with highly reliable flip-flops of the same function strengthened by the TMR structure one by one, and only replace one flip-flop each time. Through logic synthesis and analysis of the soft error physical model, calculate the basic information such as the area, power consumption, and soft error rate of the corresponding circuit after replacing one flip-flop;

[0051] (5) The process of obtaining circuit information ends. This process obtains the basic information such as the area, power consumption, and soft error rate of the flip-flops in the Booth multiplier circuit, which is beneficial to the analysis and execution of the subsequent circuit data dimensionality reduction and optimization strengthening process.

[0052] In this embodiment, the process of circuit data dimensionality reduction is specifically as follows:

[0053] (1) Flip-flop clustering. According to the basic information such as the area, power consumption, and soft error rate of the circuit after replacing one flip-flop obtained in the information acquisition process, by analyzing the influence of each flip-flop after strengthening on the indicators such as the area, power consumption, and soft error rate of the circuit, identify the potential patterns of the data, and use the corresponding clustering algorithms (such as k-means clustering algorithm, affinity propagation clustering algorithm, etc.) to perform clustering operations on the flip-flops. The performance of the flip-flops grouped into one category, such as area, power consumption, and soft error rate, is affected by strengthening in a relatively similar way. In this example, the k-means clustering algorithm is used to cluster the 229 flip-flops in the Booth multiplier. The principle of this algorithm is simple and easy to implement, and it is widely used in clustering operations. This algorithm clusters the flip-flops with relatively similar performance based on the information such as the area, power consumption, and soft error rate of each flip-flop obtained in the information acquisition process. The 229 flip-flops in the Booth multiplier are clustered into 4 clusters, containing 61, 32, 6, and 130 flip-flops respectively. The flip-flop results before and after clustering are as Figure 3 shown.

[0054] (2) Sort the flip-flops in each cluster after clustering. Use the Euclidean distance between the indicators of each flip-flop as the similarity, and combine the superiority and inferiority of the flip-flop performance and the weight settings of the designer for each indicator for sorting. Figure 4 For the schematic diagram of this sorting process, the following is the specific process of sorting the flip-flops within the cluster:

[0055] ① Define the key coefficient of each flip-flop, denoted as F:

[0056] F = -W Area ·Area - W Power·Power+W SER ·SER

[0057] where W Area 、W Power 、W SER are the weights of metrics such as area, power consumption, and soft error rate respectively. It can be seen that for flip - flops with small area and power consumption but large soft error rate, the larger the critical coefficient, the more important the impact on the circuit. Calculate the critical coefficient F of each flip - flop within the cluster. In this embodiment, it is set that W Area 、W Power 、W SER are 0.1, 0.1, and 0.8 respectively.

[0058] ② Initialize an empty list, and the length of the list is the same as the number of flip - flops within the cluster. According to the critical coefficients of each flip - flop, select the flip - flop with the largest critical coefficient F as the head of the list, and the flip - flop with the smallest critical coefficient F as the tail of the list.

[0059] ③ Based on the head and tail of the list, traverse all the remaining flip - flops in the cluster, find the flip - flop that is closest (i.e., most similar) to the current head and tail of the list, place it near the head or tail, and use it as the new head or tail of the list to update the list, and only update one point in each round.

[0060] ④ Repeat operations ① - ③ until all the flip - flops within the cluster are sorted and the entire list is filled.

[0061] After the flip - flops are clustered, the clusters are clearly distinguished from each other, but the flip - flops within the cluster are still in a chaotic and disorderly state. When the flip - flops within the cluster are sorted, it can make the data change smoother and more continuous, facilitating the subsequent optimization work.

[0062] (3) Perform real - number encoding on the sorted flip - flops within each cluster. Mark the flip - flops to be replaced with high - reliability structures as "1", and the non - replaced flip - flops as "0". Since the performance of adjacent flip - flops within the cluster is similar after sorting, in the actual replacement and reinforcement operation, the replacement will necessarily be carried out continuously, that is, "1" will be placed continuously, making the replacement result meet the designer's expectations and also making the change relatively gentle. Based on this, encode the reinforcement result, and use the number of "1"s (i.e., the number of flip - flops reinforced in the sequence) in the "1", "0" sequence after reinforcement as the encoding result, converting the binary reinforcement scheme into a decimal encoding result. For example, Figure 5 in the case of real - number encoding, consider there are 6 flip - flops (already sorted). When FF2 is reinforced, the sequence 100000 is obtained, and the encoding value is 1; if FF2 and FF3 are replaced, the sequence 110000 is obtained, and the encoding value is 2; if all 6 flip - flops are replaced, the sequence 111111 is obtained, and the encoding value is the real number 6.

[0063] (4) The circuit data dimensionality reduction process ends. Based on the basic information such as the area, power consumption, and soft error rate of the flip - flops in the circuit, the flip - flops are clustered, sorted, and real - numbered encoded. In this embodiment, the input data dimension is reduced from 2 299 to 61×32×6×130, effectively reducing the dimension of the input data and making the data change smoother and more continuous, which is conducive to the analysis and execution of the subsequent circuit optimization and hardening process, and improving the accuracy and effectiveness of the Bayesian optimization process.

[0064] In this embodiment, the circuit optimization and hardening process specifically includes the following steps:

[0065] (1) Select a suitable surrogate model to simulate the impact of replacing some flip - flops in the circuit with high - reliability - structured flip - flops on circuit metrics such as area, power consumption, and soft error rate. And through continuous iteration, expand the sample set to update and correct the model to improve the fitting accuracy of the circuit hardening objective function. The input variables of the objective function are the encodings of each cluster, and the output variables are the values of the circuit area, power consumption, and soft error rate. This includes but is not limited to using a Bayesian Neural Network (BNN) etc. as a surrogate model. For example, a Bayesian Neural Network (Bayesian Neural Network, BNN) can be selected as a probabilistic surrogate model to simulate the impact of flip - flop replacement hardening on circuit metrics such as area, power consumption, and soft error rate. The network parameters of the Bayesian Neural Network conform to a certain probability distribution, are relatively flexible, and can better simulate the circuit hardening behavior.

[0066] In this embodiment, a Bayesian Neural Network is selected as a probabilistic surrogate model to mimic the actual circuit hardening problem. The network represents the three objective functions of area, power consumption, and soft error rate (SER). The specific structure is as Figure 6 shown. The number of neurons in the input layer (Input Layer) of this Bayesian Neural Network is equal to the number of clustering clusters, with 4 neurons; there are 2 hidden layers (Hidden Layer), with 6 and 10 neurons respectively; the number of neurons in the output layer (Output Layer) is consistent with the number of objective functions considered. Considering the three metrics of area, power consumption, and soft error rate (SER), the output layer is set to contain 3 neurons.

[0067] (2) Select a suitable acquisition function to find the next evaluation point, ensure that each sampling is effective, so as to improve the optimization speed, accelerate convergence, and obtain the global optimal solution after a few iterations. This includes but is not limited to using the confidence bound as an acquisition function. For example, the Lower Confidence Bound (LCB) can be selected as the acquisition function. The LCB function can be written as:

[0068]

[0069] Among them, μ t (x) is the mean value, is the variance, and both are derived from the prior distribution; β t is used to balance the mean value and the variance, that is, comprehensively consider development and exploration and make a trade-off. Exploitation is to sample within the range where the global optimal solution is most likely to appear according to the posterior distribution, but it is easy to fall into the local optimum; Exploration is to find sampling points within the global range, especially in areas that have never been sampled before. This will prevent the final result from falling into the local optimum, but may lead to slower convergence and sometimes poorer sampling results. Consider the trade-off between development and exploration, that is, make a compromise between the convergence speed and the approximate optimum. In practical applications, generally set β t as a constant, and this value needs to be determined through trial.

[0070] In this embodiment, the Lower Confidence Bound LCB is selected as the acquisition function, and it has been verified through testing that when β t = 0.3, it can achieve a better trade-off between development and exploration and obtain an ideal acquisition result.

[0071] (3) Expand the acquisition function. Bayesian optimization is generally used for single-objective optimization. Considering that in circuit hardening design, three indicators such as area, power consumption, and soft error rate need to be comprehensively considered, in this embodiment, the acquisition function is expanded into three parts, which correspond to the three design indicators of area, power consumption, and soft error rate respectively.

[0072] (4) Multi-objective optimization. Through the multi-objective optimization algorithm, multi-objective optimization is performed on the above three acquisition functions to obtain the next sampling evaluation point. The actual multi-objective optimization problem in this embodiment can be written as:

[0073]

[0074] Among them, X = (x1, x2,..., x k ) T , X is a K-dimensional vector, K is the number of clusters after the data dimensionality reduction step of clustering, and x i is the real number coding result of each cluster.

[0075] In this embodiment, the second-generation non-dominated sorting genetic algorithm (Non-dominated Sorting Genetic Algorithm-II, NSGA-II) is used to perform multi-objective optimization on the three acquisition functions corresponding to area, power consumption, and soft error rate, obtain the Pareto solution set, and select a suitable sampling evaluation point from it.

[0076] (5) Iterate multiple times until the stopping condition is met to obtain the final Pareto solution set. From the Pareto solution set obtained in the previous round of multi-objective optimization, select the ones that better meet the requirements and add them to the initial dataset, and repeat operations such as Bayesian optimization and multi-objective optimization to solve. Iterate repeatedly until a certain stopping condition is met (such as the accuracy of area, power consumption, and soft error rate meets the requirements or the set number of iterations is reached). The output of the last round is the final Pareto solution set.

[0077] (6) When the optimization and hardening process ends, the output Pareto solution set is the encoding result of each cluster. After decoding, the final replacement and hardening scheme can be output. Designers can select the most suitable set of replacement and hardening schemes according to the actual requirements of the circuit design to optimize the circuit hardening design. Figure 7 The Pareto front finally obtained for this embodiment is given. The marked points are the performances of the final Pareto solutions in terms of area, power consumption, and soft error rate. It can be intuitively seen that there is no solution whose performance in terms of area, power consumption, and soft error rate is better than that of other solutions, indicating that the effect of multi-objective optimization is achieved. Figure 8 The Pareto solution set finally given by the present invention for the embodiment is listed. Each set of solutions is a replacement scheme. For example, the first set of solutions means that the first 35 flip-flops in the zero-th cluster, the first 19 flip-flops in the first cluster, the first 3 flip-flops in the second cluster, and the first 13 flip-flops in the third cluster are replaced with corresponding highly reliable structures respectively. Designers can select the most suitable replacement scheme according to actual requirements. It can be seen that the present invention can effectively guide designers to carry out soft error tolerance hardening design of circuits. Compared with existing circuit optimization and hardening methods, it can be applied to large-scale circuit hardening problems, can be applied to the hardening replacement of various highly reliable structures, and the optimization process is more efficient and simple.

Claims

1. A multi-objective optimization soft error reinforcement method based on Bayesian optimization theory, characterized in that, It includes three processes: circuit information acquisition, data dimensionality reduction, and optimization and hardening; among which: Circuit information acquisition process: Acquire basic information including the area, power consumption, and soft error rate of flip-flops in the circuit; Data dimensionality reduction process: Cluster, sort, and perform real-number encoding on the flip-flops in the circuit according to the acquired information to reduce the data complexity; Optimization and hardening process: Based on the Bayesian optimization theory, use the Bayesian neural network BNN as a surrogate model to simulate the impact of replacing some flip-flops in the circuit with high-reliability structure flip-flops on the area, power consumption, and soft error rate indicators of the flip-flops in the circuit. Use the acquisition function to select the next sampling evaluation point and perform multi-objective optimization to solve. After multiple iterations until a certain condition is met, obtain the best trade-off of the area, power consumption, and soft error rate of the flip-flops, give the final replacement and hardening plan, and replace the flip-flops in the circuit with corresponding high-reliability structure flip-flops; among which: In the data dimensionality reduction process, use the Euclidean distance between the area, power consumption, and soft error rate indicators of each flip-flop as the similarity, and combine the performance advantages and disadvantages of the flip-flops and the weight settings of the designer for the indicators of the flip-flops in the circuit to sort the flip-flops in each cluster after clustering; specifically as follows: ① Define the key coefficient of each flip-flop, denoted as F: F = -W Area ·Area - W Power ·Power + W SER ·SER Among which W Area 、W Power 、W SER respectively represent the weights of the area, power consumption and soft error rate metrics of the flip-flop; calculate the critical coefficient F of each flip-flop within the cluster; ② Initialize an empty list, the length of the list is the same as the number of flip-flops in the cluster. According to the key coefficients of each flip-flop, select the flip-flop with the largest key coefficient F as the head of the list, and the flip-flop with the smallest key coefficient F as the tail of the list; ③ Based on the head and tail of the list, traverse all the remaining flip-flops in the cluster, find the flip-flop that is closest to the current head and tail of the list, that is, the most similar, and place it near the head or tail of the list, and use it as the new head or tail of the list to update the list, and only update one point per round; ④ Repeat operation ③ until all the flip-flops in the cluster fill the entire list, and the sorting is completed.

2. The multi-objective optimization soft error reinforcement method based on Bayesian optimization theory according to claim 1, characterized in that, The described circuit information acquisition process specifically includes the following steps: (1) Perform logic synthesis on the circuit file to obtain basic information including the circuit netlist, area, and power consumption of the initial circuit; (2) According to the circuit netlist, regard the entire initial circuit as a directed acyclic graph G = <V, E>. The vertices V in the directed graph G include the input and output terminals of the circuit, the input and output terminals of all flip-flops in the circuit, and logic gates. The directed edges in the directed graph G include all the connections in the circuit; (3) Based on the directed acyclic graph and the established soft error physical model, calculate the soft error rate values of each flip-flop in the initial circuit; (4) Replace the flip-flops in the circuit netlist obtained after logic synthesis with high-reliability structure flip-flops with the same function one by one, and based on the analysis of logic synthesis and the soft error physical model, calculate and obtain the basic information including the area, power consumption, and soft error rate of the corresponding circuit after replacing one flip-flop; (5) The circuit information acquisition process ends.

3. The multi-objective optimization soft error reinforcement method based on Bayesian optimization theory according to claim 1 or 2, characterized in that, The high-reliability structure flip-flop is a flip-flop strengthened by a triple modular redundancy (TMR) structure.

4. The multi-objective optimization soft error reinforcement method based on Bayesian optimization theory according to claim 1, characterized in that, During the data dimensionality reduction process, when clustering flip-flops, by analyzing the impacts of each flip-flop after hardening on the area, power consumption, and soft error rate metrics of the flip-flops in the circuit, potential patterns of the data are identified, and the corresponding clustering algorithm is used to perform clustering operations on the flip-flops; the clustering algorithms include the k-means clustering algorithm and the affinity propagation clustering algorithm.

5. The multi-objective optimization soft error reinforcement method based on Bayesian optimization theory according to claim 1, characterized in that, During the data dimensionality reduction process, real-number encoding is performed on the sorted flip-flops in each cluster. The flip-flops to be replaced with highly reliable structures are denoted as "1", and the flip-flops not replaced are denoted as "0". The hardening results are encoded, and the number of "1"s in the "1", "0" sequence after hardening, that is, the number of flip-flops hardened in the sequence, is used as the encoding result, and the binary hardening scheme is converted into a decimal encoding result to ensure continuous changes.

6. The multi-objective optimization soft error reinforcement method based on Bayesian optimization theory according to claim 1, characterized in that, During the optimization hardening process, the number of neurons in the input layer of the Bayesian neural network used is equal to the number of clustering clusters of the flip-flops. There are 2 hidden layers, with 6 and 10 neurons respectively; the output layer contains 3 neurons.

7. The multi-objective optimization soft error reinforcement method based on Bayesian optimization theory according to claim 1, characterized in that, During the optimization hardening process, the lower confidence bound is selected as the acquisition function to select the next sampling evaluation point, and the acquisition function is extended into three parts, corresponding to the three design metrics of the flip-flop area, power consumption, and soft error rate respectively.

8. The multi-objective optimization soft error reinforcement method based on Bayesian optimization theory according to claim 1, characterized in that, During the optimization hardening process, the second-generation non-dominated sorting genetic algorithm NSGA-II is used as the multi-objective optimization solution algorithm to perform multi-objective optimization on the acquisition function to obtain the Pareto solution set, and the next sampling evaluation point is selected from it; the actual multi-objective optimization problem is written as: where X = (x1, x2, …, x k ) T , X is a K-dimensional vector, K is the number of clusters after clustering in the data dimensionality reduction step, and x i is the real number coding result of each cluster.

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