Jitter tolerance measurement device and jitter tolerance measurement method

Abstract

The present invention provides a jitter tolerance measurement device, which comprises: a data comparison unit, which detects FEC symbol errors of a measured signal output from a DUT accompanied by an input of a jitter signal; an error counting unit, which counts the number of codeword units of the detected FEC symbol errors in units of phase modulation amount; a CW classification unit, which classifies a plurality of codewords included in the measured signal into a plurality of groups according to the counted number of FEC symbol errors; a CW number counting unit, which counts the number of codewords of each group in units of phase modulation amount; and a display control unit, which controls displaying a first graph on a display screen, wherein the horizontal axis of the first graph is set to the phase modulation amount and the vertical axis is set to the ratio of the number of codewords of each group.

Description

Technical Field

[0001] The present invention relates to a jitter tolerance measurement device and a jitter tolerance measurement method, and in particular to a jitter tolerance measurement device and a jitter tolerance measurement method for measuring the jitter tolerance of a test object based on a communication standard using forward error correction. Background Art

[0002] In recent years, IP data communication volume has continued to increase with the spread of 5th generation mobile communication systems and IoT (Internet of Things) devices. In data centers that support large-capacity data communications, the introduction of 400GbE communication methods is being promoted, and research is being conducted on the development of 800GbE / 1.6TbE to cope with future higher-capacity transmission. In 200GbE / 400GbE standardized in 2017, PAM4 (Pulse Amplitude Modulation 4) was adopted as the transmission format due to the increase in transmission capacity. Compared with the previous NRZ (Non Return to Zero) that transmits in two values, PAM4 that transmits in four values ​​can double the transmission speed, but on the other hand, the SN ratio (Signal to Noise Ratio) deteriorates by about 10dB. Therefore, in the physical layer transmission of 200GbE / 400GbE, it is difficult to realize error-free transmission as a matter of course in NRZ transmission due to the increase in transmission speed and the deterioration of SN ratio, and thus a transmission method based on forward error correction (FEC) is used.

[0003] For example, in the FEC encoding based on RS-FEC (Reed Solomon FEC: Reed-Solomon forward error correction) (544, 514) specified in IEEE802.3, a codeword (Codeword: CW) having 544 FEC symbols is generated, and the 544 FEC symbols are composed of a parity check part and a message part, the parity check part is composed of 30 FEC symbols (FECSymbol), and the message part is composed of 514 FEC symbols. In addition, in the FEC encoding based on RS-FEC (528, 514) specified in IEEE802.3, a codeword having 528 FEC symbols is generated, and the 528 FEC symbols are composed of a parity check part and a message part, the parity check part is composed of 14 FEC symbols, and the message part is composed of 514 FEC symbols.

[0004] In this way, the codeword contains the parity check part of 30 FEC symbols (or 14 FEC symbols), so each codeword can correct the errors of up to 15 (or 7) FEC symbols. Therefore, a codeword with more than 16 (or 8) FEC symbol errors in one codeword becomes an Uncorrectable Codeword that cannot be corrected. In addition, if one FEC symbol is composed of 10 bits and the number of bit errors contained in one FEC symbol is in the range of 1 to 10, then the FEC symbol becomes an FEC symbol containing errors. Therefore, according to the distribution of bit errors, an Uncorrectable Codeword is generated in a minimum of 16 bit errors (or 8 bit errors), but sometimes an Uncorrectable Codeword is not generated in a maximum of 150 bit errors (or 70 bit errors).

[0005] In the past, jitter tolerance tests were performed by gradually adding jitter to the device under test (DUT) and measuring the amount of jitter (phase modulation) that the DUT can withstand without causing errors (for example, refer to Patent Document 1). In jitter tolerance tests to date, measurements were performed with only the bit error rate (BER) as the target, but in tests based on FEC, not only the BER but also the ratio of the number of FEC symbol errors in codeword units becomes a very important indicator. There is no fixed correlation between the BER and the number of uncorrectable codewords, so for example, even under the same BER conditions, the results of FEC jitter tolerance vary greatly depending on whether uncorrectable codewords are generated.

[0006] However, the jitter tolerance measurement device disclosed in Patent Document 1 can perform jitter tolerance measurement and estimation based on BER, but has a problem that it cannot perform a jitter tolerance test corresponding to FEC.

[0007] On the other hand, there is proposed a network test apparatus that receives a codeword transmitted from a DUT to display the distribution of the number of FEC symbol errors thereof (for example, refer to Patent Document 2).

[0008] Patent Document 1: Japanese Patent No. 6199420

[0009] Patent Document 2: Japanese Patent Application 2020-033640

[0010] In the network test device disclosed in Patent Document 2, for example, a display device is provided. Figure 7In this way, the distribution of the number of FEC symbol errors during the measurement period can be displayed in a graph, but in order to confirm how the distribution changes due to the increase in the jitter amount, data must be acquired each time, which requires the labor and time to generate a graph again. In other words, there is a problem that multiple graphs are created according to the jitter amount, and the analysis of the measurement results becomes complicated. Summary of the invention

[0011] The present invention has been made to solve such conventional problems, and an object of the present invention is to provide a jitter tolerance measurement device and a jitter tolerance measurement method capable of expressing the distribution of FEC symbol errors having different jitter amounts (phase modulation amounts) in one graph.

[0012] In order to solve the above-mentioned problems, the jitter tolerance measurement device involved in the present invention comprises: a data signal output unit, which outputs a data signal including a plurality of code words composed of a plurality of FEC symbols; a jitter signal generator, which performs phase modulation on the data signal to generate a jitter signal, and inputs the jitter signal to a test object; a modulation control unit, which controls the phase modulation amount of the phase modulation to be changed; a data comparison unit, which detects bit errors and FEC symbol errors of the test signal output from the test object accompanied by the input of the jitter signal; and an error counting unit, which counts the number of bit errors of the test signal detected by the data comparison unit and the number of code word units of FEC symbol errors of the test signal detected by the data comparison unit, The jitter tolerance measurement device has the following structure, that is, it comprises: a codeword classification unit, the error counting unit counts the number of codeword units of the FEC symbol errors in the phase modulation amount unit as the FEC symbol error number, and classifies the multiple codewords contained in the measured signal into multiple groups based on the counted FEC symbol error number; a codeword number counting unit counts the number of codewords belonging to each of the groups classified by the codeword classification unit in the phase modulation amount unit; and a display control unit controls the display of a first graph on a display screen, the first graph having a horizontal axis set to the phase modulation amount and a first vertical axis set to the number of codewords for each of the groups counted by the codeword number counting unit or a ratio of the number of codewords.

[0013] According to this configuration, the jitter tolerance measurement device according to the present invention classifies a plurality of codewords included in the measured signal into a plurality of groups according to the number of FEC symbol errors, and counts the number of codewords belonging to each group in units of phase modulation amount. Thus, the jitter tolerance measurement device according to the present invention sets the horizontal axis to the phase modulation amount, and sets the first vertical axis to the number of codewords in each group or the ratio of the number of codewords, and can represent the distribution of FEC symbol errors with different jitter amounts (phase modulation amounts) in one graph.

[0014] Furthermore, the jitter tolerance measurement device involved in the present invention can be configured as follows, that is, it further comprises: a BER calculation unit, which calculates the bit error rate of the measured signal based on the number of bit errors counted by the error counting unit, and the display control unit controls the second graph to be displayed on the display screen by overlapping the first graph, and the second graph sets the horizontal axis to the phase modulation amount and the second vertical axis to the bit error rate of the measured signal calculated by the BER calculation unit.

[0015] According to this configuration, the jitter tolerance measurement device according to the present invention can superimpose and display the distribution of FEC symbol errors and the change in BER in a graph whose horizontal axis is the phase modulation amount.

[0016] Furthermore, the jitter tolerance measurement device according to the present invention may be configured such that the display control unit displays the number of code words or the ratio of the number of code words for each of the groups counted by the CW number counting unit in different colors for each group in the first graph.

[0017] According to this configuration, the jitter tolerance measurement device according to the present invention displays the distribution of FEC symbol errors by color classification for each group, and thus can clearly visually represent the distribution of FEC symbol errors on a graph.

[0018] Furthermore, the jitter tolerance measurement device according to the present invention may be configured to further include an operation unit for changing a scale of the first vertical axis of the first graph.

[0019] According to this configuration, the jitter tolerance measurement device of the present invention can appropriately scale the first vertical axis by the user's operation of the operation unit, and can therefore clearly visually represent the number of codewords with a low ratio such as Uncorrectable Codewords or the ratio of the number of codewords on the graph.

[0020] Furthermore, the jitter tolerance measurement method according to the present invention is a mechanism comprising a data signal output step for outputting a data signal including a plurality of code words composed of a plurality of FEC symbols; a jitter signal generation step for performing phase modulation on the data signal to generate a jitter signal, and inputting the jitter signal into a test object; a modulation control step for performing control to change a phase modulation amount of the phase modulation; a data comparison step for detecting a bit error and an FEC symbol error of a test signal output from the test object accompanying the input of the jitter signal; and an error counting step for counting the number of bit errors of the test signal detected by the data comparison step and the number of code word units of FEC symbol errors of the test signal detected by the data comparison step, The jitter tolerance measurement method is characterized in that it includes: a codeword classification step, the error counting step counts the number of codeword units of the FEC symbol errors in the phase modulation amount unit as the FEC symbol error number, and classifies the multiple codewords contained in the measured signal into multiple groups based on the counted FEC symbol error number; a codeword number counting step counts the number of codewords belonging to each of the groups classified by the CW classification step in the phase modulation amount unit; and a display control step controls the display of a first graph on a display screen, the first graph sets the horizontal axis to the phase modulation amount, and sets the first vertical axis to the number of codewords for each of the groups counted by the codeword number counting step or the ratio of the number of codewords.

[0021] Furthermore, the jitter tolerance measurement method involved in the present invention may be configured as follows, namely, further comprising: a BER calculation step for calculating the bit error rate of the measured signal based on the number of bit errors counted by the error counting step; and a display control step for controlling the second graph to be displayed on a display screen by overlapping the first graph, wherein the second graph sets the horizontal axis to the phase modulation amount and sets the second vertical axis to the bit error rate of the measured signal calculated by the BER calculation step.

[0022] Effects of the Invention

[0023] The present invention provides a jitter tolerance measurement device and a jitter tolerance measurement method capable of expressing the distribution of FEC symbol errors with different jitter amounts (phase modulation amounts) in one graph. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a block diagram showing the structure of a jitter tolerance measurement device according to an embodiment of the present invention.

[0025] Figure 2 Yes means through Figure 11 is a table showing an example of the lower limit value and the upper limit value of the phase modulation amount per modulation frequency unit set by the modulation control unit.

[0026] Figure 3 This is a table showing combinations of modulation frequency and phase modulation amount in a jitter tolerance test according to the 400GAUI-8 standard.

[0027] Figure 4 It means by Figure 1 The display control unit shown displays a graph showing the distribution of the number of FEC symbol errors in units of the controlled phase modulation amount and the BER.

[0028] Figure 5 It means it is magnified 100,000 times. Figure 4 The vertical axis on the left side of the chart is on the lower side of the chart.

[0029] Figure 6 1 is a flowchart showing the process of a jitter tolerance measurement method using the jitter tolerance measurement device according to the embodiment of the present invention.

[0030] Figure 7 This is a graph showing the distribution of the number of conventional FEC symbol errors. DETAILED DESCRIPTION

[0031] Hereinafter, embodiments of a jitter tolerance measurement device and a jitter tolerance measurement method according to the present invention will be described with reference to the drawings.

[0032] like Figure 1 As shown, a jitter tolerance measurement device 1 according to an embodiment of the present invention is roughly configured to include a jitter generating unit 2 and a jitter tolerance measuring unit 3. The jitter tolerance measurement device 1 is a device for measuring jitter tolerance indicating the degree to which a DUT 4 based on a communication standard using FEC is subjected to fluctuations (jitter) in the phase of an input data signal or the like.

[0033] The communication standard corresponding to DUT4 is, for example, Ethernet (registered trademark) such as 800 / 400 / 200 / 100 / 50GbE, 1.6TbE, PCI-Express (Peripheral Component Interconnect Express) (registered trademark), etc. As DUT4, an electrical signal or an optical signal is output as a measured signal, but it is assumed that the input data signal is not corrected.

[0034] As DUT4 that outputs optical signals, for example, optical transceivers can be cited. As DUT4 that outputs electrical signals, for example, PPG, DSP (Digital Signal Processor) used in optical modules, etc. can be cited. Optical transceivers are modules used to alternately convert electrical signals and optical signals, such as optical transceiver devices such as TOSA (Transmitter Optical Sub-Assembly: optical transmitting sub-module) equipped with an electro-absorption modulated laser (Electro-absorption Modulator integrated Laser diode: EML) or ROSA (Receiver Optical Sub-Assembly: optical receiving sub-module) equipped with a photodiode (Photodiode). The standards of optical transceivers include QSFP-DD, OSPF, CFP8, SFP56, etc.

[0035] When DUT 4 outputs an optical signal, MCB (Module Compliance Board) 5 is connected to DUT 4, and MCB converts the optical signal output from DUT 4 into an electrical signal. Thus, the jitter tolerance measurement unit 3 inputs an electrical signal regardless of whether DUT 4 outputs an electrical signal or an optical signal.

[0036] The jitter generating unit 2 generates a phase modulated jitter signal with a phase modulation amount proportional to the amplitude of the modulation signal (sinusoidal jitter amplitude: SJ amplitude). Figure 1 As shown, the structure includes a data signal output unit 21, a modulation signal generator 22 and a jitter signal generator 23.

[0037] The data signal output unit 21 outputs a data signal including a plurality of code words formed by a plurality of FEC symbols. The data signal output unit 21 can output, for example, a binary NRZ signal or a multi-value modulation signal having three or more values ​​as the data signal. In the present embodiment, the case where a binary NRZ signal and a four-value multi-value modulation signal, i.e., a PAM4 signal, are output from the data signal output unit 21 is mainly described as an example.

[0038] The NRZ signal output from the data signal output unit 21 is composed of data of two bit strings consisting of 0 and 1 (hereinafter, also referred to as "bit string data"), and FEC encoding based on RS-FEC (528, 514) specified in IEEE802.3 is performed. In addition, the PAM4 signal output from the data signal output unit 21 is composed of data of four PAM4 symbol strings consisting of 0 (00), 1 (01), 2 (10), and 3 (11), and FEC encoding based on RS-FEC (544, 514) specified in IEEE802.3 is performed. These data signals also become reference data when measuring the BER or FEC symbol error of the DUT4 in the jitter tolerance measurement unit 3.

[0039] As a specific data signal generated by the data signal output unit 21, there is, for example, PRBS7 (pattern length: 2 7 -1), PRBS9 (pattern length: 2 9 -1), PRBS10 (pattern length: 2 10 -1), PRBS11 (pattern length: 2 11 -1), PRBS15 (pattern length: 2 15 -1), PRBS20 (pattern length: 2 20 -1) and other pseudo-random patterns (PRBS: Pseudo Random Bit Sequence); evaluation patterns for evaluating PAM4 signals such as PRBS13Q, PRBS31Q, and SSPRQ; and scrambled idle patterns with RS-FEC (Reed-Solomon Forward Error Correction) codes.

[0040] The modulation signal generator 22 generates a modulation signal for adding jitter to the data signal output from the data signal output unit 21. The modulation frequency and phase modulation amount (or SJ amplitude) of the modulation signal generated by the modulation signal generator 22 can be set to user-desired values ​​by operating the operation unit 37 described later, for example.

[0041] The jitter signal generator 23 generates a jitter signal by phase-modulating the data signal output from the data signal output section 21 at a desired phase modulation amount based on the modulation signal output from the modulation signal generator 22 , and inputs the generated jitter signal to the DUT 4 .

[0042] The jitter tolerance measurement unit 3 receives the measured signal output from the DUT 4 along with the input of the jitter signal generated by the jitter generation unit 2 and measures the jitter tolerance. Figure 1As shown, the signal receiving unit 31 includes a synchronization detecting unit 32 (32a, 32b), a data comparing unit 33, a control unit 35, a storage unit 36, an operating unit 37, and a display unit 38. The signal receiving unit 31 includes a PAM4 decoder 31a and a Gray decoder 31b.

[0043] When the jitter signal input to DUT4 is a PAM4 signal, the PAM4 decoder 31a generates the most significant bit string data (hereinafter also referred to as "MSB (Most Significant Bit: Most Significant Bit) data") and the least significant bit string data (hereinafter also referred to as "LSB (Least Significant Bit: Least Significant Bit) data") from the measured signal (PAM4 signal).

[0044] When the PAM4 signal input to the DUT4 is encoded based on the Gray Code, the Gray decoder 31b performs a Gray Code decoding process on the MSB data and the LSB data output from the PAM4 decoder 31a. On the other hand, when the PAM4 signal input to the DUT4 is not encoded based on the Gray Code, the Gray decoder 31b allows the MSB data and the LSB data output from the PAM4 decoder 31a to pass directly.

[0045] When the jitter signal input to the DUT4 is a PAM4 signal, the synchronization detection unit 32a synchronizes the MSB data of the PAM4 signal, which is the MSB reference data, which is read from the storage unit 36 ​​described later, with the MSB data of the signal under test output from the Gray decoder 31b. Furthermore, the synchronization detection unit 32a sets the beginning of the pattern of the MSB data of the signal under test synchronized with the MSB reference data as the beginning of the codeword, and divides the MSB data of the signal under test into FEC symbols of 10 bits from the beginning.

[0046] When the jitter signal input to the DUT4 is a PAM4 signal, the synchronization detection unit 32b synchronizes the LSB data of the PAM4 signal serving as a reference, i.e., the LSB reference data, which is read from the storage unit 36 ​​described later, with the LSB data of the signal under test output from the Gray decoder 31b. Furthermore, the synchronization detection unit 32b sets the beginning of the pattern of the LSB data of the signal under test synchronized with the LSB reference data as the beginning of the codeword, and divides the LSB data of the signal under test into FEC symbols of 10 bits from the beginning.

[0047] The data comparison unit 33 compares the MSB data and LSB data of the test signal output from the synchronization detection units 32a and 32b with the MSB reference data and the LSB reference data, respectively, and detects the most significant bit error (hereinafter also referred to as "MSB error") and the least significant bit error (hereinafter also referred to as "LSB error"). In the MSB data and LSB data of the test signal divided into 10-bit units, even if a 1-bit error occurs within 10 bits, the data comparison unit 33 detects it as a 1FEC symbol error.

[0048] When the jitter signal input to the DUT 4 is an NRZ signal, the signal receiving unit 31 samples the measured signal (NRZ signal) at a predetermined sampling period and converts it into bit string data. The bit string data converted by the signal receiving unit 31 is input to the synchronization detecting unit 32 .

[0049] When the jitter signal input to the DUT 4 is an NRZ signal, the synchronization detection unit 32 synchronizes the bit string data of the NRZ signal, i.e., the NRZ reference data, which is a reference NRZ signal read from the storage unit 36 ​​described later, with the bit string data of the signal under test output from the signal receiving unit 31. Furthermore, the synchronization detection unit 32 sets the beginning of the pattern of the bit string data of the signal under test synchronized with the NRZ reference data as the beginning of the codeword, and divides the bit string data of the signal under test into FEC symbols of 10 bits from the beginning.

[0050] When the jitter signal input to the DUT 4 is an NRZ signal, the data comparison unit 33 compares the bit string data of the test signal output from the synchronization detection unit 32 with the NRZ reference data to detect a bit error of the test signal. In the bit string data of the test signal divided into 10-bit units, even if a 1-bit error occurs within 10 bits, the data comparison unit 33 detects it as a 1FEC symbol error.

[0051] The storage unit 36 ​​stores the bit string data, MSB data, and LSB data of the data signal of the known pattern output from the data signal output unit 21. The bit string data, MSB data, and LSB data of the data signal of the known pattern become reference data for comparison with the bit string data, MSB data, and LSB data of the measured signal sent from the DUT4. In addition, the storage unit 36 ​​stores the counting result of the error counting unit 35b described later based on the control unit 35. In addition, the storage unit 36 ​​stores the comparison result data compared by the data comparison unit 33 together with the bit string data, MSB data, and LSB data of the measured signal synchronized with the reference data. In addition, the storage unit 36 ​​stores data that establishes a correspondence between the BER of the measured signal and the number of FEC symbol errors in the codeword unit and the phase modulation amount and the modulation frequency obtained by the control unit 35 described later.

[0052] The operation unit 37 is used to receive operation input by the user, and is composed of, for example, a touch panel with a contact sensor for detecting a contact position based on a contact operation on an input surface corresponding to the display screen of the display unit 38. When the user touches the position of a specific item displayed on the display screen with a finger or a stylus pen, the operation unit 37 recognizes that the position detected by the contact sensor on the display screen is consistent with the position of the item, and outputs a signal for realizing the function assigned to each item to the control unit 35. The operation unit 37 may be an operation unit that is displayed on the display unit 38 in an operable manner, or may be an operation unit that includes an input device such as a keyboard or a mouse.

[0053] The user can set the modulation frequency, the lower limit value and the upper limit value of the phase modulation amount, the step size of the phase modulation amount, the measurement time per phase modulation amount unit, etc. by operating the operation unit 37 .

[0054] The display unit 38 is composed of a display device such as a liquid crystal display or a CRT, and displays various display contents such as a setting screen and a measurement result related to the jitter tolerance measurement of the DUT 4 on the display screen according to the display control of the display control unit 35f described later. In addition, the display unit 38 displays operation objects such as buttons, soft keys, pull-down menus, and text boxes for setting various conditions.

[0055] The control unit 35 is composed of, for example, a microcomputer or a personal computer including a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and a HDD (Hard Disk Drive), and controls the operation of the above-mentioned units constituting the jitter tolerance measurement device 1. The control unit 35 transfers a predetermined program stored in the ROM to the RAM and executes it by the CPU, so that at least a part of the modulation control unit 35a, the error counting unit 35b, the BER calculation unit 35c, the CW classification unit 35d, the CW number counting unit 35e, and the display control unit 35f described later can be set as a software structure. Here, CW means codeword. In addition, at least a part of the modulation control unit 35a, the error counting unit 35b, the BER calculation unit 35c, the CW classification unit 35d, the CW number counting unit 35e, and the display control unit 35f can also be composed of a digital circuit such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). Alternatively, at least a part of the modulation control unit 35a, the error counting unit 35b, the BER calculation unit 35c, the CW classification unit 35d, the CW number counting unit 35e, and the display control unit 35f can also be composed of a hardware processing based on a digital circuit and a software processing based on a predetermined program as appropriate.

[0056] The modulation control unit 35a controls the modulation frequency and phase modulation amount of the modulation signal output from the modulation signal generator 22 according to the setting information from the operation unit 37. Figure 2 An example of a combination of a modulation frequency [MHz] and a lower limit value [UI] and an upper limit value [UI] of a phase modulation amount set by the modulation control unit 35a according to the user's operation input to the operation unit 37 is shown in FIG. Figure 3 The figure shows the combination of modulation frequency [MHz] and phase modulation amount [UI] specified by the jitter tolerance test of the 400GAUI-8 standard. Figure 3 Any of the five combinations of modulation frequency and phase modulation amount (case A to case E) shown above is required to avoid generating an uncorrectable codeword and to achieve a BER of 1E-5 or less.

[0057] like Figure 2As shown, the modulation control unit 35a in this embodiment can make the lower limit value [UI] of the phase modulation amount consistent with the standard value, and set the upper limit value [UI] of the phase modulation amount to a value greater than the standard phase modulation amount [UI]. Thus, the jitter tolerance measurement device 1 of this embodiment can not only test whether the DUT 4 satisfies the jitter tolerance specified in the standard, but also test the margin of the jitter tolerance of the DUT 4.

[0058] The error counting unit 35b counts the number of codeword units of FEC symbol errors detected by the data comparison unit 33 in units of phase modulation amount. In addition, one codeword (544 FEC symbols) of the PAM4 signal is composed of 272 MSB data of FEC symbols and 272 LSB data of FEC symbols. Therefore, the number of FEC symbol errors in one codeword of the PAM4 signal is the sum of the number of FEC symbol errors of the MSB data of the 272 FEC symbols and the number of FEC symbol errors of the LSB data of the 272 FEC symbols.

[0059] Furthermore, when the jitter signal input to the DUT4 is an NRZ signal, the error counting section 35b counts the number of bit errors detected by the data comparing section 33 in units of phase modulation amount. Furthermore, when the jitter signal input to the DUT4 is a PAM4 signal, the error counting section 35b counts the number of MSB errors and the number of LSB errors detected by the data comparing section 33 in units of phase modulation amount.

[0060] When the jitter signal input to the DUT4 is an NRZ signal, the BER calculation unit 35c calculates the value obtained by dividing the number of bit errors counted in units of phase modulation by the error counting unit 35b by the total number of bits of the corresponding bit string data as the BER of the measured signal. Furthermore, when the jitter signal input to the DUT4 is a PAM4 signal, the BER calculation unit 35c calculates the value obtained by dividing the sum of the number of MSB errors and the number of LSB errors counted in units of phase modulation by the error counting unit 35b by the total number of bits of the corresponding MSB data and LSB data as the BER of the measured signal.

[0061] In addition, the control unit 35 measures the BER and FEC symbol errors of the measured signal according to the measurement time input through the operation unit 37. If the measurement time ends, the modulation control unit 35a controls the change of the phase modulation amount of the modulation signal or changes both the modulation frequency and the phase modulation amount of the modulation signal based on these measurement results. For example, when no Uncorrectable Codeword is generated at the end of the measurement or the BER is lower than the reference value (1E-5, etc.), the modulation control unit 35a controls the increase of the phase modulation amount. And, when an Uncorrectable Codeword is generated, when the BER is higher than the reference value, or when the phase modulation amount has reached the upper limit value, the modulation control unit 35a controls the change of both the modulation frequency and the phase modulation amount. The user can arbitrarily set the number or ratio of Uncorrectable Codewords generated at this time and the threshold value of the BER value using the operation unit 37.

[0062] The CW classification unit 35 d classifies a plurality of code words included in the signal under test transmitted from the DUT 4 into a plurality of groups based on the number of FEC symbol errors counted by the error counting unit 35 b .

[0063] When the jitter signal input to the DUT4 is an NRZ signal, the CW classification unit 35d classifies the plurality of codewords into, for example, nine groups N0 to N7 and UCW. Groups N0, N1, N2, N3, N4, N5, N6, and N7 are groups of codewords whose FEC symbol error numbers are 0, 1, 2, 3, 4, 5, 6, and 7, respectively. Group UCW is a group of codewords whose FEC symbol error numbers are 8 or more and are uncorrectable codewords.

[0064] When the jitter signal input to the DUT4 is a PAM4 signal, the CW classification unit 35d classifies a plurality of codewords into 17 groups N0 to N15 and UCW, for example. Groups N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, and N15 are groups of codewords whose FEC symbol error numbers are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, and 15, respectively. Group UCW is a group of codewords whose FEC symbol error numbers are 16 or more and become Uncorrectable Codewords.

[0065] The CW number counting unit 35 e counts the number of code words belonging to each group classified by the CW classification unit 35 d in units of phase modulation amounts.

[0066] Figure 4 and Figure 5This is an example of a graph in which the display control unit 35f controls the display screen of the display unit 38 when the jitter signal input to the DUT4 is a PAM4 signal. The display control unit 35f controls the display screen of the display unit 38 to display a first graph in which the horizontal axis is set to the phase modulation amount and the vertical axis on the left (first vertical axis) is set to the number of code words or the ratio of the number of code words of each group counted by the CW number counting unit 35e. That is, the first graph shows the distribution of the number of FEC symbol errors in units of phase modulation amount. In this example, the modulation frequency is 40MHz, and the horizontal axis displays a range of 0.05UI to 0.18UI.

[0067] Furthermore, the display control unit 35f displays the number of code words or the ratio of the number of code words of each group counted by the CW number counting unit 35e in the first graph by color classification for each group. Furthermore, the display control unit 35f controls to display a second graph superimposed on the first graph on the display screen, the second graph having the horizontal axis as the phase modulation amount and the right vertical axis (second vertical axis) as the BER of the measured signal calculated by the BER calculation unit 35c.

[0068] The left vertical axis, the right vertical axis, and the horizontal axis can all be changed to any scale by the user operating the operation unit 37 . Figure 5 The operation of the operation unit 37 by the user Figure 4 The lower side of the vertical axis on the left side of the first graph is magnified 100,000 times.

[0069] exist Figure 4 and Figure 5 In the first graph shown, the areas indicated by N0 to N15 and UCW respectively indicate the ratio of the number of code words per phase modulation amount of groups N0 to N15 and UCW. In each phase modulation amount, the ratio of the number of code words of groups N0 to N15 and UCW is sequentially displayed along the vertical axis. Figure 4 and Figure 5 As shown in the first and second graphs, it can be seen at a glance that as the phase modulation amount increases, the BER of the measured signal deteriorates and the number of FEC symbol errors in one codeword increases.

[0070] In addition, Figure 4 and Figure 5 In the first graph shown, the left vertical axis is the ratio of the number of code words of each group counted by the CW number counting unit 35e, but the left vertical axis may be the number of code words of each group counted by the CW number counting unit 35e itself.

[0071] In the following, regarding the jitter tolerance measurement method using the jitter tolerance measurement device 1 of the present embodiment, refer to Figure 6 An example of its processing is described with reference to the flowchart of FIG.

[0072] First, the user inputs various parameters by operating the operation unit 37 (step S1). These parameters include the modulation frequency, the lower limit LL and upper limit UL of the phase modulation amount, and the step size Δpm of the phase modulation amount.

[0073] Next, the data signal output unit 21 outputs a data signal including a plurality of code words formed of a plurality of FEC symbols (data signal output step S2).

[0074] Next, the jitter signal generator 23 generates a jitter signal by performing phase modulation on the data signal outputted in the data signal output step S2 using the modulation signal of the modulation frequency and phase modulation amount LL+n×Δpm inputted in step S1, and inputs the generated jitter signal to the DUT 4 (jitter signal generation step S3). Here, n is an integer greater than 0, and its initial value is 0.

[0075] Next, the data comparison unit 33 detects a bit error and an FEC symbol error of the signal under test output from the DUT 4 in response to the input of the jitter signal (data comparison step S4).

[0076] Next, the error counting unit 35b counts the number of bit errors of the test signal detected by the data comparison step S4 and the number of codeword units of FEC symbol errors of the test signal detected by the data comparison step S4 in units of phase modulation amount LL+n×Δpm (error counting step S5).

[0077] Next, the BER calculation unit 35c calculates the BER of the test signal based on the number of bit errors counted in the error counting step S5 (BER calculation step S6).

[0078] Next, the CW classification unit 35d classifies a plurality of code words included in the test signal into a plurality of groups based on the number of FEC symbol errors counted in the error counting step S5 (CW classification step S7).

[0079] Next, the CW number counting unit 35e counts the number of code words belonging to each group classified in the CW classification step S7 in units of the phase modulation amount LL+n×Δpm (CW number counting step S8).

[0080] Next, the modulation control unit 35a increases the value of n by 1 (step S9). Steps S9 and S11 correspond to a modulation control step of performing control to change the phase modulation amount.

[0081] Next, the modulation control unit 35a determines whether the user setting conditions such as the detection of the number of uncorrectable codewords exceeding the reference value in the error counting step S5 or the calculation of the BER exceeding the reference value in the BER calculation step S6 are satisfied (step S10). If the user setting conditions are satisfied, the modulation control unit 35a executes the processing of step S12. On the other hand, if the user setting conditions are not satisfied, the modulation control unit 35a executes the processing after step S11.

[0082] Next, the modulation control unit 35a determines whether the phase modulation amount LL+n×Δpm is greater than the upper limit value UL (step S11). When the phase modulation amount LL+n×Δpm is greater than the upper limit value UL, the modulation control unit 35a performs the processing of step S12. On the other hand, when the phase modulation amount LL+n×Δpm is less than the upper limit value UL, the modulation control unit 35a performs the processing after step S3 again.

[0083] Next, the display control unit 35f controls to display a first graph whose horizontal axis is the phase modulation amount and whose first vertical axis is the number of code words or the ratio of the number of code words of each group counted in the CW number counting step S8 on the display screen of the display unit 38 (display control step S12). Furthermore, the display control unit 35f controls to display a second graph whose horizontal axis is the phase modulation amount and whose second vertical axis is the BER of the measured signal calculated in the BER calculation step S6 superimposed on the first graph on the display screen of the display unit 38 (display control step S12).

[0084] In addition, after changing the modulation frequency, the lower limit LL and upper limit UL of the phase modulation amount, and the step size Δpm of the phase modulation amount as needed in step S1, the processing of steps S1 to S12 may be repeated.

[0085] As described above, the jitter tolerance measurement device 1 according to the present embodiment classifies a plurality of codewords included in the measured signal into a plurality of groups according to the number of FEC symbol errors, and counts the number of codewords belonging to each group in units of phase modulation amounts. Thus, the jitter tolerance measurement device 1 according to the present embodiment can represent the distribution of FEC symbol errors with different jitter amounts (phase modulation amounts) in one graph, with the horizontal axis being the phase modulation amount and the first vertical axis being the number of codewords in each group or the ratio of the number of codewords.

[0086] Furthermore, the jitter tolerance measurement device 1 according to the present embodiment can superimpose and display the distribution of FEC symbol errors and the change in BER in a graph whose horizontal axis is the phase modulation amount.

[0087] Furthermore, the jitter tolerance measurement device 1 according to the present embodiment displays the distribution of FEC symbol errors by color classification for each group, and thus the distribution of FEC symbol errors can be clearly visually expressed on a graph.

[0088] Furthermore, the jitter tolerance measurement device 1 according to this embodiment can appropriately scale the first vertical axis by the user's operation of the operation unit 37 , and can therefore clearly visually represent the number of codewords with a low ratio, such as Uncorrectable Codewords, or the ratio of the number of codewords on the graph.

[0089] Explanation of symbols

[0090] 1-jitter tolerance measurement device, 2-jitter generating unit, 3-jitter tolerance measurement unit, 4-DUT, 21-data signal output unit, 22-modulation signal generator, 23-jitter signal generator, 31-signal receiving unit, 32-synchronization detection unit, 33-data comparison unit, 35-control unit, 35a-modulation control unit, 35b-error counting unit, 35c-BER calculation unit, 35d-CW classification unit, 35e-CW number counting unit, 35f-display control unit, 36-storage unit, 37-operation unit, 38-display unit.

Claims

1. A jitter tolerance measurement device, comprising: A data signal output unit (21) outputs a data signal including a plurality of code words formed by a plurality of FEC symbols; A jitter signal generator (23) performs phase modulation on the data signal to generate a jitter signal, and inputs the jitter signal to the object under test (4); A modulation control unit (35a) for controlling the phase modulation amount of the phase modulation; A data comparison unit (33) for detecting a bit error and an FEC symbol error of a signal under test output from the object under test accompanied by the input of the jitter signal; and an error counting unit (35b) for counting the number of bit errors of the measured signal detected by the data comparison unit and the number of codeword units of FEC symbol errors of the measured signal detected by the data comparison unit, wherein the jitter tolerance measurement device is characterized by comprising: A codeword classification unit (35d), wherein the error counting unit counts the number of codeword units of the FEC symbol errors in the phase modulation amount unit as the number of FEC symbol errors, and classifies a plurality of codewords included in the measured signal into a plurality of groups based on the counted number of FEC symbol errors; a codeword quantity counting section (35e) for counting the number of codewords belonging to each of the groups classified by the codeword classification section in units of the phase modulation amount; and The display control unit (35f) controls the display of a first graph on a display screen, wherein the horizontal axis of the first graph is the phase modulation amount and the first vertical axis is the number of codewords or the ratio of the number of codewords of each group counted by the codeword number counting unit.

2. The jitter tolerance measurement device according to claim 1, characterized in that: Also available: A BER calculation unit (35c) calculates a bit error rate of the measured signal based on the number of bit errors counted by the error counting unit, The display control unit controls to display a second graph on a display screen so as to be superimposed on the first graph, wherein the second graph has the phase modulation amount as a horizontal axis and the bit error rate of the measured signal calculated by the BER calculation unit as a second vertical axis.

3. The jitter tolerance measurement device according to claim 1 or 2, characterized in that: The display control unit displays the number of code words or the ratio of the number of code words for each of the groups counted by the code word number counting unit in the first graph in different colors for each group.

4. The jitter tolerance measurement device according to any one of claims 1 to 3, characterized in that: Also available: An operating unit (37) is used to change the scale of the first vertical axis of the first graph.

5. A jitter tolerance measurement method, comprising: A data signal output step (S2), outputting a data signal including a plurality of code words consisting of a plurality of FEC symbols; a jitter signal generating step (S3), performing phase modulation on the data signal to generate a jitter signal, and inputting the jitter signal into the object under test (4); a data comparison step (S4), detecting a bit error and an FEC symbol error of a signal under test output from the object under test accompanied by the input of the jitter signal; an error counting step (S5), counting the number of bit errors of the measured signal detected by the data comparison step and the number of codeword units of FEC symbol errors of the measured signal detected by the data comparison step; a codeword classification step (S7), wherein the error counting step counts the number of codeword units of the FEC symbol errors in the phase modulation amount unit as the number of FEC symbol errors, and classifies the plurality of codewords included in the measured signal into a plurality of groups according to the counted number of FEC symbol errors; a codeword number counting step (S8), counting the number of codewords belonging to each of the groups classified in the codeword classification step in units of phase modulation amount; a modulation control step (S9, S11) of controlling a phase modulation amount of the phase modulation; and The display control step (S12) controls the display of a first graph on a display screen, wherein the horizontal axis of the first graph is the phase modulation amount and the first vertical axis is the number of code words or the ratio of the number of code words of each group counted by the code word number counting step.

6. The jitter tolerance measurement method according to claim 5, characterized in that: Also includes: a BER calculation step (S6), calculating the bit error rate of the measured signal according to the number of bit errors counted by the error counting step, The display control step controls a second graph to be displayed on a display screen by overlapping the first graph, wherein the second graph has a horizontal axis representing the phase modulation amount and a second vertical axis representing the bit error rate of the measured signal calculated by the BER calculation step.

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