Printed circuit board and electronic component package comprising the same

Abstract

A printed circuit board and an electronic component package are provided. The printed circuit board includes a first insulating layer, a first cavity provided in one surface of the first insulating layer, a plurality of protrusions spaced apart from each other in the first cavity, and a first wiring layer embedded in the one surface of the first insulating layer.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2021-0042771, filed on April 1, 2021, and Korean Patent Application No. 10-2021-0115617, filed on August 31, 2021, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] This disclosure relates to a printed circuit board and an electronic component package including the printed circuit board. Background Technology

[0003] Recently, with the improvement of electronic device functionality, the number of input / output terminals for application processors (APs) and memory has been gradually increasing, leading to a continuous demand for miniaturization of packages. APs have continued to evolve in the form of systems-on-chips (SoCs), and more recently, as the functionality of electronic components has expanded to neural processing units (NPUs) and 5G modems, the size and thickness of electronic components have tended to increase. Therefore, in order to miniaturize and thinnern packages, cavity or slot methods are needed to insert electronic components such as APs into the substrate.

[0004] With the trend towards thinner and lighter electronic devices in the information technology (IT) field, including mobile phones, there has been a need for technologies to thin the packages of electronic components, including APs and integrated circuits (ICs), in order to meet the technological requirements of thinner and lighter electronic devices. Recently, technologies related to printed circuit boards with various structures connected to electronic components and packages on which electronic components are mounted have been developed. Summary of the Invention

[0005] One aspect of this disclosure provides a printed circuit board and an electronic component package including the printed circuit board, the printed circuit board being advantageous for reducing overall thickness and miniaturizing the product.

[0006] According to one aspect of this disclosure, a printed circuit board may include: a first insulating layer; a first cavity disposed in a surface of the first insulating layer; a plurality of protrusions spaced apart from each other in the first cavity; and a first wiring layer embedded in the one surface of the first insulating layer.

[0007] According to another aspect of this disclosure, an electronic component package may include: a first printed circuit board including an insulating layer, a first cavity disposed in a surface of the insulating layer, and a plurality of protrusions spaced apart from each other in the first cavity; a second printed circuit board disposed on one side of the first printed circuit board and having a surface thereon on which the first printed circuit board is mounted; and an electronic component mounted on said one surface of the second printed circuit board. The said one surface of the insulating layer of the first printed circuit board is in contact with the electronic component. Attached Figure Description

[0008] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is a schematic block diagram illustrating an example of an electronic device system;

[0010] Figure 2 This is a schematic perspective view showing an example of an electronic device;

[0011] Figure 3 This is a schematic cross-sectional view showing an example of a printed circuit board;

[0012] Figure 4 It is shown Figure 3 A schematic plan view of one surface of a printed circuit board;

[0013] Figure 5 This is a schematic cross-sectional view showing another example of a printed circuit board;

[0014] Figure 6 This is a schematic cross-sectional view showing another example of a printed circuit board;

[0015] Figure 7 This is a schematic cross-sectional view showing another example of a printed circuit board;

[0016] Figure 8 This is a schematic cross-sectional view showing another example of a printed circuit board;

[0017] Figures 9 to 14 It shows the manufacturing process. Figure 3 A schematic cross-sectional view illustrating an example of the manufacturing process of a printed circuit board;

[0018] Figure 15 This is a schematic cross-sectional view showing an example of an electronic component package;

[0019] Figure 16 This is a schematic cross-sectional view showing another example of an electronic component package;

[0020] Figure 17This is a schematic cross-sectional view showing another example of an electronic component package;

[0021] Figure 18 This is a schematic cross-sectional view showing another example of an electronic component package; and

[0022] Figure 19 This is a cross-sectional view schematically illustrating another example of an electronic component package. Detailed Implementation

[0023] In the following description, exemplary embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. In the drawings, the shape, size, etc., of the components may be exaggerated or reduced for clarity.

[0024] For convenience, terms such as side and side surface are used to refer to surfaces in the left / right direction or in the left / right direction in the drawings; terms such as upper side, upper part, and upper surface are used to refer to surfaces in the upward direction or in the upward direction in the drawings; and terms such as lower side, lower part, and lower surface are used to refer to surfaces in the downward direction or in the downward direction in the drawings. Furthermore, "located on the side, upper side, above, lower side, or below" conceptually includes cases where the target component is located in the corresponding direction but not in direct contact with the reference component, and cases where the target component is in direct contact with the reference component in the corresponding direction. However, these directions are defined for ease of explanation, and the claims are not specifically limited by the directions defined as described above, and the concepts of upper and lower are interchangeable at any time.

[0025] In this specification, the term "connection" between one component and another conceptually includes both indirect connections between the two components via an adhesive layer and direct connections between the two components. Additionally, "electrical connection" conceptually includes both physical connections and physical disconnections. It is understood that when an element is referred to using terms such as "first" and "second," the element is not thereby limited. They may be used only for the purpose of distinguishing that element from other elements and do not limit the order or importance of the elements. In some cases, without departing from the scope of the claims set forth herein, a first element may be referred to as a second element. Similarly, a second element may be referred to as a first element.

[0026] The term "exemplary embodiment" as used herein does not refer to the same exemplary embodiment, but is provided to emphasize a particular feature or characteristic that differs from that of another exemplary embodiment. However, the exemplary embodiments provided herein are to be understood as being implementable by combining all or part of each other. For example, unless a contrary or contradictory description is provided herein, an element described in a particular exemplary embodiment may be understood to be relevant to another exemplary embodiment even if it is not described in another exemplary embodiment.

[0027] The terminology used herein is for describing exemplary embodiments only and is not intended to limit this disclosure. In this context, the singular form includes the plural form unless the context otherwise indicates.

[0028] Figure 1 This is a schematic block diagram illustrating an example of an electronic device system.

[0029] Reference Figure 1 The electronic device 1000 may house a motherboard 1010. The motherboard 1010 may be physically or electrically connected to chip-related components 1020, network-related components 1030, other components 1040, etc. These components may be connected to other electronic components described below via various signal lines 1090.

[0030] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processing units (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, these chip-related components 1020 are not limited to these, but may also include other types of chip-related components. Furthermore, these chip-related components 1020 can be combined with each other. These chip-related components 1020 may have a package form including the aforementioned chips.

[0031] Network-related components 1030 may include components compatible with or operating according to protocols such as: Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM+, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, and 5G protocols, as well as any other wireless and wired protocols specified after the protocols listed above. However, network-related components 1030 are not limited to this, but may also include components compatible with various other wireless standards or protocols or wired standards or protocols, or components that operate according to various other wireless standards or protocols or wired standards or protocols. Furthermore, these network-related components 1030 may be combined with chip-related components 1020 and configured as a package.

[0032] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, these other components 1040 are not limited to these, but may also include passive components of the chip component type for various other purposes. Furthermore, these other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030 and configured as a package.

[0033] Depending on the type of electronic device 1000, it may include other electronic components that are physically or electrically connected to the motherboard 1010 or not physically or electrically connected to the motherboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. These other electronic components are not limited and may be audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage units (e.g., hard disk drives), optical disc (CD) drives, digital versatile optical disc (DVD) drives, etc. These other electronic components may also include other electronic components for various purposes, depending on the type of electronic device 1000.

[0034] Electronic device 1000 can be a smartphone, personal digital assistant (PDA), digital video camera, digital camera, network system, computer, monitor, tablet PC, laptop PC, netbook PC, television, video game console, smartwatch, automotive component, etc. However, electronic device 1000 is not limited to these, and can be any other electronic device that processes data.

[0035] Figure 2 This is a schematic perspective view showing an example of an electronic device.

[0036] Reference Figure 2 The electronic device can be, for example, a smartphone 1100. A motherboard 1110 can be housed in the smartphone 1100, and various electronic components 1120 can be physically or electrically connected to the motherboard 1110. Additionally, a camera module 1130 and / or a speaker 1140 can be housed in the smartphone 1100. Some of the electronic components 1120 can be chip-related components, such as a printed circuit board 1121, but are not limited thereto. The printed circuit board 1121 can have electronic components embedded in a multilayer printed circuit board, but is not limited thereto. Furthermore, the electronic device is not limited to the smartphone 1100, but can be other electronic devices as described above.

[0037] Figure 3 This is a schematic cross-sectional view showing an example of a printed circuit board.

[0038] Reference Figure 3 According to an exemplary embodiment, the printed circuit board 100A may include: a first insulating layer 111, in which a first cavity C1 is formed; a plurality of protrusions P formed in the first cavity C1; a first wiring layer 121 embedded in one surface of the first insulating layer 111; a second wiring layer 122 disposed on another surface of the first insulating layer 111; a first via layer 131 penetrating at least a portion of the first insulating layer 111 and electrically connecting the first wiring layer 121 and the second wiring layer 122 to each other; a second insulating layer 112 disposed on another surface of the first insulating layer 111 to cover at least a portion of the second wiring layer 122; a third wiring layer 123 disposed on the second insulating layer 112; a second via layer 132 penetrating at least a portion of the second insulating layer 112 and electrically connecting the second wiring layer 122 and the third wiring layer 123 to each other; and a first passivation layer 141 and a second passivation layer 142 disposed on one surface of the first insulating layer 111 and the other surface of the second insulating layer 112, respectively. Here, one surface of the first insulating layer 111 may be opposite to the other surface of the first insulating layer 111, and the other surface of the second insulating layer 112 may be opposite to one surface of the second insulating layer 112.

[0039] For example, the printed circuit board 100A according to an exemplary embodiment may be an interposer substrate that will later be connected to an electronic component. The printed circuit board 100A according to an exemplary embodiment may be manufactured such that a first cavity C1 is formed in one surface of a first insulating layer 111, and a plurality of protrusions P are disposed in the first cavity C1. In this case, when the printed circuit board 100A is later bonded to the electronic component, the electronic component can be more easily installed, and the printed circuit board 100A can be stably bonded to the electronic component without damaging it.

[0040] Furthermore, the first cavity C1 and the plurality of protrusions P of the printed circuit board 100A according to the exemplary embodiment can facilitate the bonding between the electronic components and the printed circuit board 100A (as described above), and an encapsulant can be filled in the first cavity C1 to maintain a stable bonding structure. In this case, as in the manufacturing process (described later), the first cavity C1 and the plurality of protrusions P can be formed by plating and removing the second region M2 of the metal layer M. Therefore, a separate process is not required, and the first cavity C1 and the plurality of protrusions P can be formed in the process of manufacturing the first wiring layer 121, thus simplifying the process and reducing manufacturing costs.

[0041] Additionally, in the manufacturing process (described later), the first cavity C1 and the plurality of protrusions P of the printed circuit board 100A according to the exemplary embodiment can be formed by plating and removing the metal layer M in a second region M2. High roughness can be formed by roughening the surface of the second region M2, and high roughness can also be formed on the inner wall of the first cavity C1 formed by removing the metal layer M in the second region M2.

[0042] Additionally, as in the manufacturing process (described later), the first wiring layer 121 of the printed circuit board 100A according to an exemplary embodiment can be formed by plating a first region M1 of the metal layer M. During the manufacturing process, a high roughness can be formed on the surface of the first region M1 by roughening; therefore, the first wiring layer 121 can include surfaces with different roughnesses. Specifically, the roughness of the surface of the first wiring layer 121 in contact with the first insulating layer 111 can be relatively higher than the roughness of the surface of the first wiring layer 121 exposed from the first insulating layer 111.

[0043] The components of the printed circuit board 100A according to an exemplary embodiment will be described in more detail below with reference to the accompanying drawings.

[0044] The insulating layer 110 may include a first insulating layer 111 and a second insulating layer 112. The insulating layer 110 may also improve the rigidity of the printed circuit board 100A depending on the specific material. A first cavity C1 may be formed in one surface of the insulating layer 110, and a plurality of protrusions P may be formed in the first cavity C1. The first cavity C1 may be a space with all four sides blocked, but if necessary, discontinuous portions, such as outwardly open portions, may exist in certain areas of the first cavity C1. Multiple first cavities C1 may be present if desired. The plurality of protrusions P formed in the first cavity C1 may be arranged to be spaced apart from each other. An encapsulant 400 (described later) may fill the first cavity C1. That is, the encapsulant 400 (described later) may be disposed between the plurality of protrusions P in the first cavity C1.

[0045] The material of insulating layer 110 can be an insulating material, such as a thermosetting resin (e.g., epoxy resin) or a thermoplastic resin (e.g., polyimide). Optionally, the material of insulating layer 110 can be a material that includes inorganic fillers (e.g., silica) and reinforcing materials (e.g., glass fiber) in the thermosetting or thermoplastic resin. For example, the material of insulating layer 110 can be a prepreg, but is not limited to this, and the material of insulating layer 110 can be a material that does not include reinforcing materials (e.g., glass fiber), such as Ajinomoto laminate (ABF). If desired, the material of insulating layer 110 can be a photosensitive insulating material (e.g., photosensitive dielectric (PID)). See reference. Figure 3 The insulating layer 110 is currently shown to include a first insulating layer 111 and a second insulating layer 112, but the insulating layer 110 may also include a first insulating layer 111 and a second insulating layer 112. Figure 3 The number of layers shown indicates whether there are many or few layers.

[0046] Figure 4 It is shown Figure 3 A schematic plan view of one surface of a printed circuit board.

[0047] Multiple protrusions P may be formed and spaced apart from each other in the first cavity C1. Multiple protrusions P may be formed on the lower surface of the first cavity C1 and may protrude from the lower surface of the first cavity C1 toward the interior of the first cavity C1. The height of the multiple protrusions P may be substantially the same as the height of the first cavity C1. Therefore, one end of the multiple protrusions P and one surface of the first insulating layer 111 may be coplanar with each other. The multiple protrusions P can be used to support components, such as electronic components, that will later be disposed in the first cavity C1 or on one surface of the first insulating layer 111. That is, since the multiple protrusions P are configured to protrude from the lower surface of the first cavity C1, when an electronic component (described later) is disposed on one surface of the first insulating layer 111, the electronic component may be spaced apart from the lower surface of the first cavity C1 by the height of the protrusions P, and the encapsulant 400 may fill the spaced apart between the electronic component and the lower surface of the first cavity C1 to ensure the adhesion of the electronic component. Since the process can be further simplified by only requiring the printed circuit board to be placed on the electronic component until the electronic component contacts the multiple protrusions P, without the need for processes such as distance measurement and device setup for spacing the electronic component and the lower surface of the first cavity C1 from each other. Here, the lower surface of the first cavity C1 may refer to the bottom surface of the first cavity C1, and the lower surface of the second cavity C2 (described later) may refer to the bottom surface of the second cavity C2.

[0048] The first cavity C1 and the plurality of protrusions P can be formed by removing the second region M2 of the metal layer M (described later) instead of by laser processing or machining. Therefore, a high roughness can be formed during the manufacturing process (described later) by roughening the inner wall and lower surface of the first cavity C1 and the surfaces of the plurality of protrusions P. For example, the inner wall and lower surface of the first cavity C1 and the surfaces of the plurality of protrusions P can have a higher roughness than the surface of the first wiring layer 121 exposed from one surface of the first insulating layer 111. Due to the high roughness formed on the inner wall and lower surface of the first cavity C1, the adhesion between the encapsulant 400 (described later) and the first cavity C1 can be improved when the encapsulant 400 is disposed in the first cavity C1.

[0049] The plurality of wiring layers 120 may include a first wiring layer 121, a second wiring layer 122 and a third wiring layer 123. The plurality of wiring layers 120 may be configured to transmit signals of the printed circuit board 100A and may be disposed on or between insulating layers 110.

[0050] The first wiring layer 121 may be embedded in one surface of the first insulating layer 111, and at least a portion of the first wiring layer 121 may be exposed outward from the first insulating layer 111. Some surfaces of the first wiring layer 121 may have a slightly higher roughness by performing roughening on the surface during the manufacturing process (described later). For example, the roughness of the surface of the first wiring layer 121 in contact with the first insulating layer 111 may be higher than the roughness of the surface of the first wiring layer 121 exposed outward from the first insulating layer 111. As described above, the high roughness of the surface of the first wiring layer 121 in contact with the first insulating layer 111 can improve the adhesion between the first wiring layer 121 and the first insulating layer 111. (Refer to...) Figure 3 The first wiring layer 121 may be exposed outward from one surface of the first insulating layer 111, and due to the characteristics of the etching process, the first wiring layer 121 may have a structure in which the exposed surface of the first wiring layer 121 is recessed into the interior of the printed circuit board 100A by a predetermined distance compared to one surface of the first insulating layer 111. Although not shown, a surface treatment layer including at least one of nickel (Ni) and gold (Au) or an organic film formed by a surface treatment such as organic solderability protection (OSP) may be provided on the surface of the first wiring layer 121 exposed from one surface of the first insulating layer 111 to protect the surface of the first wiring layer 121 from oxidation.

[0051] The second wiring layer 122 may be disposed on the other surface of the first insulating layer 111, and may have a structure in which the second wiring layer 122 is embedded in the second insulating layer 112 from one surface of the second insulating layer 112. The third wiring layer 123 may be disposed on the other surface of the second insulating layer 112.

[0052] The material of each of the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123 can be a metallic material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first wiring layer 121, the second wiring layer 122, and the third wiring layer 123 can perform various functions according to their design. For example, the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123 may include ground patterns, power patterns, signal patterns, etc. These patterns may be in the form of lines, surfaces, or pads, respectively. The first wiring layer 121 can be formed by a plating process such as additive process (AP), semi-additive process (SAP), modified semi-additive process (MSAP), or via sealing (TT), and may therefore include a seed layer as an electroless plating layer and an electroplated layer formed based on the seed layer. When the insulating layer 110 is provided in the form of resin-coated copper (RCC), each of the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123 may also include a metal foil (such as copper foil), and if desired, a primer resin may be present on the surface of the metal foil. The wiring layer exposed from the outermost of the plurality of wiring layers 120 can be used as connection pads for connection with other substrates or components. For example, from Figure 3 The outermost exposed first wiring layer 121 and third wiring layer 123 of the printed circuit board 100A can be connected to electrical connection metal (described later) to serve as connection pads.

[0053] Reference Figure 3 Currently, only the first routing layer 121, the second routing layer 122, and the third routing layer 123 are shown, but they can also be configured to be more complex. Figure 3 The diagram shows either more or fewer wiring layers.

[0054] The plurality of via layers 130 may include a first via layer 131 and a second via layer 132. The plurality of via layers 130 may include: a first via layer 131, penetrating a first insulating layer 111 and electrically connecting a first wiring layer 121 and a second wiring layer 122 to each other; and a second via layer 132, penetrating a second insulating layer 112 and electrically connecting a second wiring layer 122 and a third wiring layer 123 to each other. The material of each via layer in the first via layer 131 and the second via layer 132 may be a metallic material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Depending on their design, the first via layer 131 and the second via layer 132 may include signal vias, ground vias, power vias, etc. Each via in the first via layer 131 and the second via layer 132 may be formed by completely filling each via with a metallic material, or by forming a metallic material along the wall of each via. Each via in the first via layer 131 and the second via layer 132 may also be formed by a process such as AP, SAP, MSAP, or TT, and may include a seed layer as an electroless layer and an electroplated layer formed based on the seed layer. Each via in the first via layer 131 and the second via layer 132 may have a tapered shape in which the width of its upper surface is greater than the width of its lower surface.

[0055] In addition, Figure 3 Only the first via layer 131 and the second via layer 132 are shown, but more or fewer via layers may be provided if needed.

[0056] The first passivation layer 141 and the second passivation layer 142 protect internal components from external physical or chemical damage. The first passivation layer 141 and the second passivation layer 142 may each have a plurality of first openings and a plurality of second openings. Each of the plurality of first openings exposes at least a portion of the first wiring layer 121 and at least a portion of the first insulating layer 111. Each of the plurality of second openings exposes at least a portion of the third wiring layer 123. The materials of the first passivation layer 141 and the second passivation layer 142 may be insulating materials, such as thermosetting resins (e.g., epoxy resins), thermoplastic resins (e.g., polyimide), or mixtures of thermosetting and thermoplastic resins with inorganic fillers (e.g., ABF), but are not limited thereto.

[0057] Figure 5 This is a schematic cross-sectional view showing another example of a printed circuit board.

[0058] according to Figure 5The printed circuit board 100B shown in another exemplary embodiment differs from the printed circuit board 100A according to the exemplary embodiment described above in that a fourth wiring layer 124 is disposed on the first insulating layer 111 and the first wiring layer 121. In this case, the fourth wiring layer 124 may be disposed on the exposed surface of the first wiring layer 121, and the first wiring layer 121 may be covered by the first insulating layer 111 and the fourth wiring layer 124.

[0059] Additionally, at least a portion of the fourth wiring layer 124 may be exposed through a first opening in the first passivation layer 141. The fourth wiring layer 124 exposed through the first opening may be used as a connection pad.

[0060] The fourth wiring layer 124 may include a metallic material used as the material for each of the first wiring layers 121, the second wiring layer 122, and the third wiring layer 123, and may be fabricated using processes such as AP, SAP, MSAP, or TT. The fourth wiring layer 124 may contact the first wiring layer 121, and the width of the fourth wiring layer 124 may be greater than the width of the first wiring layer 121. That is, when viewed from the stacking direction of the printed circuit board 100B, the fourth wiring layer 124 may be configured such that its cross-section includes the cross-section of the first wiring layer 121. Therefore, the connection pads can have a larger area, making electrical connections to other components easier.

[0061] In addition, as described above, a high roughness can be formed on the surface of the first wiring layer 121 that contacts the first insulating layer 111 by roughening. Therefore, the roughness of the surface of the first wiring layer 121 that contacts the first insulating layer 111 can be higher than the roughness of the surface of the first wiring layer 121 that contacts the fourth wiring layer 124.

[0062] The description of other configurations is repeated above in the description of other configurations in the printed circuit board 100A according to the exemplary embodiments, and therefore is omitted.

[0063] Figure 6 This is a schematic cross-sectional view showing another example of a printed circuit board.

[0064] Figure 7 This is a schematic cross-sectional view showing another example of a printed circuit board.

[0065] according to Figure 6 and Figure 7 The printed circuit boards 100C and 100D of the other exemplary embodiments shown differ from the printed circuit boards 100A and 100B according to the above exemplary embodiments and another exemplary embodiment in that the second cavity C2 is additionally formed in one surface of the first insulating layer 111. In this case, the first cavity C1 may be formed on the lower surface of the second cavity C2.

[0066] exist Figure 6 In the printed circuit board 100C of another exemplary embodiment shown, the second cavity C2 can be manufactured by a process described later, and specifically, the second cavity C2 can be formed by removing the second region M2 of the metal layer M instead of laser processing or machining, so that the roughness on the surface formed on the second region M2 can be maintained as is on the lower surface and inner wall of the second cavity C2. The lower surface and inner wall of the second cavity C2 can maintain the high roughness as described above, thereby ensuring high adhesion of components (such as encapsulant 400) that later come into contact with the lower surface and inner wall of the second cavity C2.

[0067] A first cavity C1 may be formed on the lower surface of a second cavity C2, and as described above, a plurality of protrusions P may be formed spaced apart from each other in the first cavity C1. Similar to the lower surface and inner wall of the second cavity C2, the lower surface and inner wall of the first cavity C1 and the surfaces of the plurality of protrusions P may also maintain a high roughness.

[0068] Reference Figure 7 The present invention discloses a printed circuit board 100D having a second cavity C2 and the aforementioned fourth wiring layer 124, according to another exemplary embodiment.

[0069] The description of other configurations is repeated above in the description of other configurations in the printed circuit board 100A according to the exemplary embodiments, and therefore is omitted.

[0070] Figure 8 This is a schematic cross-sectional view showing another example of a printed circuit board.

[0071] according to Figure 8 The printed circuit board 100E shown in another exemplary embodiment differs from the printed circuit board 100D according to the other exemplary embodiment described above in that the groove R is additionally formed on the side surface of the second cavity C2.

[0072] The groove R can be formed on the side surface of the second cavity C2. Similar to the first cavity C1 and the second cavity C2 described above, the groove R can also be formed by removing the second region M2 of the metal layer M, and thus a high roughness can be formed on the lower surface and inner wall of the groove R, so as to ensure adhesion to the encapsulant 400.

[0073] Additionally, the groove R can be formed on the side surface of the second cavity C2, thus the side surface of the second cavity C2 can have steps. Since the second cavity C2 has steps as described above, the bonding area with components (e.g., encapsulant 400) later disposed in the second cavity C2 can be increased, and the adhesion between the second cavity C2 and the components inside the second cavity C2 can be improved due to the anchoring effect of the step structure.

[0074] Figures 9 to 14It shows the manufacturing process. Figure 3 A schematic cross-sectional view of an example of the process of a printed circuit board.

[0075] Reference Figure 9 A carrier 700 can be prepared. The carrier 700 may include a core 710, a first copper foil 711, and a second copper foil 712.

[0076] Reference Figure 10 A metal layer M can be disposed on the second copper foil 712, and the metal layer M can be patterned and divided into a first region M1 and a second region M2. In this case, the first region M1 can have the shape of a wiring layer surrounding the second region M2.

[0077] Subsequently, a high roughness can be formed on the surface of the patterned metal layer M by roughening (such as black oxidation treatment). In this case, a high roughness can be formed on the surface of the second copper foil 712 exposed by the patterning of the metal layer M and on the roughened surfaces of the first region M1 and the second region M2.

[0078] Reference Figure 11 and Figure 12 A first insulating layer 111 can be stacked on the metal layer M, and a second wiring layer 122 and a first via layer 131 can be provided. Subsequently, a second insulating layer 112 covering the second wiring layer 122 can be stacked, and a third wiring layer 123 and a second via layer 132 can be provided.

[0079] Reference Figure 13 This allows the first copper foil 711 and the second copper foil 712 to be separated from each other, making it possible to remove a portion of the carrier 700.

[0080] Subsequently, the exposed second copper foil 712 can be etched and removed first. The second copper foil 712 is etched so that the first wiring layer 121 can be completed. In this case, due to the effect of the etching process of the second copper foil 712, the lower surface of the first wiring layer 121 can also be slightly removed, so that the first wiring layer 121 can have a structure in which the lower surface of the first wiring layer 121 is recessed by a predetermined distance compared to one surface of the first insulating layer 111.

[0081] Next, as Figure 14As shown, a mask (not shown) can be placed on the first wiring layer 121, and then the second region M2 of the metal layer M can be etched and removed. Thereafter, the mask can be separated, and by removing the second region M2, a first cavity C1 can be formed in one surface of the first insulating layer 111, and a plurality of protrusions P protruding from the lower surface of the first cavity C1 can be formed. As can be seen from the above process, the plurality of protrusions P can be formed using a portion of the first insulating layer 111, thereby eliminating the need to separately provide materials and processes for setting the plurality of protrusions P, thus reducing costs and improving efficiency. The same surface roughness as the second region M2 of the metal layer M can be formed on the inner wall and lower surface of the first cavity C1 and on the surfaces of the plurality of protrusions P.

[0082] Subsequently, it can be manufactured by setting the first passivation layer 141 and the second passivation layer 142. Figure 3 Printed circuit boards.

[0083] Figure 15 This is a schematic cross-sectional view showing an example of an electronic component package.

[0084] according to Figure 15 The electronic component package 600A of the exemplary embodiments shown may include the printed circuit board 100A according to the exemplary embodiments described above. In the following description of the electronic component package 600A, the first printed circuit board 100A refers to the printed circuit board 100A according to the exemplary embodiments described above.

[0085] The description of the first printed circuit board 100A may be repeated with the description of the printed circuit board 100A according to the exemplary embodiment described above.

[0086] according to Figure 15 The electronic component package 600A of the exemplary embodiment shown may include: a first printed circuit board 100A; a second printed circuit board 200 connected to the first printed circuit board 100A; an electronic component 300 mounted on the second printed circuit board 200; a first electrical connection metal 510 electrically connecting the second printed circuit board 200 and the electronic component 300 to each other; a second electrical connection metal 520 electrically connecting the first printed circuit board 100A and the second printed circuit board 200 to each other; a plurality of protrusions P disposed in a first cavity C1; and an encapsulant 400 disposed between the first printed circuit board 100A and the second printed circuit board 200 to fill the first cavity C1 and cover at least a portion of the electronic component 300.

[0087] The second printed circuit board 200 may be a printed circuit board on which electronic components 300 are mounted, and may include a stacked insulating layer 210, a stacked wiring layer 220, a stacked via layer 230 and a third passivation layer 240.

[0088] Stacked wiring layer 220 may be disposed outside or inside stacked insulating layer 210, and stacked via layer 230 may penetrate at least a portion of stacked insulating layer 210 and electrically connect stacked wiring layers 220 disposed on different layers to each other. Third passivation layer 240 is disposed on the outer layer of stacked insulating layer 210 and may have an opening that exposes a portion of stacked wiring layer 220.

[0089] The material of the stacked insulating layer 210 can be an insulating material, such as a thermosetting resin (e.g., epoxy resin) or a thermoplastic resin (e.g., polyimide). Optionally, the material of the stacked insulating layer 210 can be a material containing inorganic fillers (e.g., silica), reinforcing materials (e.g., glass fiber), etc., in thermosetting and thermoplastic resins. For example, the material of the stacked insulating layer 210 can be a prepreg, but is not limited thereto, and the material of the stacked insulating layer 210 can be a material that does not include reinforcing materials (e.g., glass fiber), such as ABF. If desired, the material of the stacked insulating layer 210 can be a photosensitive insulating material (e.g., PID). The stacked insulating layer 210 may include a ratio of... Figure 15 The number of layers shown may be more or less.

[0090] The material of each wiring layer in stacked wiring layer 220 can be a metallic material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Stacked wiring layers 220 can perform various functions depending on their design. For example, stacked wiring layers 220 may include ground patterns, power patterns, signal patterns, etc. These patterns may be in the form of lines, surfaces, or pads, respectively. Each wiring layer in stacked wiring layer 220 can also be formed by plating processes such as AP, SAP, MSAP, TT, etc., and may therefore include a seed layer as an electroless plating layer and an electroplated layer formed based on the seed layer. When the stacked insulating layer 210 is provided in the form of RCC, stacked wiring layer 220 may also include a metal foil (such as copper foil), and if desired, a primer resin may be present on the surface of the metal foil. The wiring layers exposed from the outermost layer in stacked wiring layer 220 can be used as connection pads for connection with other substrates or components. For example, from Figure 15 The outermost exposed stacked wiring layer 220 of the second printed circuit board 200 can be connected to the first electrical connection metal 510 and the second electrical connection metal 520 (described later) to serve as connection pads.

[0091] Stacked wiring layer 220 may include more than Figure 15 The number of layers shown may be more or less.

[0092] The material of each via in the stacked via layer 230 can be a metallic material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Depending on their design, the stacked via layer 230 may include signal vias, ground vias, power vias, etc. Each via in the stacked via layer 230 can be formed by completely filling each via with a metallic material, or by forming a metallic material along the wall of each via. Each via in the stacked via layer 230 can also be formed using processes such as AP, SAP, MSAP, TT, etc., and may include a seed layer as an electroless plating layer and an electroplated layer formed based on the seed layer. Each via in the stacked via layer 230 may also have a tapered shape where the width of its upper surface is greater than the width of its lower surface.

[0093] If necessary, the via layer 230 may include a ratio of Figure 15 The number of layers shown may be more or less.

[0094] Electronic component 300 may be an integrated circuit (IC) die provided with hundreds to millions or more components integrated on a single chip. Electronic component 300 may be, for example, a processor chip (such as a central processing unit (e.g., CPU), graphics processing unit (e.g., GPU), field-programmable gate array (FPGA), digital signal processor, cryptographic processor, microprocessor, or microcontroller), and more specifically, an application processor (AP), but is not limited thereto. Additionally, electronic component 300 may be a memory chip (such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM)) or flash memory, or may be a logic chip (such as an analog-to-digital converter or an application-specific integrated circuit (ASIC)). If desired, electronic component 300 may be a surface-mount passive component, such as a surface-mount capacitor such as a multilayer ceramic capacitor (MLCC) or a surface-mount inductor such as a power inductor (PI). Electronic component 300 may be configured such that the surface of electronic component 300 having connection pads (not shown) faces downwards, and the opposite surface faces upwards. The bonding pads of the electronic component 300 may include a metallic material (such as copper (Cu) or aluminum (Al)) and may be connected to the first electrical connection metal 510. The electronic component 300 may be covered by the encapsulant 400 without a separate adhesive film, so that the back surface and side surface of the electronic component 300 may be in physical contact with the encapsulant 400.

[0095] In the electronic component package 600A according to an exemplary embodiment, the electronic component 300 may contact one surface of the first insulating layer 111 of the first printed circuit board 100A. At least a portion of the first insulating layer 111 may be exposed from the first passivation layer 141 through a first opening, and the electronic component 300 may be configured to contact the exposed surface of the first insulating layer 111. Additionally, a first cavity C1 may be formed in the region where the electronic component 300 and the first insulating layer 111 are in contact with each other. Because the first insulating layer 111 and the electronic component 300 are in contact with each other as described above, when the first printed circuit board 100A is stacked on the second printed circuit board 200, separate distance measurement or fine control processes are not required.

[0096] Specifically, in the prior art, when electronic components are placed in a separate housing space or cavity, a predetermined interval distance needs to be ensured between the electronic components and the housing space to ensure the space for encapsulant to be placed between the electronic components and the housing space. A fine substrate mounting process is required to ensure such an interval distance. Therefore, defects (damage to the electronic components) may occur when fixing the electronic components due to substrate distance adjustment failures, etc.

[0097] On the other hand, in the electronic component package 600A according to an exemplary embodiment, a first cavity C1 can be pre-formed in one surface of the first insulating layer 111, and a plurality of protrusions P protruding from the lower surface of the first cavity C1 can be pre-formed. These protrusions P allow the electronic component 300 to be spaced apart from the lower surface of the first cavity C1 by a predetermined distance, ensuring sufficient space for the encapsulant 400 to be filled. Therefore, even if the first insulating layer 111 and the electronic component 300 are in contact with each other, the encapsulant 400 can still fill the first cavity C1. That is, the encapsulant 400 can fill the space between the plurality of protrusions P or the space between the plurality of protrusions P and the inner wall of the first cavity C1. Therefore, it is not necessary to ensure the spacing between the electronic component 300 and the first insulating layer 111, thereby eliminating the need for devices and processes for measuring the spacing and maintaining the spacing, simplifying the process and reducing manufacturing costs.

[0098] Additionally, when the first printed circuit board 100A is stacked on the electronic component 300, the plurality of protrusions P can be used as supports between the electronic component 300 and the first printed circuit board 100A, and thus can contact the upper surface of the electronic component 300.

[0099] Encapsulant 400 may be disposed on one surface of the first insulating layer 111 and may cover at least a portion of one surface of the first insulating layer 111, at least a portion of the upper surface of the second printed circuit board 200, and at least a portion of the outer surface of the electronic component 300. Additionally, encapsulant 400 may fill at least a portion of the first cavity C1 and thus cover at least a portion of the upper surface of the electronic component 300. For example, encapsulant 400 may be in physical contact with at least a portion of each of the upper, lower, and side surfaces of the electronic component 300. Encapsulant 400 may be fluid in stage B (referring to the stage before curing), thus flowing along the outer surface of the electronic component 300 and the surface of the first insulating layer 111. In this case, since the first cavity C1 is formed in the first insulating layer 111, encapsulant 400 may fill the interior of the first cavity C1, thus ensuring adhesion between the electronic component 300 and the first insulating layer 111 of the first printed circuit board 100A. The encapsulant 400 can fill the first cavity C1 and contact at least a portion of the upper surface of the electronic component 300, so that the electronic component 300 can be more stably fixed.

[0100] Furthermore, as described above, by roughening one surface of the first insulating layer 111, the inner wall and lower surface of the first cavity C1, and the surfaces of the plurality of protrusions P to form a high roughness, sufficient adhesion between the encapsulant 400 and the first insulating layer 111 can be ensured, and thus a more stable package structure can be achieved. The roughness of the surface of the first wiring layer 121 that contacts the first insulating layer 111 can be greater than the roughness of the surface of the first wiring layer 121 that contacts the second electrical connection metal 520, thus improving the adhesion between the first printed circuit board 100A and the second printed circuit board 200 while ensuring electrical connection between them.

[0101] The encapsulant 400 can be made of an insulating material, such as a thermosetting resin (e.g., epoxy resin) or a thermoplastic resin (e.g., polyimide). Optionally, the encapsulant 400 can be made of a material containing inorganic fillers (e.g., silica) in both thermosetting and thermoplastic resins. For example, the encapsulant 400 can be made of ABF (Alternating Acid Plastic). ABF can be provided in the form of resin-coated copper (RCC), but is not limited thereto. If desired, the encapsulant 400 can be made of a photosensitive material (e.g., PID). The encapsulant 400 can be made of known epoxy molding compounds (EMC), but is not limited thereto.

[0102] The first electrical connection metal 510 and the second electrical connection metal 520 may be disposed in at least some openings of the third passivation layer 240. The first electrical connection metal 510 and the second electrical connection metal 520 may physically connect and / or electrically connect the second printed circuit board 200 to the outside. For example, the first electrical connection metal 510 may electrically connect the exposed stacked wiring layer 220 and the electronic component 300 to each other, and the second electrical connection metal 520 may electrically connect the exposed stacked wiring layer 220 and the first wiring layer 121 to each other. Each electrical connection metal in the first electrical connection metal 510 and the second electrical connection metal 520 may be formed using tin (Sn) or a tin-containing alloy (e.g., solder), but is not limited thereto. Each electrical connection metal in the first electrical connection metal 510 and the second electrical connection metal 520 may be a pad, a solder ball, a pin, or a pillar-shaped metal pillar.

[0103] In the electronic component package 600A according to an exemplary embodiment, the volume of the second electrical connection metal 520 may be larger than the volume of the first electrical connection metal 510. Furthermore, since the electronic component 300 is in contact with one surface of the first insulating layer 111, the thickness of the second electrical connection metal 520 in the stacking direction of the electronic component package 600A may be substantially the same as the sum of the thicknesses of the electronic component 300 and the first electrical connection metal 510 in that stacking direction.

[0104] Here, the phrase "substantially the same" does not mean that the thicknesses are exactly the same numerically, but rather comprehensively includes the meaning of equal thicknesses, including errors in the manufacturing process.

[0105] In the description of the electronic component package 600A, the description of the printed circuit board 100A is repeated in the description of the first printed circuit board 100A according to the exemplary embodiment described above.

[0106] Figure 16 This is a schematic cross-sectional view showing another example of an electronic component package.

[0107] according to Figure 16 The electronic component package 600B shown in another exemplary embodiment differs from the electronic component package 600A according to the exemplary embodiment described above in the structure of the first printed circuit board.

[0108] Reference Figure 16 The first printed circuit board mounted on the second printed circuit board 200 of the electronic component package 600B according to another exemplary embodiment may be the printed circuit board 100B according to the other exemplary embodiment described above.

[0109] Therefore, a fourth wiring layer 124, which has a width greater than that of the first wiring layer 121, can be additionally disposed on the first wiring layer 121.

[0110] Because of the fourth wiring layer 124, the volume of the second electrical connection metal 520 can be relatively small in the electronic component package 600B according to another exemplary embodiment. The second electrical connection metal 520 can be formed with a small size, allowing the electronic component package 600B according to another exemplary embodiment to be implemented with a more refined structure in terms of mounting. Furthermore, the smaller volume of the second electrical connection metal 520 in the electronic component package 600B according to another exemplary embodiment is advantageous because it prevents short circuits between the second electrical connection metals 520 or between the second electrical connection metal 520 and the first electrical connection metal 510.

[0111] The descriptions of other components are repeated from the descriptions of other components in the electronic component package 600A according to the exemplary embodiment and the printed circuit board 100B according to another exemplary embodiment, and are therefore omitted.

[0112] Figure 17 This is a schematic cross-sectional view showing another example of an electronic component package.

[0113] according to Figure 17 The electronic component package 600C shown in another exemplary embodiment differs from the electronic component package 600A according to the exemplary embodiment described above in terms of the structure of the first printed circuit board.

[0114] Reference Figure 17 The first printed circuit board mounted on the second printed circuit board 200 of the electronic component package 600C according to another exemplary embodiment may be the printed circuit board 100C according to the other exemplary embodiment described above.

[0115] Therefore, the second cavity C2 can be formed in one surface of the first insulating layer 111 of the first printed circuit board 100C, and the first cavity C1 can be formed on the lower surface of the second cavity C2.

[0116] Reference Figure 17The width of the second cavity C2 may be greater than the width of the electronic component 300. Therefore, when the electronic component 300 and the first printed circuit board 100C are mounted on the second printed circuit board 200, at least a portion of the electronic component 300 may be disposed within the second cavity C2. Furthermore, the width of the second cavity C2 may be greater than the width of the first cavity C1. For example, the second cavity C2 may be wider than the first cavity C1, such that the inner walls of the first cavity C1 and the inner walls of the second cavity C2 may have steps. The upper surface of the electronic component 300 disposed in the second cavity C2 may contact the lower surface of the second cavity C2 and may contact the plurality of protrusions P disposed in the first cavity C1. Additionally, since the width of the second cavity C2 is greater than the width of the electronic component 300, when the encapsulant 400 fills the interior of the second cavity C2, the encapsulant 400 may cover at least a portion of the upper surface and at least a portion of the side surface of the electronic component 300. Since the encapsulant 400 can cover at least a portion of each of the upper and side surfaces of the electronic component 300, the electronic component 300 can be stably bonded and secured. Furthermore, since the space for the encapsulant 400 is secured by the plurality of protrusions P formed in the first cavity C1, the processes and costs required to ensure the distance between the lower surface of the second cavity C2 and the electronic component 300 are not incurred. This is advantageous because it improves yield and reduces costs.

[0117] Furthermore, similar to the first cavity C1 described above, the second cavity C2 may also have a high roughness formed on the inner wall and lower surface of the second cavity C2 through roughening. Therefore, high adhesion between the encapsulant 400 and the first insulating layer 111 can be ensured.

[0118] The descriptions of other components are repeated from the descriptions of other components in the electronic component package 600A according to an exemplary embodiment and the printed circuit board 100C according to another exemplary embodiment, and are therefore omitted.

[0119] Figure 18 This is a schematic cross-sectional view showing another example of an electronic component package.

[0120] according to Figure 18 The electronic component package 600D shown in another exemplary embodiment differs in structure from the electronic component package 600C according to the other exemplary embodiment described above in the structure of the first printed circuit board.

[0121] Reference Figure 18 The first printed circuit board mounted on the second printed circuit board 200 of the electronic component package 600D according to another exemplary embodiment may be the printed circuit board 100D according to the other exemplary embodiment described above.

[0122] Therefore, according to Figure 18The first printed circuit board 100D of the electronic component package 600D shown in another exemplary embodiment may further include a fourth wiring layer 124 disposed on the first wiring layer 121, and the second cavity C2 may be formed in one surface of the first insulating layer 111.

[0123] Figure 18 The description of other components in the electronic component package 600D according to another exemplary embodiment shown herein is repeated with the description of other components in the first printed circuit board 100D according to the exemplary embodiment and the electronic component packages 600B and 600C according to another exemplary embodiment described above.

[0124] Figure 19 This is a cross-sectional view schematically illustrating another example of an electronic component package.

[0125] according to Figure 19 The electronic component package 600E shown in another exemplary embodiment differs in structure from the electronic component package 600D according to the other exemplary embodiment described above in the structure of the first printed circuit board.

[0126] Reference Figure 19 The first printed circuit board mounted on the second printed circuit board 200 of the electronic component package 600E according to another exemplary embodiment may be the printed circuit board 100E according to the other exemplary embodiment described above.

[0127] Therefore, the groove R can be formed on the side surface of the second cavity C2 formed in the first insulating layer 111 of the first printed circuit board 100E, and thus the side surface of the second cavity C2 can have a step.

[0128] Since the side surface of the second cavity C2 has steps, the encapsulant 400 can also be filled in the groove R, and the adhesion between the encapsulant 400 and the first insulating layer 111 can be further improved due to the anchoring effect of the step structure, etc.

[0129] Furthermore, similar to the first cavity C1 and the second cavity C2 described above, the groove R may also have a high roughness formed on the inner wall and lower surface of the groove R through roughening. Therefore, high adhesion between the encapsulant 400 and the first insulating layer 111 can be ensured.

[0130] The descriptions of other components are repeated from the descriptions of other components in the printed circuit board 100E according to another exemplary embodiment and the electronic component package 600D according to another exemplary embodiment, and are therefore omitted.

[0131] As described above, according to exemplary embodiments in this disclosure, a printed circuit board that facilitates reducing overall thickness and miniaturizing products, as well as an electronic component package including the printed circuit board, can be provided.

[0132] Although exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A printed circuit board comprising: a first insulating layer; a first cavity provided in one surface of the first insulating layer; a plurality of protrusions spaced apart from each other in the first cavity; a first wiring layer embedded in the one surface of the first insulating layer, wherein the plurality of protrusions and the first insulating layer are integrated, and an edge region of the first cavity is flat, a bottom surface and inner walls of the first cavity and surfaces of the plurality of protrusions have a roughness greater than that of another surface of the first insulating layer opposite to the one surface of the first insulating layer. 2.The printed circuit board of claim 1, further comprising a second cavity provided in the one surface of the first insulating layer, wherein the first cavity is provided at a bottom surface of the second cavity, and the bottom surface and inner walls of the second cavity have a roughness greater than that of the another surface of the first insulating layer. 3.The printed circuit board of claim 2, further comprising a groove portion provided on a side surface of the second cavity, and a bottom surface and inner walls of the groove portion have a roughness greater than that of the another surface of the first insulating layer.

4. The printed circuit board of claim 2, wherein, the second cavity is wider than the first cavity, such that the inner walls of the first cavity and the inner walls of the second cavity have a step. 5.The printed circuit board of claim 1, further comprising: a second wiring layer provided on the another surface of the first insulating layer; a first via layer penetrating at least a portion of the first insulating layer and connecting the first wiring layer and the second wiring layer to each other; a second insulating layer provided on the another surface of the first insulating layer and having one surface in which the second wiring layer is embedded; and a third wiring layer provided on another surface of the second insulating layer; a second via layer penetrating at least a portion of the second insulating layer and connecting the second wiring layer and the third wiring layer to each other. 6.The printed circuit board of claim 1, further comprising a fourth wiring layer provided on the one surface of the first insulating layer, the fourth wiring layer covers at least a portion of the first wiring layer. wherein, 7.The printed circuit board of claim 5, further comprising a passivation layer provided on the one surface of the first insulating layer and the another surface of the second insulating layer. the first wiring layer is exposed from the one surface of the first insulating layer, and 8. The printed circuit board of claim 1, wherein, a roughness of a surface of the first wiring layer in contact with the first insulating layer is relatively greater than a roughness of a surface of the first wiring layer exposed from the first insulating layer, and a roughness of the one surface of the first insulating layer and the surface of the first wiring layer in contact with the first insulating layer is greater than that of the another surface of the first insulating layer, and end portions of the plurality of protrusions are flush with the edge region of the first cavity. 9.An electronic component package comprising: ​ a first printed circuit board including an insulating layer, a first cavity provided in one surface of the insulating layer, and a plurality of protrusion portions spaced apart from each other in the first cavity and integrated with the insulating layer; a second printed circuit board provided on one side of the first printed circuit board and having one surface on which the first printed circuit board is mounted; and an electronic component mounted on the one surface of the second printed circuit board, wherein, in the one surface of the insulating layer of the first printed circuit board, an edge region of the first cavity is in contact with the electronic component, and a bottom surface and inner walls of the first cavity and surfaces of the plurality of protrusion portions have a roughness greater than that of another surface of the insulating layer opposite to the one surface of the insulating layer.

10. The electronic component package of claim 9, wherein, The plurality of protrusion portions are in contact with one surface of the electronic component. 11.The electronic component package of claim 9, further comprising an encapsulant provided between the first printed circuit board and the second printed circuit board and covering at least a portion of the electronic component.

12. The electronic component package of claim 11, wherein, The encapsulant is provided in at least a portion of the first cavity. 13.The electronic component package of claim 12, further comprising a second cavity provided on the one surface of the insulating layer, wherein the first cavity is provided on a bottom surface of the second cavity, and the encapsulant is provided in at least a portion of the second cavity, the bottom surface and inner walls of the second cavity having a roughness greater than that of the another surface of the insulating layer.

14. The electronic component package of claim 13, wherein, The second cavity is wider than the first cavity, such that inner walls of the first cavity and inner walls of the second cavity have a step.

15. The electronic component package of claim 9, wherein, The first printed circuit board further includes: a first wiring layer embedded in the one surface of the insulating layer; and a second wiring layer provided on the first wiring layer and protruding from the one surface of the insulating layer. 16.The electronic component package of claim 15, further comprising: a first electrically connecting metal provided between the second printed circuit board and the electronic component; and a second electrically connecting metal provided between the first printed circuit board and the second printed circuit board.

17. The electronic component package of claim 16, wherein, A surface of the first wiring layer in contact with the insulating layer has a roughness greater than that of a surface of the second wiring layer in contact with the second electrically connecting metal.

18. The electronic component package of claim 15, wherein, A surface of the first wiring layer in contact with the insulating layer has a roughness greater than that of a surface of the first wiring layer in contact with the second wiring layer. 19.The electronic component package of claim 13, further comprising a groove portion provided on a side surface of the second cavity, wherein the encapsulant is further provided in the groove portion, the groove portion having a bottom surface and inner walls having a roughness greater than that of the another surface of the insulating layer.

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