Roof control system with driver behavior recognition

Abstract

The present invention discloses an intelligent roof control system with a driver behavior recognition function, which specifically includes: a switch button and a lighting control module, a high-speed bus communication module, a power supply module, a camera, an image preprocessing module, an image storage, an integrated control module, and an emergency safety response module. The present invention integrates a camera, an image storage and processing system in the roof control module to realize the roof driving behavior recognition technology, and integrates it with the existing automobile emergency warning and rescue system. The intelligent roof control system that adopts multi-sensor fusion to realize the driver behavior recognition function improves the in-vehicle safety control capability and has the advantages of high reliability and high intelligence.

Description

Technical Field

[0001] The present invention belongs to the field of automobile intelligent control technology. The present invention adopts multimodal control technology, combines driving behavior recognition and other safety control technologies to improve the in-vehicle safety control capability, and provides an intelligent roof control system with driver behavior recognition function to achieve high safety and high reliability. Technical Background

[0002] With the rapid development of my country's economy and the continuous improvement of people's living standards, the number of vehicles owned by ordinary families and units in my country has continued to rise. While enjoying the convenience brought by cars, people are more concerned about the comfort and safety of vehicles. In recent years, automobile safety accidents have occurred frequently, especially safety accidents caused by sudden abnormal conditions of drivers. Therefore, there is a strong practical need to design early warning and identification and management systems for the above-mentioned safety accidents of automobiles.

[0003] With the development of intelligent recognition technology, image and voice recognition technology has been widely used in various security monitoring systems. Using similar technology to improve driver behavior recognition and improve the safety monitoring effect in the car is a technical means with great application value. The car ceiling light is at the highest position in the interior space of the car. It is a good way to integrate the above-mentioned emergency warning and rescue system with the car ceiling light control system. To this end, it is necessary to develop an intelligent roof control system with driver behavior recognition function that combines driving behavior recognition technology to improve the safety control capability in the car. Summary of the invention

[0004] The purpose of the present invention is to overcome the deficiencies in the prior art and provide an intelligent roof control system with a driver behavior recognition function.

[0005] The object of the present invention can be achieved by the following technical solutions: an intelligent roof control system with driver behavior recognition function, characterized in that it includes: a switch button and lighting control module, a high-speed bus communication module, a power supply module, a camera, an image preprocessing module, an image storage, an integrated control module and an emergency safety response module;

[0006] The connection relationship of the above system is: the first control signal output end of the integrated control module is connected to the control signal input end of the switch button and the lighting control module, the second control signal output end of the integrated control module is connected to the control signal input end of the high-speed bus communication module, the third control signal output end of the integrated control module is connected to the control signal input end of the power supply module, and the fourth control signal output end of the integrated control module is connected to the control signal input end of the emergency safety response module; the first data port of the integrated control module is connected to the first data port of the image preprocessing module, the second data port of the integrated control module is connected to the first data port of the image memory, the second data port of the image preprocessing module is connected to the second data port of the image memory, the third data port of the integrated control module is connected to the data port of the switch button and the lighting control module, the fourth data port of the integrated control module is connected to the data port of the high-speed bus communication module, and the fifth data port of the integrated control module is connected to the power supply status output end of the power supply module; the power supply module provides power for all the above circuits.

[0007] When the system is started, different functional modules are turned on in order: first, the power supply module, the high-speed bus communication module and the integrated control module are turned on; secondly, the emergency safety response module is turned on, and the emergency safety response module performs emergency processing when an abnormal situation occurs; then the switch button and the lighting control module, the camera, the image preprocessing module, and the image storage module are turned on, and the camera, the image preprocessing module and the image storage module cooperate to form a driving behavior recognition control module; the integrated control module performs function control according to the driving behavior recognition data generated by the driving behavior recognition control module and the instructions of the switch button;

[0008] When all functional modules are turned on, the integrated control module comprehensively judges and determines the working mode of the intelligent roof control system with driver behavior recognition function according to all output data provided by the driving behavior recognition control module, the switch button and lighting control module, the high-speed bus communication module and the power supply module through their respective data output terminals; the working mode includes two modes: emergency safety mode and normal working mode; when any one or more signal indications of the high-speed bus communication module and the driving behavior recognition control module are abnormal, the integrated control module turns on the emergency safety mode, and the emergency safety response module sends a distress signal to the outside; when the intelligent roof control system with driver behavior recognition function enters the emergency safety mode, the emergency safety response module will be turned on all the time.

[0009] Specifically, the driving behavior recognition control module uses a VGG16 deep learning network, a multi-level spatial attention module and a multi-level channel attention module to build a network, and then trains the network to obtain a preferred network model.

[0010] The driving behavior recognition control module includes 6 sub-networks, specifically including:

[0011] The first-level subnetwork takes the original RGB image block with a resolution of 224*224*3 as input, where 224*224*3 means that the input image block size is 224*224 pixels and the number of channels is 3. It passes through 2 64-channel 3*3 convolutional layers + ReLU activation layers, 1 hybrid attention module, and 1 2*2 maximum pooling layer, and outputs a feature map with a resolution of 112*112*64, where the feature map size is 112*112 pixels and the number of channels is 64;

[0012] The second-level sub-network takes a feature map with a resolution of 112*112*64 as input, passes through two 128-channel 3*3 convolutional layers + ReLU activation layers, a hybrid attention module, and a 2*2 maximum pooling layer, and outputs a feature map with a resolution of 56*56*128, where the feature map size is 56*56 pixels and the number of channels is 128;

[0013] The third-level sub-network takes a feature map with a resolution of 56*56*128 as input, passes through three 256-channel 3*3 convolutional layers + ReLU activation layers, one hybrid attention module, and one 2*2 maximum pooling layer, and outputs a feature map with a resolution of 28*28*256, where the feature map size is 28*28 pixels and the number of channels is 256;

[0014] The fourth-level sub-network takes a feature map with a resolution of 28*28*256 as input, passes through three 512-channel 3*3 convolutional layers + ReLU activation layers, one hybrid attention module, and one 2*2 maximum pooling layer, and outputs a feature map with a resolution of 14*14*512, where the feature map size is 14*14 pixels and the number of channels is 512;

[0015] The fifth-level subnetwork takes a feature map with a resolution of 14*14*512 as input, passes through three 512-channel 3*3 convolutional layers + ReLU activation layers, one hybrid attention module, and one 2*2 maximum pooling layer, and outputs a feature map with a resolution of 7*7*512, where the feature map size is 7*7 pixels and the number of channels is 512;

[0016] The sixth-level subnetwork takes a feature map with a resolution of 7*7*512 as input, passes through two 4096-node fully connected layers + ReLU activation layers, a 5-node fully connected layer + ReLU activation layer, and a Softmax normalization layer, and outputs a 5-dimensional feature vector to represent the probabilities of five different driving behavior categories.

[0017] Furthermore, the second-level subnetwork, the third-level subnetwork, the fourth-level subnetwork, and the fifth-level subnetwork of the driving behavior recognition control module each include a hybrid attention module, each of which is composed of a parallel structure of a spatial attention module and a channel attention module, which can simultaneously capture the semantic relevance of the spatial dimension and the channel dimension, and generate hybrid attention features through the following steps:

[0018] Step 1: The spatial attention module first applies three 1*1 convolutional layers to reduce the dimensionality of the input features of the hybrid attention module to obtain three reduced dimensionality features;

[0019] Step 2: The spatial attention module uses any two dimensionality reduction features output by the 1*1 convolutional layer to generate a spatial attention matrix to reflect the importance of each pixel in the spatial feature for driver behavior recognition. The channel attention module uses the input features of the mixed attention module to generate a channel attention matrix to reflect the importance of each channel feature for driver behavior recognition.

[0020] Step 3: The spatial attention module performs matrix multiplication on the generated spatial attention matrix and another dimension reduction feature output by the 1*1 convolution layer, and then performs element-by-element summation on the input feature of the hybrid attention module after dimensionality increase by the 1*1 convolution layer to obtain spatial attention features that reflect the semantic relevance of the spatial dimension. The channel attention module performs matrix multiplication on the input feature of the hybrid attention module and the generated channel attention matrix, and then performs element-by-element summation on the input feature of the hybrid attention module to obtain channel attention features that reflect the semantic relevance of the channel dimension.

[0021] Step 4: Perform element-by-element sum operation on the spatial attention features and the channel attention features to obtain the mixed attention features.

[0022] Preferably, the power supply module includes: a Buck converter, a power switch tube Q1, a freewheeling inductor L1, a voltage-dividing resistor R73, a voltage-dividing resistor R74, a freewheeling tube Q2 and an output capacitor COUT;

[0023] The Buck converter 70 internally includes: a frequency-jittering clock generating circuit, an EA amplifier, a current comparator COMP, a current sampling circuit CS, a pulse locking Lock module and a control driving module Logic&Driver;

[0024] On the one hand, the feedback voltage FB after voltage division of the switching power supply output voltage is input into the error amplifier EA and subtracted from the reference voltage Vref to generate a compensation reference voltage Vc; on the other hand, the reference voltage Vc is compared with the sampled switching power supply output current signal CS in the comparator COMP to determine the time point when the power switch tube is turned on or off. The pulse locking Lock module modulates the pulse signal under the control of the frequency-jittering clock generating circuit, and the modulated output Dctrl finally enters the control drive module Logic&Driver to generate gate drive switch signals for Q1 and Q2.

[0025] Further, the frequency-jittering clock generating circuit includes: a PMOS tube M800, a PMOS tube M801, a PMOS tube M802, a PMOS tube M803, a PMOS tube M805, a PMOS tube M806, a PMOS tube M821, a PMOS tube M830, an NMOS tube M808, an NMOS tube M809, an NMOS tube M810, a PMOS tube M811, an NMOS tube M822, a resistor R81, a resistor R821, a resistor R822, a capacitor C81, a capacitor C82, a capacitor C821, N switch NMOS tubes M831 to M83N, N series resistors R831 to R83N, a pseudo-random code generating circuit, an inverter Inv800, an inverter Inv801, an inverter Inv802, an inverter Inv830, X clock output inverters, a buffer Buf80, a PMOS tube M840, an NMOS transistor M841, PMOS transistor M845, NMOS transistor M846, PMOS transistor M847, NMOS transistor M848, capacitor C840, resistor R840, capacitor C841, resistor R841, capacitor C842 and resistor R842;

[0026] The PMOS tube M800 is connected to the upper end of the drain resistor R821, and the gates of the PMOS tube M800, the PMOS tube M801, the PMOS tube M802 and the PMOS tube M803 are all connected to the bias voltage Vbc81; the lower end of the resistor R821 is connected to the upper end of the resistor R822, the source of the PMOS tube M821 and the gate of the PMOS tube M805; the drain of the PMOS tube M821 is connected to the drain of the NMOS tube M822, and is connected to the upper end of the capacitor C821;

[0027] The drain of the source of the PMOS tube M801 is connected to the source of the PMOS tube M805 and the source of the PMOS tube M806; the drain of the PMOS tube M805 is connected to the gate and drain of the NMOS tube M808 and the gate of the NMOS tube M809; the drain of the PMOS tube M806 is connected to the drain of the NMOS tube M809, the gate of the NMOS tube M810 and the upper end of the resistor R81; the lower end of the resistor R81 is connected to the upper end of the capacitor C81; the drain of the NMOS tube M810 is connected to the drain of the PMOS tube M802 and the gate of the PMOS tube M811; the source of the PMOS tube M811 is connected to the lower end of the resistor R83 and the upper end of the capacitor C82, and is also connected to the power supply voltage port of the inverter Inv800, the power supply voltage port of the inverter Inv801, the power supply voltage port of the inverter Inv802 and the buffer Buf80 as the oscillator power supply voltage VCC_OSC. The upper end of the resistor R83 is connected to the drain of the PMOS tube M803;

[0028] The drain of the PMOS tube M830 is connected to the upper end of the resistor R830, the upper end of R831 is the upper end of the resistor string composed of N series resistors, and the lower end of R83N is the lower end of the resistor string composed of N series resistors. The connection relationship of the resistor string composed of N series resistors is: the lower end of the resistor R831 is connected to the upper end of the resistor R832, ​​the lower end of the resistor R832 is connected to the upper end of the resistor R833, the lower end of the resistor R83M-1 is connected to the upper end of the resistor R83M, and the lower end of the resistor R83N-1 is connected to the upper end of the resistor R83N; The drain of the transistor M831 is connected to the upper end of the resistor R831, the source of the NMOS transistor M831 is connected to the lower end of the resistor R831, the upper end of the resistor R832 and the drain of the NMOS transistor M832; the source of the NMOS transistor M832 is connected to the lower end of the resistor R832, ​​the upper end of the resistor R833 and the drain of the NMOS transistor M833; The source of the NMOS tube M83M-1 is connected to the lower end of the resistor R83M-1, the upper end of the resistor R83M and the drain of the NMOS tube M83M; the source of the NMOS tube M83N-1 is connected to the lower end of the resistor R83N-1, the upper end of the resistor R83N and the drain of the NMOS tube M83N; the pseudo-random code P1 output by the pseudo-random code generating circuit is connected to the gate of the NMOS tube M831, the pseudo-random code P2 output by the pseudo-random code generating circuit is connected to the gate of the NMOS tube M832, the pseudo-random code PM output by the pseudo-random code generating circuit is connected to the gate of the NMOS tube M83M, and the pseudo-random code PN output by the pseudo-random code generating circuit is connected to the gate of the NMOS tube M83N;

[0029] The source of the NMOS tube M808, the source of the NMOS tube M809, the source of the NMOS tube M822, the lower end of the capacitor C821, the lower end of the capacitor C81, the lower end of the resistor R822, the source of the NMOS tube M83N, the lower end of the resistor R83N, the drain of the PMOS tube M811 and the lower end of the capacitor C82 are all connected to the ground voltage GND; the source of the PMOS tube M800, the source of the PMOS tube M801, the source of the PMOS tube M802, the source of the PMOS tube M803 and the source of the PMOS tube M830 are simultaneously connected to the power supply voltage VCC;

[0030] Inverter Inv800, inverter Inv801, and inverter Inv802 form a reference clock ring oscillator, the output of the reference clock ring oscillator is connected to the input end of buffer Buf80, and the output end of buffer Buf80 is the reference clock signal OSC_out; the left side of capacitor C840 is connected to the reference clock signal OSC_out, and the right side of capacitor C840 is simultaneously connected to the upper end of resistor R840, the lower end of capacitor C841, and the upper end of capacitor C842; the upper end of capacitor C841 is connected to the lower end of resistor R841 and the gate of PMOS tube M85, and the lower end of capacitor C842 is connected to the upper end of resistor R842 and the gate of NMOS tube M86; the upper end of resistor R841 is connected to the drain of PMOS tube M840, the lower end of resistor R842 is connected to the drain of NMOS tube M841, the gate of PMOS tube M842 is connected to bias voltage Vb82P, and NMOS tube M821 is connected to bias voltage Vb82P. The gate of the PMOS tube M845 is connected to the bias voltage Vb82N; the drain of the PMOS tube M845 is connected to the drain of the NMOS tube M846, and is also connected to the gates of the PMOS tube M847 and the NMOS tube M848; the drain of the PMOS tube M847 is connected to the drain of the NMOS tube M848, and is also connected to the input ends of the X clock output inverters and the input end of the inverter Inv830; the output ends of the X output inverters are connected to the X output clock signals CK1 to CKX; the output end of the inverter Inv830 is used as the feedback clock CK_fb, and is also connected to the gate of the PMOS tube M821 and the gate of the NMOS tube M822; the lower end of the resistor R840, the NMOS tube M841 The source of the NMOS tube M846 and the source of the NMOS tube M848 are simultaneously connected to the ground voltage GND; the source of the PMOS tube M840, the source of the PMOS tube M845 and the source of the PMOS tube M847 are simultaneously connected to the power supply voltage VCC;

[0031] Where X is any positive integer, M is a positive integer less than N, and N = 2 K , K is any positive integer.

[0032] Specifically, the jitter clock generation circuit is divided into seven functional sub-modules in terms of specific circuit structure: a two-stage error amplifier composed of a PMOS tube M801, a PMOS tube M802, a PMOS tube M805, a PMOS tube M806, an NMOS tube M808, an NMOS tube M809, an NMOS tube M810, a resistor R81 and a capacitor C81; a two-stage error amplifier composed of a PMOS tube M803, a PMOS tube M811, a resistor R83 and a capacitor C82 A follower buffer is formed by a PMOS tube M800, a PMOS tube M821, an NMOS tube M822, a resistor R821, a resistor R822 and a capacitor C821; a frequency-jittering reference voltage generating circuit is formed by a PMOS tube M830, a resistor R830, N series resistors, N switch NMOS tubes and a pseudo-random code generating circuit; a reference clock ring oscillator is formed by an inverter Inv800, an inverter Inv801 and an inverter Inv802; a filtering coupling circuit is formed by a buffer Buf80, a PMOS tube M840, an NMOS tube M841, a capacitor C840, a resistor R840, a capacitor C841, a resistor R841, a capacitor C842 and a resistor R842; a PMOS tube M845, an NMOS tube M846, a PMOS tube M847, an NMOS A clock output buffer circuit consisting of a tube M848, X clock output inverters and an inverter Inv830;

[0033] The first differential input terminal of the two-stage error amplifier is the gate of the PMOS tube M805, the second differential input terminal of the two-stage error amplifier is the gate of the PMOS tube M806, and the amplified output terminal of the two-stage error amplifier is connected to the drain of the PMOS tube M802 and the drain of the NMOS tube M810; the signal input terminal of the follower buffer is the gate of the PMOS tube M811, and the signal output terminal of the follower buffer is the oscillator power supply voltage VCC_OSC; the input terminal CK_fb of the feedback clock detection circuit is connected to the gate of the PMOS tube M821 and the gate of the NMOS tube M822, and the output terminal of the feedback clock detection circuit is the clock feedback voltage Vckfb, which is connected to the first differential input terminal of the two-stage error amplifier; The reference voltage input terminal Vref of the frequency-jittering reference voltage generating circuit is the gate of the PMOS tube M830, and the frequency-jittering reference voltage Vrdith generated by the frequency-jittering reference voltage generating circuit is connected to the second differential input terminal of the two-stage error amplifier; the amplification output terminal of the two-stage error amplifier is connected to the signal input terminal of the follower buffer, and the signal output terminal of the follower buffer is the oscillator power supply voltage VCC_OSC; the reference clock ring oscillator generates a reference clock signal OSC_out according to the oscillator power supply voltage VCC_OSC; the filter coupling circuit filters and couples the reference clock signal OSC_out, and then obtains the X-channel output clocks CK1~CKX and the feedback clock CK_fb through the clock output buffer circuit.

[0034] Preferably, the frequency-jittering reference voltage Vrdith in the frequency-jittering reference voltage generating circuit is obtained by dividing the total resistance of a resistor string consisting of a resistor R830 and N series resistors;

[0035] The resistance values ​​of any two resistors in the N series resistors are different, and the resistance value of a single resistor in the N resistors is selected using a pseudo-random distribution, that is, the ratio between any two resistors is different, so as to realize the random characteristics of the amplitude of the frequency jitter reference voltage Vrdith;

[0036] The pseudo-random code generating circuit generates N bits of pseudo-random codes P1 to PN, in which only one bit of pseudo-random code outputs a high level at any time, and the remaining N-1 bits are all low levels; and the time length for which any one bit of the N bits of pseudo-random codes P1 to PN outputs a high level is different, thereby realizing the random characteristics of the frequency-jittering reference voltage Vrdith in time.

[0037] The advantages of the present invention are: the present invention integrates a camera, an image storage and processing system in a roof control module to realize roof driving behavior recognition technology, and integrates it with the existing automobile emergency warning and rescue system to improve the reliability of recognition, thereby enhancing the safety control capability in the vehicle. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a block diagram of the intelligent roof control system with driver behavior recognition function of the present invention;

[0039] Figure 2 This is a control flow chart of the system of the present invention;

[0040] Figure 3 This is a schematic diagram of the learning model of the driving behavior recognition module of the present invention;

[0041] Figure 4 This is a flow chart of sub-networks at various levels of the learning model of the driving behavior recognition module of the present invention;

[0042] Figure 5 This is the attention block flow chart of the driving behavior recognition module of the present invention;

[0043] Figure 6 This is a schematic diagram of the reading light driving circuit of the present invention;

[0044] Figure 7 This is a structural block diagram of the power supply module of the present invention;

[0045] Figure 8 This is an embodiment of the frequency-jittering clock generating circuit of the present invention. DETAILED DESCRIPTION

[0046] The present invention is further described in detail below with reference to the accompanying drawings and examples.

[0047] See also Figure 1 As shown, an intelligent roof control system with driver behavior recognition function includes a switch button and lighting control module, a high-speed bus communication module, a power supply module, a camera, an image preprocessing module, an image storage, an integrated control module and an emergency safety response module;

[0048] Figure 1The connection relationship of the system shown is: the first control signal output end of the integrated control module is connected to the control signal input end of the switch button and the lighting control module, the second control signal output end of the integrated control module is connected to the control signal input end of the high-speed bus communication module, the third control signal output end of the integrated control module is connected to the control signal input end of the power supply module, and the fourth control signal output end of the integrated control module is connected to the control signal input end of the emergency safety response module; the first data port of the integrated control module is connected to the first data port of the image preprocessing module, the second data port of the integrated control module is connected to the first data port of the image memory, the second data port of the image preprocessing module is connected to the second data port of the image memory, the third data port of the integrated control module is connected to the data port of the switch button and the lighting control module, the fourth data port of the integrated control module is connected to the data port of the high-speed bus communication module, and the fifth data port of the integrated control module is connected to the power supply status output end of the power supply module; the power supply module provides power for all the above circuits.

[0049] like Figure 2 As shown, when the intelligent roof control system with driver behavior recognition function is started, different functional modules are turned on in sequence: first, the power supply module, the high-speed bus communication module and the integrated control module are turned on; secondly, the emergency safety response module is turned on, and the emergency safety response module performs emergency processing when an abnormal situation occurs; then the switch button and the lighting control module, the camera, the image preprocessing module, and the image storage module are turned on, and the camera, the image preprocessing module and the image storage module cooperate to form a driving behavior recognition control module; the integrated control module performs function control according to the driving behavior recognition data generated by the driving behavior recognition control module and the instructions of the switch button;

[0050] When all functional modules are turned on, the integrated control module comprehensively judges and determines the working mode of the intelligent roof control system with driver behavior recognition function according to all output data provided by the driving behavior recognition control module, the switch button and lighting control module, the high-speed bus communication module and the power supply module through their respective data output terminals; the working mode includes two modes: emergency safety mode and normal working mode; when any one or more signal indications of the high-speed bus communication module and the driving behavior recognition control module are abnormal, the integrated control module turns on the emergency safety mode, and the emergency safety response module sends a distress signal to the outside; when the intelligent roof control system with driver behavior recognition function enters the emergency safety mode, the emergency safety response module will be turned on all the time.

[0051] The image preprocessing module of the present invention can be implemented by a general video image signal processor (ISP, Image Signal Processing). The original image signal provided by the camera must undergo a series of post-processing before it can be converted into a digital image required for behavior recognition training extraction. The ISP is used to process the original data stream of the camera to improve the final image quality so that the image recognition platform and the vehicle driver can use it. Some operations that the ISP needs to perform to convert the image into digital form include: Bayer, black level compensation, lens correction, bad pixel correction, color interpolation (demosaic), Bayer noise removal, white balance (AWB) correction, color correction, gamma correction, color space conversion (RGB to YUV), color noise removal and edge enhancement in YUV color space, color and contrast enhancement, and automatic exposure control, image compression, etc. in the middle. The ISP merges images with different exposure values ​​to generate an image, further provides local tone scaling for the HDR image, fills dark areas with long exposure pixels, and fills similar bright areas with short exposure pixels. This makes the video stream have an extended dynamic range, which is very suitable for use by drivers and image recognition platforms. As data rates increase, the ISP module can be separated from the image sensor to limit power consumption and heat generation, thereby improving image quality.

[0052] The new generation of high-performance visual SoCs with dedicated ISPs have advanced HDR and LFM functions and can process multiple input data streams simultaneously. The internal structure of an ISP usually includes: CPU, which is a central processing unit, can run various image processing algorithms such as AF and LSC, and control peripheral devices. The CPU inside mainstream ISPs is generally ARM Cortex-A series, such as Cortex-A5 and Cortex-A7; SUB IP is a general term for various functional modules, which perform their own professional processing on images. Common SUB IPs include DIS, CSC, VRA, etc.; Image transmission interface, mainly divided into two types, parallel port ITU and serial port CSI. CSI is the abbreviation of MIPI CSI. In view of the many advantages of MIPI CSI, the MIPI-CSI interface has been widely used in the field of mobile phone cameras to transmit image data and various custom data; General peripherals, referring to I2C, SPI, PWM, UART, WATCHDOG, etc., ISP contains an I2C controller for reading OTP information, controlling VCM, etc.

[0053] In addition to the conventional automotive ECU execution control functions, the integrated control module of the present invention must also have high-speed processing and parallel computing capabilities, and the power consumption control is also very strict. The integrated control module is a high-performance image processing platform. These platforms are based on computer vision technology and can analyze, detect and interpret one or more elements of an image to make reasonable decisions. The image processing platform extracts information from the image frame based on specific predefined concepts. It can perform tasks including identifying pedestrians, bicycles and other VRUs, image classification, and reading traffic and road signs. These actions range from simple audiovisual warnings to the driver to more complex decision-making applications (such as AEB, ACC, LKA and other autonomous driving functions).

[0054] In order to realize the functions of the present invention, the image processing platform used must meet a series of prerequisites: high-speed processing, the platform needs to have real-time data processing capabilities, should be able to quickly detect and identify image patterns, and determine whether there is potential danger, and make appropriate decisions; parallel computing capabilities, the platform must have the ability to support multiple applications at the same time, and the powerful computing power can process the data of multiple cameras in parallel with extremely low latency within milliseconds; power consumption: the automotive image processing computing platform should support low-power operation. Conventional image recognition systems are based on power-hungry processing units GPU, so the design of these platforms must reduce power consumption as much as possible, which is crucial; thermal management, the image processing platform and the image sensor will generate a lot of heat together, which may cause thermal management problems. The location of these components also increases the heating problem. Exposure to sunlight and engine heat will also increase the thermal load of these components; ultra-high data transmission rate, the on-board camera module can generate nearly GB of data per second, and a high-speed dedicated data transmission interface is required to pass the generated data to the processing unit. In the near future, each car will be equipped with 5-12 camera modules, so a high-speed fiber optic interface solution is needed to transmit data from the camera module to the image processing platform to achieve high-speed and low-latency data transmission between the component and the application processor.

[0055] The emergency safety response module described in the present invention is equipped with an SOS emergency call system and an E-Call system. The main function of the SOS emergency call system is that when the vehicle is in an emergency, the SOS emergency call can provide emergency rescue services based on user feedback. For example, when a user is injured in a car accident or develops a disease, just press the SOS button, the emergency call service will start and help the user seek help. The "Emergency Rescue" E-Call system uses mobile phones and satellite positioning functions to establish a telephone connection with the unified number of the nearest rescue center (such as 122 in China and 112 in the European Union) after a traffic accident. In addition to the voice connection, the on-board eCall system also reports and transmits information about the accident location, accident type and vehicle. Of all the people who died in traffic accidents, the vast majority (more than 90%) lost their lives before arriving at the hospital, but the probability of successful rescue of the injured who were successfully delivered to the hospital is very high. The emergency safety response module described in the present invention will provide car owners with all-round travel safety protection, allowing all vehicles to have the intelligent first aid system that is only available in luxury vehicles. When a vehicle collision or other traffic accident occurs, the collision signal can be actively transmitted back to the rescue service center in the first time, providing the car owner with the most timely rescue and first aid, greatly shortening the time for saving lives.

[0056] The high-speed bus communication module of the present invention is used for communication between the roof control module and the core CPU of the vehicle body. In addition, it is also necessary to control the typical vehicle light signal, so it is necessary to transmit the core signal control and electrical ECU control functions, and it is not necessary to transmit high-speed image and video signals. Therefore, a communication network combining CAN bus and LIN bus is adopted. If CAN bus is used everywhere, the bus architecture cost of the whole vehicle will become very high. In some places such as vehicle body electronic accessories (such as windows, rearview mirrors, headlights, car locks, etc.), messages do not need to be transmitted at "high speed" like on the CAN bus, and LIN bus is used for communication. LIN bus is a low-cost serial communication protocol based on UART / SCI (universal asynchronous receiver / serial interface). The target of LIN bus in the present invention is low-end communication between nodes of vehicle body network module, and it is mainly used for serial communication of sensors and actuators such as touch shielding signal, SOS alarm button signal, front left reading light button signal, front right reading light button signal and reading light full light button signal. CAN bus is a multi-master bus system. It is different from traditional bus systems such as USB or Ethernet in that it realizes the transmission of large amounts of data from node A to node B under the coordination of the bus controller. The messages of the CAN network are broadcast, that is, the data detected by all nodes on the network at the same time are consistent, so it is more suitable for the rapid transmission of short messages such as high-speed control instructions. In the present invention, when any one or more signal indications of the high-speed bus communication module and the driving behavior recognition control module are abnormal, the CAN bus is used to realize the rapid transmission of high-speed control instructions in the interconnection system in the car.

[0057] Figure 3 This is a schematic diagram of the learning model of the driving behavior recognition module of the present invention. Based on the training sample data, a network is constructed by integrating the VGG16 deep learning network, the multi-level spatial attention module and the multi-level channel attention module, and then the network is trained to obtain the optimal network model, which specifically includes the following steps:

[0058] Step 1: Use the built-in roof surveillance camera to capture the driver's image and establish a driver behavior recognition dataset. Randomly select 224*224 RGB image blocks as training samples for driver behavior recognition, covering five different driving behaviors: normal driving, making phone calls, playing with mobile phones, smoking, and drinking water. Use 1 to 5 to represent the driving behavior labels corresponding to the training samples.

[0059] Step 2: Construct a network by integrating the VGG16 deep learning network with the multi-level spatial attention module and the multi-level channel attention module. Figure 4 This is a flow chart of the sub-networks at each level of the learning model of the driving behavior recognition module of the present invention, including 6 levels of sub-networks, as follows:

[0060] The first-level subnetwork takes the original RGB image block with a resolution of 224*224*3 as input, where 224*224*3 means that the input image block size is 224*224 pixels and the number of channels is 3. It passes through 2 64-channel 3*3 convolutional layers + ReLU activation layers, 1 hybrid attention module, and 1 2*2 maximum pooling layer, and outputs a feature map with a resolution of 112*112*64, where the feature map size is 112*112 pixels and the number of channels is 64;

[0061] The second-level sub-network takes a feature map with a resolution of 112*112*64 as input, passes through two 128-channel 3*3 convolutional layers + ReLU activation layers, a hybrid attention module, and a 2*2 maximum pooling layer, and outputs a feature map with a resolution of 56*56*128, where the feature map size is 56*56 pixels and the number of channels is 128;

[0062] The third-level sub-network takes a feature map with a resolution of 56*56*128 as input, passes through three 256-channel 3*3 convolutional layers + ReLU activation layers, one hybrid attention module, and one 2*2 maximum pooling layer, and outputs a feature map with a resolution of 28*28*256, where the feature map size is 28*28 pixels and the number of channels is 256;

[0063] The fourth-level sub-network takes a feature map with a resolution of 28*28*256 as input, passes through three 512-channel 3*3 convolutional layers + ReLU activation layers, one hybrid attention module, and one 2*2 maximum pooling layer, and outputs a feature map with a resolution of 14*14*512, where the feature map size is 14*14 pixels and the number of channels is 512;

[0064] The fifth-level subnetwork takes a feature map with a resolution of 14*14*512 as input, passes through three 512-channel 3*3 convolutional layers + ReLU activation layers, one hybrid attention module, and one 2*2 maximum pooling layer, and outputs a feature map with a resolution of 7*7*512, where the feature map size is 7*7 pixels and the number of channels is 512;

[0065] The sixth-level subnetwork takes a feature map with a resolution of 7*7*512 as input, passes through two 4096-node fully connected layers + ReLU activation layers, a 5-node fully connected layer + ReLU activation layer, and a Softmax normalization layer, and outputs a 5-dimensional feature vector to represent the probabilities of five different driving behavior categories.

[0066] Figure 4The second, third, fourth, and fifth subnetworks in the figure all contain a hybrid attention module, which is composed of a parallel structure of a spatial attention module and a channel attention module. It can capture the semantic relevance of the spatial dimension and the channel dimension at the same time, and generate hybrid attention features through the following steps:

[0067] Step 2.1, the spatial attention module first applies three 1*1 convolutional layers to reduce the dimensionality of the input features of the hybrid attention module to obtain three reduced dimensionality features;

[0068] Step 2.2, the spatial attention module uses any two dimensionality reduction features output by the 1*1 convolutional layer to generate a spatial attention matrix to reflect the importance of each pixel in the spatial feature for driver behavior recognition. The channel attention module uses the input features of the mixed attention module to generate a channel attention matrix to reflect the importance of each channel feature for driver behavior recognition.

[0069] In step 2.3, the spatial attention module performs matrix multiplication on the generated spatial attention matrix and another dimension reduction feature output by the 1*1 convolution layer, and then performs element-by-element summation on the input feature of the hybrid attention module after dimensionality increase by the 1*1 convolution layer to obtain the spatial attention feature that reflects the semantic correlation of the spatial dimension. The channel attention module performs matrix multiplication on the input feature of the hybrid attention module and the generated channel attention matrix, and then performs element-by-element summation on the input feature of the hybrid attention module to obtain the channel attention feature that reflects the semantic correlation of the channel dimension.

[0070] In step 2.4, the spatial attention feature and the channel attention feature are summed element by element to obtain the mixed attention feature.

[0071] The specific formula is as follows:

[0072] Step 2.1, apply three 1*1 convolutional layers to reduce the dimension of the input feature x of the hybrid attention module, which can be specifically expressed as:

[0073]

[0074] Among them, W a , W b , W c Represents the weight matrices to be learned by the three 1*1 convolutional layers, x a 、x b 、x c They represent the dimensionality reduction features of the 1*1 convolutional layer output respectively.

[0075] Step 2.2, apply dimension reduction feature x a 、x bThe input features x of the hybrid attention module generate the spatial attention matrix A s And the channel attention matrix A c , which can be specifically expressed as:

[0076]

[0077] Among them, A s Reflects the importance of each pixel in the spatial feature for driving behavior recognition, A c Reflects the importance of each channel feature for driver behavior recognition.

[0078] Step 2.3, apply the spatial attention matrix A s , dimension reduction feature x c After matrix multiplication, the 1*1 convolution layer is used to increase the dimension and perform element-by-element summation with the input feature x to obtain the spatial attention feature f that reflects the semantic correlation of the spatial dimension. s (x), apply input feature x, channel attention matrix A c After matrix multiplication, the matrix is ​​summed element by element with the input feature x to obtain the channel attention feature f that reflects the semantic relevance of the channel dimension. c (x), which can be specifically expressed as:

[0079]

[0080] Where W d is the weight matrix to be learned by the 1*1 convolutional layer, and +x represents residual learning.

[0081] Step 2.4, the spatial attention feature f s (x) and channel attention features f c (x) performs element-by-element summation to obtain the mixed attention feature f(x), which can be specifically expressed as:

[0082] f(x)=f s (x)+f c (x)

[0083] Step 3: Send the training samples representing different driving behaviors to the constructed network for training, apply the cross entropy loss function to supervise the network training process, and continuously optimize the network model parameters through multiple iterations of the stochastic gradient descent method to obtain the optimal model for driver behavior recognition. The cross entropy loss function L can be specifically expressed as:

[0084]

[0085] Where N represents the total number of driving behavior categories, v i represents the real category, Represents the predicted class output.

[0086] The above results in an optimal model for driver behavior recognition. Using this model for driver behavior recognition can improve the performance of driver behavior recognition.

[0087] The switch button and light control module described in the present invention are usually provided with a touch shielding button, an SOS alarm button, a front left reading light button, a front right reading light button, and a reading light full-brightness button; the categories of the touch signals include touch shielding signals, SOS alarm button signals, front left reading light button signals, front right reading light button signals, and reading light full-brightness button signals. Figure 6 The figure shows a typical reading light driving display circuit including an NPN transistor Q6, the collector of the NPN transistor Q6 is connected to one end of a resistor R13, one end of the resistor R13 is also grounded via a capacitor C22, and the other end of the resistor R13 is used to connect to the front right reading light control output end of the car ceiling light MCU; a capacitor C11 is connected between the collector and emitter of the NPN transistor Q6, the emitter of the NPN transistor Q6 is grounded, and the NPN The collector of transistor Q6 is also connected to the base of NPN transistor Q4, the emitter of NPN transistor Q4 is grounded via resistor R43, the base of NPN transistor Q6 is connected to the emitter of NPN transistor Q4, the collector of NPN transistor Q4 is connected to the cathode of light-emitting diode LED17, the anode of light-emitting diode LED17 is connected to the VS output end of the power module via a parallel resistor composed of resistors R1, R2 and R3, and capacitor C1 and resistor R8 are connected in parallel at both ends of the light-emitting diode LED17; the capacitance of capacitor C22 is 10nF.

[0088] Figure 7 The circuit block diagram of the power supply module of the present invention adopts Buck converter for control, and has the advantages of simple structure and small steady-state error of output voltage. The power supply system includes: Buck converter, power switch tube Q1, freewheeling inductor L1, voltage divider resistor R73, voltage divider resistor R74, freewheeling tube Q2 and output capacitor COUT. The power circuit that realizes power conversion by controlling the switching time of each cycle, the PWM signal generated by Buck controller 70 controls the closing and opening of switch tubes Q1 and Q2, and the inductor L1 and output capacitor COUT form a second-order filter network, which filters the square wave signal with an amplitude of VIN generated by the left chopper circuit, thereby generating a DC voltage VOUT. By controlling the closing time of the switch tube Q1, the duty cycle of the Buck converter can be controlled, and we can control the size of the output voltage.

[0089] The Buck converter 70 internally includes: a frequency-jittering clock generation circuit, an EA amplifier, a current comparator COMP, a current sampling circuit CS, a pulse lock Lock module, and a control drive module Logic & Driver. When the overall switching power supply is working, on the one hand, the feedback voltage FB after the switching power supply output voltage is divided is input to the error amplifier EA and amplified by subtracting the reference voltage Vref to generate a compensation reference voltage Vc; on the other hand, the reference voltage Vc is compared with the sampled switching power supply output current signal CS in the comparator COMP to determine the time point when the power switch tube is turned on or off. The pulse lock Lock module modulates the pulse signal under the control of the frequency-jittering clock generation circuit, and the modulated output Dctrl finally enters the control drive module Logic & Driver to generate the gate drive switch signal of Q1 and Q2. In order to limit the EMI interference of the power supply, the Buck controller of the present invention adopts frequency-jittering technology to reduce the EMI peak energy. The Buck controller adopts a frequency-jittering clock generation circuit to modulate the signal bandwidth of the output control switching frequency, and reduce the EMI peak by bandwidth amplification.

[0090] like Figure 8 As shown, the jitter clock generating circuit of the present invention includes: a PMOS tube M800, a PMOS tube M801, a PMOS tube M802, a PMOS tube M803, a PMOS tube M805, a PMOS tube M806, a PMOS tube M821, a PMOS tube M830, an NMOS tube M808, an NMOS tube M809, an NMOS tube M810, a PMOS tube M811, an NMOS tube M822, a resistor R81, a resistor R821, a resistor R822, a capacitor C81, a capacitor C82, a capacitor C821, N switch NMOS tubes M831~M83N, N series resistors R831~R83N, a pseudo-random code generating circuit, an inverter Inv800, an inverter Inv801, an inverter Inv802, an inverter Inv830, X clock output inverters, a buffer Buf80, a PMOS tube M840, an NMOS transistor M841, PMOS transistor M845, NMOS transistor M846, PMOS transistor M847, NMOS transistor M848, capacitor C840, resistor R840, capacitor C841, resistor R841, capacitor C842 and resistor R842;

[0091] The PMOS tube M800 is connected to the upper end of the drain resistor R821, and the gates of the PMOS tube M800, the PMOS tube M801, the PMOS tube M802 and the PMOS tube M803 are all connected to the bias voltage Vbc81; the lower end of the resistor R821 is connected to the upper end of the resistor R822, the source of the PMOS tube M821 and the gate of the PMOS tube M805; the drain of the PMOS tube M821 is connected to the drain of the NMOS tube M822, and is connected to the upper end of the capacitor C821;

[0092] The drain of the source of the PMOS tube M801 is connected to the source of the PMOS tube M805 and the source of the PMOS tube M806; the drain of the PMOS tube M805 is connected to the gate and drain of the NMOS tube M808 and the gate of the NMOS tube M809; the drain of the PMOS tube M806 is connected to the drain of the NMOS tube M809, the gate of the NMOS tube M810 and the upper end of the resistor R81; the lower end of the resistor R81 is connected to the upper end of the capacitor C81; the drain of the NMOS tube M810 is connected to the drain of the PMOS tube M802 and the gate of the PMOS tube M811; the source of the PMOS tube M811 is connected to the lower end of the resistor R83 and the upper end of the capacitor C82, and is also connected to the power supply voltage port of the inverter Inv800, the power supply voltage port of the inverter Inv801, the power supply voltage port of the inverter Inv802 and the buffer Buf80 as the oscillator power supply voltage VCC_OSC. The upper end of the resistor R83 is connected to the drain of the PMOS tube M803;

[0093] The drain of the PMOS tube M830 is connected to the upper end of the resistor R830, the upper end of R831 is the upper end of the resistor string composed of N series resistors, and the lower end of R83N is the lower end of the resistor string composed of N series resistors. The connection relationship of the resistor string composed of N series resistors is as follows: the lower end of the resistor R831 is connected to the upper end of the resistor R832, ​​the lower end of the resistor R832 is connected to the upper end of the resistor R833, the lower end of the resistor R83M-1 is connected to the upper end of the resistor R83M (where M is an integer less than N), and the lower end of the resistor R83N-1 is connected to the upper end of the resistor R83N; the drain of the NMOS tube M831 is connected to the upper end of the resistor R831, and the source of the NMOS tube M831 is connected to the lower end of the resistor R831, the upper end of the resistor R832 and the NMOS tube M832. The source of the NMOS tube M832 is connected to the lower end of the resistor R832, ​​the upper end of the resistor R833 and the drain of the NMOS tube M833; the source of the NMOS tube M83M-1 is connected to the lower end of the resistor R83M-1, the upper end of the resistor R83M and the drain of the NMOS tube M83M; the source of the NMOS tube M83N-1 is connected to the lower end of the resistor R83N-1, the upper end of the resistor R83N and the drain of the NMOS tube M83N; the pseudo-random code P1 output by the pseudo-random code generating circuit is connected to the gate of the NMOS tube M831, the pseudo-random code P2 output by the pseudo-random code generating circuit is connected to the gate of the NMOS tube M832, the pseudo-random code PM output by the pseudo-random code generating circuit is connected to the gate of the NMOS tube M83M, and the pseudo-random code PN output by the pseudo-random code generating circuit is connected to the gate of the NMOS tube M83N;

[0094] The source of the NMOS tube M808, the source of the NMOS tube M809, the source of the NMOS tube M822, the lower end of the capacitor C821, the lower end of the capacitor C81, the lower end of the resistor R822, the source of the NMOS tube M83N, the lower end of the resistor R83N, the drain of the PMOS tube M811 and the lower end of the capacitor C82 are all connected to the ground voltage GND; the source of the PMOS tube M800, the source of the PMOS tube M801, the source of the PMOS tube M802, the source of the PMOS tube M803 and the source of the PMOS tube M830 are simultaneously connected to the power supply voltage VCC;

[0095] Inverter Inv800, inverter Inv801, and inverter Inv802 form a reference clock ring oscillator, the output of the reference clock ring oscillator is connected to the input end of buffer Buf80, and the output end of buffer Buf80 is the reference clock signal OSC_out; the left side of capacitor C840 is connected to the reference clock signal OSC_out, and the right side of capacitor C840 is simultaneously connected to the upper end of resistor R840, the lower end of capacitor C841, and the upper end of capacitor C842; the upper end of capacitor C841 is connected to the lower end of resistor R841 and the gate of PMOS tube M85, and the lower end of capacitor C842 is connected to the upper end of resistor R842 and the gate of NMOS tube M86; the upper end of resistor R841 is connected to the drain of PMOS tube M840, the lower end of resistor R842 is connected to the drain of NMOS tube M841, the gate of PMOS tube M842 is connected to bias voltage Vb82P, and NMOS tube M821 is connected to bias voltage Vb82P. The gate of the PMOS tube M845 is connected to the bias voltage Vb82N; the drain of the PMOS tube M845 is connected to the drain of the NMOS tube M846, and is also connected to the gates of the PMOS tube M847 and the NMOS tube M848; the drain of the PMOS tube M847 is connected to the drain of the NMOS tube M848, and is also connected to the input ends of the X clock output inverters and the input end of the inverter Inv830; the output ends of the X output inverters are connected to the X output clock signals CK1 to CKX; the output end of the inverter Inv830 is used as the feedback clock CK_fb, and is also connected to the gate of the PMOS tube M821 and the gate of the NMOS tube M822; the lower end of the resistor R840, the NMOS tube M841 The source of the NMOS tube M846 and the source of the NMOS tube M848 are connected to the ground voltage GND at the same time; the source of the PMOS tube M840, the source of the PMOS tube M845 and the source of the PMOS tube M847 are connected to the power supply voltage VCC at the same time; wherein X is an arbitrary positive integer.

[0096] like Figure 8The circuit shown is divided into seven functional sub-modules in terms of specific circuit structure: a two-stage error amplifier composed of PMOS tube M801, PMOS tube M802, PMOS tube M805, PMOS tube M806, NMOS tube M808, NMOS tube M809, NMOS tube M810, resistor R81 and capacitor C81; a follower buffer composed of PMOS tube M803, PMOS tube M811, resistor R83 and capacitor C82; a follower buffer composed of PMOS tube M800, PMOS tube M821, NMOS tube M822, resistor R821, resistor R822 and capacitor C821; a frequency-jittering reference voltage generating circuit consisting of a PMOS tube M830, a resistor R830, N series resistors, N switch NMOS tubes and a pseudo-random code generating circuit; a reference clock ring oscillator consisting of an inverter Inv800, an inverter Inv801 and an inverter Inv802; a filtering coupling circuit consisting of a buffer Buf80, a PMOS tube M840, an NMOS tube M841, a capacitor C840, a resistor R840, a capacitor C841, a resistor R841, a capacitor C842 and a resistor R842; a clock output buffer circuit consisting of a PMOS tube M845, an NMOS tube M846, a PMOS tube M847, an NMOS tube M848, X clock output inverters and an inverter Inv830;

[0097] The first differential input terminal of the two-stage error amplifier is the gate of the PMOS tube M805, the second differential input terminal of the two-stage error amplifier is the gate of the PMOS tube M806, and the amplified output terminal of the two-stage error amplifier is connected to the drain of the PMOS tube M802 and the drain of the NMOS tube M810; the signal input terminal of the follower buffer is the gate of the PMOS tube M811, and the signal output terminal of the follower buffer is the oscillator power supply voltage VCC_OSC; the input terminal CK_fb of the feedback clock detection circuit is connected to the gate of the PMOS tube M821 and the gate of the NMOS tube M822, and the output terminal of the feedback clock detection circuit is the clock feedback voltage Vckfb, which is connected to the first differential input terminal of the two-stage error amplifier; The reference voltage input terminal Vref of the frequency-jittering reference voltage generating circuit is the gate of the PMOS tube M830, and the frequency-jittering reference voltage Vrdith generated by the frequency-jittering reference voltage generating circuit is connected to the second differential input terminal of the two-stage error amplifier; the amplification output terminal of the two-stage error amplifier is connected to the signal input terminal of the follower buffer, and the signal output terminal of the follower buffer is the oscillator power supply voltage VCC_OSC; the reference clock ring oscillator generates a reference clock signal OSC_out according to the oscillator power supply voltage VCC_OSC; the filter coupling circuit filters and couples the reference clock signal OSC_out, and then obtains the X-channel output clocks CK1~CKX and the feedback clock CK_fb through the clock output buffer circuit.

[0098] Since the output frequency of the clock signal in the chip is particularly susceptible to PVT fluctuations, the present invention adopts two measures to limit the impact of PVT fluctuations on the frequency of the output clocks CK1~CKX. First, the oscillator power supply voltage VCC_OSC based on the reference clock ring oscillator is generated based on the reference voltage, which is different from the VCC voltage and has higher anti-interference characteristics; second, the feedback clock CK_fb is used to feedback control the oscillator power supply voltage VCC_OSC, and finally maintain the stability of the output clocks CK1~CKX. When the power supply voltage VCC changes, as long as the oscillator power supply voltage VCC_OSC controlled by the reference signal remains unchanged, the frequency of the output clocks CK1~CKX will also remain unchanged.

[0099] Assuming that the PVT change causes the frequency of the feedback clock CK_fb to shift, the feedback clock detection circuit will detect the shift and change the clock feedback voltage Vckfb, which will be processed by the two-stage error amplifier for error amplification and connected to the signal input end of the follower buffer, and finally change the size of the oscillator power supply voltage VCC_OSC output by the follower buffer. The PMOS tube M821 and NMOS tube M822 inside the feedback clock detection circuit will charge and discharge the capacitor C821 under the control of the feedback clock CK_fb, so that the capacitor C821 forms an equivalent impedance RC821, and the resistance after RC821 and R822 are connected in parallel and divided by R821 to obtain the final clock feedback voltage Vckfb. The frequency of the feedback clock CK_fb is obviously inversely proportional to the equivalent impedance RC821.

[0100] When the frequency of the feedback clock CK_fb decreases, the equivalent impedance RC821 will become higher, the error voltage output of the two-stage error amplifier will increase, and eventually the voltage of the oscillator power supply voltage VCC_OSC output by the follower buffer will increase. The increase in the voltage of the oscillator power supply voltage VCC_OSC will increase the frequency of the reference clock signal OSC_out output by the reference clock ring oscillator, and eventually compensate for the increase in the frequency of the feedback clock CK_fb; if the frequency of the feedback clock CK_fb increases, the equivalent impedance RC821 will decrease, the error voltage output of the two-stage error amplifier will decrease, and eventually the voltage of the oscillator power supply voltage VCC_OSC output by the follower buffer will decrease. The decrease in the voltage of the oscillator power supply voltage VCC_OSC will decrease the frequency of the reference clock signal OSC_out output by the reference clock ring oscillator, and eventually compensate for the decrease in the frequency of the feedback clock CK_fb.

[0101] Figure 8In the given embodiment, a filtering coupling circuit is composed of a buffer Buf80, a PMOS tube M840, an NMOS tube M841, a capacitor C840, a resistor R840, a capacitor C841, a resistor R841, a capacitor C842 and a resistor R842; a clock output buffer circuit is composed of a PMOS tube M845, an NMOS tube M846, a PMOS tube M847, an NMOS tube M848, X clock output inverters and an inverter Inv830. Capacitor C80 and resistor R80 form a high-pass filter to isolate the high and low level DC components of the reference clock signal OSC_out; capacitor C81 and resistor R81 form a second high-pass filter, and capacitor C82 and resistor R82 form a third high-pass filter; the outputs of the second high-pass filter and the third high-pass filter are respectively connected to the two clock signal input terminals of the clock output buffer circuit, namely, the gate of the PMOS tube M85 and the gate of the NMOS tube M86; the two input clock signals of the clock output buffer circuit are processed by the push-pull amplifier circuit composed of the PMOS tube M85 and the NMOS tube M86 to obtain new clock signals with high and low level conversion and shifting, and then buffered and shaped by the output inverter to obtain the final output clock. The function of the above process is to convert the input clock with a swing of VCC_OSC into an output clock with a swing of VCC through the capacitive coupling of the high-pass filter to achieve level conversion. The power supply used by the output clock is VCC, and even if there is a large interference, it will not be fed back to the input clock, thereby ensuring the stability of the reference clock signal OSC_out.

[0102] The present invention generates an oscillator power supply voltage VCC_OSC with a pseudo-random jitter characteristic by modulating the oscillator power supply voltage VCC_OSC using a pseudo-random code inside the jitter reference voltage generation circuit, so that the output clock CK1~CKX signals are all converted into jitter clocks, thereby achieving the goal of reducing EMI interference. In the jitter reference voltage generation circuit, the jitter reference voltage Vrdith is obtained by dividing the total resistance Rs83 of the resistor string composed of resistor R830 and N series resistors. The total resistance Rs83 of the resistor string composed of N series resistors is controlled by an N-bit pseudo-random code, so the jitter reference voltage Vrdith generated by the jitter reference voltage generation circuit has a pseudo-random characteristic. In the implementation scheme of the present invention, the resistance values ​​of any two resistors in the N series resistors are not the same, and the resistance value of a single resistor in the N resistors is selected using a pseudo-random distribution, that is, the ratio between any two resistors is not the same. In this way, it can be ensured that the voltage amplitude difference between the jitter reference voltages Vrdith under the control of different pseudo-random codes is different, and the random characteristics of the amplitude of the jitter reference voltage Vrdith are realized. The pseudo-random code generating circuit generates N-bit pseudo-random codes P1-PN, at any time only one pseudo-random code outputs a high level, and the remaining N-1 bits are all low levels; and the time lengths for any one pseudo-random code in the N-bit pseudo-random codes P1-PN to output a high level are all different. In this way, it can be ensured that the effective duration of any voltage between the frequency-jittering reference voltages Vrdith under the control of different pseudo-random codes is different, and the random characteristics of the frequency-jittering reference voltage Vrdith in time are realized. The frequency-jittering reference voltage Vrdith provided by the present invention has pseudo-random characteristics not only in amplitude, but also in time, so that it is closer to a natural noise signal. And as the number of pseudo-random code bits increases, the frequency-jittering reference voltage Vrdith is closer to a natural noise signal.

[0103] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An intelligent roof control system with driver behavior recognition function, characterized in that include: Switch button and lighting control module, high-speed bus communication module, power supply module, camera, image preprocessing module, image storage, integrated control module and emergency safety response module; The connection relationship of the above system is as follows: the first control signal output end of the integrated control module is connected to the control signal input end of the switch button and the lighting control module, the second control signal output end of the integrated control module is connected to the control signal input end of the high-speed bus communication module, the third control signal output end of the integrated control module is connected to the control signal input end of the power supply module, and the fourth control signal output end of the integrated control module is connected to the control signal input end of the emergency safety response module; the first data port of the integrated control module is connected to the first data port of the image preprocessing module, the second data port of the integrated control module is connected to the first data port of the image memory, the second data port of the image preprocessing module is connected to the second data port of the image memory, the third data port of the integrated control module is connected to the data port of the switch button and the lighting control module, the fourth data port of the integrated control module is connected to the data port of the high-speed bus communication module, and the fifth data port of the integrated control module is connected to the power supply status output end of the power supply module; the power supply module provides power for all the above circuits; When the system starts, different functional modules are turned on in order: first, the power supply module, high-speed bus communication module and integrated control module are turned on; second, the emergency safety response module is turned on, and the emergency safety response module performs emergency processing when an abnormal situation occurs; then the switch button and the lighting control module, camera, image preprocessing module and image storage module are turned on, and the camera, image preprocessing module and image storage module cooperate to form a driving behavior recognition control module; The integrated control module performs function control according to the driving behavior recognition data generated by the driving behavior recognition control module and the instructions of the switch button; When all functional modules are turned on, the integrated control module comprehensively judges and determines the working mode of the intelligent roof control system with driver behavior recognition function according to all output data provided by the driving behavior recognition control module, the switch button and lighting control module, the high-speed bus communication module and the power supply module through their respective data output terminals; the working mode includes two modes: emergency safety mode and normal working mode; when any one or more signal indications of the high-speed bus communication module and the driving behavior recognition control module are abnormal, the integrated control module turns on the emergency safety mode, and the emergency safety response module sends a distress signal to the outside; when the intelligent roof control system with driver behavior recognition function enters the emergency safety mode, the emergency safety response module will be turned on all the time; The driving behavior recognition control module uses a VGG16 deep learning network, a multi-level spatial attention module, and a multi-level channel attention module to build a network, and then trains the network to obtain an optimal network model; The driving behavior recognition control module includes 6 sub-networks, specifically including: The first-level subnetwork takes the original RGB image block with a resolution of 224*224*3 as input, where 224*224*3 means that the input image block size is 224*224 pixels and the number of channels is 3. It passes through 2 64-channel 3*3 convolutional layers + ReLU activation layers, 1 hybrid attention module, and 1 2*2 maximum pooling layer, and outputs a feature map with a resolution of 112*112*64, where the feature map size is 112*112 pixels and the number of channels is 64; The second-level sub-network takes a feature map with a resolution of 112*112*64 as input, passes through two 128-channel 3*3 convolutional layers + ReLU activation layers, one hybrid attention module, and one 2*2 maximum pooling layer, and outputs a feature map with a resolution of 56*56*128, where the feature map size is 56*56 pixels and the number of channels is 128; The third-level sub-network takes a feature map with a resolution of 56*56*128 as input, passes through three 256-channel 3*3 convolutional layers + ReLU activation layers, one hybrid attention module, and one 2*2 maximum pooling layer, and outputs a feature map with a resolution of 28*28*256, where the feature map size is 28*28 pixels and the number of channels is 256; The fourth-level sub-network takes a feature map with a resolution of 28*28*256 as input, passes through three 512-channel 3*3 convolutional layers + ReLU activation layers, one hybrid attention module, and one 2*2 maximum pooling layer, and outputs a feature map with a resolution of 14*14*512, where the feature map size is 14*14 pixels and the number of channels is 512; The fifth-level subnetwork takes a feature map with a resolution of 14*14*512 as input, passes through three 512-channel 3*3 convolutional layers + ReLU activation layers, one hybrid attention module, and one 2*2 maximum pooling layer, and outputs a feature map with a resolution of 7*7*512, where the feature map size is 7*7 pixels and the number of channels is 512; The sixth-level subnetwork takes a feature map with a resolution of 7*7*512 as input, passes through two 4096-node fully connected layers + ReLU activation layers, a 5-node fully connected layer + ReLU activation layer, and a Softmax normalization layer, and outputs a 5-dimensional feature vector to represent the probabilities of five different driving behavior categories; The second-level subnetwork, the third-level subnetwork, the fourth-level subnetwork, and the fifth-level subnetwork of the driving behavior recognition control module each include a hybrid attention module, each of which is composed of a parallel structure of a spatial attention module and a channel attention module, which can simultaneously capture the semantic relevance of the spatial dimension and the channel dimension, and generate hybrid attention features through the following steps: Step 1: The spatial attention module first applies three 1*1 convolutional layers to reduce the dimensionality of the input features of the hybrid attention module to obtain three reduced dimensionality features; Step 2: The spatial attention module uses any two dimensionality reduction features output by the 1*1 convolutional layer to generate a spatial attention matrix to reflect the importance of each pixel in the spatial feature for driver behavior recognition. The channel attention module uses the input features of the mixed attention module to generate a channel attention matrix to reflect the importance of each channel feature for driver behavior recognition. Step 3: The spatial attention module performs matrix multiplication on the generated spatial attention matrix and another dimension reduction feature output by the 1*1 convolution layer, and then performs element-by-element summation on the input feature of the hybrid attention module after dimensionality increase by the 1*1 convolution layer to obtain the spatial attention feature reflecting the semantic relevance of the spatial dimension. The channel attention module performs matrix multiplication on the input feature of the hybrid attention module and the generated channel attention matrix, and then performs element-by-element summation on the input feature of the hybrid attention module to obtain the channel attention feature reflecting the semantic relevance of the channel dimension. Step 4: Perform element-by-element sum operation on the spatial attention features and the channel attention features to obtain the mixed attention features.

2. The intelligent roof control system with driver behavior recognition function according to claim 1 is characterized in that The power supply module includes: a Buck converter, a power switch tube Q1, a freewheeling inductor L1, a voltage dividing resistor R73, a voltage dividing resistor R74, a freewheeling tube Q2 and an output capacitor COUT; The Buck converter 70 internally includes: a frequency-jittering clock generating circuit, an EA amplifier, a current comparator COMP, a current sampling circuit CS, a pulse locking Lock module and a control driving module Logic & Driver; On the one hand, the feedback voltage FB after voltage division of the switching power supply output voltage is input into the error amplifier EA and subtracted from the reference voltage Vref to generate a compensation reference voltage Vc; on the other hand, the reference voltage Vc is compared with the sampled switching power supply output current signal CS in the comparator COMP to determine the time point when the power switch tube is turned on or off. The pulse locking Lock module modulates the pulse signal under the control of the jitter clock generating circuit, and the modulated output Dctrl finally enters the control drive module Logic&Driver to generate gate drive switching signals for the power switch tube Q1 and the freewheeling tube Q2.

3. The intelligent roof control system with driver behavior recognition function according to claim 2 is characterized in that The jitter clock generating circuit includes: PMOS tube M800, PMOS tube M801, PMOS tube M802, PMOS tube M803, PMOS tube M805, PMOS tube M806, PMOS tube M821, PMOS tube M830, NMOS tube M808, NMOS tube M809, NMOS tube M810, PMOS tube M811, NMOS tube M822, resistor R81, resistor R821, resistor R822, capacitor C81, capacitor C82, capacitor C821, N switch NMOS tubes M831~ M83N, N series resistors R831~R83N, a pseudo-random code generating circuit, an inverter Inv800, an inverter Inv801, an inverter Inv802, an inverter Inv830, X clock output inverters, a buffer Buf80, a PMOS tube M840, an NMOS tube M841, a PMOS tube M845, an NMOS tube M846, a PMOS tube M847, an NMOS tube M848, a capacitor C840, a resistor R840, a capacitor C841, a resistor R841, a capacitor C842 and a resistor R842; The PMOS tube M800 is connected to the upper end of the drain resistor R821, and the gates of the PMOS tube M800, the PMOS tube M801, the PMOS tube M802 and the PMOS tube M803 are all connected to the bias voltage Vbc81; the lower end of the resistor R821 is connected to the upper end of the resistor R822, the source of the PMOS tube M821 and the gate of the PMOS tube M805; the drain of the PMOS tube M821 is connected to the drain of the NMOS tube M822, and is connected to the upper end of the capacitor C821; The source and drain of the PMOS tube M801 are connected to the source of the PMOS tube M805 and the source of the PMOS tube M806; the drain of the PMOS tube M805 is connected to the gate and drain of the NMOS tube M808 and the gate of the NMOS tube M809; the drain of the PMOS tube M806 is connected to the drain of the NMOS tube M809, the gate of the NMOS tube M810 and the upper end of the resistor R81; the lower end of the resistor R81 is connected to the upper end of the capacitor C81; the drain of the NMOS tube M810 is connected to the gate of the NMOS tube M810. connected to the drain of the PMOS tube M802 and the gate of the PMOS tube M811; the source of the PMOS tube M811 is connected to the lower end of the resistor R83 and the upper end of the capacitor C82, and is also connected to the power supply voltage port of the inverter Inv800, the power supply voltage port of the inverter Inv801, the power supply voltage port of the inverter Inv802 and the power supply voltage port of the buffer Buf80 as the oscillator power supply voltage VCC_OSC; the upper end of the resistor R83 is connected to the drain of the PMOS tube M803; The drain of the PMOS tube M830 is connected to the upper end of the resistor R830, the upper end of R831 is the upper end of the resistor string composed of N series resistors, and the lower end of R83N is the lower end of the resistor string composed of N series resistors. The connection relationship of the resistor string composed of N series resistors is as follows: the lower end of the resistor R831 is connected to the upper end of the resistor R832, ​​the lower end of the resistor R832 is connected to the upper end of the resistor R833, the lower end of the resistor R83M-1 is connected to the upper end of the resistor R83M, and the lower end of the resistor R83N-1 is connected to the upper end of the resistor R83N; the drain of the NMOS tube M831 is connected to the upper end of the resistor R831, the source of the NMOS tube M831 is connected to the lower end of the resistor R831, the upper end of the resistor R832 and the drain of the NMOS tube M832; the source of the NMOS tube M832 connected to the lower end of the resistor R832, ​​the upper end of the resistor R833 and the drain of the NMOS tube M833; the source of the NMOS tube M83M-1 is connected to the lower end of the resistor R83M-1, the upper end of the resistor R83M and the drain of the NMOS tube M83M; the source of the NMOS tube M83N-1 is connected to the lower end of the resistor R83N-1, the upper end of the resistor R83N and the drain of the NMOS tube M83N; the pseudo-random code P1 output by the pseudo-random code generating circuit is connected to the gate of the NMOS tube M831, the pseudo-random code P2 output by the pseudo-random code generating circuit is connected to the gate of the NMOS tube M832, the pseudo-random code PM output by the pseudo-random code generating circuit is connected to the gate of the NMOS tube M83M, and the pseudo-random code PN output by the pseudo-random code generating circuit is connected to the gate of the NMOS tube M83N; The source of the NMOS tube M808, the source of the NMOS tube M809, the source of the NMOS tube M822, the lower end of the capacitor C821, the lower end of the capacitor C81, the lower end of the resistor R822, the source of the NMOS tube M83N, the lower end of the resistor R83N, the drain of the PMOS tube M811 and the lower end of the capacitor C82 are all connected to the ground voltage GND; the source of the PMOS tube M800, the source of the PMOS tube M801, the source of the PMOS tube M802, the source of the PMOS tube M803 and the source of the PMOS tube M830 are simultaneously connected to the power supply voltage VCC; Inverter Inv800, inverter Inv801, and inverter Inv802 form a reference clock ring oscillator, the output of the reference clock ring oscillator is connected to the input end of buffer Buf80, and the output end of buffer Buf80 is the reference clock signal OSC_out; the left side of capacitor C840 is connected to the reference clock signal OSC_out, and the right side of capacitor C840 is simultaneously connected to the upper end of resistor R840, the lower end of capacitor C841, and the upper end of capacitor C842; the upper end of capacitor C841 is connected to the lower end of resistor R841 and the gate of PMOS tube M85, and the lower end of capacitor C842 is connected to the upper end of resistor R842 and the gate of NMOS tube M86; the upper end of resistor R841 is connected to the drain of PMOS tube M840, the lower end of resistor R842 is connected to the drain of NMOS tube M841, the gate of PMOS tube M842 is connected to bias voltage Vb82P, and the gate of NMOS tube M821 is connected to Vb82P. The bias voltage Vb82N is connected; the drain of the PMOS tube M845 is connected to the drain of the NMOS tube M846, and is also connected to the gates of the PMOS tube M847 and the NMOS tube M848; the drain of the PMOS tube M847 is connected to the drain of the NMOS tube M848, and is also connected to the input ends of the X clock output inverters and the input end of the inverter Inv830; the output ends of the X output inverters are connected to the X output clock signals CK1~CKX; the inverter Inv The output end of 830 is used as the feedback clock CK_fb, and is also connected to the gate of the PMOS tube M821 and the gate of the NMOS tube M822; the lower end of the resistor R840, the source of the NMOS tube M841, the source of the NMOS tube M846 and the source of the NMOS tube M848 are simultaneously connected to the ground voltage GND; the source of the PMOS tube M840, the source of the PMOS tube M845 and the source of the PMOS tube M847 are simultaneously connected to the power supply voltage VCC; Where X is any positive integer, M is a positive integer less than N, N=2 K , K is any positive integer.

4. The intelligent roof control system with driver behavior recognition function according to claim 3 is characterized in that The jitter clock generation circuit is divided into seven functional sub-modules in terms of specific circuit structure: a two-stage error amplifier composed of a PMOS tube M801, a PMOS tube M802, a PMOS tube M805, a PMOS tube M806, a NMOS tube M808, a NMOS tube M809, a NMOS tube M810, a resistor R81 and a capacitor C81; a follower buffer composed of a PMOS tube M803, a PMOS tube M811, a resistor R83 and a capacitor C82; a feedback clock detection circuit composed of a PMOS tube M800, a PMOS tube M821, a NMOS tube M822, a resistor R821, a resistor R822 and a capacitor C821; a PMOS tube M830, a resistor R831, a resistor R832 and a capacitor C833. R830, N series resistors, N switch NMOS tubes and a pseudo-random code generating circuit constitute a frequency-jittering reference voltage generating circuit; an inverter Inv800, an inverter Inv801, and an inverter Inv802 constitute a reference clock ring oscillator; a filter coupling circuit constituted by a buffer Buf80, a PMOS tube M840, an NMOS tube M841, a capacitor C840, a resistor R840, a capacitor C841, a resistor R841, a capacitor C842 and a resistor R842; a clock output buffer circuit constituted by a PMOS tube M845, an NMOS tube M846, a PMOS tube M847, an NMOS tube M848, X clock output inverters and an inverter Inv830; The first differential input terminal of the two-stage error amplifier is the gate of the PMOS tube M805, the second differential input terminal of the two-stage error amplifier is the gate of the PMOS tube M806, and the amplified output terminal of the two-stage error amplifier is connected to the drain of the PMOS tube M802 and the drain of the NMOS tube M810; the signal input terminal of the follower buffer is the gate of the PMOS tube M811, and the signal output terminal of the follower buffer is the oscillator power supply voltage VCC_OSC; the input terminal CK_fb of the feedback clock detection circuit is connected to the gate of the PMOS tube M821 and the gate of the NMOS tube M822, and the output terminal of the feedback clock detection circuit is the clock feedback voltage Vckfb, which is connected to the first differential input terminal of the two-stage error amplifier; The reference voltage input terminal Vref of the frequency-jittering reference voltage generating circuit is the gate of the PMOS tube M830, and the frequency-jittering reference voltage Vrdith generated by the frequency-jittering reference voltage generating circuit is connected to the second differential input terminal of the two-stage error amplifier; the amplification output terminal of the two-stage error amplifier is connected to the signal input terminal of the follower buffer, and the signal output terminal of the follower buffer is the oscillator power supply voltage VCC_OSC; the reference clock ring oscillator generates a reference clock signal OSC_out according to the oscillator power supply voltage VCC_OSC; the filtering coupling circuit filters and couples the reference clock signal OSC_out, and then obtains the X-channel output clocks CK1~CKX and the feedback clock CK_fb through the clock output buffer circuit.

5. The intelligent roof control system with driver behavior recognition function according to claim 4 is characterized in that The frequency-jittering reference voltage Vrdith in the frequency-jittering reference voltage generating circuit is obtained by dividing the total resistance of a resistor string consisting of a resistor R830 and N series resistors; The resistance values ​​of any two resistors in the N series resistors are different, and the resistance value of a single resistor in the N resistors is selected using a pseudo-random distribution, that is, the ratio between any two resistors is different, so as to realize the random characteristics of the amplitude of the frequency jitter reference voltage Vrdith; The pseudo-random code generating circuit generates N bits of pseudo-random codes P1~PN, and at any time only one bit of pseudo-random code outputs a high level, and the remaining N-1 bits are all low levels; and the time length of the output of the high level of any one bit of the N bits of pseudo-random codes P1~PN is different, so as to realize the random characteristics of the jitter reference voltage Vrdith in time.

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