Dead time generation circuit, method, and switching circuit

Abstract

This application provides a dead-time generation circuit, method, and switching circuit. The dead-time generation circuit includes: a comparator that compares the drain voltage of a low-side switch with a predetermined reference voltage; a D flip-flop that receives the comparison signal output by the comparator and outputs the comparison signal using the turn-on pulse signal of the low-side switch as a trigger clock signal; an up / down counter that performs up / down counting based on the comparison signal output by the D flip-flop and outputs an indication signal; and a time constant circuit that generates the dead time based on the indication signal. Therefore, not only can a better dead time be generated and adaptively adjusted, reducing switching losses and improving conversion efficiency, but the structure is also simple and low-cost, with short computation time, enabling it to handle high-speed switching operations.

Description

Technical Field

[0001] This application relates to the field of switch control technology, and in particular to a dead time generation circuit, method, and switch circuit. Background Technology

[0002] A switching circuit can include a high-side switch (e.g., a high-side control power transistor) and a low-side switch (e.g., a low-side synchronous rectifier transistor). When the low-side switch is off, the high-side switch is on for a period of time; when the high-side switch is off, the low-side switch is on for a period of time. However, generally, the high-side and low-side switches cannot be on simultaneously; a dead time (DT) is required between the off / on states of the high-side and low-side switches.

[0003] Fixed dead-time control can result in a dead time that is too long or too short, which is detrimental to power conversion efficiency. Therefore, some solutions have emerged that can adaptively adjust the dead time, that is, dynamically control the dead time to achieve higher power conversion efficiency.

[0004] Reference 1: CN201846233U.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention

[0006] However, the inventors discovered that current solutions for adaptive dead-time adjustment are based on analog circuits. They need to consider the unique characteristics of analog circuits, such as amplifier gain, capacitor capacitance, control current, and buffer delay generated by the dead time. Therefore, the design is cumbersome, the structure is complex and the cost is high. Furthermore, the calculation time is long and it is difficult to cope with high-speed switching actions.

[0007] To address at least one of the above problems, embodiments of this application provide a dead-time generation circuit, a method, and a switching circuit.

[0008] According to one aspect of the embodiments of this application, a dead-time generation circuit is provided to generate a dead-time between a high-side switch and a low-side switch; the dead-time generation circuit has:

[0009] A comparator that compares the drain voltage of the low-side switch with a specified reference voltage;

[0010] The D flip-flop receives the comparison signal output by the comparator and outputs the comparison signal using the turn-on pulse signal of the low-side switch as the trigger clock signal.

[0011] An up / down counter that performs up / down counting based on the comparison signal output by the D flip-flop and outputs an indication signal; and

[0012] A time constant circuit that generates the dead time based on the indicated signal.

[0013] According to another aspect of the embodiments of this application, a switching circuit is provided, including a high-side switch and a low-side switch, wherein the drain of the high-side switch and the drain of the low-side switch are connected, and the switching circuit further includes a dead-time generation circuit as described above.

[0014] According to another aspect of the embodiments of this application, a dead time generation method is provided to generate a dead time between a high-side switch and a low-side switch, the dead time generation method comprising:

[0015] The drain voltage of the low-side switch is compared with a specified reference voltage;

[0016] The system receives the comparison signal output by the comparator and uses the turn-on pulse signal of the low-side switch as a trigger clock signal to output the comparison signal.

[0017] The comparison signal is used to perform addition and subtraction counting, and an indication signal is output; and

[0018] The dead time is generated based on the indicated signal.

[0019] One of the beneficial effects of this application's embodiments is that: the drain voltage of the low-side switch is compared with a predetermined reference voltage; the comparison signal output by the comparator is received, and the comparison signal is output using the turn-on pulse signal of the low-side switch as a trigger clock signal; addition and subtraction are performed according to the comparison signal output by the D flip-flop, and an indication signal is output; and the dead time is generated according to the indication signal. Therefore, not only can a better dead time be generated and adaptively adjusted, reducing switching losses and improving conversion efficiency, but the structure is also simple and low-cost, with short computation time, enabling it to handle high-speed switching operations.

[0020] Specific embodiments of this application are disclosed in detail with reference to the following description and accompanying drawings, indicating how the principles of this application can be adopted. It should be understood that the embodiments of this application are not limited in scope. Within the spirit and scope of the appended claims, embodiments of this application include many changes, modifications, and equivalents.

[0021] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0022] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components. Attached Figure Description

[0023] The elements and features described in one drawing or embodiment of this application may be combined with elements and features shown in one or more other drawings or embodiments. Furthermore, in the drawings, similar reference numerals denote corresponding parts in several drawings and can be used to indicate corresponding parts used in more than one embodiment.

[0024] Figure 1 This is a schematic diagram of a switching circuit according to an embodiment of this application;

[0025] Figure 2 This is a schematic diagram of a dead-time generation circuit according to an embodiment of this application;

[0026] Figure 3 This is a schematic diagram of a time constant circuit according to an embodiment of this application;

[0027] Figure 4 This is an example diagram illustrating that the dead time in an embodiment of this application needs to be increased;

[0028] Figure 5 This is an example diagram illustrating how the dead time in an embodiment of this application needs to be reduced;

[0029] Figure 6 This is a schematic diagram of the dead time generation method according to an embodiment of this application. Detailed Implementation

[0030] Referring to the accompanying drawings, the foregoing and other features of this application will become apparent from the following description. Specific embodiments of this application are specifically disclosed in the description and drawings, illustrating partial implementations in which the principles of this application may be adopted. It should be understood that this application is not limited to the described embodiments; rather, it includes all modifications, variations, and equivalents falling within the scope of the appended claims.

[0031] In the embodiments of this application, the terms "first," "second," etc., are used to distinguish different elements by name, but do not indicate the spatial arrangement or chronological order of these elements, and these elements should not be limited by these terms. The term "and / or" includes any one or more of the terms listed in association and all combinations thereof. The terms "comprising," "including," "having," etc., refer to the presence of the stated features, elements, components, or assemblies, but do not exclude the presence or addition of one or more other features, elements, components, or assemblies.

[0032] In the embodiments of this application, the singular forms "a," "the," etc., including the plural forms, should be broadly interpreted as "a kind" or "a class" rather than limited to the meaning of "an." Furthermore, the term "the" should be understood to include both the singular and plural forms, unless the context explicitly indicates otherwise. Additionally, the term "according to" should be understood as "at least partially based on…," and the term "based on" should be understood as "at least partially based on…," unless the context explicitly indicates otherwise.

[0033] In some embodiments of this application, a zero-voltage switch (ZVS) is used as an example for illustration, but this application is not limited to this and can also be applied to other types of switching circuits.

[0034] First aspect of the embodiments

[0035] This application provides a switching circuit and a dead time generation circuit.

[0036] Figure 1 This is a schematic diagram of a switching circuit according to an embodiment of this application, as shown below. Figure 1 As shown, the switching circuit 100 includes a high-side switch 101 and a low-side switch 102, a driver 103, and a dead-time generation circuit 104. Figure 1 As shown, the source of the high-side switch 101 receives the input voltage Vin, the source of the low-side switch 102 can be grounded, the drain of the high-side switch 101 and the drain of the low-side switch 102 are connected, and output voltage (e.g., the voltage signal of the drain is Vsw) to the load.

[0037] like Figure 1As shown, a pulse width modulation (PWM) signal can be input into a dead time generation circuit 104. The dead time generation circuit 104 outputs control signals Ho and Lo, which are input into a driver 103. The driver 103 outputs a control signal to the gate of the high-side switch 101 (e.g., the voltage signal of the gate of the high-side switch 101 is Vg1) and outputs a control signal to the gate of the low-side switch 102 (e.g., the voltage signal of the gate of the low-side switch 102 is Vg2), thereby controlling the high-side switch 101 and the low-side switch 102.

[0038] It is worth noting that the above Figure 1 The switching circuit of this application is only illustrated schematically, but the application is not limited thereto. For example, the connection relationship between various modules or components can be appropriately adjusted, and other modules or components can be added or removed. Those skilled in the art can make appropriate modifications based on the above description, and are not limited to the above-described embodiments. Figure 1 The records.

[0039] Figure 2 This is a schematic diagram of a dead time generation circuit according to an embodiment of this application. The dead time generation circuit 104 generates the dead time between the high-side switch 101 and the low-side switch 102, wherein the dead time can be reflected in the output Ho and Lo signals.

[0040] like Figure 2 As shown, the dead time generation circuit 104 has:

[0041] Comparator 201 compares the drain voltage Vsw of the low-side switch 102 with a specified reference voltage V1;

[0042] D flip-flop 202 receives the comparison signal output by comparator 201 and outputs the comparison signal using the turn-on pulse signal of low-side switch 102 (e.g., the gate voltage signal Vg2) as the trigger clock signal (CLK).

[0043] The up / down counter 203 performs up / down counting based on the comparison signal output by the D flip-flop 202 and outputs an indication signal (e.g., Figure 2 (represented by o3~o0 in Chinese); and

[0044] The time constant circuit 204 generates the dead time according to the indicated signal.

[0045] It is worth noting that the above Figure 2The dead-time generation circuit of this application has only been illustrated schematically, but this application is not limited thereto. For example, the connection relationship between various modules or components can be appropriately adjusted, and other modules or components can be added or removed. Those skilled in the art can make appropriate modifications based on the above content, and are not limited to the above-described embodiments. Figure 2 The records.

[0046] In some embodiments, the specified reference voltage is zero volts, but this application is not limited thereto.

[0047] In some embodiments, the time constant circuit 204 includes at least a capacitor and a resistor; the time constant circuit 204 generates the dead time through an RC time constant formed by the capacitor and the resistor. For details regarding the RC circuit structure and the RC time constant, please refer to relevant technologies, which will not be elaborated here.

[0048] Figure 3 This is a schematic diagram of a time constant circuit according to an embodiment of this application, illustrating the configuration of some components. For example... Figure 3 As shown, the time constant circuit 204 may include a high-side portion 2041 and a low-side portion 2042, wherein the high-side portion 2041 is input with a high-side input signal Hin and outputs a high-side output signal Ho, and the low-side portion 2042 is input with a low-side input signal Lin and outputs a low-side output signal Lo.

[0049] like Figure 3 As shown, the high side 2041 may include a capacitor 301 and a plurality of (e.g., four) resistors 302, which have different resistance values ​​(e.g., 8R, 4R, 2R and R respectively). Each resistor 302 can be short-circuited by a corresponding switch 303, which is turned off or on according to an indication signal from the up / down counter 203.

[0050] Thus, by means of the indication signal, one or more of the switches 303 can be turned on, thereby short-circuiting one or more of the resistors 302, while others of the switches 303 are turned off, thereby changing the overall resistance value of the RC circuit structure in the high side 2041, and thus changing the RC time constant of the high side 2041.

[0051] like Figure 3 As shown, the low side 2042 may include a capacitor 304 and a plurality of (e.g., four) resistors 305, which may have different resistance values ​​(e.g., 8R, 4R, 2R and R respectively). Each resistor 305 may be short-circuited by a corresponding switch 306, which may be turned off or on according to an indication signal from the up / down counter 203.

[0052] Thus, by means of the indication signal, one or more of the switches 306 can be turned on, thereby short-circuiting one or more of the resistors 305, while others of the switches 305 are turned off, thereby changing the overall resistance value of the RC circuit structure in the lower side 2042, and thus changing the RC time constant of the lower side 2042.

[0053] Furthermore, the dead time between the high-side switch 101 and the low-side switch 102 can be generated and adjusted. In specific implementations, the dead time can be represented by the time offset of the waveforms of signals Ho and Lo; for details, please refer to relevant technologies.

[0054] It is worth noting that the above Figure 3 The time constant circuit of this application embodiment has only been illustrated schematically, but this application is not limited thereto. For example, the connection relationship between various modules or components can be appropriately adjusted, and other modules or components can be added or removed. Those skilled in the art can make appropriate modifications based on the above content, and are not limited to the above-described embodiments. Figure 3 The records.

[0055] In some embodiments, such as Figure 2 As shown, the up / down counter 203 also uses the turn-on pulse signal of the low-side switch 102 (e.g., the gate voltage signal Vg2) as the trigger clock signal (CLK); the indication signal includes multiple digital signals, which respectively indicate whether multiple resistors in the time constant circuit are used.

[0056] For example, such as Figure 3 As shown, the up / down counter 203 can output a 4-bit digital signal (as shown in o3 to o0). Furthermore, it can count up or count down. For more details on up / down counters, please refer to relevant technical documentation.

[0057] In some embodiments, the resistance value of the combined resistance of the multiple resistors included in the time constant circuit 204 is changed by the indication signal; and the dead time can be adjusted by changing the RC time constant formed by the capacitor and the multiple resistors.

[0058] Figure 4 This is an example diagram showing that the dead time in an embodiment of this application needs to be increased.

[0059] In some embodiments, when the drain voltage Vsw of the low-side switch 102 is greater than the reference voltage V1 (e.g., 0) (Vsw>0), the comparator 201 outputs a first signal (e.g., low level), the up-down counter 203 counts up according to the first signal (e.g., low level), and the time constant circuit 204 increases the resistance value according to the indication signal to increase the dead time.

[0060] Still with Figure 3 For example, Table 1 shows an example of dead time adjustment in an embodiment of this application, where 0 indicates that switch 303 or switch 306 is off, and 1 indicates that switch 303 or switch 306 is on. For example, if the indication signal is "0000", then all switches 303 are off, and all resistors 302 are not short-circuited. At this time, the combined resistance value is 8R + 4R + 2R + R = 15R.

[0061] Table 1

[0062]

[0063] The following is a schematic description of the up / down counter 203.

[0064] Assuming the current indicator signal is "1000", in the RC circuit structure of the high side 2041, the first switch of switch 303 is on (the corresponding resistor 8R is short-circuited), and the other three switches are off (the corresponding resistors 4R, 2R, and R are used). Therefore, the combined resistance value is 4R + 2R + R = 7R. In the RC circuit structure of the low side 2042, the first switch of switch 306 is on (the corresponding resistor 8R is short-circuited), and the other three switches are off (the corresponding resistors 4R, 2R, and R are used). Therefore, the combined resistance value is 4R + 2R + R = 7R.

[0065] For example, the up / down counter 203 counts up based on a first signal (e.g., a low level). For instance, if it changes from "1000" to "0111", the combined resistance value becomes 8R, the resistance value is increased, and the dead time is correspondingly increased. Furthermore, based on the trigger clock signal, it can change from "0111" to "0110", which changes the combined resistance value to 9R, the resistance value is increased, and the dead time continues to increase accordingly, and so on.

[0066] Figure 5 This is an example diagram illustrating how the dead time in an embodiment of this application needs to be reduced.

[0067] In some embodiments, when the drain voltage Vsw of the low-side switch 102 is less than the reference voltage (e.g., 0) (Vsw<0), the comparator 201 outputs a second signal (e.g., high level), the up-down counter 203 counts down according to the second signal (e.g., high level), and the time constant circuit 204 reduces the resistance value according to the indication signal to reduce the dead time.

[0068] Still with Figure 3 Taking Table 1 as an example, assuming the indicator signal is "1000" in the current state, in the RC circuit structure of the high side 2041, the first switch of switch 303 is on (the corresponding resistor 8R is short-circuited), and the other three switches are off (the corresponding resistors 4R, 2R, and R are used). Therefore, the combined resistance value is 4R + 2R + R = 7R. In the RC circuit structure of the low side 2042, the first switch of switch 306 is on (the corresponding resistor 8R is short-circuited), and the other three switches are off (the corresponding resistors 4R, 2R, and R are used). Therefore, the combined resistance value is 4R + 2R + R = 7R.

[0069] For example, the up / down counter 203 counts down based on a second signal (e.g., a high level), such as changing from "1000" to "1001", which changes the combined resistance value to 6R, thus reducing the resistance value and correspondingly decreasing the dead time. Furthermore, based on a trigger clock signal, it can change from "1001" to "1010", which changes the combined resistance value to 5R, further reducing the resistance value and continuing to decrease the dead time, and so on.

[0070] The above illustrations illustrate this application, but the application is not limited thereto. For example, the dead time can be increased when the drain voltage of the low-side switch is less than the reference voltage, and decreased when the drain voltage of the low-side switch is greater than the reference voltage, etc.; adjustments can be made according to the needs of the actual scenario. Furthermore, in the above example, the high-side portion 2041 and the low-side portion 2041 are adjusted in the same way according to the indication signal, but the application is not limited thereto. For example, the high-side portion 2041 and the low-side portion 2041 can also be adjusted independently of each other.

[0071] Therefore, the embodiments of this application, through digital logic circuits such as comparators, D flip-flops, and up / down counters, have a simple structure, low cost, and short computation time, enabling them to handle high-speed switching operations. Furthermore, this application can be applied to half-bridge and full-bridge circuits using ZVS circuits, for example, to LLC converter circuits above 1MHz, and to 6.78MHz wirelessly powered power amplifiers using magnetic resonance, etc.

[0072] In this embodiment, the scaling (increasing / decreasing) of the dead time can be determined by comparing the switching voltage of the low-side switch with the reference voltage, and the result can be reflected in the next dead time. For example, instead of real-time adjustment, it can be calculated and adjusted every cycle, ensuring that the logic circuit's calculation time is timely even under high-speed operation.

[0073] Furthermore, the D flip-flop can reflect the comparator's output in the up / down counter when the low-side switch is turned on. The up / down counter maintains the dead time length and adjusts the dead time based on the D flip-flop's output; the counter's output value is then reflected in the dead time generation circuit. This results in a simple structure and high accuracy.

[0074] The above embodiments are merely illustrative examples of embodiments of this application, but this application is not limited thereto, and appropriate modifications can be made based on the above embodiments. For example, the above embodiments can be used alone, or one or more of the above embodiments can be combined.

[0075] As can be seen from the above embodiments, the drain voltage of the low-side switch is compared with a predetermined reference voltage; the comparison signal output by the comparator is received, and the comparison signal is output using the turn-on pulse signal of the low-side switch as a trigger clock signal; the comparison signal is incremented or decremented according to the comparison signal output by the D flip-flop, and an indication signal is output; and the dead time is generated according to the indication signal. Therefore, not only can a better dead time be generated and adaptively adjusted, reducing switching losses and improving conversion efficiency, but the structure is also simple and low-cost, with short computation time, enabling it to handle high-speed switching operations.

[0076] Second aspect of the embodiments

[0077] This application also provides a dead-time generation method to generate the dead time between a high-side switch and a low-side switch. The second aspect's embodiment corresponds to the dead-time generation circuit described in the first aspect's embodiment, and the same content as the first aspect's embodiment will not be repeated here.

[0078] Figure 6 This is a schematic diagram of the dead time generation method according to an embodiment of this application, as shown below. Figure 6 As shown, the dead time generation method includes:

[0079] 601, compares the drain voltage of the low-side switch with a specified reference voltage;

[0080] 602, receives the comparison signal output by the comparator, and outputs the comparison signal using the turn-on pulse signal of the low-side switch as the trigger clock signal;

[0081] 603, perform addition and subtraction counting based on the comparison signal, and output an indication signal; and

[0082] 604, Generate the dead time according to the indicated signal.

[0083] It is worth noting that the above Figure 6 The embodiments described herein are merely illustrative and are not limited thereto. For example, the execution order of various operations can be appropriately adjusted, and additional operations can be added or some operations can be removed. Those skilled in the art can make appropriate modifications based on the above description, and are not limited to the above-described embodiments. Figure 6 The records.

[0084] In some embodiments, the method further includes: changing the resistance value of a plurality of resistors included in the time constant circuit by means of the indication signal; and adjusting the dead time by changing the RC time constant formed by the capacitor and the plurality of resistors.

[0085] The above embodiments are merely illustrative examples of embodiments of this application, but this application is not limited thereto, and appropriate modifications can be made based on the above embodiments. For example, the above embodiments can be used alone, or one or more of the above embodiments can be combined.

[0086] As can be seen from the above embodiments, the drain voltage of the low-side switch is compared with a predetermined reference voltage; the comparison signal output by the comparator is received, and the comparison signal is output using the turn-on pulse signal of the low-side switch as a trigger clock signal; the comparison signal is incremented or decremented according to the comparison signal output by the D flip-flop, and an indication signal is output; and the dead time is generated according to the indication signal. Therefore, not only can a better dead time be generated and adaptively adjusted, reducing switching losses and improving conversion efficiency, but the structure is also simple and low-cost, with short computation time, enabling it to handle high-speed switching operations.

[0087] The apparatus and methods described above in this application can be implemented in hardware or in combination with software. This application relates to a computer-readable program that, when executed by a logic component, enables the logic component to implement the apparatus or components described above, or to implement the various methods or steps described above. This application also relates to storage media for storing the above programs, such as hard disks, magnetic disks, optical disks, DVDs, flash memory, etc.

[0088] The methods / apparatus described in conjunction with the embodiments of this application can be directly embodied in hardware, software modules executed by a processor, or a combination of both. For example, one or more and / or combinations of one or more functional block diagrams shown in the figures can correspond to various software modules in a computer program flow, or to various hardware modules. These software modules can correspond to the various steps shown in the figures, respectively. These hardware modules can be implemented, for example, using a field-programmable gate array (FPGA) to embed these software modules.

[0089] The software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. A storage medium can be coupled to the processor, enabling the processor to read information from and write information to the storage medium; or the storage medium can be an integral part of the processor. The processor and storage medium can reside in an ASIC. The software module can be stored in the memory of a mobile terminal or in a memory card that can be inserted into the mobile terminal. For example, if the device (such as a mobile terminal) uses a high-capacity MEGA-SIM card or a high-capacity flash memory device, the software module can be stored in the MEGA-SIM card or the high-capacity flash memory device.

[0090] One or more and / or one or more combinations of functional blocks described in the accompanying drawings can be implemented as a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, or any suitable combination thereof for performing the functions described herein. One or more and / or one or more combinations of functional blocks described in the accompanying drawings can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in communication with a DSP, or any other such configuration.

[0091] The present application has been described above with reference to specific embodiments. However, those skilled in the art should understand that these descriptions are exemplary and not intended to limit the scope of protection of the present application. Those skilled in the art can make various modifications and variations to the present application based on its spirit and principles, and these modifications and variations are also within the scope of the present application.

Claims

1. A dead-time generation circuit that generates a dead-time between a high-side switch and a low-side switch, characterized by, The dead time generation circuit has: a comparator that compares a drain voltage of the low-side switch with a prescribed reference voltage; a D flip-flop that receives a comparison signal output by the comparator and outputs the comparison signal with a turn-on pulse signal of the low-side switch as a trigger clock signal; an add-subtract counter that adds and subtracts counts based on the comparison signal output by the D flip-flop and outputs an indication signal; and a time constant circuit that generates the dead time based on the indication signal. The add-subtract counter also uses the turn-on pulse signal of the low-side switch as a trigger clock signal, and the indication signal includes a plurality of digital signals that respectively indicate whether a plurality of resistors in the time constant circuit are used. The time constant circuit includes at least a capacitor and a resistor, and generates the dead time by an RC time constant formed by the capacitor and the resistor.

2. The dead time generation circuit of claim 1, wherein, The resistance values of a plurality of resistors included in the time constant circuit are changed by the indication signal, and the dead time is adjusted by changing an RC time constant formed by a capacitor and the plurality of resistors.

3. Dead time generation circuitry as claimed in claim 1 or 2, wherein, The comparator outputs a first signal when the drain voltage of the low-side switch is greater than the reference voltage, the add-subtract counter counts up based on the first signal, and the time constant circuit increases the resistance values based on the indication signal to increase the dead time.

4. The dead time generation circuit of claim 3, wherein, The comparator outputs a second signal when the drain voltage of the low-side switch is less than the reference voltage, the add-subtract counter counts down based on the second signal, and the time constant circuit decreases the resistance values based on the indication signal to decrease the dead time.

5. The dead time generation circuit of claim 3, wherein, The switching circuit further includes the dead time generation circuit according to any one of claims 1 to 5.

6. A switching circuit comprising a high-side switch and a low-side switch, the drain of the high-side switch and the drain of the low-side switch being connected, characterized in that, The dead time generation method includes:

7. A dead-time generation method of generating a dead-time between a high-side switch and a low-side switch, characterized by, comparing a drain voltage of the low-side switch with a prescribed reference voltage; receiving a comparison signal output by the comparator and outputting the comparison signal with a turn-on pulse signal of the low-side switch as a trigger clock signal; adding and subtracting counts based on the comparison signal and outputting an indication signal; and generating the dead time based on the indication signal. The turn-on pulse signal of the low-side switch is used as a trigger clock signal, and the indication signal includes a plurality of digital signals that respectively indicate whether a plurality of resistors in the time constant circuit are used. The method further includes:

8. The dead time generation method of claim 7, wherein, changing resistance values of a plurality of resistors included in the time constant circuit by the indication signal; and adjusting the dead time by changing an RC time constant formed by a capacitor and the plurality of resistors. ​

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