Memory device, semiconductor structure and method for forming the same

Abstract

The present disclosure provides a storage device, a semiconductor structure and a method for forming the same, and relates to the field of semiconductor technology. The formation method includes: providing a substrate; forming an insulating dielectric layer on the substrate, the insulating dielectric layer at least including a sacrificial film layer; forming a mask layer on the surface of the sacrificial film layer, the etching rate of the mask layer being greater than the etching rate of the sacrificial film layer; etching the insulating dielectric layer using the mask layer as a mask to form a plurality of capacitor holes in the insulating dielectric layer that expose the substrate respectively; removing the mask layer using an etching process; and forming a lower electrode layer of a columnar capacitor in each capacitor hole. The formation method of the semiconductor structure disclosed in the present disclosure can ensure the etching height of the capacitor hole and increase the charge storage capacity.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a memory device, a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration and fast transmission speed. Capacitors are the core components of dynamic random access memory and are mainly used to store charges.

[0003] Generally, in the process of manufacturing capacitors, it is necessary to form a stacked film layer on a substrate, etch a capacitor hole in the stacked film layer, and then form a capacitor in the capacitor hole. However, in the process of etching to form the capacitor hole, it is easy to damage the surface of the stacked film layer, so that the thickness of the stacked film layer is reduced, and then the height of the capacitor hole formed in the stacked film layer is reduced, resulting in a decrease in the height of the capacitor formed therein and a decrease in the charge storage capacity.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to overcome the deficiencies in the above-mentioned prior art and to provide a storage device, a semiconductor structure and a method for forming the same, which can ensure the etching height of the capacitor hole and improve the charge storage capacity.

[0006] According to one aspect of the present disclosure, there is provided a method for forming a semiconductor structure, comprising:

[0007] providing a substrate;

[0008] forming an insulating dielectric layer on the substrate, wherein the insulating dielectric layer at least comprises a sacrificial film layer;

[0009] forming a mask layer on the surface of the sacrificial film layer, wherein an etching rate of the mask layer is greater than an etching rate of the sacrificial film layer;

[0010] Etching the insulating dielectric layer using the mask layer as a mask to form a plurality of capacitor holes in the insulating dielectric layer that respectively expose the substrate;

[0011] Removing the mask layer by an etching process;

[0012] A lower electrode layer of a columnar capacitor is formed in each of the capacitor holes.

[0013] In an exemplary embodiment of the present disclosure, an etching selectivity ratio of the mask layer and the sacrificial film layer is greater than or equal to 20.

[0014] In an exemplary embodiment of the present disclosure, removing the mask layer by an etching process includes:

[0015] The mask layer is dry-etched using chlorine gas.

[0016] In an exemplary embodiment of the present disclosure, the material of the mask layer is polysilicon, and the material of the sacrificial film layer is silicon oxide.

[0017] In an exemplary embodiment of the present disclosure, the lower electrode layer forming the columnar capacitor in each of the capacitor holes includes:

[0018] Forming a conductive layer on the surface of the sacrificial film layer, wherein the conductive layer fills the capacitor holes;

[0019] The conductive layer is etched back to form a lower electrode layer of a columnar capacitor in each of the capacitor holes, and the top of the lower electrode layer protrudes from the surface of the sacrificial film layer.

[0020] In an exemplary embodiment of the present disclosure, the insulating dielectric layer includes a first supporting layer, a first sacrificial layer, and a second supporting layer stacked and distributed in a direction perpendicular to the substrate, the sacrificial film layer is located on a surface of the second supporting layer, and the forming method further includes:

[0021] A third supporting layer is formed on the surface of the sacrificial film layer, and the third supporting layer surrounds the outer periphery of the lower electrode layer.

[0022] In an exemplary embodiment of the present disclosure, the forming method further includes:

[0023] The sacrificial film layer and the first sacrificial layer are removed.

[0024] In an exemplary embodiment of the present disclosure, a third supporting layer is formed on the surface of the sacrificial film layer, and the third supporting layer surrounds the outer periphery of the lower electrode layer, including:

[0025] forming an electrode support layer on the surface of the structure formed by the sacrificial film layer and the lower electrode layer;

[0026] The electrode support layer located on the top of the lower electrode layer is removed to form a third support layer surrounding the side wall of the lower electrode layer.

[0027] In an exemplary embodiment of the present disclosure, removing the sacrificial film layer and the first sacrificial layer includes:

[0028] Forming an etched via in a stacked area of ​​the first sacrificial layer, the second supporting layer, the sacrificial film layer and the third supporting layer, wherein the etched via at least penetrates the third supporting layer, the sacrificial film layer and the second supporting layer;

[0029] The first sacrificial layer and the sacrificial film layer are etched at the etching vias to remove the first sacrificial layer and the sacrificial film layer.

[0030] In an exemplary embodiment of the present disclosure, removing the sacrificial film layer and the first sacrificial layer includes:

[0031] Using a first etching process to etch the electrode support layer in a stacking area of ​​the first sacrificial layer, the second support layer, the sacrificial film layer, and the electrode support layer to form a first via hole, wherein the first via hole penetrates the electrode support layer and exposes the sacrificial film layer;

[0032] Using a second etching process to etch the sacrificial film layer at the first via hole to remove the sacrificial film layer and expose the second supporting layer;

[0033] Etching the second supporting layer using the first etching process to form a second via hole, wherein the second via hole penetrates the second supporting layer and exposes the first sacrificial layer;

[0034] The first sacrificial layer is etched at the second via hole using the second etching process to remove the first sacrificial layer.

[0035] In an exemplary embodiment of the present disclosure, the first etching process is a dry etching process, and the second etching process is a wet etching process.

[0036] In an exemplary embodiment of the present disclosure, the forming method further includes:

[0037] forming an interlayer dielectric layer on a surface of a structure composed of a lower electrode layer of the columnar capacitor, the first supporting layer, the second supporting layer and the third supporting layer;

[0038] An upper electrode layer is formed on the surface of the interlayer dielectric layer.

[0039] In an exemplary embodiment of the present disclosure, the substrate includes a plurality of conductive contact plugs distributed at intervals, and each of the conductive contact plugs is connected to each of the lower electrode layers in a one-to-one correspondence.

[0040] According to one aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure is formed by any of the above-mentioned methods for forming a semiconductor structure.

[0041] According to one aspect of the present disclosure, a memory device is provided, comprising any of the semiconductor structures described above.

[0042] The memory device, semiconductor structure and formation method disclosed herein, because the etching rate of the mask layer is greater than the etching rate of the sacrificial film layer, the surface damage to the sacrificial film layer is small when the mask layer is removed by etching. After the mask layer is removed, the thickness of the sacrificial film layer will not be greatly reduced, and the height of the capacitor hole finally formed will be less affected, which can ensure that the height of the lower electrode layer of the columnar capacitor formed in the capacitor hole will not be reduced, thereby increasing the capacitor storage capacity. At the same time, by forming columnar capacitors in multiple capacitor holes, multiple columnar capacitors can collect charges at the same time during use, further increasing the capacitor storage capacity.

[0043] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0045] Figure 1 FIG. 1 is a schematic diagram of a structure before a capacitor hole is formed in the related art.

[0046] Figure 2 Schematic diagram of a capacitor hole in a semiconductor structure in the related art.

[0047] Figure 3 The present invention is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0048] Figure 4 This is a schematic diagram after completing step S130 in the embodiment of the present disclosure.

[0049] Figure 5 This is a schematic diagram after completing step S140 in the embodiment of the present disclosure.

[0050] Figure 6 This is a schematic diagram after completing step S150 in the embodiment of the present disclosure.

[0051] Figure 7 This is a schematic diagram after completing step S160 in the embodiment of the present disclosure.

[0052] Figure 8 Flow chart of step S160 in the embodiment of the present disclosure.

[0053] Fig. 9 This is a schematic diagram after completing step S1601 in the implementation manner of the present disclosure.

[0054] Fig.10 The present invention is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0055] Fig.11 Flow chart of step S170 in the embodiment of the present disclosure.

[0056] Fig.12 This is a schematic diagram after completing step S210 in the embodiment of the present disclosure.

[0057] Fig.13 This is a schematic diagram after completing step S180 in the implementation manner of the present disclosure.

[0058] Fig.14 This is a flowchart of step S180 in one implementation of the present disclosure.

[0059] Fig.15 Schematic diagram of a photoresist layer in an embodiment of the present disclosure.

[0060] Fig.16 This is a flowchart of step S180 in another implementation manner of the present disclosure.

[0061] Fig.17 This is a schematic diagram after completing step S410 in the embodiment of the present disclosure.

[0062] Fig.18 This is a schematic diagram after completing step S420 in the implementation manner of the present disclosure.

[0063] Fig.19 This is a schematic diagram after completing step S430 in the implementation manner of the present disclosure.

[0064] In the figure: 100, substrate; 210, first supporting layer; 220, first sacrificial layer; 230, second supporting layer; 240, second sacrificial layer; 250, third supporting layer; 300, mask layer; 400, capacitor hole; 1, substrate; 11, conductive contact plug; 2, insulating dielectric layer; 21, first supporting layer; 22, first sacrificial layer; 23, second supporting layer; 24, sacrificial film layer; 25, third supporting layer; 250, electrode supporting layer; 2510, first via hole; 2520, second via hole; 201, capacitor hole; 3, mask layer; 201, capacitor hole; 4, lower electrode layer; 41, conductive layer; 5, photoresist layer; 51, developing area. DETAILED DESCRIPTION

[0065] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0066] The features, structures or characteristics described above may be combined in one or more embodiments in any suitable manner, and if possible, the features discussed in each embodiment are interchangeable. In the above description, many specific details are provided to provide a full understanding of the embodiments of the present invention. However, those skilled in the art will appreciate that the technical solution of the present invention may be practiced without one or more of the specific details, or other methods, materials, etc. may be adopted. In other cases, known structures, materials or operations are not shown or described in detail to avoid blurring various aspects of the present invention.

[0067] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0068] The terms "a", "an", "the", "said", "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc. The terms "first", "second", and "third" are used only as labels and are not intended to limit the quantity of their objects.

[0069] In the related art, the semiconductor structure mainly includes a substrate 100, a columnar capacitor and a support structure formed on the periphery of the columnar capacitor. Figure 1 As shown, it is necessary to form a first supporting layer 210, a first sacrificial layer 220, a second supporting layer 230, a second sacrificial layer 240 and a third supporting layer 250 stacked and distributed along a direction perpendicular to the substrate 100 on the substrate 100, and the first supporting layer 210, the first sacrificial layer 220, the second supporting layer 230, the second sacrificial layer 240 and the third supporting layer 250 are etched to form a capacitor hole 400, as shown in FIG. Figure 2As shown. In the process of etching to form the capacitor hole 400, it is necessary to form a mask layer 300 on the surface of the third support layer 250. After the capacitor hole 400 is etched, the mask layer 300 needs to be removed. However, in the process of removing the mask layer 300, usually because the etching rates of the materials of the mask layer 300 and the third support layer 250 are similar, it is easy to remove part of the third support layer 250 at the same time in the process of etching and removing the mask layer 300, so that the thickness of the third support layer 250 is reduced, and then the height of the capacitor hole 400 is reduced (that is, H2 < H1 in the figure), so that the height of the capacitor finally formed is reduced, and the capacitor storage capacity is reduced.

[0070] The present disclosure provides a method for forming a semiconductor structure. For example, the semiconductor structure may be a capacitor, such as Figure 3 As shown, the forming method may include:

[0071] Step S110, providing a substrate;

[0072] Step S120, forming an insulating dielectric layer on the substrate, wherein the insulating dielectric layer at least includes a sacrificial film layer;

[0073] Step S130, forming a mask layer on the surface of the sacrificial film layer, wherein an etching rate of the mask layer is greater than an etching rate of the sacrificial film layer;

[0074] Step S140, etching the insulating dielectric layer using the mask layer as a mask to form a plurality of capacitor holes in the insulating dielectric layer that respectively expose the substrate;

[0075] Step S150, removing the mask layer by an etching process;

[0076] Step S160, forming a lower electrode layer of a columnar capacitor in each of the capacitor holes.

[0077] In the method for forming a semiconductor structure disclosed in the present invention, since the etching rate of the mask layer is greater than the etching rate of the sacrificial film layer, the surface damage to the sacrificial film layer is small when the mask layer is removed by etching. After the mask layer is removed, the thickness of the sacrificial film layer will not be greatly reduced, and the height of the capacitor hole finally formed will be less affected, which can ensure that the height of the lower electrode layer of the columnar capacitor formed in the capacitor hole will not be reduced, thereby increasing the capacitor storage capacity. At the same time, by forming columnar capacitors in multiple capacitor holes, multiple columnar capacitors can collect charges at the same time during use, further increasing the capacitor storage capacity.

[0078] The following is a detailed description of each step of the method for forming a semiconductor structure according to an embodiment of the present disclosure:

[0079] In step S110 , a substrate is provided.

[0080] like Figure 4 As shown, the substrate 1 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be silicon or other semiconductor materials. The shape and material of the substrate 1 are not particularly limited herein.

[0081] A plurality of conductive contact plugs 11 distributed at intervals may be formed on the substrate 1. The conductive contact plugs 11 may be distributed in an array and may be made of a conductor or semiconductor material, for example, tungsten, copper or polysilicon.

[0082] For example, the substrate 1 may be provided with a plurality of vias distributed in an array, each of which may be a through hole, and a conductive contact plug 11 may be formed in the via. For example, the conductive contact plug 11 may be formed in the via by vacuum evaporation, magnetron sputtering or chemical vapor deposition. Of course, the conductive contact plug 11 may also be formed by other methods, which are not listed here one by one.

[0083] In step S120, an insulating dielectric layer is formed on the substrate, wherein the insulating dielectric layer at least includes a sacrificial film layer.

[0084] An insulating dielectric layer 2 may be formed on the surface of the substrate 1, and the insulating dielectric layer 2 may cover each conductive contact plug 11. The insulating dielectric layer 2 may be made of an insulating material, for example, silicon oxide, silicon nitride or SiCN. The insulating dielectric layer 2 may include a single film layer or a multi-layer film layer, which is not particularly limited here. In one embodiment, the insulating dielectric layer 2 may include at least a sacrificial film layer 24. Of course, the insulating dielectric layer 2 may also include other film layers, which are not particularly limited here. For example, the insulating dielectric layer 2 may also include a first supporting layer 21, a first sacrificial layer 22 and a second supporting layer 23 stacked and distributed in a direction perpendicular to the substrate 1.

[0085] The first supporting layer 21, the first sacrificial layer 22, the second supporting layer 23 and the sacrificial film layer 24 may be formed on the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the stacked first supporting layer 21, the first sacrificial layer 22, the second supporting layer 23 and the sacrificial film layer 24 may also be formed by other methods, which are not listed here one by one.

[0086] In an exemplary embodiment of the present disclosure, a first supporting layer 21 may be formed on the surface of the substrate 1 and may cover each conductive contact plug 11, and the material of the first supporting layer 21 may be silicon nitride or SiCN; a first sacrificial layer 22 may be formed on the surface of the first supporting layer 21 facing away from the substrate 1, and the material of the first sacrificial layer 22 may be SiO2; a second supporting layer 23 may be formed on the surface of the first sacrificial layer 22 facing away from the substrate 1, and the material of the first supporting layer 21 may be the same; a sacrificial film layer 24 may be formed on the surface of the second supporting layer 23 facing away from the substrate 1, and the material of the first sacrificial layer 22 may be the same, for example, the material of the first sacrificial layer 22 may be silicon oxide.

[0087] In step S130, a mask layer is formed on the surface of the sacrificial film layer, and an etching rate of the mask layer is greater than an etching rate of the sacrificial film layer.

[0088] The mask layer 3 may be formed on the side of the sacrificial film layer 24 away from the substrate 1 by chemical vapor deposition, vacuum evaporation, atomic layer deposition or other methods. The mask layer 3 may have multiple layers or a single layer structure, and its material may be at least one of polysilicon, SiO2, SiN, TaN and TiN. Of course, it may also be other materials, which are not listed here. In one embodiment, the mask layer 3 may be a single layer structure, and its material may be polysilicon.

[0089] A photoresist layer can be formed on the surface of the mask layer 3 facing away from the substrate 1 by spin coating or other methods. The material of the photoresist layer can be a positive photoresist or a negative photoresist, which is not particularly limited here. The photoresist layer can be exposed using a mask, and the pattern of the mask can match the pattern required for the sacrificial film layer 24. Subsequently, the exposed photoresist layer can be developed to form a plurality of development areas, each of which can expose the mask layer 3, and the pattern of the development area can be the same as the pattern required for the sacrificial film layer 24, and the width of the development area can be the same as the size of the required capacitor hole.

[0090] The mask layer 3 can be etched in the developing area by a plasma etching process, and the sacrificial film layer 24 can be exposed in the etched area, thereby forming a desired mask pattern on the mask layer 3. It should be noted that after completing the above etching process, the photoresist layer can be removed by cleaning with a cleaning solution or by ashing or other processes, so that the mask layer 3 is no longer covered by the photoresist layer, and a hard mask structure is obtained. Figure 4 The structure after step S130 in the embodiment of the formation method disclosed herein is shown.

[0091] In an exemplary embodiment of the present disclosure, the etching rate of the mask layer 3 may be greater than the etching rate of the sacrificial film layer 24, thereby reducing the damage to the sacrificial film layer 24 during the etching process when the mask layer 3 is removed by etching, and the thickness of the sacrificial film layer 24 will not be significantly reduced after the mask layer 3 is removed. For example, the etching selectivity ratio of the mask layer 3 and the sacrificial film layer 24 may be greater than or equal to 20. For example, the etching selectivity ratio of the mask layer 3 and the sacrificial film layer 24 may be 20, 30, 40, 50 or 60. Of course, it may also be other etching selectivity ratios, which are not listed here one by one. Taking the etching selectivity ratio of the mask layer 3 and the sacrificial film layer 24 as 20 as an example, for every etching removal of 20nm thick mask layer 3, 1nm thick sacrificial film layer 24 can be etched away at the same time.

[0092] It should be noted that the larger the etching selectivity ratio of the mask layer 3 to the sacrificial film layer 24, the better, thereby ensuring that the damage caused to the surface of the sacrificial film layer 24 during the etching process of removing the mask layer 3 can be ignored, so that the thickness of the sacrificial film layer 24 will not be affected during the removal of the mask layer 3. In the embodiment of the present disclosure, the material type of the mask layer 3 and the sacrificial film layer 24 and the type of etching gas can be controlled to make the mask layer 3 and the sacrificial film layer 24 have a larger etching selectivity ratio. Preferably, the material of the mask layer 3 is polysilicon, the material of the sacrificial film layer 24 is silicon oxide, and the etching gas is chlorine.

[0093] In step S140, the insulating dielectric layer is etched using the mask layer as a mask to form a plurality of capacitor holes in the insulating dielectric layer that expose the substrate respectively.

[0094] like Figure 5 As shown, the insulating dielectric layer 2 can be anisotropically etched according to the mask pattern. For example, the substrate 1 can be used as an etching stop layer, and the insulating dielectric layer 2 can be etched in the developing area of ​​the mask pattern by a dry etching process to form a plurality of capacitor holes 201 in the insulating dielectric layer 2 that respectively expose the substrate 1.

[0095] In the direction parallel to the substrate 1, the cross section of the capacitor hole 201 may be circular, elliptical, rectangular or irregular, which is not particularly limited here. The number of capacitor holes 201 may be the same as the number of conductive contact plugs 11, and each capacitor hole 201 may expose each conductive contact plug 11 one by one.

[0096] In step S150, the mask layer is removed by an etching process.

[0097] After forming each capacitor hole 201, the mask layer 3 located on the surface of the sacrificial film layer 24 can be removed. For example, the mask layer 3 can be etched by a dry etching process, for example, the mask layer 3 can be dry-etched by chlorine gas. Specifically, the material of the mask layer 3 is polysilicon, and the material of the sacrificial film layer 24 is silicon oxide. The polysilicon in the mask layer 3 can be selectively etched by chlorine gas without damaging the silicon oxide surface in the sacrificial film layer 24, and the thickness of the sacrificial film layer 24 will not be reduced. It can be ensured that the height of the capacitor hole 201 formed by etching will not be reduced due to the reduction of the thickness of the sacrificial film layer 24. Figure 6 The structure after step S150 in the embodiment of the formation method disclosed herein is shown.

[0098] In step S160, a lower electrode layer of a columnar capacitor is formed in each of the capacitor holes.

[0099] Conductive materials may be filled in each capacitor hole 201 to form the lower electrode layer 4 of the columnar capacitor. The lower electrode layer 4 may fill each capacitor hole 201 and be connected to each conductive contact plug 11 exposed in each capacitor hole 201 in a one-to-one correspondence, so that the charges collected in the columnar capacitor can be stored through each conductive contact plug 11. The conductive material may be a metal material or a non-metal material with strong conductive properties. For example, the material may be titanium nitride or tungsten, which is not particularly limited here. Figure 7 The structure after step S160 in the embodiment of the formation method of the present disclosure is completed is shown.

[0100] In one embodiment of the present disclosure, Figure 8 As shown, a lower electrode layer 4 of a columnar capacitor is formed in each of the capacitor holes 201, that is, step S160 may include steps S1601-S1602, wherein:

[0101] Step S1601, forming a conductive layer on the surface of the sacrificial film layer, wherein the conductive layer fills the capacitor holes.

[0102] Conductive material can be deposited on the surface of the sacrificial film layer 24 by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition, thereby forming a conductive layer 41; in this process, the conductive layer 41 can fill each capacitor hole 201 and contact and connect with each conductive contact plug 11 exposed in each capacitor hole 201. The conductive material can be titanium nitride. Of course, the conductive material can also be other materials with strong conductive function, which will not be listed here one by one. Fig. 9 The structure after step S1601 in the embodiment of the formation method of the present disclosure is completed is shown.

[0103] Step S1602, etching back the conductive layer to form a lower electrode layer of a columnar capacitor in each of the capacitor holes, wherein the top of the lower electrode layer protrudes from the surface of the sacrificial film layer.

[0104] The surface of the conductive layer 41 can be etched by etching back to remove the conductive layer 41 located on the top surface of the sacrificial film layer 24, and only the conductive layer 41 that is opposite to the area where the capacitor hole 201 is located is retained, thereby forming the lower electrode layer 4 of the columnar capacitor that fills each capacitor hole 201. In this process, since the conductive layer 41 is formed on the surface of the sacrificial film layer 24, after removing the excess portion of the conductive layer 41, the top of the conductive layer 41 that is opposite to the area where the capacitor hole 201 is located can protrude from the surface of the sacrificial film layer 24, thereby making the lower electrode layer 4 of the finally formed columnar capacitor protrude from the surface of the sacrificial film layer 24, which can increase the height of the lower electrode layer 4 of the columnar capacitor, and help to improve the capacitor storage capacity.

[0105] In an exemplary embodiment of the present disclosure, Fig.10 As shown, the method for forming a semiconductor structure disclosed in the present invention may further include:

[0106] Step S170 , forming a third supporting layer on the surface of the sacrificial film layer, wherein the third supporting layer surrounds the outer periphery of the lower electrode layer.

[0107] A third supporting layer 25 surrounding the outer periphery of the lower electrode layer 4 of the columnar capacitor can be formed on the surface of the sacrificial film layer 24, and the top of the lower electrode layer 4 of the columnar capacitor can be supported by the third supporting layer 25 to prevent the top of the lower electrode layer 4 of the columnar capacitor from being deformed due to external force or subsequent processes.

[0108] In an exemplary embodiment of the present disclosure, a third supporting layer 25 is formed on the surface of the sacrificial film layer 24, and the third supporting layer 25 surrounds the outer periphery of the lower electrode layer 4, that is, step S170 may include steps S210 and S220. Fig.11 As shown, where:

[0109] Step S210 , forming an electrode support layer on the surface of the structure formed by the sacrificial film layer and the lower electrode layer.

[0110] like Fig.12 As shown, an electrode support layer 250 may be formed on the surface of the structure formed by the sacrificial film layer 24 and the lower electrode layer 4 of the columnar capacitor. The electrode support layer 250 may be a thin film covering the surface of the sacrificial film layer 24 and the lower electrode layer 4 of the columnar capacitor, or a coating covering the surface of the sacrificial film layer 24 and the lower electrode layer 4 of the columnar capacitor, which is not particularly limited herein. For example, the electrode support layer 250 may be formed on the surface of the structure formed by the sacrificial film layer 24 and the lower electrode layer 4 of the columnar capacitor by chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0111] The electrode support layer 250 may be made of an insulating material so that the lower electrode layers 4 of two adjacent columnar capacitors are insulated and isolated by the electrode support layer 250 to prevent short circuits between the lower electrode layers 4 of the two adjacent columnar capacitors and improve product yield. For example, the material of the electrode support layer 250 may be the same as that of the first support layer 21 and / or the second support layer 23, for example, the material may be silicon nitride.

[0112] Step S220: removing the electrode support layer located on the top of the lower electrode layer to form a third support layer surrounding the side wall of the lower electrode layer.

[0113] The electrode support layer 250 located on the top of the lower electrode layer 4 of the columnar capacitor can be removed to expose the top of the lower electrode layer 4 of the columnar capacitor, which can increase the contact area between the lower electrode layer 4 of the columnar capacitor and other surrounding structures, and help the lower electrode layer 4 of the columnar capacitor collect charges.

[0114] In an exemplary embodiment of the present disclosure, the method for forming a semiconductor structure of the present disclosure may further include:

[0115] Step S180: removing the sacrificial film layer and the first sacrificial layer.

[0116] The sacrificial film layer 24 and the first sacrificial layer 22 can be removed by a wet etching process, so that the insulating dielectric layer 2 finally formed is composed of the remaining first support layer 21, the second support layer 23 and the third support layer 25. The bottom of the lower electrode layer 4 of the columnar capacitor can be laterally supported by the first support layer 21 to prevent the bottom of the lower electrode layer 4 of the columnar capacitor from collapsing; the second support layer 23 is coated on the periphery of the lower electrode layer 4 of the columnar capacitor and is located in the middle of the lower electrode layer 4 of the columnar capacitor. The middle of the lower electrode layer 4 of the columnar capacitor can be laterally supported by the second support layer 23 to prevent the middle of the lower electrode layer 4 of the columnar capacitor from deforming and short-circuiting; the third support layer 25 is coated on the periphery of the lower electrode layer 4 of the columnar capacitor and is located at the top of the lower electrode layer 4 of the columnar capacitor. The top of the lower electrode layer 4 of the columnar capacitor is supported by the third support layer 25 to prevent the top of the lower electrode layer 4 of the columnar capacitor from deforming under the action of external force or subsequent processes. The structure after completing step S180 is as follows. Fig.13 shown.

[0117] In one embodiment of the present disclosure, Fig.14 As shown, step S180 may include steps S310 to S320, wherein:

[0118] Step S310 , forming an etching via in a stacked area of ​​the first sacrificial layer, the second supporting layer, the sacrificial film layer, and the third supporting layer, wherein the etching via at least penetrates the third supporting layer, the sacrificial film layer, and the second supporting layer.

[0119] A photoresist layer 5 may be formed on the surface of the third supporting layer 25, and the photoresist layer 5 may be exposed and developed to form a developing area 51, and the developing area 51 may at least overlap with the area where the first sacrificial layer 22, the second supporting layer 23, the sacrificial film layer 24 and the third supporting layer 25 are stacked together. Fig.15 As shown. The first etching process can be used to etch the third support layer 25, the sacrificial film layer 24, the second support layer 23 and the first sacrificial layer 22 in the developing area 51 to form an etched via. It should be noted that during the etching process, the first sacrificial layer 22 can be directly etched through, or the etched via can at least penetrate the second support layer 23, the sacrificial film layer 24 and the third support layer 25; that is, the etched via can at least etch through the third support layer 25, the sacrificial film layer 24 and the second support layer 23, thereby exposing the first sacrificial layer 22, which is not specifically limited here.

[0120] For example, the first etching process may be a dry etching process, and chlorine and oxygen may be used as etching gases for dry etching. During the dry etching process, the ratio of chlorine and oxygen may be adjusted according to actual needs, thereby achieving the purpose of controlling the etching rate.

[0121] Step S320 , etching the first sacrificial layer and the sacrificial film layer at the etching via hole to remove the first sacrificial layer and the sacrificial film layer.

[0122] The first sacrificial layer 22 and the remaining sacrificial film layer 24 may be etched at the etching via by a second etching process to remove the first sacrificial layer 22 and the sacrificial film layer 24. The second etching process may be a wet etching process, that is, the first sacrificial layer 22 and the remaining sacrificial film layer 24 may be removed by a wet etching process. For example, an acidic solution may be used to selectively etch the first sacrificial layer 22 and the sacrificial film layer 24. The acidic solution may be hydrofluoric acid, for example, it may be buffered hydrofluoric acid (BHF), hydrofluoric acid with a concentration of 49%, or dilute hydrofluoric acid (DHF). When DHF is used as the acidic solution, the ratio of hydrofluoric acid to deionized water may be 1:1 to 1:10, and no special limitation is made to the ratio and concentration of the acidic solution.

[0123] In another embodiment of the present disclosure, the third support layer 25 may be formed during the process of removing the first sacrificial layer 22 and the sacrificial film layer 24. In this embodiment, Fig.16 As shown, the sacrificial film layer 24 and the first sacrificial layer 22 are removed, that is, step S180 may include steps S410 to S440, wherein:

[0124] Step S410, using a first etching process to etch the electrode support layer in the stacking area of ​​the first sacrificial layer, the second support layer, the sacrificial film layer and the electrode support layer to form a first via hole, wherein the first via hole penetrates the electrode support layer and exposes the sacrificial film layer.

[0125] A photoresist layer 5 may be formed on the surface of the electrode support layer 250 , and the photoresist layer 5 may be exposed and developed to form a development area 51 , which may at least overlap with the area where the first sacrificial layer 22 , the second support layer 23 , the sacrificial film layer 24 and the electrode support layer 250 are stacked together.

[0126] The electrode support layer 250 may be etched in the developing area 51 by a first etching process to form a first via hole 2150. The first via hole 2510 may penetrate the electrode support layer 250 and expose the sacrificial film layer 24. The first etching process may be a dry etching process, and chlorine and oxygen may be used as etching gases for dry etching. During the dry etching process, the ratio of chlorine and oxygen may be adjusted according to actual needs, thereby achieving the purpose of controlling the etching rate. The structure after completing step S410 is as shown in FIG. Fig.17 shown.

[0127] Step S420: using a second etching process to etch the sacrificial film layer at the first via hole to remove the sacrificial film layer and expose the second supporting layer.

[0128] The sacrificial film layer 24 may be etched at the first via hole 2510 to remove the sacrificial film layer 24, thereby exposing the second support layer 23 located below the sacrificial film layer 24. For example, the sacrificial film layer 24 may be etched using a second etching process, and the second etching process may be a wet etching process, that is, the sacrificial film layer 24 may be removed using a wet etching process. The structure after completing step S420 is as follows: Fig.18 As shown. For example, an acidic solution may be used to etch the sacrificial film layer 24. The acidic solution may be hydrofluoric acid, for example, buffered hydrofluoric acid (BHF), hydrofluoric acid with a concentration of 49%, or dilute hydrofluoric acid (DHF). When DHF is used as the acidic solution, the ratio of hydrofluoric acid to deionized water may be 1:1 to 1:10. The ratio and concentration of the acidic solution are not particularly limited.

[0129] Step S430: Etching the second supporting layer using the first etching process to form a second via hole, wherein the second via hole penetrates the second supporting layer and exposes the first sacrificial layer.

[0130] The second supporting layer 23 may be etched using the first etching process to form a second via hole 2520. The second via hole 2520 may penetrate the second supporting layer 23 and expose the first sacrificial layer 22. The specific etching details of the first etching process may refer to the etching details of the first etching process in the etching process of the third supporting layer 25, which will not be described in detail here. The structure after completing step S430 is as follows: Fig.19 shown.

[0131] Step S440: using the second etching process to etch the first sacrificial layer at the second via hole to remove the first sacrificial layer.

[0132] The first sacrificial layer 22 may be etched at the second via hole to remove the first sacrificial layer 22, thereby exposing the first supporting layer 21 below the first sacrificial layer 22. For example, the first sacrificial layer 22 may be etched using a second etching process, and the specific details of the second etching process may refer to the etching details of the second etching process in the etching process of the first sacrificial layer 22, which will not be described in detail herein.

[0133] In an exemplary embodiment of the present disclosure, the method for forming a semiconductor structure of the present disclosure may further include step S190 and step S200, wherein:

[0134] Step S190 , forming an interlayer dielectric layer on the surface of the structure formed by the lower electrode layer of the columnar capacitor, the first supporting layer, the second supporting layer and the third supporting layer.

[0135] An interlayer dielectric layer can be formed on the inner surface and outer surface of the structure composed of the lower electrode layer 4, the first support layer 21, the second support layer 23 and the third support layer 25 of the columnar capacitor. For example, the interlayer dielectric layer can be a thin film formed on the inner surface and outer surface of the structure composed of the lower electrode layer 4, the first support layer 21, the second support layer 23 and the third support layer 25 of the columnar capacitor. The interlayer dielectric layer can be formed by vacuum evaporation or magnetron sputtering. Of course, the interlayer dielectric layer can also be formed by other processes, which are not listed here. The interlayer dielectric layer can be a single-layer film structure composed of the same material, or a mixed film layer structure composed of film layers of different materials. For example, it can include a material with a higher dielectric constant, for example, it can be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide or a mixture thereof. Of course, it can also be other materials, which are not listed here.

[0136] Step S200: forming an upper electrode layer on the surface of the interlayer dielectric layer.

[0137] The upper electrode layer can be formed on the surface of the interlayer dielectric layer by chemical vapor deposition process. Of course, the upper electrode layer can also be formed by other processes, which are not specifically limited here. The material of the upper electrode layer can be titanium nitride, of course, it can also be other materials, which are not listed here one by one.

[0138] It should be noted that, although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0139] The present application also provides a semiconductor structure, which can be formed by the method for forming a semiconductor structure in any of the above embodiments. The specific details, formation process and beneficial effects of each part of the semiconductor structure have been described in detail in the corresponding method for forming the semiconductor structure, so they will not be repeated here.

[0140] The present disclosure also provides a memory device, which may include the semiconductor structure in any of the above embodiments. The beneficial effects of the memory device can be referred to the method for forming the semiconductor structure in the above embodiments, which will not be described in detail here.

[0141] For example, the storage device may be a DRAM (Dynamic Random Access Memory). Of course, it may also be other storage devices, which are not listed here one by one.

[0142] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming an insulating dielectric layer on the substrate, wherein the insulating dielectric layer at least comprises a sacrificial film layer; forming a mask layer on the surface of the sacrificial film layer, wherein the etching rate of the mask layer is greater than the etching rate of the sacrificial film layer; and the etching selectivity ratio of the mask layer to the sacrificial film layer is greater than or equal to 20; Etching the insulating dielectric layer using the mask layer as a mask to form a plurality of capacitor holes in the insulating dielectric layer that respectively expose the substrate; Removing the mask layer by an etching process; forming a lower electrode layer of a columnar capacitor in each of the capacitor holes; Wherein, a lower electrode layer of a columnar capacitor is formed in each of the capacitor holes, comprising: Forming a conductive layer on the surface of the sacrificial film layer, wherein the conductive layer fills the capacitor holes; Etching back the conductive layer to form a lower electrode layer of a columnar capacitor in each of the capacitor holes, wherein the top of the lower electrode layer protrudes from the surface of the sacrificial film layer; The insulating dielectric layer includes a first supporting layer, a first sacrificial layer and a second supporting layer stacked and distributed in a direction perpendicular to the substrate, the sacrificial film layer is located on the surface of the second supporting layer, and the forming method further includes: forming a third supporting layer on the surface of the sacrificial film layer, wherein the third supporting layer surrounds the outer periphery of the lower electrode layer; removing the sacrificial film layer and the first sacrificial layer; Wherein, a third supporting layer is formed on the surface of the sacrificial film layer, and the third supporting layer surrounds the outer periphery of the lower electrode layer, including: forming an electrode support layer on the surface of the structure formed by the sacrificial film layer and the lower electrode layer; The electrode support layer located on the top of the lower electrode layer is removed to form a third support layer surrounding the side wall of the lower electrode layer.

2. The forming method according to claim 1, characterized in that: The step of removing the mask layer by an etching process comprises: The mask layer is dry-etched using chlorine gas.

3. The forming method according to claim 1, characterized in that: The material of the mask layer is polysilicon, and the material of the sacrificial film layer is silicon oxide.

4. The forming method according to claim 1, characterized in that: The removing of the sacrificial film layer and the first sacrificial layer comprises: Forming an etched via in a stacked area of ​​the first sacrificial layer, the second supporting layer, the sacrificial film layer and the third supporting layer, wherein the etched via at least penetrates the third supporting layer, the sacrificial film layer and the second supporting layer; The first sacrificial layer and the sacrificial film layer are etched at the etching vias to remove the first sacrificial layer and the sacrificial film layer.

5. The forming method according to claim 1, characterized in that: The removing of the sacrificial film layer and the first sacrificial layer comprises: Using a first etching process to etch the electrode support layer in a stacking area of ​​the first sacrificial layer, the second support layer, the sacrificial film layer, and the electrode support layer to form a first via hole, wherein the first via hole penetrates the electrode support layer and exposes the sacrificial film layer; Using a second etching process to etch the sacrificial film layer at the first via hole to remove the sacrificial film layer and expose the second supporting layer; Etching the second supporting layer using the first etching process to form a second via hole, wherein the second via hole penetrates the second supporting layer and exposes the first sacrificial layer; The first sacrificial layer is etched at the second via hole using the second etching process to remove the first sacrificial layer.

6. The forming method according to claim 5, characterized in that: The first etching process is a dry etching process, and the second etching process is a wet etching process.

7. The forming method according to claim 1, characterized in that: The forming method further comprises: forming an interlayer dielectric layer on a surface of a structure composed of a lower electrode layer of the columnar capacitor, the first supporting layer, the second supporting layer and the third supporting layer; An upper electrode layer is formed on the surface of the interlayer dielectric layer.

8. The forming method according to any one of claims 1 to 7, characterized in that: The substrate includes a plurality of conductive contact plugs distributed at intervals, and each of the conductive contact plugs is connected to each of the lower electrode layers in a one-to-one correspondence.

9. A semiconductor structure, characterized in that: The semiconductor structure is formed by the method for forming a semiconductor structure according to any one of claims 1 to 7.

10. A storage device, characterized in that: Comprising the semiconductor structure as claimed in claim 9.

Images