Chip-on-film packaging structure

Abstract

The present invention provides a thin film chip package structure, comprising a flexible substrate, a first circuit layer, a second circuit layer, and a chip. The flexible substrate has a first surface and a second surface facing each other, and a chip coverage area located on the first surface, wherein the chip coverage area is divided into a first side area, a central area, and a second side area along the longitudinal direction. The flexible substrate includes a first area, a second area, and a third area corresponding to the first side area, the central area, and the second side area, respectively. The first circuit layer and the second circuit layer are located on the first surface and the second surface, respectively. The chip is disposed in the chip coverage area and is bonded to the first circuit layer. The ratio of the circuit laying area of the second circuit layer to the circuit laying area of the first circuit layer is between 0.9 and 1.2 in the first area and the third area.

Description

Technical Field

[0001] The present invention relates to a packaging structure, and in particular to a chip-on-film packaging structure. Background Art

[0002] As electronic products become increasingly demanding in terms of functionality and the density of integrated circuits (ICs) within chips continues to increase, the number of pins on flexible circuit substrates with chip-on-film packaging structures must also increase. This makes wiring on the previously widely used single-sided flexible substrates increasingly difficult, leading to a shift towards double-sided designs for flexible circuit substrates.

[0003] Furthermore, in a double-sided flexible circuit board design, the mismatch in the coefficient of thermal expansion (CTE) between different materials (for example, the flexible substrate and the metal used in the circuit layer) generates thermal stress on the two opposing surfaces. This stress depends on the layout area of the circuit layer. The greater the difference in layout area between the two opposing surfaces, the more severe the uneven stress, leading to deformation and warping of the flexible substrate. When performing the inner lead bonding (ILB) process in a FFT package using thermocompression, the high temperature exerts a particularly significant thermal effect on the chip footprint. Therefore, the warping of the flexible substrate caused by the uneven thermal stress in this area is more severe, which can further lead to poor lead bonding, peeling, or fracture. Summary of the Invention

[0004] The present invention provides a chip-on-film packaging structure, which can improve the problems of warping and deformation of a flexible substrate and poor pin bonding, peeling or breaking, thereby improving its reliability.

[0005] A thin film chip package structure of the present invention includes a flexible substrate, a first circuit layer, a second circuit layer, and a chip. The flexible substrate has a first surface and a second surface relative to each other, and a chip coverage area located on the first surface, wherein the chip coverage area is divided into a first side area, a central area, and a second side area along the longitudinal direction. The flexible substrate includes a first area, a second area, and a third area corresponding to the first side area, the central area, and the second side area, respectively. The first circuit layer and the second circuit layer are located on the first surface and the second surface, respectively. The chip is arranged in the chip coverage area and is bonded to the first circuit layer. The ratio of the circuit laying area of the second circuit layer to the circuit laying area of the first circuit layer is between 0.9 and 1.2 in the first area and the third area.

[0006] In one embodiment of the present invention, the length of the first side region in the long direction and the length of the second side region in the long direction are respectively 1 / 4 to 1 / 6 of the length of the long side of the chip footprint.

[0007] In one embodiment of the present invention, the length of the first side region in the long direction and the length of the second side region in the long direction are respectively 1 / 5 of the length of the long side of the chip footprint.

[0008] In one embodiment of the present invention, the chip footprint is expanded outward by a distance to form edges of the first area, the second area, and the third area.

[0009] In one embodiment of the present invention, the area between the edge and the chip footprint includes a first expansion area surrounding three sides of the first side area, a second expansion area adjacent to two opposite sides of the central area, and a third expansion area surrounding three sides of the second side area. The first area includes the first side area and the first expansion area, the second area includes the central area and the second expansion area, and the third area includes the second side area and the third expansion area.

[0010] In one embodiment of the present invention, the distance is 1 / 8 to 1 / 12 of the length of the long side of the chip footprint.

[0011] In one embodiment of the present invention, the distance is 1 / 10 of the length of the long side of the chip footprint.

[0012] In one embodiment of the present invention, the distance is 400 micrometers.

[0013] In one embodiment of the present invention, a ratio of a circuit laying area of the second circuit layer to a circuit laying area of the first circuit layer is not greater than 1.5 in the second region.

[0014] In one embodiment of the present invention, the chip is bonded to the first circuit layer via a plurality of bumps.

[0015] Based on the foregoing, in the chip-on-film packaging structure of the present invention, the chip footprint area of the flexible substrate is subjected to the most severe thermal effects during the packaging process (e.g., the inner pin bonding process). In particular, the warping deformation at the corresponding chip edges is greater than the warping deformation at the corresponding chip center. Therefore, the circuit layout on the flexible substrate is designed such that the ratio of the circuit laying area of the second circuit layer to the circuit laying area of the first circuit layer is between 0.9 and 1.2 in the first and third regions corresponding to the chip edges. This ensures that the circuit laying area ratios on the two opposing surfaces of the flexible substrate are similar. This prevents warping of the flexible substrate caused by uneven stress resulting from the mismatch in the thermal expansion coefficients of the two opposing surfaces, thereby improving issues such as poor pin bonding, peeling, or breakage, and enhancing the reliability of the chip-on-film packaging structure.

[0016] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A is a partial top view of a chip-on-film package structure according to an embodiment of the present invention;

[0018] Figure 1B yes Figure 1A A partial enlarged view of region B in FIG;

[0019] Figure 2A is a partial bottom view of a chip-on-film package structure according to an embodiment of the present invention;

[0020] Figure 2B yes Figure 2A A partial enlarged view of region C in FIG;

[0021] Figure 3 yes Figure 1A Schematic cross-sectional view of the chip-on-film package structure along line AA.

[0022] It should be noted that Figure 1A and Figure 1B The chip, bumps and solder mask are presented in perspective, and the packaging colloid is omitted. Figure 2A and Figure 2B The solder mask is also presented in perspective. DETAILED DESCRIPTION

[0023] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0024] Directional terms used herein (eg, up, down, right, left, front, back, top, bottom) are used only with reference to the drawings and are not intended to imply an absolute orientation.

[0025] The present invention will be more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, dimensions, or sizes of layers or regions in the drawings may be exaggerated for clarity. Identical or similar reference numbers denote identical or similar elements, and detailed descriptions will not be repeated in the following paragraphs.

[0026] Figure 1A FIG. 1 is a partial top view of a chip-on-film package structure according to an embodiment of the present invention. Figure 1B yes Figure 1A A partial enlarged view of area B in FIG. Figure 2AFIG. 1 is a partial bottom view of a chip-on-film package structure according to an embodiment of the present invention. Figure 2B yes Figure 2A A partial enlarged view of area C in FIG. Figure 3 yes Figure 1A The cross-sectional view of the chip-on-film package structure along line AA is shown in Figures 1 to Figure 3 In this embodiment, a chip-on-film package structure 100 includes a flexible substrate 110, a first circuit layer 120, a second circuit layer 130, and a chip 140. The flexible substrate 110 has a first surface 110a and a second surface 110b that are opposite to each other, and a chip footprint 112 located on the first surface 110a. Specifically, the chip footprint 112 may include two opposing long sides 112L and two opposing short sides 112S. The chip footprint 112 is divided along a long-side direction D into a first side region 1121 adjacent to one of the two short sides 112S, a central region 1122, and a second side region 1123 adjacent to the other of the two short sides 112S. The flexible substrate 110 includes a first region R1, a second region R2, and a third region R3 corresponding to the first side region 1121, the central region 1122, and the second side region 1123, respectively. On the other hand, the first circuit layer 120 and the second circuit layer 130 are respectively located on the first surface 110a and the second surface 110b, and the chip 140 is disposed in the chip footprint 112 and bonded to the first circuit layer 120. For example, the chip 140 is bonded and electrically connected to the first circuit layer 120 via a plurality of bumps 142, but the present invention is not limited thereto.

[0027] Here, the material of the flexible substrate 110 is, for example, polyethylene terephthalate (PET), polyimide (PI), polyethersulfone (PES), polycarbonate (PC), or other suitable flexible materials. The material of the first circuit layer 120 and the second circuit layer 130 is, for example, copper (which can form a double-sided copper foil substrate) or other suitable conductive metal materials. The chip 140 can be a driver chip or any other suitable chip.

[0028] In this embodiment, the chip-on-film packaging structure 100 designs the circuit layout on the flexible substrate 110 so that the ratio of the circuit laying area of the second circuit layer 130 to the circuit laying area of the first circuit layer 120 is between 0.9 and 1.2 in the first region R1 and the third region R3. This ensures that the ratio of the circuit laying areas on the two opposing surfaces of the flexible substrate 110 (the first surface 110a and the second surface 110b) is similar. This prevents warping of the flexible substrate 110 caused by uneven stress resulting from the mismatch in the thermal expansion coefficients of the two opposing surfaces, thereby improving the problems of poor pin bonding, peeling, or breakage, and enhancing the reliability of the chip-on-film packaging structure 100. Furthermore, since the mismatch in thermal expansion coefficients between the flexible substrate 110 made of flexible material and the circuit layer made of metal material is positively correlated with the laying area of the circuit layer, and a larger mismatch in thermal expansion coefficients will also generate greater thermal stress, the greater the difference in the proportion of the circuit laying areas on the two opposite surfaces of the flexible substrate 110, the more uneven the thermal stress will be generated on the two opposite surfaces, thereby causing more obvious warping deformation of the flexible substrate 110. In addition, in the inner pin bonding process, the chip 140 is generally bonded to the chip covering area 112 of the flexible substrate 110 by thermal compression. Therefore, the thermal effect on the chip covering area 112 is more intense. The warping deformation of the first side area 1121 and the second side area 1123 of the chip covering area 112 of the flexible substrate 110 corresponding to the two sides of the chip 140 (i.e., adjacent to the two short sides 112S) is greater than the warping deformation of the central area 1122 corresponding to the center of the chip 140. Therefore, the film chip package structure 100 of this embodiment is designed for the flexible substrate 110 in the The layout areas of the circuit layers on the two surfaces (the first surface 110a and the second surface 110b) corresponding to the first region R1 and the third region R3 of the first side region 1121 and the second side region 1123 are designed to be close to each other, so that the ratio of the layout area of the second circuit layer 130 to the layout area of the first circuit layer 120 is between 0.9 and 1.2. In this way, the layout area ratios are close, thereby reducing warping deformation caused by uneven thermal stress, improving problems such as poor pin bonding, peeling or breakage, and thereby enhancing the reliability of the film flip chip package structure 100.

[0029] In some embodiments, the length L1 of the first side region 1121 in the longitudinal direction D and the length L2 of the second side region 1123 in the longitudinal direction D are each 1 / 4 to 1 / 6 of the length L of the long side of the chip footprint 112. Furthermore, the length L1 of the first side region 1121 in the longitudinal direction D and the length L2 of the second side region 1123 in the longitudinal direction D can each be 1 / 5 of the length L of the long side of the chip footprint 112, but the present invention is not limited thereto.

[0030] In some embodiments, the length L1 of the first side area 1121 in the long side direction D is the same as the length L2 of the second side area 1123 in the long side direction D, but the present invention is not limited to this. According to actual design requirements, the length L1 of the first side area 1121 in the long side direction D and the length L2 of the second side area 1123 in the long side direction D can be different.

[0031] In some embodiments, the chip footprint 112 expands outward by a distance d to form edges e of the first region R1 , the second region R2 , and the third region R3 . Furthermore, the area between the edge e and the chip footprint 112 may include a first expansion region E1 surrounding three sides of the first side region 1121 (e.g., one of the two short sides 112S and a side portion connecting the two long sides 112L of the short side 112S); a second expansion region E2 adjacent to two opposite sides of the central region 1122 (e.g., a middle portion of the two long sides 112L); and a third expansion region E3 surrounding three sides of the second side region 1123 (e.g., the other of the two short sides 112S and a side portion connecting the two long sides 112L of the short side 112S). The first region R1 includes the first side region 1121 and the first expansion region E1, the second region R2 includes the central region 1122 and the second expansion region E2, and the third region R3 includes the second side region 1123 and the third expansion region E3. Since the thermal effect during the inner pin bonding process mainly acts on the chip footprint 112 and its adjacent areas, especially the areas adjacent to the two short sides 112S, where the warping and deformation caused by heat are more obvious, the circuit laying area ratio on the two surfaces of the first area R1 (corresponding to the first side area 1121) and the third area R3 (corresponding to the second side area 1123) adjacent to the two short sides 112S is designed. This can more effectively improve the warping and deformation and the problems of poor pin bonding, peeling or breakage of the film flip package structure 100, thereby further improving the reliability of the film flip package structure 100, but the present invention is not limited to this.

[0032] In some embodiments, distance d is 1 / 8 to 1 / 12 of the length L of the long side of chip footprint 112. Furthermore, distance d can be 1 / 10 of the length L of the long side of chip footprint 112. For example, distance d can be 400 microns. It should be noted that the present invention is not limited to the aforementioned values and ranges of the overhang distances; the overhang distance can be determined based on actual design requirements.

[0033] In some embodiments, since the deformation of the flexible substrate 110 in the central area of the chip coverage area 112 is relatively small, but considering that the difference in the thermal expansion coefficients of the two surfaces is too large and still easily leads to warping and deformation, the ratio of the circuit laying area of the second circuit layer 130 in the second region R2 to the circuit laying area of the first circuit layer 120 is designed to be no greater than 1.5. Compared with the ratio of the circuit laying area of the second circuit layer 130 to the circuit laying area of the first circuit layer 120 in the first region R1 and the third region R3, this has greater spatial application flexibility, but the present invention is not limited to this.

[0034] In some embodiments, the chip-on-film packaging structure 100 further includes a solder mask layer 150, wherein the solder mask layer 150 is located on the flexible substrate 110 and partially covers the first circuit layer 120 and the second circuit layer 130 to prevent the first circuit layer 120 and the second circuit layer 130 from being contaminated by moisture or foreign matter and affecting electrical performance, but the present invention is not limited thereto.

[0035] In some embodiments, the chip-on-film package structure 100 further includes an encapsulant 160. The encapsulant 160 can be filled into the gap between the chip 140 and the flexible substrate 110 to protect the electrical contacts between the chip 140 and the flexible substrate 110. The encapsulant 160 is, for example, an underfill, but the present invention is not limited thereto.

[0036] In summary, during the packaging process (e.g., the inner pin bonding process) of the chip-on-film package structure of the present invention, the chip-covering area of the flexible substrate is subjected to the most severe thermal effects. In particular, the warping deformation at the two sides of the chip is greater than the warping deformation at the center of the chip. Therefore, the circuit layout on the flexible substrate is designed such that the ratio of the circuit laying area of the second circuit layer to the circuit laying area of the first circuit layer is between 0.9 and 1.2 in the first and third regions at the two sides of the chip. This ensures that the circuit laying area ratios on the two opposing surfaces of the flexible substrate are similar. This prevents warping of the flexible substrate caused by uneven stress resulting from the mismatch in the thermal expansion coefficients of the two opposing surfaces, thereby improving the problems of poor pin bonding, peeling, or breakage, and enhancing the reliability of the chip-on-film package structure.

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip-on-film packaging structure, characterized in that: include: A flexible substrate having a first surface and a second surface facing each other, and a chip coverage area on the first surface, the chip coverage area being divided into a first side area, a central area, and a second side area along a longitudinal direction. The flexible substrate includes a first region, a second region, and a third region. The chip coverage area extends outward by a distance to form edges of the first region, the second region, and the third region. The first region, the second region, and the third region correspond to the first side area, the central area, and the second side area, respectively. The length of the first side area and the length of the second side area in the longitudinal direction are respectively 1 / 4 to 1 / 6 of the length of the long side of the chip coverage area, and the distance is 1 / 8 to 1 / 12 of the length of the long side of the chip coverage area. a first circuit layer, located on the first surface; a second circuit layer, located on the second surface; as well as A chip is disposed in the chip coverage area and connected to the first circuit layer, wherein A ratio of a circuit laying area of the second circuit layer to a circuit laying area of the first circuit layer is between 0.9 and 1.2 in the first region and the third region.

2. The chip-on-film packaging structure according to claim 1, wherein: The length of the first side area in the long side direction and the length of the second side area in the long side direction are respectively 1 / 5 of the length of the long side of the chip coverage area.

3. The chip-on-film packaging structure according to claim 1, wherein: A first expansion area surrounding three sides of the first side area, a second expansion area adjacent to two opposite sides of the central area, and a third expansion area surrounding three sides of the second side area are included between the edge and the chip coverage area, wherein the first area includes the first side area and the first expansion area, the second area includes the central area and the second expansion area, and the third area includes the second side area and the third expansion area.

4. The chip-on-film packaging structure according to claim 1, wherein: The distance is 1 / 10 of the length of the long side of the chip coverage area.

5. The chip-on-film packaging structure according to claim 1, wherein: The distance is 400 micrometers.

6. The chip-on-film packaging structure according to claim 1, wherein: A ratio of a circuit laying area of the second circuit layer to a circuit laying area of the first circuit layer is not greater than 1.5 in the second region.

7. The chip-on-film packaging structure according to claim 1, wherein: The chip is bonded to the first circuit layer via a plurality of bumps.

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