Transistor parasitic capacitance test module, device and method

Abstract

The present application provides a transistor parasitic capacitance test module, device and method, the transistor parasitic capacitance test module includes: a first module and a second module; the first module and the second module both include a transistor to be tested and a first transistor; the transistor to be tested and the corresponding first transistor share a body region and a first electrode, the first electrode being a drain or a source; different from the first module, the contact hole in the port corresponding to the first electrode in the second module is removed; the first module is used to determine the gate port capacitance of the transistor to be tested; the second module is used to determine the metal layer parasitic capacitance and / or contact hole parasitic capacitance of the transistor to be tested; wherein the gate port capacitance is the capacitance between the gate port and each other port to be examined. By removing only the transistor contact hole, the parasitic capacitance is measured, thereby improving the accuracy of the parasitic capacitance measurement.

Description

Technical Field

[0001] The present application relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a transistor parasitic capacitance test module, device and method. Background Art

[0002] As circuit scale continues to increase, device size continues to shrink, and circuit physical structure continues to become more complex, parasitic capacitance of transistors, such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), has an increasingly greater impact on circuit performance and has become a bottleneck limiting the speed and power consumption of high-frequency digital circuits.

[0003] The parasitic capacitance of MOSFET mainly includes: gate to contact hole capacitance, gate to interconnect metal capacitance, gate to active area capacitance, gate to body area (well) capacitance, etc. When measuring the gate to contact hole capacitance and gate to interconnect metal capacitance, the de-embedding result or the proportion of each capacitance component is usually obtained by changing the doping type, removing the active area, etc.

[0004] The above method changes the active area of ​​the core component of the transistor, which causes the performance of other components of the transistor to be different from the original transistor, resulting in large errors in the results of de-embedding or splitting calculations. The final test results are less accurate and cannot meet the needs of high-precision simulation, modeling, circuit design, etc. Summary of the invention

[0005] The present application provides a transistor parasitic capacitance test module, device and method to solve the problem of low accuracy in transistor parasitic capacitance testing.

[0006] In a first aspect, the present application provides a transistor parasitic capacitance test module, comprising: a first module and a second module; the first module and the second module both comprise a transistor to be tested and a first transistor;

[0007] Among them, the transistor to be tested shares a body region and a first electrode with the corresponding first transistor, and the first electrode is a source or a drain; except the first electrode in the second module, each electrode, including the gate, the source and the drain, is connected to the corresponding interconnecting metal through a contact hole to form a port; the contact hole in the port corresponding to the first electrode in the second module is removed; the first module is used to determine the gate port capacitance of the transistor to be tested; the second module is used to determine the metal layer parasitic capacitance and / or the contact hole parasitic capacitance of the transistor to be tested; wherein the gate port capacitance of the transistor to be tested is the capacitance between the gate port of the transistor to be tested and the other ports of the transistor to be tested; the metal layer parasitic capacitance of the transistor to be tested is the parasitic capacitance between the gate port of the transistor to be tested and the interconnecting metal of the other ports of the transistor to be tested; the contact hole parasitic capacitance of the transistor to be tested is the parasitic capacitance between the gate port of the transistor to be tested and the contact hole of the other ports of the transistor to be tested, and the port includes the corresponding electrode, the contact hole on the electrode and the corresponding interconnecting metal.

[0008] In a possible design, the first module is specifically used to:

[0009] After applying an operating voltage to the gate of the first transistor to turn on the first transistor, the capacitance between the gate port and the first port of the transistor to be tested in the first module is determined as the gate port capacitance; wherein the first port includes a port corresponding to the first electrode, a port corresponding to the second electrode, and a port corresponding to the third electrode, the second electrode is an electrode of the first transistor in the first module or the second module excluding the first electrode and the gate, and the third electrode is an electrode of the transistor to be tested in the first module or the second module excluding the first electrode and the gate.

[0010] In a possible design, the second module is specifically used for:

[0011] After applying an operating voltage to the gate of the first transistor to turn on the first transistor, the metal layer parasitic capacitance is determined based on the capacitance between the gate port of the transistor to be tested in the second module and the interconnected metal corresponding to the first electrode; the contact hole parasitic capacitance is determined based on the capacitance between the gate port of the transistor to be tested and the second port in the second module, the metal layer parasitic capacitance and the gate port capacitance; wherein the second port includes a port corresponding to the second electrode and a port corresponding to the third electrode, the second electrode is an electrode of the first transistor in the first module or the second module excluding the first electrode and the gate, and the third electrode is an electrode of the transistor to be tested in the first module or the second module excluding the first electrode and the gate.

[0012] In one possible design, the interconnect metal corresponding to the second electrode and the interconnect metal corresponding to the third electrode are connected together as the second port, and the parasitic capacitance of the metal layer is twice the first capacitance; the parasitic capacitance of the contact hole is twice the difference between the gate port capacitance and the sum of the first capacitance and the second capacitance; wherein the first capacitance is the capacitance between the gate port of the transistor to be tested in the second module and the interconnect metal corresponding to the first electrode, and the second capacitance is the capacitance between the gate port of the transistor to be tested in the second module and the second port.

[0013] In one possible design, the first module and the second module also include a second transistor; wherein the transistor to be tested is arranged between the corresponding first transistor and the corresponding second transistor, the transistor to be tested and the corresponding second transistor share a body region and a third electrode, and the first electrode and the third electrode constitute the source and drain of the transistor to be tested; there is no contact hole between the third electrode in the second module and the corresponding interconnection metal.

[0014] In a possible design, the first module is specifically used to:

[0015] After applying an operating voltage to the gates of the first transistor and the second transistor to turn on the first transistor and the second transistor, the capacitance between the gate port and the third port of the transistor to be tested in the first module is determined as the gate port capacitance; wherein the third port includes ports corresponding to four electrodes, namely, a first electrode, a second electrode, a third electrode and a fourth electrode, the second electrode is an electrode of the first transistor in the first module or the second module excluding the first electrode and the gate, and the fourth electrode is an electrode of the second transistor in the first module or the second module excluding the gate and the third electrode.

[0016] In a possible design, the second module is specifically used for:

[0017] After applying an operating voltage to the gates of the first transistor and the second transistor to turn on the first transistor and the second transistor, determine that the capacitance between the gate port and the fourth port of the transistor to be tested in the second module is the metal layer parasitic capacitance; determine the contact hole parasitic capacitance based on the capacitance between the gate port and the fifth port of the transistor to be tested in the second module, the metal layer parasitic capacitance and the gate port capacitance; wherein the fourth port includes a port corresponding to the first electrode and a port corresponding to the third electrode, the fifth port includes a port corresponding to the second electrode and a port corresponding to the fourth electrode, the second electrode is an electrode of the first transistor in the first module or the second module excluding the first electrode and the gate, and the fourth electrode is an electrode of the second transistor in the first module or the second module excluding the gate and the third electrode.

[0018] In one possible design, the interconnect metal corresponding to the first electrode and the interconnect metal corresponding to the third electrode are connected together as a fourth port, the interconnect metal corresponding to the second electrode and the interconnect metal corresponding to the fourth electrode are connected together as a fifth port, and the contact hole parasitic capacitance is the difference between the gate port capacitance and the sum of the metal layer parasitic capacitance and the third capacitance; wherein the third capacitance is the capacitance between the gate port of the transistor to be tested in the second module and the fifth port.

[0019] In a second aspect, the present application provides a transistor parasitic capacitance testing device, which includes a measuring device and a transistor parasitic capacitance testing module provided in the first aspect of the present application, and the measuring device is used to detect the metal layer parasitic capacitance and / or contact hole parasitic capacitance of the transistor to be tested.

[0020] In a third aspect, the present application provides a transistor parasitic capacitance testing method, which is applied to the transistor parasitic capacitance testing module provided in the first aspect of the present application, and the method includes:

[0021] Based on the first module, the gate port capacitance of the gate of the transistor to be tested is determined; based on the second module and the gate port capacitance, the metal layer parasitic capacitance and / or the contact hole parasitic capacitance of the transistor to be tested is determined.

[0022] Optionally, based on the first module, determining the gate port capacitance of the gate of the transistor to be tested includes:

[0023] Applying an operating voltage to the gate of the first transistor of the first module to turn on the first transistor of the first module; determining the capacitance between the gate port and the first port of the transistor to be tested in the first module as the gate port capacitance; wherein the first port includes a port corresponding to the first electrode, a port corresponding to the second electrode, and a port corresponding to the third electrode.

[0024] Optionally, determining the metal layer parasitic capacitance and / or the contact hole parasitic capacitance of the transistor to be tested based on the second module and the gate port capacitance includes:

[0025] Applying an operating voltage to the gate of the first transistor of the second module to turn on the first transistor of the second module; determining the metal layer parasitic capacitance based on the capacitance between the gate port of the transistor to be tested in the second module and the interconnected metal corresponding to the first electrode; determining the contact hole parasitic capacitance based on the capacitance between the gate port of the transistor to be tested in the second module and the second port, the metal layer parasitic capacitance and the gate port capacitance; wherein the second port includes a port corresponding to the second electrode and a port corresponding to the third electrode, the second electrode is an electrode of the first transistor in the first module or the second module excluding the first electrode and the gate, and the third electrode is an electrode of the transistor to be tested in the first module or the second module excluding the first electrode and the gate.

[0026] Optionally, based on the first module, determining the gate port capacitance of the gate of the transistor to be tested includes:

[0027] Applying an operating voltage to the gates of the first transistor and the second transistor of the first module to turn on the first transistor and the second transistor of the first module; determining the capacitance between the gate port and the third port of the transistor to be tested in the first module, which is the gate port capacitance; wherein the third port includes ports corresponding to four electrodes, namely, a first electrode, a second electrode, a third electrode and a fourth electrode, wherein the second electrode is an electrode of the first transistor in the first module or the second module excluding the first electrode and the gate, and the fourth electrode is an electrode of the second transistor in the first module or the second module excluding the gate and the third electrode.

[0028] Optionally, determining the metal layer parasitic capacitance and / or the contact hole parasitic capacitance of the transistor to be tested based on the second module and the gate port capacitance includes:

[0029] After applying an operating voltage to the gates of the first transistor and the second transistor of the second module to turn on the first transistor and the second transistor of the second module, determine that the capacitance between the gate port and the fourth port of the transistor to be tested in the second module is the metal layer parasitic capacitance; determine the contact hole parasitic capacitance based on the capacitance between the gate port and the fifth port of the transistor to be tested in the second module, the metal layer parasitic capacitance and the gate port capacitance; wherein the fourth port includes a port corresponding to the first electrode and a port corresponding to the third electrode, the fifth port includes a port corresponding to the second electrode and a port corresponding to the fourth electrode, the second electrode is an electrode of the first transistor in the first module or the second module excluding the first electrode and the gate, and the fourth electrode is an electrode of the second transistor in the first module or the second module excluding the gate and the third electrode.

[0030] The transistor parasitic capacitance test module, device and method provided in the present application provide a test module consisting of at least a first module and a second module, wherein the first module and the second module both include a transistor to be tested and a first transistor, wherein in the first module and the second module, the transistor to be tested shares a body region and a first electrode with the corresponding first transistor, and the first electrode may be a drain or a source, and in the first module, each electrode, including a source, a drain and a gate, is connected to a corresponding interconnect metal through a contact hole to form a corresponding port, so as to lead out a corresponding electrode based on the port; the second module can be obtained by removing the contact hole of the first electrode in the first module, that is, the difference between the second module and the first module is that the first electrode in the first module is connected to the corresponding interconnect metal through a contact hole, and the contact hole between the first electrode and the corresponding interconnect metal in the second module is removed; by testing the transistor parasitic capacitance through a module consisting of the first module and the second module with only the contact hole removed, the core structure of the component during normal use is retained, the consistency of the component characteristics during test and actual use is maintained, and the accuracy of measuring the parasitic capacitance using a comparative splitting method is guaranteed to the greatest extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0032] Figure 1 It is a schematic diagram of the structure of a transistor in the prior art;

[0033] Figure 2 A schematic diagram of the structure of a transistor parasitic capacitance test module provided by an embodiment of the present application;

[0034] Figure 3 For this application Figure 2A schematic diagram of the connection of the first module during testing provided in the illustrated embodiment;

[0035] Figure 4 For this application Figure 2 A schematic diagram of the connection of the second module during testing provided in the illustrated embodiment;

[0036] Figure 5 A schematic structural diagram of a transistor parasitic capacitance test module provided by another embodiment of the present application;

[0037] Figure 6 For this application Figure 5 An equivalent circuit diagram of a first module provided in the illustrated embodiment;

[0038] Figure 7 For this application Figure 5 A schematic diagram of the connection of the first module during testing in the illustrated embodiment;

[0039] Figure 8 For this application Figure 5 A schematic diagram of the connection of the second module during testing in the illustrated embodiment;

[0040] Fig. 9 A schematic diagram of a flow chart of a transistor parasitic capacitance testing method provided in accordance with an embodiment of the present application.

[0041] Description of reference numerals:

[0042] GT-gate;

[0043] D-drain;

[0044] S-source;

[0045] O-gate oxide layer;

[0046] W-body region;

[0047] M-interconnect metal;

[0048] CT-contact hole;

[0049] 20- Transistor parasitic capacitance test module;

[0050] 210-first module;

[0051] 220-second module;

[0052] 204-transistor to be tested;

[0053] 206-a first transistor;

[0054] 208- a second transistor;

[0055] E1 - first electrode;

[0056] E2 - second electrode;

[0057] E3 - third electrode;

[0058] E3 - fourth electrode;

[0059] T1-first port;

[0060] T2 - second port;

[0061] T3-third port;

[0062] T4-fourth port;

[0063] T5 - Fifth port.

[0064] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0065] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0066] As circuit scale continues to increase, device size becomes smaller and smaller, and the distance between devices becomes closer and closer, the parasitic capacitance of MOSFET devices has an increasingly greater impact on the overall performance of the circuit. In order to improve circuit performance, it is necessary to accurately measure the parasitic capacitance of MOSFET, especially the capacitance Cct from the gate to the contact hole (Contact, CT), the capacitance Cmetal from the gate to the interconnect metal (Metal), etc.

[0067] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0068] Figure 1 1 is a schematic diagram of the structure of a transistor in the prior art, where MOSFET is used as an example. Figure 1As shown, in the MOSFET, the gate GT, the drain D, the source S, the gate oxide layer O, the body region W, the interconnection metal M used for lead-out, and the contact hole CT connecting the interconnection metal M with the corresponding electrode, the gate oxide layer O is located between the gate GT and the body region W, the ion-heavily doped active region is composed of the drain D and the source S, and the body region W is an ion-lightly doped region with an ion type opposite to that of the active region.

[0069] exist Figure 1 In the figure, the gate port capacitance Cgt of MOSFET starting from the gate GT mainly includes: the capacitance Cct between the gate GT and the contact hole, the capacitance Cmetal between the gate GT and the interconnect metal, the capacitance Cf between the gate GT and the active area, and a variable capacitance Cint between the gate GT and the channel or body area W. The capacitance Cf between the gate GT and the active area includes the capacitance Cgd between the gate GT and the drain D, and the capacitance Cgs between the gate GT and the source S. Among them, the capacitance of the gate GT to the body area W can be directly obtained through the traditional MOSFET device CV test circuit. Since the distance between the gate GT and the contact hole (such as the contact hole CT2) is very small, the contribution of Cct and Cmetal is relatively large, and separate detection is required, that is, Cct and Cmetal need to be separated from the overall gate port capacitance Cgt.

[0070] When measuring the two parasitic capacitances Cct and Cmetal, the common measurement methods include obtaining the above parasitic capacitances by subtracting the contact holes, active areas, and some metal structures by comparison, or retaining the connection relationship by changing the doping type, and then obtaining the above parasitic capacitances by taking out the results of the metal and contact holes respectively. Both of the above methods adjust the active area of ​​the core component of the MOSFET, delete or change the doping type, resulting in the characteristics of the tested device being different from the characteristics of the original device, and ultimately resulting in large errors in the measurement results of the parasitic capacitances Cct and Cmetal, and low accuracy, which cannot meet the needs.

[0071] In order to improve the accuracy of measuring parasitic capacitance Cct and Cmetal, an embodiment of the present application provides a test module that does not change the core components of the transistor (including active areas, gates, etc.), and the test module includes two modules. The first module is implemented by adding a transistor on one side or both sides of a single transistor, and sharing a source and drain region with each other. The other module, i.e., the second module, can be implemented by removing the contact hole at the common electrode (first electrode) on the basis of the first module. The test module composed of the first module and the second module implements the measurement of parasitic capacitance Cct and / or Cmetal, so as to retain the core structure of the transistor when the circuit is in normal use as much as possible, thereby maximizing the accuracy of the comparative split measurement.

[0072] For ease of distinction, the following method is uniformly used to represent corresponding components in subsequent drawings: the interconnect metal M is filled with horizontal lines, the contact hole CT is filled with slashes “\”, the gate GT is filled with reverse slashes “ / ”, the source S and the drain D are not distinguished and are filled with mesh lines, the gate oxide layer O is filled with dots, and the body area W is not filled.

[0073] Figure 2 A schematic diagram of the structure of a transistor parasitic capacitance test module provided by an embodiment of the present application is shown in FIG. Figure 2 As shown, the transistor parasitic capacitance test module 20 includes: a first module 210 and a second module 220 , and the first module 210 and the second module 220 both include a transistor to be tested 204 and a first transistor 206 .

[0074] The transistor to be tested 204 and the corresponding first transistor 206 share a body region W and a first electrode E1, and the first electrode E1 may be a source or a drain, for example, the first electrode E1 may be a drain D of the transistor to be tested 204 and a source S of the first transistor 206, or the first electrode E1 may be a source S of the transistor to be tested 204 and a drain D of the first transistor 206. In some cases, the source and the drain may be interchangeable, and the first electrode E1 may be a source S of the transistor to be tested 204 and a source S of the first transistor 206, or may be a drain D of the transistor to be tested 204 and a drain D of the first transistor 206. Except for the first electrode E1 in the second module 220, each electrode, including the gate GT, the source S and the drain D, is connected to the corresponding interconnect metal M through a contact hole CT, thereby forming ports corresponding to the electrodes, such as a gate port, a source port, and a drain port; the contact hole CT between the first electrode E1 in the second module 220 and the corresponding interconnect metal M is removed, that is, the contact hole CT in the port corresponding to the first electrode E1 in the second module 220 is removed; the first module 210 is used to determine the gate port capacitance Cgt of the transistor 204 to be tested; the second module 220 is used to determine the metal layer parasitic capacitance Cmetal and / or the contact hole parasitic capacitance Cct of the transistor 204 to be tested.

[0075] The gate port capacitance Cgt is used to characterize the capacitance between the gate port and other ports that need to be examined. The gate port capacitance Cgt of the transistor under test 204 is the capacitance between the gate port of the transistor under test 204 and other ports of the transistor under test 204, which are one or more ports except the gate port, and may include a source port, a drain port, and may also include a body region.

[0076] The metal layer parasitic capacitance Cmetal is used to characterize the parasitic capacitance between the gate port and the interconnecting metal M of other ports (source port and drain port). The metal layer parasitic capacitance Cmetal of the transistor to be tested 204 includes the parasitic capacitance between the gate port of the transistor to be tested 204 and the interconnecting metal M of other ports (source port and drain port) of the transistor to be tested 204.

[0077] The contact hole parasitic capacitance Cct is used to characterize the parasitic capacitance between the gate port and the contact hole CT of other ports (source port and drain port). The contact hole parasitic capacitance Cct of the transistor under test 204 is the parasitic capacitance between the gate port of the transistor under test 204 and the contact hole CT of other ports (source port and drain port) of the transistor under test 204.

[0078] The port referred to in this application includes the corresponding electrode (gate GT, source S or drain D), the contact hole CT on the electrode (if any) and the corresponding interconnection metal M.

[0079] After preparing two first modules 210, the above-mentioned second module 220 can be obtained by removing the contact hole CT between the first electrode E1 and the corresponding interconnection metal M in one of the first modules 210, that is, removing the contact hole CT in the port corresponding to the first electrode E1 in one of the first modules 210, so as to ensure that the only difference between the first module 210 and the second module 220 is whether the contact hole CT at the first electrode E1 is included.

[0080] The transistor to be tested 204 and the first transistor 206 may be the same transistor, such as MOSFET, FinField-Effect Transistor (FinField-Effect Transistor), etc.

[0081] In one embodiment, the first transistor 206 and the transistor to be tested 204 have the same doping type, such as both are PMOSFET or both are NMOSFET.

[0082] In one embodiment, the transistor to be tested 204 or the first transistor 206 may be a planar bulk silicon MOSFET, a SOI (Silicon On Insulator) MOSFET, a FinFET, or the like.

[0083] Specifically, after the first transistor 206 in the first module 210 is turned on, the gate port capacitance Cgt of the transistor to be tested 204 may be determined based on the first module 210 after the first transistor 206 is turned on.

[0084] Turning on the first transistor 206 may specifically include grounding the body region W of the first transistor 206 and applying an operating voltage to the gate GT, such as a sufficiently large positive voltage (the first transistor 206 is NMOS) or negative voltage (the first transistor 206 is PMOS).

[0085] After turning on the first transistor 206, the source S and drain D of the first transistor 206 and the transistor to be tested 204 can be connected to one end, and the capacitance between the gate port of the transistor to be tested 204 and any source S or drain D in the first module 210 is the gate port capacitance Cgt of the transistor to be tested 204.

[0086] In one embodiment, the ports corresponding to the first electrode E1, the second electrode E2 and the third electrode E3 in the first module 210 are connected as one port, which is recorded as the first port T1. The second electrode E2 is the electrode of the first transistor 206 in the first module 210 or the second module 220 except the first electrode E1 and the gate GT, and the third electrode E3 is the electrode of the transistor to be tested 204 in the first module 210 or the second module 220 except the first electrode E1 and the gate GT. That is, the drain D and the source S of the transistor to be tested 204 and the first transistor 206 in the first module 210 are connected together as the first port T1.

[0087] In one embodiment, the ports corresponding to the first electrode E1, the second electrode E2 and the third electrode E3 in the first module 210 can be respectively applied with corresponding voltages to simulate the use condition of the transistor to be tested 204, so that the ports corresponding to the first electrode E1, the second electrode E2 and the third electrode E3 are all used as the first port T1. That is, the drain D and the source S of the transistor to be tested 204 and the first transistor 206 in the first module 210 are both used as different first ports T1.

[0088] After the first transistor 206 in the first module 210 is turned on, the capacitance between the gate port of the transistor to be tested 204 and the first port T1 is determined to be the gate port capacitance Cgt.

[0089] In one embodiment, the interconnecting metals corresponding to the second electrode E2 and the third electrode E3 in the second module 220 are connected together as a port, which is recorded as the second port T2. After the first transistor 206 is turned on, the metal layer parasitic capacitance Cmetal can be obtained by measuring the capacitance between the gate port of the transistor to be tested 204 and the interconnecting metal corresponding to the first electrode E1; and the contact hole parasitic capacitance Cct can be obtained by measuring the capacitance between the interconnecting metal corresponding to the first electrode E1 and the second port T2, combined with the above metal layer parasitic capacitance Cmetal and the gate port capacitance Cgt.

[0090] The transistor parasitic capacitance test module provided in the present application provides a test module composed of a first module and a second module, wherein the first module and the second module both include a transistor to be tested and a first transistor, wherein in the first module and the second module, the transistor to be tested shares a body region and a first electrode with the corresponding first transistor, and the first electrode may be a drain or a source, and in the first module, each electrode, including a source, a drain and a gate, is connected to a corresponding interconnect metal through a contact hole to form a corresponding port, so as to lead out a corresponding electrode based on the port; the second module can be obtained by removing the contact hole of the first electrode in the first module, that is, the difference between the second module and the first module is that the first electrode in the first module is connected to the corresponding interconnect metal through a contact hole, and the contact hole between the first electrode and the corresponding interconnect metal in the second module is removed; by testing the transistor parasitic capacitance with a module composed of the first module and the second module with only the contact hole removed, the core structure of the component during normal use is retained, the consistency of the component characteristics during test and actual use is maintained, and the accuracy of measuring the parasitic capacitance using a comparative splitting method is guaranteed to the greatest extent.

[0091] Optionally, the first module 210 is specifically configured to:

[0092] After applying the working voltage to the gate GT of the first transistor 206 to turn on the first transistor 206 , the capacitance between the gate port of the transistor to be tested 204 and the first port T1 in the first module 210 is determined as the gate port capacitance Cgt.

[0093] Among them, the first port T1 includes a port corresponding to the first electrode E1, a port corresponding to the second electrode E2 and a port corresponding to the third electrode E3, the second electrode E2 is an electrode of the first transistor 206 in the first module 210 or the second module 220 excluding the first electrode E1 and the gate GT, and the third electrode E3 is an electrode of the transistor to be tested 204 in the first module 210 or the second module 220 excluding the first electrode E1 and the gate GT.

[0094] When testing the gate port capacitance Cgt, corresponding voltages can be applied to the ports corresponding to the first electrode E1, the second electrode E2, and the third electrode E3 to simulate the actual working conditions of the transistor 204 to be tested. The voltages applied to the ports corresponding to the three electrodes E1 to E3 can be different or the same.

[0095] Optionally, the first module 210 is specifically configured to:

[0096] After connecting the interconnecting metals corresponding to the first electrode E1, the second electrode E2 and the third electrode E3 as the first port T1, and applying an operating voltage to the gate GT of the first transistor 206 to turn on the first transistor 206, the capacitance between the gate port of the transistor to be tested 204 in the first module 210 and the first port T1 is determined to be the gate port capacitance Cgt of the transistor to be tested 204.

[0097] Taking the first electrode E1 as the drain D of the transistor to be tested 204 and the source S of the first transistor 206 as an example, the second electrode E2 is the source S of the transistor to be tested 204 and the drain D of the first transistor 206. Taking the first electrode E1 as the source S of the transistor to be tested 204 and the drain D of the first transistor 206 as an example, the second electrode E2 is the drain D of the transistor to be tested 204 and the source S of the first transistor 206.

[0098] When testing the gate port capacitance Cgt, the body region W shared by the first module 210 may be grounded.

[0099] In one embodiment, when testing the gate port capacitance Cgt, a bias voltage may be added to the gate GT, the body region W and the first port T1 of the first transistor 206 based on the actual working conditions of the transistor, so that the gate port capacitance Cgt obtained by the test is more in line with the actual usage scenario.

[0100] For example, Figure 3 For this application Figure 2 The connection diagram of the first module provided in the embodiment shown in FIG. Figure 3 As shown, when testing the gate port capacitance Cgt, after the body region W of the first module 210 is grounded, in order to simplify the test steps, the interconnection metal M in the ports corresponding to the first electrode E1, the second electrode E2 and the third electrode E3 can be connected together as the first port T1, so that the gate port of the first transistor 206 in the first module 210 is used as the control port, and a suitable working voltage is applied to the control port to ensure that the first transistor 206 is turned on. Thus, the capacitance between the first port T1 and the gate port of the transistor to be tested 204 in the first module 210 is measured by the measuring device, and the gate port capacitance Cgt of the transistor to be tested 204 is obtained.

[0101] In the first module 210, since the first transistor 206 and the transistor to be tested 204 share the body region W, after the first transistor 206 and the transistor to be tested 204 are turned on, it is equivalent to connecting a resistor in series on one side of the transistor to be tested 204. The gate port capacitance Cgt of the transistor to be tested 204 can be obtained by measuring the capacitance between the gate port of the transistor to be tested 204 and any other electrode except the gate GT of the first transistor 206, such as the source S or drain D of the first transistor 206 and the source S or drain D of the transistor to be tested 204, that is, by measuring the capacitance between the gate port of the transistor to be tested 204 and the first port T1.

[0102] By adding a transistor of the same type on one side of a single transistor and sharing a source and drain region with each other, a first module 210 is obtained. Through simple connection, the gate port capacitance Cgt can be measured based on the first module 210, laying the foundation for the subsequent measurement of the parasitic capacitance of the metal layer and the parasitic capacitance of the contact hole. The first module 210 has a simple structure, low test complexity, and is easy to implement.

[0103] Optionally, the second module 220 is specifically used for:

[0104] After applying an operating voltage to the gate GT of the first transistor 206 to turn on the first transistor 206, the metal layer parasitic capacitance Cmetal of the transistor to be tested 204 is determined based on the capacitance between the gate port of the transistor to be tested 204 and the interconnecting metal corresponding to the first electrode E1 in the second module 220; the contact hole parasitic capacitance Cct of the transistor to be tested 204 is determined based on the capacitance between the gate port of the transistor to be tested 204 and the second port T2 in the second module 220, the determined metal layer parasitic capacitance Cmetal and the gate port capacitance Cgt.

[0105] The second port T2 includes a port corresponding to the second electrode E2 and a port corresponding to the third electrode E3.

[0106] In one embodiment, when testing the metal layer parasitic capacitance Cmetal and the contact hole parasitic capacitance Cct, the required voltage can be applied to the port corresponding to the second electrode E2 and the port corresponding to the third electrode E3 according to actual needs. The voltages applied to the two ports can be different or the same.

[0107] Optionally, the second module 220 is specifically used for:

[0108] After connecting the interconnecting metal of the second electrode E2 and the interconnecting metal of the third electrode E3 as the second port T2, and applying an operating voltage to the gate GT of the first transistor 206 to turn on the first transistor 206, the metal layer parasitic capacitance Cmetal of the transistor to be tested 204 is determined based on the capacitance between the gate port of the transistor to be tested 204 and the interconnecting metal corresponding to the first electrode E1 in the second module 220; the contact hole parasitic capacitance Cct of the transistor to be tested 204 is determined based on the capacitance between the gate port of the transistor to be tested 204 and the second port T2 in the second module 220, the determined metal layer parasitic capacitance Cmetal, and the gate port capacitance Cgt.

[0109] During testing, a certain voltage may be applied to the second port T2 according to actual needs.

[0110] When testing the metal layer parasitic capacitance Cmetal and the contact hole parasitic capacitance Cct, it can be done through the first module 210 and the second module 220. Since the second module 220 lacks the contact hole at the first electrode E1 compared to the first module 210, the metal layer parasitic capacitance Cmetal and the contact hole parasitic capacitance Cct can be tested by comparing and splitting the first module 210 and the second module 220.

[0111] Specifically, after the first transistor 206 is turned on, the specific turning-on method can refer to the description of the aforementioned related parts, which will not be repeated here. Since the first electrode E1 (source S or drain D) of the transistor 204 to be tested in the second module 220 is disconnected from the corresponding interconnection metal, that is, the contact hole at the first electrode E1 is removed, the capacitance cannot be measured through the interconnection metal corresponding to the first electrode E1. Since in the second module 220, the transistor 204 to be tested and the first transistor 206 share the body region W, the state can be applied from the external port (T2) to the active area of ​​the transistor 24 to be tested through the first electrode E1 of the first transistor 206, the conductive channel after the first transistor 206 is turned on, the second electrode E2, and the interconnection metal layer corresponding to the second electrode E2, so as to measure the corresponding capacitance.

[0112] Optionally, the metal layer parasitic capacitance Cmetal is twice the first capacitance; the contact hole parasitic capacitance Cct is twice the difference between the gate port capacitance Cgt and the sum of the first capacitance and the second capacitance; wherein the first capacitance is the capacitance between the gate port of the transistor to be tested 204 in the second module 220 and the interconnecting metal corresponding to the first electrode E1, and the second capacitance is the capacitance between the gate GT of the transistor to be tested 204 in the second module 220 and the second port T2.

[0113] For example, Figure 4 For this application Figure 2The connection diagram of the second module provided in the embodiment shown in FIG. Figure 4 As shown, when performing the metal layer parasitic capacitance Cmetal and the contact hole parasitic capacitance Cct test, the body region W of the second module 220 needs to be grounded, and the interconnected metal connection corresponding to the second electrode E2 and the third electrode E3 is used as the second port T2, so that the gate port of the first transistor 206 in the second module 210 is used as the control port, and a suitable working voltage is applied to the control port to ensure that the first transistor 206 is turned on. Thus, the capacitance between the gate port of the transistor to be tested 204 and the interconnecting metal corresponding to the first electrode E1 is measured by the measuring device, and Cmetal / 2 is obtained; the capacitance between the gate port of the transistor to be tested 204 and the second port T2 in the second module 220 is measured by the measuring device, and Cint+Cf+Cct / 2+Cmetal / 2 is obtained. Since Cgt=Cint+Cf+Cct+Cmetal, finally, the difference between Cgt and the sum of the two capacitances obtained by the above measurement is calculated, that is, Cgt–(Cmetal / 2+Cint+Cf+Cct / 2+Cmetal / 2)=Cct / 2, and the metal layer parasitic capacitance Cmetal and the contact hole parasitic capacitance Cct are obtained.

[0114] In order to further improve the measurement accuracy, the embodiment of the present application also provides another transistor parasitic capacitance test module, which is configured by adding a transistor of the same type on both sides of the source S and the drain D of the transistor to be tested 204, respectively, and having a source and drain region (including an active region, a contact hole and an interconnect metal) shared between them, such as Figure 5 The symmetrical structure shown. Figure 5 A schematic diagram of a transistor parasitic capacitance test module according to another embodiment of the present invention, combined with Figure 2 and Figure 5 It can be seen that in this embodiment, the first module 210 and the second module 220 of the transistor parasitic capacitance testing module 20 both further include a second transistor 208 .

[0115] The transistor to be tested 204 is disposed between the corresponding first transistor 206 and the corresponding second transistor 208, the transistor to be tested 204 and the corresponding second transistor 208 share a body region W and a third electrode E3, the first electrode E1 and the third electrode E3 form a source S and a drain D of the transistor to be tested 204, and there is no contact hole CT between the third electrode E3 in the second module 220 and the corresponding interconnection metal M. That is, the contact hole CT in the port corresponding to the third electrode E3 in the second module 220 is removed.

[0116] Exemplarily, the third electrode E3 may be the drain D of the transistor to be tested 204 and the source S of the second transistor 208, or the third electrode E3 may be the source S of the transistor to be tested 204 and the drain D of the second transistor 208. In some cases, the source S and the drain D may be interchangeable, and the third electrode E3 may be the drain D of the transistor to be tested 204 and the drain D of the second transistor 208, or the third electrode E3 may be the source S of the transistor to be tested 204 and the source S of the second transistor 208.

[0117] After preparing the two first modules 210 , the contact holes corresponding to the first electrode E1 and the third electrode E3 of one of the first modules 210 may be removed to obtain the second module 220 .

[0118] In one embodiment, the first transistor 206 and the second transistor 208 may both be transistors of the same doping type as the transistor under test 204C. For example, the transistor under test 204, the first transistor 206, and the second transistor 208 may be the same transistor.

[0119] Figure 6 For this application Figure 5 The equivalent circuit diagram of the first module provided in the embodiment shown in FIG. Figure 5 and Figure 6 It can be seen that the transistor parasitic capacitance test module 20 is configured by respectively setting a transistor on both sides of the transistor to be tested 204, namely, a first transistor 206 and a second transistor 208. The transistor to be tested 204, the first transistor 206 and the second transistor 208 share the same body region W. The first transistor 206 and the transistor to be tested 204 share a first electrode E1, which can be the source S or drain D of the transistor to be tested 204. The second transistor 208 and the transistor to be tested 204 share a third electrode E3, which can be the drain or source S of the transistor to be tested 204. Figure 6 In the example, the first electrode E1 is the source S of the transistor under test 204, and the third electrode E3 is the drain D of the transistor under test 204. Since the transistor under test 204, the first transistor 206 and the second transistor 208 share a body region W, the body region W is usually grounded when in use.

[0120] When performing a parasitic capacitance test, the transistors on both sides of the transistor to be tested 204, i.e., the first transistor 206 and the second transistor 208, can be turned on first. After turning on the first transistor 206 and the second transistor 208, the metal layer parasitic capacitance Cmetal and the contact hole parasitic capacitance Cct are determined by measuring the capacitance between the gate port and the corresponding port of the transistor to be tested 204 in the first module 210 and the second module 220.

[0121] Optionally, the first module 210 is specifically configured to:

[0122] After applying working voltage to the gates GT of the first transistor 206 and the second transistor 208 to turn on the first transistor 206 and the second transistor 208 , the capacitance between the gate port of the transistor under test 204 and the third port T3 in the first module 210 is determined as the gate port capacitance Cgt of the transistor under test 204 .

[0123] The third port T3 includes ports corresponding to the first electrode E1, the second electrode E2, the third electrode E3 and the fourth electrode E4. The fourth electrode E4 is an electrode of the second transistor 208 in the first module 210 or the second module 220 other than the gate GT and the third electrode E3, such as the source S or the drain D.

[0124] When testing the gate port capacitance Cgt, the same or different voltages may be applied to each fourth port (ie, the first electrode E1 , the second electrode E2 , the third electrode E3 , and the fourth electrode E4 ).

[0125] Optionally, the first module 210 is specifically configured to:

[0126] After connecting the interconnecting metals corresponding to the first electrode E1, the second electrode E2, the third electrode E3 and the fourth electrode E4 as the third port T3, and applying an operating voltage to the gates GT of the first transistor 206 and the second transistor 208 to turn on the first transistor 206 and the second transistor 208, the capacitance between the gate port of the transistor to be tested 204 in the first module 210 and the third port T3 is determined to be the gate port capacitance Cgt of the transistor to be tested 204.

[0127] Since the first transistor 206 and the second transistor 208 share the same body region with the transistor to be tested 204, after the first transistor 206 and the second transistor 208 are turned on, they can be equivalent to a resistor, so that the transistors on the left and right sides of the transistor to be tested 204, i.e., the first transistor 206 and the second transistor 208, are used to control the DC state. Therefore, by measuring the capacitance between the lead-out end of the gate GT of the transistor to be tested 204, i.e., the gate port, and the third port T3, the gate port capacitance Cgt of the transistor to be tested 204 can be obtained.

[0128] When testing the gate port capacitance Cgt, the body region W shared by the first module 210 may be grounded.

[0129] In one embodiment, when testing the gate port capacitance Cgt, a bias voltage may be added to the gate GT, the body region W and the third port T3 of the first transistor 206 based on the actual working conditions of the transistor, so that the gate port capacitance Cgt obtained by the test is more in line with the actual usage scenario.

[0130] In one embodiment, the interconnected metals of the four electrodes, namely the first electrode E1, the second electrode E2, the third electrode E3 and the fourth electrode E4 in the first module 210, are connected together as a port, denoted as the third port T3, and the body region is grounded. During testing, a sufficiently large operating voltage is applied to the first transistor 206 in the first module 210 through a measuring device, thereby turning on the first transistor 206 and applying a state to the active region of the transistor to be tested 204 to test the gate port capacitance Cgt of the transistor to be tested 204.

[0131] Figure 7 For this application Figure 5 The connection diagram of the first module during testing in the embodiment shown is as follows: Figure 7 As shown in Figure 2, when testing the gate terminal capacitance Cgt, it is necessary to Figure 5 In the illustrated embodiment, the body region W of the first module 210 is grounded, the interconnected metal connections corresponding to the first electrode E1, the second electrode E2, the third electrode E3 and the fourth electrode E4 are used as the third port T3, the gate port of the first transistor 206 and the gate port of the second transistor 208 in the first module 210 are connected as the control port, and a suitable working voltage is applied to the control port to ensure that the first transistor 206 and the second transistor 208 are turned on. Thus, the capacitance between the third port T3 and the gate port of the transistor to be tested 204 in the first module 210 is measured by the measuring device to obtain the gate port capacitance Cgt of the transistor to be tested 204.

[0132] In the first module 210, since the first transistor 206 and the transistor to be tested 204 share the body region W, after the first transistor 206 and the second transistor 208 are turned on, it is equivalent to connecting a resistor in series on both sides of the transistor to be tested 204. The gate port capacitance Cgt of the transistor to be tested 204 can be obtained by measuring the capacitance between the gate port of the transistor to be tested 204 and the third port T3.

[0133] Optionally, the second module 220 is specifically used for:

[0134] After applying an operating voltage to the gates GT of the first transistor 206 and the second transistor 208 to turn on the first transistor 206 and the second transistor 208, the capacitance between the gate port of the transistor to be tested 204 and the fourth port T4 in the second module 220 is determined to be the metal layer parasitic capacitance Cmetal; based on the capacitance between the gate port of the transistor to be tested 204 and the fifth port T5 in the second module 220, the metal layer parasitic capacitance Cmetal and the gate port capacitance Cgt, the contact hole parasitic capacitance Cct of the transistor to be tested 204 is determined.

[0135] The fourth port T4 includes a port corresponding to the first electrode E1 and a port corresponding to the third electrode E3, the fifth port T5 includes a port corresponding to the second electrode E2 and a port corresponding to the fourth electrode E4, and the fourth electrode E4 is an electrode of the second transistor 208 in the first module 210 or the second module 220 except the gate GT and the third electrode E3.

[0136] When testing the metal layer parasitic capacitance Cmetal and the contact hole parasitic capacitance Cct, the same or different voltages may be applied to each port in the fourth port T4 and each port in the fifth port T5 according to actual requirements.

[0137] Optionally, the second module 220 is specifically used for:

[0138] After connecting the interconnect metal corresponding to the first electrode E1 and the interconnect metal corresponding to the third electrode E3 as the fourth port T4, connecting the interconnect metal corresponding to the second electrode E2 and the interconnect metal corresponding to the fourth electrode E4 as the fifth port T5, and applying an operating voltage to the gates GT of the first transistor 206 and the second transistor 208 to turn on the first transistor 206 and the second transistor 208, the capacitance between the gate port of the transistor to be tested 204 in the second module 220 and the fourth port T4 is determined to be the metal layer parasitic capacitance Cmetal; based on the capacitance between the gate port of the transistor to be tested 204 in the second module 220 and the fifth port T5, the metal layer parasitic capacitance Cmetal and the gate port capacitance Cgt, the contact hole parasitic capacitance Cct of the transistor to be tested 204 is determined.

[0139] In one embodiment, in the second module 220, the interconnecting metals corresponding to the first electrode E1 and the third electrode E3 are connected together as the fourth port T4; the interconnecting metals corresponding to the second electrode E2 and the fourth electrode E4 are connected together as the fifth port T5; the gate ports of the first transistor 206 and the second transistor 208 are connected together as the control port; the body region W can be grounded or connected to a certain voltage according to actual needs; the control port is configured to apply a working voltage to turn on the first transistor 206 and the second transistor 208. Therefore, after turning on the first transistor 206 and the second transistor 208, the metal layer parasitic capacitance Cmetal and the contact hole parasitic capacitance Cct are calculated based on the capacitance between the gate port of the transistor to be tested 204 and the fourth port T4, and the capacitance between the gate port and the fifth port obtained by the test.

[0140] Optionally, the contact hole parasitic capacitance Cct is the difference between the gate port capacitance Cgt and the sum of the metal layer parasitic capacitance Cmetal and the third capacitance; wherein the third capacitance is the capacitance between the gate port of the transistor to be tested 204 and the fifth port T5 in the second module 220 .

[0141] Figure 8 For this application Figure 5 The connection diagram of the second module during testing in the embodiment shown is as follows: Figure 8 As shown in the figure, when testing the metal layer parasitic capacitance Cmetal and the contact hole parasitic capacitance Cct, Figure 5 In the illustrated embodiment, the body region W of the second module 220 is grounded, the interconnected metal connection corresponding to the first electrode E1 and the third electrode E3 is used as the fourth port T4, the interconnected metal connection corresponding to the second electrode E2 and the fourth electrode E4 is used as the fifth port T3, and after the gate port of the first transistor 206 and the gate port of the second transistor 208 in the second module 220 are connected as the control port, a suitable operating voltage is applied to the control port to ensure that the first transistor 206 and the second transistor 208 are turned on. Thus, by measuring the capacitance between the fourth port T4 and the gate port of the transistor to be tested 204 in the second module 210 through the measuring device, the metal layer parasitic capacitance Cmetal of the transistor to be tested 204 can be obtained; by measuring the capacitance between the fifth port T5 and the gate port of the transistor to be tested 204 in the second module 210 through the measuring device, the above-mentioned third capacitance can be obtained, and its value is Cint+Cf. Since the gate port capacitance Cgt=Cint+Cf+Cmetal+Cct, the contact hole parasitic capacitance Cct can be obtained by calculating the gate port capacitance Cgt minus the measured metal layer parasitic capacitance Cmetal and the difference minus the third capacitance.

[0142] By adopting Figure 5 The module provided in the illustrated embodiment tests the parasitic capacitance by removing only part of the contact holes and keeping the core components consistent, and by using transistors arranged on both sides, it is possible to apply a state to the transistor 204 to be tested from the outside, which is easy to operate and has a high test accuracy.

[0143] An embodiment of the present application provides a transistor parasitic capacitance testing device, which includes a measuring device and a transistor parasitic capacitance testing module 20 provided by any of the above embodiments of the present application, wherein the measuring device is used to detect the metal layer parasitic capacitance Cmetal and / or the contact hole parasitic capacitance Cct of the transistor 204 to be tested.

[0144] The measuring device may be any device suitable for testing transistor capacitance.

[0145] In one embodiment, the transistor parasitic capacitance test device further includes a communication module, such as an input / output interface, a wireless communication module, etc., to output the measured metal layer parasitic capacitance Cmetal and / or contact hole parasitic capacitance Cct of the transistor to be tested 204. For example, the metal layer parasitic capacitance Cmetal and / or the contact hole parasitic capacitance Cct are sent to a user terminal, a display terminal, etc., so that the user can perform circuit design, simulation, modeling, etc. based on the metal layer parasitic capacitance Cmetal and / or the contact hole parasitic capacitance Cct.

[0146] In one embodiment, the transistor parasitic capacitance testing device further includes a display terminal to display the measured metal layer parasitic capacitance Cmetal and / or contact hole parasitic capacitance Cct.

[0147] In one embodiment, the voltage input to the control port can be changed to obtain a variation curve of the metal layer parasitic capacitance Cmetal and / or the contact hole parasitic capacitance Cct of the transistor 204 to be tested under different working conditions, and then the variation curve is output through the communication module and displayed through the display terminal.

[0148] Fig. 9 1 is a flow chart of a transistor parasitic capacitance testing method provided by an embodiment of the present application. The transistor parasitic capacitance testing method provided by this embodiment is applied to the transistor parasitic capacitance testing module 20 provided by any of the above embodiments of the present application. Fig. 9 As shown, the method comprises the following steps:

[0149] Step S901: determining the gate port capacitance of the gate of the transistor to be tested based on the first module.

[0150] Step S902: determining the metal layer parasitic capacitance and / or the contact hole parasitic capacitance of the transistor to be tested based on the second module and the gate port capacitance.

[0151] Optionally, based on the first module, determining the gate port capacitance of the gate of the transistor to be tested includes:

[0152] Applying an operating voltage to the gate of the first transistor of the first module to turn on the first transistor of the first module; determining the capacitance between the gate port and the first port of the transistor to be tested in the first module as the gate port capacitance; wherein the first port includes a port corresponding to the first electrode, a port corresponding to the second electrode, and a port corresponding to the third electrode.

[0153] Optionally, before applying an operating voltage to the gate of the first transistor to turn on the first transistor, the method further includes:

[0154] The interconnecting metals corresponding to the first electrode, the second electrode and the third electrode are connected to serve as the first port.

[0155] Optionally, determining the metal layer parasitic capacitance and / or the contact hole parasitic capacitance of the transistor to be tested based on the second module and the gate port capacitance includes:

[0156] Applying an operating voltage to the gate of the first transistor of the second module to turn on the first transistor of the second module; determining the metal layer parasitic capacitance based on the capacitance between the gate port of the transistor to be tested in the second module and the interconnected metal corresponding to the first electrode; determining the contact hole parasitic capacitance based on the capacitance between the gate port of the transistor to be tested in the second module and the second port, the metal layer parasitic capacitance and the gate port capacitance; wherein the second port includes a port corresponding to the second electrode and a port corresponding to the third electrode, the second electrode is an electrode of the first transistor in the first module or the second module excluding the first electrode and the gate, and the third electrode is an electrode of the transistor to be tested in the first module or the second module excluding the first electrode and the gate.

[0157] Optionally, before applying an operating voltage to the gate of the first transistor of the second module to turn on the first transistor of the second module, the method further includes:

[0158] The interconnection metal connecting the second electrode and the interconnection metal connecting the third electrode serves as a second port.

[0159] Optionally, based on the first module, determining the gate port capacitance of the gate of the transistor to be tested includes:

[0160] Applying an operating voltage to the gates of the first transistor and the second transistor of the first module to turn on the first transistor and the second transistor of the first module; determining the capacitance between the gate port and the third port of the transistor to be tested in the first module as the gate port capacitance.

[0161] Among them, the third port includes ports corresponding to four electrodes, namely, a first electrode, a second electrode, a third electrode and a fourth electrode. The second electrode is an electrode of the first transistor in the first module or the second module excluding the first electrode and the gate. The fourth electrode is an electrode of the second transistor in the first module or the second module excluding the gate and the third electrode.

[0162] Optionally, before applying an operating voltage to the gates of the first transistor and the second transistor of the first module to turn on the first transistor and the second transistor of the first module, the method further includes:

[0163] The interconnecting metals corresponding to the first electrode, the second electrode, the third electrode and the fourth electrode are connected to serve as a third port.

[0164] Optionally, determining the metal layer parasitic capacitance and / or the contact hole parasitic capacitance of the transistor to be tested based on the second module and the gate port capacitance includes:

[0165] After applying an operating voltage to the gates of the first transistor and the second transistor of the second module to turn on the first transistor and the second transistor of the second module, determine that the capacitance between the gate port and the fourth port of the transistor to be tested in the second module is the metal layer parasitic capacitance; determine the contact hole parasitic capacitance based on the capacitance between the gate port and the fifth port of the transistor to be tested in the second module, the metal layer parasitic capacitance and the gate port capacitance; wherein the fourth port includes a port corresponding to the first electrode and a port corresponding to the third electrode, the fifth port includes a port corresponding to the second electrode and a port corresponding to the fourth electrode, the second electrode is an electrode of the first transistor in the first module or the second module excluding the first electrode and the gate, and the fourth electrode is an electrode of the second transistor in the first module or the second module excluding the gate and the third electrode.

[0166] Optionally, before applying an operating voltage to the gates of the first transistor and the second transistor to turn on the first transistor and the second transistor, the method further includes:

[0167] The interconnection metal corresponding to the first electrode and the interconnection metal corresponding to the third electrode are connected as the fourth port; the interconnection metal corresponding to the second electrode and the interconnection metal corresponding to the fourth electrode are connected as the fifth port.

[0168] An embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the transistor parasitic capacitance testing method provided by any embodiment of the present application is implemented.

[0169] An embodiment of the present application also provides a computer program product, including a computer program, which, when executed by a processor, is used to implement the transistor parasitic capacitance testing method provided in any embodiment of the present application.

[0170] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0171] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0172] In addition, each functional module in each embodiment of the present application can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The above-mentioned module-composed unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

[0173] The above-mentioned integrated module implemented in the form of a software function module can be stored in a computer-readable storage medium. The above-mentioned software function module is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to perform some steps of the method described in each embodiment of the present application.

[0174] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0175] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A transistor parasitic capacitance test module, characterized in that: include: A first module and a second module; the first module and the second module both include a transistor to be tested and a first transistor; The transistor to be tested shares a body region and a first electrode with the corresponding first transistor, and the first electrode is a source or a drain; Each electrode, including a gate, a source and a drain, except the first electrode in the second module is connected to a corresponding interconnect metal through a contact hole; the contact hole in the port corresponding to the first electrode in the second module is removed; the first module is used to determine the gate port capacitance of the transistor to be tested; The second module is used to determine the metal layer parasitic capacitance and / or the contact hole parasitic capacitance of the transistor to be tested; Among them, the gate port capacitance of the transistor to be tested is the capacitance between the gate port of the transistor to be tested and the other ports of the transistor to be tested; the metal layer parasitic capacitance of the transistor to be tested includes the parasitic capacitance between the gate port of the transistor to be tested and the interconnecting metal of the other ports of the transistor to be tested; the contact hole parasitic capacitance of the transistor to be tested is the parasitic capacitance between the gate port of the transistor to be tested and the contact hole of the other ports of the transistor to be tested, and the port includes the corresponding electrode, the contact hole on the electrode and the corresponding interconnecting metal.

2. The module according to claim 1, characterized in that: The first module is specifically used for: After applying an operating voltage to the gate of the first transistor to turn on the first transistor, determining a capacitance between a gate port and a first port of the transistor to be tested in the first module as the gate port capacitance; Among them, the first port includes a port corresponding to the first electrode, a port corresponding to the second electrode and a port corresponding to the third electrode, the second electrode is the electrode of the first transistor in the first module or the second module excluding the first electrode and the gate, and the third electrode is the electrode of the transistor to be tested in the first module or the second module excluding the first electrode and the gate.

3. The module according to claim 1, characterized in that: The second module is specifically used for: After applying an operating voltage to the gate of the first transistor to turn on the first transistor, determining the metal layer parasitic capacitance based on the capacitance between the gate port of the transistor to be tested and the interconnect metal corresponding to the first electrode in the second module; Determine the contact hole parasitic capacitance based on the capacitance between the gate port and the second port of the transistor to be tested in the second module, the metal layer parasitic capacitance, and the gate port capacitance; Among them, the second port includes a port corresponding to a second electrode and a port corresponding to a third electrode, the second electrode is an electrode of the first transistor in the first module or the second module excluding the first electrode and the gate, and the third electrode is an electrode of the transistor to be tested in the first module or the second module excluding the first electrode and the gate.

4. The module according to claim 3, characterized in that: The parasitic capacitance of the metal layer is twice that of the first capacitance; The contact hole parasitic capacitance is twice the difference between the gate port capacitance and the sum of the first capacitance and the second capacitance; The first capacitor is the capacitance between the gate port of the transistor to be tested in the second module and the interconnect metal corresponding to the first electrode, and the second capacitor is the capacitance between the gate port of the transistor to be tested in the second module and the second port.

5. The module according to claim 1, characterized in that: The first module and the second module also each include a second transistor; The transistor to be tested is arranged between the corresponding first transistor and the corresponding second transistor, the transistor to be tested and the corresponding second transistor share a body region and a third electrode, and the first electrode and the third electrode constitute a source and a drain of the transistor to be tested; There is no contact hole between the third electrode in the second module and the corresponding interconnection metal.

6. The module according to claim 5, characterized in that: The first module is specifically used for: After applying an operating voltage to the gates of the first transistor and the second transistor to turn on the first transistor and the second transistor, determining a capacitance between a gate port and a third port of the transistor to be tested in the first module as the gate port capacitance; Among them, the third port includes ports corresponding to four electrodes, namely, a first electrode, a second electrode, a third electrode and a fourth electrode. The second electrode is an electrode of the first transistor in the first module or the second module excluding the first electrode and the gate. The fourth electrode is an electrode of the second transistor in the first module or the second module excluding the gate and the third electrode.

7. The module according to claim 5, characterized in that: The second module is specifically used for: After applying an operating voltage to the gates of the first transistor and the second transistor to turn on the first transistor and the second transistor, determining that the capacitance between the gate port of the transistor to be tested and the fourth port in the second module is the metal layer parasitic capacitance; Determine the contact hole parasitic capacitance based on the capacitance between the gate port and the fifth port of the transistor to be tested in the second module, the metal layer parasitic capacitance, and the gate port capacitance; Among them, the fourth port includes a port corresponding to the first electrode and a port corresponding to the third electrode, the fifth port includes a port corresponding to the second electrode and a port corresponding to the fourth electrode, the second electrode is an electrode of the first transistor in the first module or the second module excluding the first electrode and the gate, and the fourth electrode is an electrode of the second transistor in the first module or the second module excluding the gate and the third electrode.

8. The module according to claim 7, characterized in that: The contact hole parasitic capacitance is the difference between the gate port capacitance and the sum of the metal layer parasitic capacitance and the third capacitance; The third capacitor is a capacitor between the gate port of the transistor to be tested and the fifth port in the second module.

9. A transistor parasitic capacitance testing device, characterized in that: include: A measuring device and a transistor parasitic capacitance test module as described in any one of claims 1 to 8.

10. A transistor parasitic capacitance testing method, characterized in that: The method is applied to the transistor parasitic capacitance test module provided by any one of claims 1 to 8, and the method comprises: Based on the first module, determining the gate port capacitance of the gate of the transistor to be tested; Based on the second module and the gate port capacitance, the metal layer parasitic capacitance and / or the contact hole parasitic capacitance of the transistor to be tested is determined.

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