Cmos transistor based on alpn / gapn heterojunction and method of manufacturing the same

Abstract

The application discloses a CMOS transistor based on an AlPN / GaPN heterojunction and a preparation method thereof. The transistor comprises, from bottom to top, a substrate, a first AlN layer, a second AlN layer, a GaN buffer layer and a SiN isolation layer, wherein a P-HEMT active area groove and an N-HEMT active area groove are formed in the SiN isolation layer; a first AlPN barrier layer, a first GaPN channel layer and a first GaN cap layer are sequentially arranged in the P-HEMT active area groove from bottom to top; a second GaPN channel layer, a second AlPN barrier layer and a second GaN cap layer are sequentially arranged in the N-HEMT active area groove from bottom to top; a first source, a first drain and a first gate are arranged on the upper surface of the first GaN cap layer and are spaced from each other; and a second source, a second drain and a second gate are arranged on the upper surface of the second GaN cap layer and are spaced from each other. The AlPN / GaPN heterojunction can realize lattice matching, the in-plane stress of the heterojunction can be effectively relieved, and the electrical performance of two-dimensional electron gas can be effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic integrated circuits, and in particular relates to a CMOS transistor based on an AlPN / GaPN heterojunction and a preparation method thereof. Background Art

[0002] Third-generation semiconductors, represented by gallium nitride (GaN), possess superior physical and chemical properties, including wide bandgap, high breakdown field strength, high thermal conductivity, low dielectric constant, high electron saturation drift velocity, strong radiation resistance, and good chemical stability. Following first-generation semiconductor silicon and second-generation semiconductor gallium arsenide, they have become key materials for the fabrication of next-generation microelectronic devices and circuits. They are particularly well-suited for the development of high-frequency, high-power, high-temperature, and radiation-resistant electronic devices and circuits. GaN-based semiconductor materials, as the most important of these third-generation semiconductors, have a wide bandgap, effectively suppressing interband tunneling and gate-induced drain leakage, leading to widespread commercial application.

[0003] Currently used ternary alloy heterojunction structures, such as AlGaN / GaN heterojunctions, have stress between the barrier layer and the channel layer, and between the channel layer and the underlying buffer layer. This can lead to poor film crystallization quality. Carriers in the channel below suffer from high alloy disorder scattering and inter-carrier scattering, which deteriorates the electrical properties of the two-dimensional electron gas, such as mobility, surface density, and sheet resistance. This in turn reduces device performance and limits the development of many applications. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a CMOS transistor based on an AlPN / GaPN heterojunction and a method for manufacturing the same. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] One aspect of the present invention provides a CMOS transistor based on an AlPN / GaPN heterojunction, comprising a substrate, a first AlN layer, a second AlN layer, a GaN buffer layer, and a SiN isolation layer arranged in sequence from bottom to top, wherein:

[0006] A P-HEMT active region groove and an N-HEMT active region groove are formed on the SiN isolation layer, and the P-HEMT active region groove and the N-HEMT active region groove extend from the upper surface of the SiN isolation layer to the upper surface of the GaN buffer layer;

[0007] The P-HEMT active region groove is provided with a first AlPN barrier layer, a first GaPN channel layer and a first GaN cap layer in sequence from bottom to top; the N-HEMT active region groove is provided with a second GaPN channel layer, a second AlPN barrier layer and a second GaN cap layer in sequence from bottom to top;

[0008] A first source electrode, a first drain electrode, and a first gate electrode are provided on the upper surface of the first GaN cap layer and are spaced apart from each other; a second source electrode, a second drain electrode, and a second gate electrode are provided on the upper surface of the second GaN cap layer and are spaced apart from each other;

[0009] The growth temperature of the first AlN layer is lower than the growth temperature of the second AlN layer.

[0010] In one embodiment of the present invention, the P-HEMT active region groove and the N-HEMT active region groove are symmetrically opened inside the SiN isolation layer, and both extend from one side surface of the SiN isolation layer to the other opposite side surface.

[0011] In one embodiment of the present invention, the first source, the first drain and the first gate are isolated from each other by SiN material, and the first gate is located between the first source and the first drain; the second source, the second drain and the second gate are isolated from each other by SiN material, and the second gate is located between the second source and the second drain.

[0012] In one embodiment of the present invention, a pre-laid aluminum layer is further included between the substrate and the first AlN layer.

[0013] In one embodiment of the present invention, the surface areas of the first AlPN barrier layer and the first GaPN channel layer are equal, and both are equal to the inner surface area of ​​the P-HEMT active region groove; the surface areas of the second GaPN channel layer and the second AlPN barrier layer are equal, and both are equal to the inner surface area of ​​the N-HEMT active region groove.

[0014] In one embodiment of the present invention, the first AlPN barrier layer and the first GaPN channel layer form a heterojunction structure AlPN / GaPN, and the second GaPN channel layer and the second AlPN barrier layer form a heterojunction structure GaPN / AlPN.

[0015] In one embodiment of the present invention, the thickness of the first AlPN barrier layer is 20-40 nm, the thickness of the first GaPN channel layer is 10-30 nm; the thickness of the second GaPN channel layer is 10-30 nm, and the thickness of the second AlPN barrier layer is 20-40 nm.

[0016] Another aspect of the present invention provides a method for preparing a CMOS transistor based on an AlPN / GaPN heterojunction, which is used to prepare the CMOS transistor described in any one of the above embodiments, and the preparation method comprises:

[0017] selecting a substrate and performing a pre-baking process on the substrate;

[0018] sequentially growing a first AlN layer, a second AlN layer, and a GaN buffer layer on the substrate;

[0019] Depositing a SiN isolation layer on the GaN buffer layer, and etching a P-HEMT active area groove on the SiN isolation layer;

[0020] forming a first AlPN barrier layer and a first GaPN channel layer from bottom to top in the groove of the P-HEMT active area;

[0021] Etching an N-HEMT active region groove on the SiN isolation layer, and forming a second GaPN channel layer and a second AlPN barrier layer from bottom to top in the N-HEMT active region groove;

[0022] growing a first GaN cap layer on the first GaPN channel layer, and growing a second GaN cap layer on the second AlPN barrier layer;

[0023] A first source electrode, a first drain electrode, and a first gate electrode are formed on the first GaN cap layer, and a second source electrode, a second drain electrode, and a second gate electrode are formed on the second GaN cap layer.

[0024] In one embodiment of the present invention, the first AlN layer, the second AlN layer and the GaN buffer layer are sequentially grown on the substrate, comprising:

[0025] At a temperature of 1050° C. to 1150° C., trimethylaluminum is introduced into a reaction chamber of an MOCVD device to grow a pre-laid aluminum layer with a thickness of 30 to 100 nm on the substrate;

[0026] introducing trimethylaluminum and ammonia to grow a first AlN layer with a thickness of 20-40 nm on the pre-deposited aluminum layer;

[0027] The reaction chamber temperature is adjusted to 1150° C. to 1250° C., and trimethylaluminum and ammonia are introduced to grow a second AlN layer with a thickness of 150 to 200 nm on the first AlN layer;

[0028] The temperature of the reaction chamber is adjusted to 1100° C.-1200° C., and trimethylgallium and ammonia are introduced to grow a GaN buffer layer with a thickness of 800-1000 nm on the second AlN layer.

[0029] In one embodiment of the present invention, a first AlPN barrier layer and a first GaPN channel layer are formed from bottom to top in the groove of the P-HEMT active region, including:

[0030] Adjusting the temperature of the MOCVD equipment reaction chamber to 1150°C-1160°C, introducing trimethylaluminum, tert-butylphosphine, and ammonia to react and form a first AlPN barrier layer with a thickness of 20-40 nm, wherein the lower surface of the first AlPN barrier layer contacts the upper surface of the GaN buffer layer, wherein the flow rate of trimethylaluminum is 100 sccm, the flow rate of tert-butylphosphine is 30 sccm, and the flow rate of ammonia is 4000 sccm;

[0031] The temperature of the MOCVD equipment reaction chamber was adjusted to 1070°C-1085°C, and trimethylgallium, tert-butylphosphine, and ammonia were introduced to react on the first AlPN barrier layer to form a first GaPN channel layer with a thickness of 10-30 nm. The flow rate of trimethylgallium was 500 sccm, the flow rate of tert-butylphosphine was 800 sccm, and the flow rate of ammonia was 50,000 sccm.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] 1. The CMOS transistor of the present invention is based on an AlPN / GaPN heterojunction, which can achieve lattice matching. The in-plane stress of the heterojunction can be effectively alleviated, and the electrical performance of the two-dimensional electron gas can be effectively improved. In addition, the two-dimensional hole gas mobility in GaPN / AlPN is relatively large, thereby enabling high-performance CMOS transistors and circuit applications.

[0034] 2. This embodiment utilizes the two-dimensional hole gas induced by polarization in the GaPN / AlPN heterojunction as the source of P-type HEMT carriers and realizes monolithic integration with N-type HEMT materials, which can fill the gap of high-performance PMOS transistors and thus meet the requirements of high-performance CMOS.

[0035] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Schematic diagram of the structure of a CMOS transistor based on an AlPN / GaPN heterojunction provided by an embodiment of the present invention;

[0037] Figure 2 1 is a top view of a CMOS transistor based on an AlPN / GaPN heterojunction provided by an embodiment of the present invention;

[0038] Figure 3 This is a flow chart of a method for preparing a CMOS transistor based on an AlPN / GaPN heterojunction provided by an embodiment of the present invention;

[0039] Figures 4a to 4gThis is a schematic diagram of a preparation process of a CMOS transistor based on an AlPN / GaPN heterojunction provided by an embodiment of the present invention.

[0040] Description of reference numerals:

[0041] 1-substrate; 2-first AlN layer; 3-second AlN layer; 4-GaN buffer layer; 5-SiN isolation layer; 6-P-HEMT active region groove; 7-first AlPN barrier layer; 8-first GaPN channel layer; 9-N-HEMT active region groove; 10-second GaPN channel layer; 11-second AlPN barrier layer; 12-first GaN cap layer; 13-second GaN cap layer; 14-first source; 15-first drain; 16-first gate; 17-second source; 18-second drain; 19-second gate. DETAILED DESCRIPTION

[0042] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following is a detailed description of a CMOS transistor based on an AlPN / GaPN heterojunction and a preparation method thereof proposed in accordance with the present invention, in conjunction with the accompanying drawings and specific embodiments.

[0043] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0044] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the element.

[0045] Example 1

[0046] See Figure 1 , Figure 1The present invention provides a schematic structural diagram of a CMOS transistor based on an AlPN / GaPN and GaPN / AlPN heterojunction according to an embodiment of the present invention. The CMOS transistor comprises, arranged from bottom to top, a substrate 1, a first AlN layer 2, a second AlN layer 3, a GaN buffer layer 4, and a SiN isolation layer 5. A P-HEMT active region recess 6 and an N-HEMT active region recess 9 are formed on the SiN isolation layer 5. The depths of the P-HEMT active region recess 6 and the N-HEMT active region recess 9 are both equal to the thickness of the SiN isolation layer 5. In other words, the P-HEMT active region recess 6 and the N-HEMT active region recess 9 extend from the upper surface of the SiN isolation layer 5 to the upper surface of the GaN buffer layer 4. A first AlPN barrier layer 7, a first GaPN channel layer 8, and a first GaN cap layer 12 are sequentially arranged in the P-HEMT active region groove 6 from bottom to top; a second GaPN channel layer 10, a second AlPN barrier layer 11, and a second GaN cap layer 13 are sequentially arranged in the N-HEMT active region groove 9 from bottom to top; a first source electrode 14, a first drain electrode 15, and a first gate electrode 16 are spaced apart from each other on the upper surface of the first GaN cap layer 12; and a second source electrode 17, a second drain electrode 18, and a second gate electrode 19 are spaced apart from each other on the upper surface of the second GaN cap layer 13.

[0047] In this embodiment, the substrate 1 is a sapphire substrate. The first AlN layer 2 is a low-temperature AlN layer, and the second AlN layer 3 is a high-temperature AlN layer. The growth temperature of the first AlN layer 2 is lower than the growth temperature of the second AlN layer 3. Preferably, the thickness of the first AlN layer 2 is 20-40 nm, and the thickness of the second AlN layer 3 is 150-200 nm. The first AlN layer 2 is formed by reaction at a temperature of 1050°C-1150°C, and the second AlN layer 3 is formed by reaction at a temperature of 1150°C-1250°C. AlN growth at relatively low temperatures adopts a three-dimensional growth mode, and at relatively high temperatures adopts a two-dimensional growth mode. The thickness of the GaN buffer layer 4 is 800-1000 nm.

[0048] Furthermore, a pre-laid aluminum layer (not shown in the drawings) is also included between the substrate 1 and the first AlN layer 2, with a thickness of about 20-40 nm. Since Al atoms have poor mobility on the substrate surface, the pre-laid aluminum layer can effectively improve the mobility of aluminum and improve the quality of subsequent epitaxial layers, thereby improving the electrical performance of the transistor.

[0049] See Figure 1 and Figure 2 , Figure 2FIG2 is a top view of a CMOS transistor based on an AlPN / GaPN heterojunction according to an embodiment of the present invention. A P-HEMT active region recess 6 and an N-HEMT active region recess 9 are symmetrically disposed within a SiN isolation layer 5 and extend from one side of the SiN isolation layer 5 to the other opposite side. In other words, both the P-HEMT active region recess 6 and the N-HEMT active region recess 9 are open-ended trenches, and their widths are equal to the width of the SiN isolation layer 5.

[0050] Furthermore, the P-HEMT active region recess 6 and the N-HEMT active region recess 9 have the same depth. The lower surfaces of the P-HEMT active region recess 6 and the N-HEMT active region recess 9 are in contact with the upper surface of the GaN buffer layer 4. The surface areas of the first AlPN barrier layer 7 and the first GaPN channel layer 8 are equal, both equal to the inner surface area of ​​the P-HEMT active region recess 6. The first AlPN barrier layer 7 and the first GaPN channel layer 8 form a heterojunction structure AlPN / GaPN. The surface areas of the second GaPN channel layer 10 and the second AlPN barrier layer 11 are equal, both equal to the inner surface area of ​​the N-HEMT active region recess 9. The second GaPN channel layer 10 and the second AlPN barrier layer 11 form a heterojunction structure GaPN / AlPN.

[0051] Furthermore, the thickness of the first AlPN barrier layer 7 is 20-40 nm, the thickness of the first GaPN channel layer 8 is 10-30 nm; the thickness of the second GaPN channel layer 10 is 10-30 nm, and the thickness of the second AlPN barrier layer 11 is 20-40 nm.

[0052] like Figure 2 As shown, the first source 14, the first drain 15, and the first gate 16 are isolated from each other by SiN material, and the first gate 16 is located between the first source 14 and the first drain 15. The lower surfaces of the first source 14, the first drain 15, and the first gate 16 are in contact with the upper surface of the first GaN cap layer 12, and form ohmic contacts respectively.

[0053] The second source 17, the second drain 18 and the second gate 19 are isolated from each other by SiN material, and the second gate 19 is located between the second source 17 and the second drain 18. The lower surfaces of the second source 17, the second drain 18 and the second gate 19 are in contact with the upper surface of the second GaN cap layer 13, and form ohmic contacts respectively.

[0054] Preferably, the first source electrode 14 , the first drain electrode 15 , the second source electrode 17 and the second drain electrode 18 comprise four metal layers of Ti / Al / Ni / Au from bottom to top, and the first gate electrode 16 and the second gate electrode 19 comprise two metal layers of Ni / Au from bottom to top.

[0055] This embodiment proposes a CMOS transistor based on an AlPN / GaPN heterojunction. Compared with the traditional AlGaN / GaN heterojunction transistor, the lattice matching between the two materials AlPN and GaPN is extremely small. This embodiment uses AlPN as a barrier layer, which can effectively suppress the high lattice vibration scattering caused by the degradation of the thin film material quality, and uses band modulation to improve the confinement of the two-dimensional electron gas, thereby improving the electrical properties such as the surface density and mobility of the two-dimensional electron gas. AlPN and GaPN can achieve better lattice matching than traditional AlGaN and GaN, avoiding the adverse effects of warping and heat dissipation problems caused by in-plane stress on the performance of subsequent devices. In addition, this embodiment uses the two-dimensional hole gas induced by polarization in the GaPN / AlPN heterojunction as the source of P-type HEMT carriers, and realizes monolithic integration with N-type HEMT materials, which can fill the gap in high-performance PMOS transistors and thus meet the requirements of high-performance CMOS.

[0056] Example 2

[0057] Based on the above embodiments, this embodiment proposes a method for preparing a CMOS transistor based on an AlPN / GaPN heterojunction. The preparation process is carried out under the conditions of metal organic chemical vapor deposition (MOCVD) equipment. The MOCVD growth process is carried out under certain pressure and temperature. The metal organic sources in the preparation process are ammonia, TMAl (trimethylaluminum), TMGa (trimethylgallium), and tBp (tert-butyl phosphine), and the carrier gas is N2. Specifically, the preparation method of the CMOS transistor of this embodiment includes the following steps:

[0058] S1: selecting a substrate 1 and performing a pre-baking process on the substrate.

[0059] Specifically, sapphire is selected as the substrate 1 and is pre-baked in an MOCVD device.

[0060] S2: A first AlN layer 2, a second AlN layer 3 and a GaN buffer layer 4 are sequentially grown on the substrate 1. Figure 4a shown.

[0061] S2 of this embodiment includes:

[0062] S21: Under the temperature condition of 1050° C.-1150° C., trimethylaluminum is introduced into the reaction chamber of the MOCVD equipment to grow a pre-deposited aluminum layer on the substrate 1 .

[0063] Specifically, under the temperature condition of 1100°C in the reaction chamber of the MOCVD equipment, trimethylaluminum is introduced for 3 minutes, and a pre-laid aluminum layer is grown on the substrate 1 to obtain a 30-100nm pre-laid aluminum layer (not shown in the accompanying drawings). Since Al atoms have poor mobility on the substrate surface, the pre-laid aluminum layer can effectively improve the mobility of aluminum and improve the quality of subsequent epitaxial layers, thereby improving the electrical performance of the transistor.

[0064] S22: Under the temperature condition of 1050° C.-1150° C., trimethylaluminum and ammonia are introduced to grow a first AlN layer 2 on the pre-deposited aluminum layer.

[0065] Specifically, under the temperature condition of 1100° C. in the MOCVD equipment reaction chamber, trimethylaluminum and ammonia are introduced to grow a first AlN layer 2 with a thickness of 20-40 nm on the pre-deposited aluminum layer. AlN grows in a three-dimensional growth mode at a relatively low temperature.

[0066] S23 : adjusting the temperature of the reaction chamber to 1150° C.-1250° C., introducing trimethylaluminum and ammonia to grow a second AlN layer 3 on the first AlN layer 2 .

[0067] Specifically, under a temperature of 1210°C in the MOCVD chamber, trimethylaluminum and ammonia are introduced to grow a 150-200nm thick second AlN layer 3 on the first AlN layer 2. AlN grows at a relatively high temperature in a two-dimensional pattern. This embodiment utilizes a variable temperature growth pattern for the second AlN layer 3 and the first AlN layer 2, resulting in lower roughness and better crystal quality in the subsequent epitaxial layer.

[0068] S24 : adjusting the temperature of the reaction chamber to 1100° C.-1200° C., introducing trimethylgallium and ammonia to grow a GaN buffer layer 4 on the second AlN layer 3 .

[0069] Specifically, under the temperature condition of 1150° C. in the reaction chamber of the MOCVD equipment, trimethylgallium and ammonia are introduced for 40 minutes to grow a GaN buffer layer 4 with a thickness of 800-1000 nm on the basis of the second AlN layer 3 .

[0070] S3: depositing a SiN isolation layer 5 on the GaN buffer layer 4, and etching a P-HEMT active region groove 6 on the SiN isolation layer 5, as shown in FIG. Figure 4b1 and Figure 4b2 As shown, Figure 4b2 yes Figure 4b1 The corresponding top view.

[0071] Specifically, a SiN spacer layer 5 is deposited on the GaN buffer layer 4. A P-HEMT active area pattern is then formed on the SiN spacer layer 5 by photolithography. The P-HEMT active area pattern is then etched to form a P-HEMT active area recess 6. The depth of the P-HEMT active area recess 6 is equal to the thickness of the SiN spacer layer 5, so that the bottom surface of the P-HEMT active area recess 6 extends to the top surface of the GaN buffer layer 4. The P-HEMT active area recess 6 also extends from one side surface of the SiN spacer layer 5 to the opposite side surface. In other words, the P-HEMT active area recess 6 is a trench open at both ends, and its width is equal to the width of the SiN spacer layer 5.

[0072] S4: forming a first AlPN barrier layer 7 and a first GaPN channel layer 8 from bottom to top in the P-HEMT active region groove 6 .

[0073] Specifically, the MOCVD chamber temperature is adjusted to 1150°C-1160°C, and trimethylaluminum, tert-butylphosphine, and ammonia are introduced to grow a first AlPN barrier layer 7 with a thickness of 20-40 nm in the P-HEMT active region recess 6. The lower surface of the first AlPN barrier layer 7 contacts the upper surface of the GaN buffer layer 4. This first AlPN barrier layer 7 has a low V / III ratio (the molar ratio of Group V element N to Group III element Ga or Al) to allow P elements to replace N vacancies and reduce tensile stress. In this embodiment, the V / III ratio of this first AlPN barrier layer 7 is greater than or equal to 1000.

[0074] Subsequently, the MOCVD chamber temperature is adjusted to 1070°C-1085°C, and trimethylgallium, tert-butylphosphine, and ammonia gases are introduced to grow a 10-30 nm thick first GaPN channel layer 8 on the first AlPN barrier layer 7. The V / III ratio of this first GaPN channel layer 8 is lower than that of the first AlPN barrier layer 7, allowing P elements to replace Ga vacancies and reduce compressive stress. In this embodiment, the depth of the P-HEMT active region recess 6 is equal to the combined thickness of the first AlPN barrier layer 7 and the first GaPN channel layer 8.

[0075] S5: etching an N-HEMT active region groove 9 on the SiN isolation layer 5, and forming a second GaPN channel layer 10 and a second AlPN barrier layer 11 from bottom to top in the N-HEMT active region groove 9.

[0076] Specifically, first, SiN material is deposited on the upper surface of the sample obtained in step S4 as a hard mask, and the N-HEMT active area pattern is photolithographically formed and the SiN isolation layer 5 in the N-HEMT active area pattern is etched away to form an N-HEMT active area groove 9 separated from the P-HEMT active area groove 6, as shown in FIG. Figure 4d1 and Figure 4d2 As shown, Figure 4d2 yes Figure 4d1 Corresponding top view. In this embodiment, the P-HEMT active area recess 6 and the N-HEMT active area recess 9 are symmetrically defined on either side of the upper surface of the SiN isolation layer 5 and have the same shape and depth. In other words, the depth of the N-HEMT active area recess 9 is equal to the thickness of the SiN isolation layer 5, so that the lower surface of the N-HEMT active area recess 9 extends to the upper surface of the GaN buffer layer 4. Both the P-HEMT active area recess 6 and the N-HEMT active area recess 9 are open-ended trenches, and their widths are equal to the width of the SiN isolation layer 5.

[0077] Furthermore, the temperature of the MOCVD equipment reaction chamber is adjusted to 1070°C-1085°C, and trimethylgallium, tert-butylphosphine, and ammonia are introduced to grow a second GaPN channel layer 10 with a thickness of 10-30 nm in the N-HEMT active area recess 9. The V / III ratio of the second GaPN channel layer 10 is lower than that of the first AlPN barrier layer 7, so that P elements replace Ga vacancies and reduce compressive stress.

[0078] Then, the temperature of the MOCVD equipment reaction chamber is adjusted to 1150-1160°C, trimethylaluminum, tert-butylphosphine and ammonia are introduced, and a second AlPN barrier layer 11 with a thickness of 20-40 nm is grown on the second GaPN channel layer 10. Figure 4e As shown. The V / III ratio of the second AlPN barrier layer 11 is the same as that of the first AlPN barrier layer 7, allowing P elements to replace N vacancies and reduce tensile stress. In this embodiment, the depth of the N-HEMT active area recess 9 is equal to the sum of the thicknesses of the second AlPN barrier layer 11 and the second GaPN channel layer 10.

[0079] S6 : growing a first GaN cap layer 12 on the first GaPN channel layer 8 , and growing a second GaN cap layer 13 on the second AlPN barrier layer 11 .

[0080] Specifically, based on the previous step, the N-HEMT active region and the P-HEMT active region are simultaneously etched out, that is, the upper surfaces of the first GaPN channel layer 8 and the second GaN cap layer 13 are simultaneously exposed, and the GaN cap layer is grown to form a 3 nm thick first GaN cap layer 12 and a 3 nm thick second GaN cap layer 13 on the first GaPN channel layer 8 and the second AlPN barrier layer 11, respectively. Figure 4f shown.

[0081] S7: forming a first source electrode 14, a first drain electrode 15 and a first gate electrode 16 on the first GaN cap layer 12, and forming a second source electrode 17, a second drain electrode 18 and a second gate electrode 19 on the second GaN cap layer 13, as shown in FIG. Figure 4g shown.

[0082] Specifically, SiN is deposited as a hard mask on the first GaN cap layer 12 and the second GaN cap layer 13. A first source groove, a first drain groove, and a first gate groove are etched on the first GaN cap layer 12, and a second source groove, a second drain groove, and a second gate groove are etched on the second GaN cap layer 13. Subsequently, Ti / Al / Ni / Au metal is deposited in the first source groove and the first drain groove to make ohmic contacts between the first source and the first drain, and Ti / Al / Ni / Au metal is deposited in the second source groove and the second drain groove to make ohmic contacts between the first and second sources and the second drain. Annealing is then performed, and after annealing, Ni / Au metal is deposited in the first gate groove to make an ohmic contact between the first gate, and Ni / Au metal is deposited in the second gate groove to make ohmic contacts between the first and second gates.

[0083] This embodiment utilizes the two-dimensional hole gas induced by polarization in the GaPN / AlPN heterojunction as the source of P-type HEMT carriers and realizes monolithic integration with N-type HEMT materials, which can fill the gap of high-performance PMOS transistors and thus meet the requirements of high-performance CMOS.

[0084] Example 3

[0085] Based on the above embodiment, this embodiment specifically describes a method for preparing a CMOS transistor based on an AlPN / GaPN heterojunction. The preparation process includes:

[0086] (1) A pre-treated (0001) sapphire substrate was placed in an MOCVD device, and a pre-deposition aluminum layer was grown on the substrate with a trimethylaluminum flow rate of 20 sccm for 3 minutes; then a first AlN layer with a thickness of 25 nm was grown at 1100°C; then a second AlN layer with a thickness of 180 nm was grown at 1210°C; and a GaN buffer layer with a thickness of 1 μm was grown at 1030°C by introducing trimethylgallium with a flow rate of 50 sccm and ammonia with a flow rate of 3500 sccm.

[0087] (2) Deposit a SiN isolation layer, photolithograph and etch a groove in the P-HEMT active area. The depth of the groove in the P-HEMT active area is equal to the thickness of the SiN isolation layer. At 1150°C, trimethylaluminum with a flow rate of 100 sccm, tert-butyl phosphine with a flow rate of 30 sccm, and ammonia with a flow rate of 4000 sccm are introduced to grow a first AlPN barrier layer with a thickness of 20 nm. The lower surface of the first AlPN barrier layer contacts the upper surface of the GaN buffer layer.

[0088] (3) The temperature of the MOCVD equipment reaction chamber was adjusted to 1070°C, and trimethylgallium, tert-butylphosphine, and ammonia were introduced to react on the first AlPN barrier layer to form a first GaPN channel layer with a thickness of 10 nm. The flow rate of trimethylgallium was 500 sccm, the flow rate of tert-butylphosphine was 800 sccm, and the flow rate of ammonia was 50,000 sccm.

[0089] (4) Photolithography and etching were performed to form a groove for the N-HEMT active region. The depth of the groove for the N-HEMT active region was equal to the thickness of the SiN isolation layer. At a temperature of 1070°C, trimethylgallium, tert-butylphosphine, and ammonia were introduced to react and form a second GaPN channel layer with a thickness of 10 nm. The flow rate of trimethylgallium was 500 sccm, the flow rate of tert-butylphosphine was 800 sccm, and the flow rate of ammonia was 50,000 sccm. The lower surface of the second GaPN channel layer was in contact with the upper surface of the GaN buffer layer.

[0090] (5) The reaction chamber temperature was adjusted to 1150° C., and trimethylaluminum with a flow rate of 100 sccm, tert-butyl phosphine with a flow rate of 30 sccm, and ammonia with a flow rate of 4000 sccm were introduced to grow a second AlPN barrier layer with a thickness of 20 nm on the second GaPN channel layer.

[0091] (6) Deposit a SiN mask, photolithograph and etch out the N-HEMT active area and the P-HEMT active area, grow a first GaN cap layer on the first GaPN channel layer, grow a second GaN cap layer on the second AlPN barrier layer, then etch out a first source groove, a first drain groove, and a first gate groove on the first GaN cap layer, and simultaneously etch out a second source groove, a second drain groove, and a second gate groove on the second GaN cap layer; then, deposit Ti / Al / Ni / Au metal in the first source groove and the first drain groove to make ohmic contacts between the first source and the first drain, and deposit Ti / Al / Ni / Au metal in the second source groove and the second drain groove to make ohmic contacts between the first and second sources and the second drain. Then, annealing is performed, and after annealing, Ni / Au metal is deposited in the first gate groove to make ohmic contacts between the first gate, and Ni / Au metal is deposited in the second gate groove to make ohmic contacts between the first and second gates.

[0092] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A CMOS transistor based on an AlPN / GaPN heterojunction, characterized in that: The invention comprises a substrate (1), a first AlN layer (2), a second AlN layer (3), a GaN buffer layer (4) and a SiN isolation layer (5) which are arranged in sequence from bottom to top, wherein: A P-HEMT active region groove (6) and an N-HEMT active region groove (9) are provided on the SiN isolation layer (5), and the P-HEMT active region groove (6) and the N-HEMT active region groove (9) extend from the upper surface of the SiN isolation layer (5) to the upper surface of the GaN buffer layer (4); A first AlPN barrier layer (7), a first GaPN channel layer (8), and a first GaN cap layer (12) are sequentially arranged in the P-HEMT active region groove (6) from bottom to top; a second GaPN channel layer (10), a second AlPN barrier layer (11), and a second GaN cap layer (13) are sequentially arranged in the N-HEMT active region groove (9) from bottom to top; A first source electrode (14), a first drain electrode (15), and a first gate electrode (16) spaced apart from each other are provided on the upper surface of the first GaN cap layer (12); a second source electrode (17), a second drain electrode (18), and a second gate electrode (19) spaced apart from each other are provided on the upper surface of the second GaN cap layer (13); The growth temperature of the first AlN layer (2) is lower than the growth temperature of the second AlN layer (3), the growth temperature of the first AlN layer (2) is 1050°C-1150°C, and the growth temperature of the second AlN layer (3) is 1150°C-1250°C.

2. The CMOS transistor based on the AlPN / GaPN heterojunction according to claim 1, characterized in that: The P-HEMT active region groove (6) and the N-HEMT active region groove (9) are symmetrically opened inside the SiN isolation layer (5), and both extend from one side surface of the SiN isolation layer (5) to the other opposite side surface.

3. The CMOS transistor based on the AlPN / GaPN heterojunction according to claim 1, characterized in that: The first source (14), the first drain (15) and the first gate (16) are isolated from each other by SiN material, and the first gate (16) is located between the first source (14) and the first drain (15); the second source (17), the second drain (18) and the second gate (19) are isolated from each other by SiN material, and the second gate (19) is located between the second source (17) and the second drain (18).

4. The CMOS transistor based on the AlPN / GaPN heterojunction according to claim 1, characterized in that: A pre-laid aluminum layer is also included between the substrate (1) and the first AlN layer (2).

5. The CMOS transistor based on the AlPN / GaPN heterojunction according to claim 1, characterized in that: The surface areas of the first AlPN barrier layer (7) and the first GaPN channel layer (8) are equal, and both are equal to the inner surface area of ​​the P-HEMT active region groove (6); the surface areas of the second GaPN channel layer (10) and the second AlPN barrier layer (11) are equal, and both are equal to the inner surface area of ​​the N-HEMT active region groove (9).

6. The CMOS transistor based on AlPN / GaPN heterojunction according to claim 1, characterized in that: The first AlPN barrier layer (7) and the first GaPN channel layer (8) form a heterojunction structure AlPN / GaPN, and the second GaPN channel layer (10) and the second AlPN barrier layer (11) form a heterojunction structure GaPN / AlPN.

7. The CMOS transistor based on the AlPN / GaPN heterojunction according to claim 1, characterized in that: The thickness of the first AlPN barrier layer (7) is 20-40 nm, and the thickness of the first GaPN channel layer (8) is 10-30 nm; the thickness of the second GaPN channel layer (10) is 10-30 nm, and the thickness of the second AlPN barrier layer (11) is 20-40 nm.

8. A method for preparing a CMOS transistor based on an AlPN / GaPN heterojunction, characterized in that: For preparing the CMOS transistor according to any one of claims 1 to 7, the preparation method comprising: selecting a substrate and performing a pre-baking process on the substrate; sequentially growing a first AlN layer, a second AlN layer, and a GaN buffer layer on the substrate; Depositing a SiN isolation layer on the GaN buffer layer, and etching a P-HEMT active area groove on the SiN isolation layer; forming a first AlPN barrier layer and a first GaPN channel layer from bottom to top in the groove of the P-HEMT active area; Etching an N-HEMT active region groove on the SiN isolation layer, and forming a second GaPN channel layer and a second AlPN barrier layer from bottom to top in the N-HEMT active region groove; growing a first GaN cap layer on the first GaPN channel layer, and growing a second GaN cap layer on the second AlPN barrier layer; A first source electrode, a first drain electrode, and a first gate electrode are formed on the first GaN cap layer, and a second source electrode, a second drain electrode, and a second gate electrode are formed on the second GaN cap layer.

9. The method for preparing a CMOS transistor based on an AlPN / GaPN heterojunction according to claim 8, wherein: Sequentially growing a first AlN layer, a second AlN layer, and a GaN buffer layer on the substrate, comprising: At a temperature of 1050° C. to 1150° C., trimethylaluminum is introduced into a reaction chamber of an MOCVD device to grow a pre-laid aluminum layer with a thickness of 30 to 100 nm on the substrate; introducing trimethylaluminum and ammonia to grow a first AlN layer with a thickness of 20-40 nm on the pre-deposited aluminum layer; The reaction chamber temperature is adjusted to 1150° C. to 1250° C., and trimethylaluminum and ammonia are introduced to grow a second AlN layer with a thickness of 150 to 200 nm on the first AlN layer; The temperature of the reaction chamber is adjusted to 1100° C.-1200° C., and trimethylgallium and ammonia are introduced to grow a GaN buffer layer with a thickness of 800-1000 nm on the second AlN layer.

10. The method for preparing a CMOS transistor based on an AlPN / GaPN heterojunction according to claim 8 or 9, characterized in that: A first AlPN barrier layer and a first GaPN channel layer are formed from bottom to top in the groove of the P-HEMT active area, including: Adjusting the temperature of the MOCVD equipment reaction chamber to 1150°C-1160°C, introducing trimethylaluminum, tert-butylphosphine, and ammonia to react and form a first AlPN barrier layer with a thickness of 20-40 nm, wherein the lower surface of the first AlPN barrier layer contacts the upper surface of the GaN buffer layer, wherein the flow rate of trimethylaluminum is 100 sccm, the flow rate of tert-butylphosphine is 30 sccm, and the flow rate of ammonia is 4000 sccm; The temperature of the MOCVD equipment reaction chamber was adjusted to 1070°C-1085°C, and trimethylgallium, tert-butylphosphine, and ammonia were introduced to react on the first AlPN barrier layer to form a first GaPN channel layer with a thickness of 10-30 nm. The flow rate of trimethylgallium was 500 sccm, the flow rate of tert-butylphosphine was 800 sccm, and the flow rate of ammonia was 50,000 sccm.

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