PMOS driving circuit with gate voltage clamping protection function and enable translation circuit

Abstract

The application provides a PMOS driving circuit with a gate voltage clamping protection function and an enable shift circuit. In the PMOS driving circuit, the first end of a first clamping branch is connected with a power supply end, and the second end is connected with a first stage output node of a two-stage open-loop comparator circuit; the first end of a second clamping branch is connected with the power supply end, and the second end is connected with a second stage output node of the two-stage open-loop comparator circuit; the first end of a first discharging branch is connected with the second stage output node, and the second end is grounded; an enhanced pull-down driving clamping circuit is connected with the first stage output node and the second stage output node; an inverter is arranged between two input ends of the two-stage open-loop comparator, the input end of the inverter is connected with a first input end, and the output end of the inverter is connected with a second input end. The circuit realizes an output characteristic with a clamping function, has strong output driving capability, and can drive a large-size PMOS tube which needs gate voltage clamping. The application also provides an enable shift circuit for realizing the gate voltage clamping protection function.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and particularly to a PMOS driving circuit with gate voltage clamping protection function and an enable shift circuit. BACKGROUND

[0002] PMOS type switching devices are widely used in integrated circuit driving chips. In some existing integrated circuit processes, the common characteristics of such PMOS type switching devices are as follows: the tube size is relatively large, the internal resistance is relatively small, the voltage between the gate and the source is limited, and the voltage between the source and the drain is relatively high, so it is suitable for various switch control. Therefore, the driving circuit using such PMOS type switching devices requires strong driving capability and output characteristics with clamping function. If the requirement is not met, the reliability of the PMOS type switching device will be reduced, thereby affecting the chip quality. SUMMARY

[0003] A first object of the present application is to provide a PMOS driving circuit with gate voltage clamping protection function and strong driving capability.

[0004] A second object of the present application is to provide another PMOS driving circuit with gate voltage clamping protection function and strong driving capability.

[0005] A third object of the present application is to provide an enable shift circuit with gate voltage clamping protection function for internal module enable control of a chip.

[0006] In order to achieve the above-mentioned first purpose, the application provides a PMOS driving circuit with a gate voltage clamping protection function, comprising a two-stage open-loop comparator circuit, wherein the PMOS driving circuit further comprises: a first clamping branch, a second clamping branch, a first discharging branch, and an enhanced pull-down driving clamping circuit; a first end of the first clamping branch is connected to a power supply end, and a second end of the first clamping branch is connected to a first-stage output node of the two-stage open-loop comparator circuit; a first end of the second clamping branch is connected to the power supply end, and a second end of the second clamping branch is connected to a second-stage output node of the two-stage open-loop comparator circuit; a first end of the first discharging branch is connected to the second-stage output node, and a second end of the first discharging branch is grounded; the enhanced pull-down driving clamping circuit is connected to the first-stage output node and the second-stage output node; an inverter is arranged between a first input end and a second input end of the two-stage open-loop comparator, an input end of the inverter is connected to the first input end, and an output end of the inverter is connected to the second input end; when the first input end receives a low-level signal, the first clamping branch clamps the voltage of the first-stage output node, and the second-stage output node outputs a first driving voltage to a gate of an external PMOS tube; when the first input end receives a high-level signal, the second-stage output node and the enhanced pull-down driving clamping circuit control the gate capacitance of the external PMOS tube to be discharged to a second preset value, and the second clamping branch clamps the voltage of the second-stage output node to a second driving voltage.

[0007] As can be seen from the above scheme, in the application, the gate-source voltage of all PMOS tubes is controlled within a safe range, the first clamping circuit and the second clamping circuit are arranged to protect the gate of the PMOS tube, the enhanced pull-down driving clamping circuit improves the driving capability of the load capacitance of the second-stage output node, and at the same time, drives the second clamping circuit to clamp the gate voltage of the external PMOS tube, so that the gate-source voltage of the external PMOS tube is relatively fixed, and a large-size PMOS switching device can be driven.

[0008] Further, the enhanced pull-down driving clamping circuit comprises a second discharging branch and a driving-enhanced bias branch; a first end of the second discharging branch is connected to the second-stage output node, and a second end of the second discharging branch is grounded; the driving-enhanced bias branch is connected to the first-stage output node, the second-stage output node, and the second discharging branch; when the first input end receives a high-level signal, the driving-enhanced bias branch controls the first discharging branch and the second discharging branch to discharge the gate capacitance of the external PMOS tube to the second preset value.

[0009] Further, the first discharging branch comprises a first NMOS and a fifth NMOS, the second clamping branch comprises a first PMOS and a second NMOS, the driving-enhanced biasing branch comprises a third PMOS, a first clamping component, a third NMOS and a fourth NMOS; the drain of the first NMOS is connected to the second-stage output node, the gate of the first NMOS is connected to the input end of the inverter and the first input end, and the source of the first NMOS is connected to the drain of the fifth NMOS; the gate of the fifth NMOS is connected to the two-stage open-loop comparator circuit, and the source of the fifth NMOS is grounded; the source of the first PMOS is connected to the second-stage output node and the second end of the second clamping branch, the gate of the first PMOS is connected to the driving-enhanced biasing branch, and the drain of the first PMOS is connected to the drain of the second NMOS; the gate of the second NMOS is connected to the input end of the inverter and the first input end, and the source of the second NMOS is grounded; the source of the third PMOS is connected to the power supply end, the gate of the third PMOS is connected to the first-stage output node, and the drain of the third PMOS is connected to the gate of the second PMOS; the first end of the first clamping component is connected to the power supply end, and the second end is connected to the third PMOS; the gate of the third NMOS is connected to the input end of the inverter and the first input end, the source of the third NMOS is connected to the drain of the fourth NMOS; the source of the fourth NMOS is connected to the drain of the third NMOS, the gate of the fourth NMOS is connected to the two-stage open-loop comparator circuit, and the source of the fourth NMOS is grounded; and the fourth NMOS is in an on state.

[0010] Further, the first clamping component comprises a fourth PMOS, a fifth PMOS and a sixth PMOS connected in series; the source of the fourth PMOS is connected to the power supply end, the gate of the fourth PMOS is connected to the drain of the fourth PMOS; the source of the fifth PMOS is connected to the drain of the fourth PMOS, the gate of the fifth PMOS is connected to the drain of the fifth PMOS; the source of the sixth PMOS is connected to the drain of the fifth PMOS, the gate of the sixth PMOS is connected to the drain of the sixth PMOS, and the drain of the sixth PMOS is connected to the gate of the first PMOS and the drain of the third NMOS.

[0011] Further, the second clamping branch comprises a second PMOS, the source of the second PMOS is connected to the power supply end, the gate of the second PMOS is connected to the drain of the second PMOS, and the drain of the second PMOS is connected to the second-stage output node and the source of the first PMOS.

[0012] Further, the two-stage open-loop comparator circuit comprises a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a current source; a source of the seventh PMOS transistor is connected to a power supply end, a gate of the seventh PMOS transistor is connected to a gate of the eighth PMOS transistor and a drain of the seventh PMOS transistor, and a drain of the seventh PMOS transistor is connected to a drain of the eighth NMOS transistor; a gate of the eighth NMOS transistor is connected to the first input end and an input end of the inverter, a source of the eighth NMOS transistor is connected to a drain of the seventh NMOS transistor; a source of the eighth PMOS transistor is connected to the power supply end, a gate of the eighth PMOS transistor is connected to a gate of the seventh PMOS transistor, a drain of the eighth PMOS transistor is connected to a drain of the ninth NMOS transistor and a gate of the ninth PMOS transistor; a gate of the ninth NMOS transistor is connected to an output end of the inverter, a source of the ninth NMOS transistor is connected to a drain of the seventh NMOS transistor; a first-stage output node is arranged at the drain of the eighth PMOS transistor; a second-stage output node is arranged at a drain of the ninth PMOS transistor; a gate of the seventh NMOS transistor is connected to a gate of the sixth NMOS transistor, and a source of the seventh NMOS transistor is grounded; a drain of the sixth NMOS transistor is connected to the gate of the sixth NMOS transistor, and a source of the sixth NMOS transistor is grounded; the gate of the sixth NMOS transistor is connected to the first discharging branch and the enhanced pull-down driving clamping circuit; one end of the current source is connected to the drain and the gate of the sixth NMOS transistor, the other end of the current source is grounded, and a current direction of the current source is flowing into the drain of the sixth NMOS transistor; a first end of the first clamping branch is connected to the power supply end, and a second end of the first clamping branch is connected to the gate of the ninth PMOS transistor.

[0013] Further, the first clamping branch comprises a second clamping component.

[0014] Further, the second clamping component comprises a tenth PMOS transistor, an eleventh PMOS transistor, and a twelfth PMOS transistor; a source of the tenth PMOS transistor is connected to the power supply end, a gate of the tenth PMOS transistor is connected to a drain of the tenth PMOS transistor, and a drain of the tenth PMOS transistor is connected to a source of the eleventh PMOS transistor; a source of the eleventh PMOS transistor is connected to the drain of the tenth PMOS transistor, a gate of the eleventh PMOS transistor is connected to a drain of the eleventh PMOS transistor, and a drain of the eleventh PMOS transistor is connected to a source of the twelfth PMOS transistor; a source of the twelfth PMOS transistor is connected to the drain of the eleventh PMOS transistor, a gate of the twelfth PMOS transistor is connected to a drain of the twelfth PMOS transistor, and a drain of the twelfth PMOS transistor is connected to the gate of the ninth PMOS transistor.

[0015] In order to achieve the second purpose, the application provides a PMOS drive circuit with gate voltage clamping protection function, comprising two-stage open-loop comparator circuit, wherein, further comprising: second clamping branch, first discharging branch, enhanced pull-down drive clamping circuit; the first end of the first discharging branch is connected with the power supply end, and the second end is grounded; the first end of the second clamping branch is connected with the power supply end, and the second end is connected with the second-stage output node of the two-stage open-loop comparator circuit; the first end of the first discharging branch is connected with the second-stage output node, and the second end of the first discharging branch is grounded; the enhanced pull-down drive clamping circuit is connected with the first-stage output node and the second-stage output node; the inverter is connected between the first input end and the second input end of the two-stage open-loop comparator, the input end of the inverter is connected with the first input end, and the output end of the inverter is connected with the second input end; when the first input end receives a low-level signal, the second-stage output node outputs a first drive voltage to the gate of the external PMOS tube; when the first input end receives a high-level signal, the second-stage output node and the enhanced pull-down drive clamping circuit control the gate capacitance discharge of the external PMOS tube to a second preset value, and the second clamping branch clamps the voltage of the second-stage output node to a second drive voltage.

[0016] As can be seen from the above scheme, the PMOS switch device with large size which needs gate clamping can be driven.

[0017] In order to achieve the third purpose, the application provides an enable translation circuit with gate voltage clamping protection function, comprising two-stage open-loop comparator circuit, wherein, further comprising: first clamping branch; the first end of the first clamping branch is connected with the power supply end, and the second end is connected with the first-stage output node of the two-stage open-loop comparator circuit; the inverter is connected between the first input end and the second input end of the two-stage open-loop comparator, the input end of the inverter is connected with the first input end, and the output end of the inverter is connected with the second input end; when the first input end receives a low-level signal, the first clamping branch clamps the voltage of the first-stage output node.

[0018] As can be seen from the above scheme, the low-voltage to high-voltage enable translation circuit structure with clamping control can be realized, which is used as the enable control of the functional module in the chip, protects the gate voltage of the enable control PMOS tube of the functional module, keeps the gate-source voltage of the enable control PMOS tube stable, and increases the reliability. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is the circuit principle diagram of the two-stage open-loop comparator circuit of the prior art.

[0020] Figure 2 It is the circuit principle diagram of the PMOS drive circuit with gate voltage clamping protection function in the PMOS drive circuit embodiment with gate voltage clamping protection function of the application.

[0021] Figure 3 is Figure 2 is

[0022] Figure 4 is the circuit schematic diagram of the enable translation circuit with the gate voltage clamping protection function in the embodiment of the enable translation circuit with the gate voltage clamping protection function of the application.

[0023] The application is further described below in combination with the drawings and embodiments. DETAILED DESCRIPTION

[0024] The PMOS driving circuit with the gate voltage clamping protection function of the application can control the gate-source voltage of the PMOS tube within a safe range by reasonably designing the clamping circuit, and realize driving of a larger size PMOS switching device by double pull-down driving.

[0025] The gate voltage clamping protection function is determined by the manufacturing process used by the chip and the designer adopting this type of PMOS device. The characteristics of this type of PMOS device are as follows: the gate-source voltage of the PMOS when turned on is relatively low, and the typical value is 5V, while the voltage resistance between the drain and the source is relatively high, such as 25V, 40V, 100V, or even higher. However, this type of PMOS device has a significant advantage that the on-resistance of the tube is relatively low under the same on-current driving condition, so this type of device is particularly suitable for active control switching, and is widely used in the fields of switching power supply management, battery management, motor drive, automotive drive chip and other electronic products. If this type of PMOS device needs to be used inside the chip, voltage clamping protection needs to be done on the gate-source voltage of the PMOS. The realization principle of the gate protection clamping voltage of the application is derived from the current-voltage I / V characteristic of the MOS when working in the saturation region, and its expression is as follows:

[0026]

[0027] Among them, the up, Cox and Vth parameters are determined by the manufacturing process itself, and can be obtained as follows:

[0028]

[0029] As can be seen from the above formula, if the width-length ratio W / L of the MOS is fixed and the bias current Id is determined, the Vgs voltage of the MOS tube is a certain value; changing the width-length ratio W / L of the PMOS or the bias current or both will change the Vgs voltage of the PMOS. The PMOS gate voltage clamping control in the application is based on the voltage drop of a PMOS or the voltage drop generated by the series connection of multiple PMOSs.

[0030] ​​PMOS driving circuit with gate voltage clamping protection function

[0031] Referring to Figure 1 , the prior art two-stage open-loop comparator circuit includes a seventh PMOS tube P7, an eighth PMOS tube P8, a ninth PMOS tube P9, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a ninth NMOS tube N9, a current source; the source of the seventh PMOS tube P7 is connected to the power supply end VDD, the gate of the seventh PMOS tube P7 is connected to the gate of the eighth PMOS tube P8 and the drain of the seventh PMOS tube P7, and the drain of the seventh PMOS tube P7 is connected to the drain of the eighth NMOS tube N8; the gate of the eighth NMOS tube N8 is connected to the INN end, and the source of the eighth NMOS tube N8 is connected to the drain of the seventh NMOS tube N7; the source of the eighth PMOS tube P8 is connected to the power supply end VDD, the gate of the eighth PMOS tube P8 is connected to the gate of the seventh PMOS tube P7, the drain of the eighth PMOS tube P8 is connected to the drain of the ninth NMOS tube N9 and the gate of the ninth PMOS tube P9; the gate of the ninth NMOS tube N9 is connected to the IPN end, and the source of the ninth NMOS tube N9 is connected to the drain of the seventh NMOS tube N7; the gate of the seventh NMOS tube N7 is connected to the gate of the sixth NMOS tube N6, and the source of the seventh NMOS tube N7 is grounded; the drain of the sixth NMOS tube N6 is connected to the gate of the sixth NMOS tube N6, and the source of the sixth NMOS tube N6 is grounded; the drain of the fifth NMOS tube N5 is connected to a discharge branch, the gate of the fifth NMOS tube N5 is connected to the gate of the sixth NMOS tube N6, and the source of the fifth NMOS tube N5 is grounded; the first-stage output node is arranged at the drain of the eighth PMOS tube P8; the second-stage output node (OUT) is arranged at the drain of the ninth PMOS tube P9; one end of the current source is connected to the drain and gate of the sixth NMOS tube N6, the other end of the current source is grounded, and the current direction of the current source is flowing into the drain of the sixth NMOS tube N6.

[0032] The output characteristic of the above-mentioned prior art two-stage open-loop comparator circuit is that when the input IPN end voltage is greater than the IN end voltage, the second-stage output node, i.e., the OUT node, outputs a high level; when the input INP end voltage is less than the INN end voltage, the second-stage output node, i.e., the OUT node, outputs a low level. Due to the limitation of the performance parameters of the architecture itself, such as the limited driving capacity of the second-stage output node to the capacitive load when the pull-down current is fixed, and the second-stage output node outputting a low level as the power supply ground, it is obviously not suitable for driving large-size switching PMOS devices of the type described in the present application.

[0033] The PMOS driving circuit 1 with gate voltage clamping protection function of the present embodiment is realized based on the above-mentioned prior art two-stage open-loop comparator circuit, referring to Figure 2, including two-stage open-loop comparator circuit 11, first clamping branch 12, second clamping branch 13, first discharge branch 14, enhanced pull-down drive clamp circuit 15. Two-stage open-loop comparator circuit is connected with first clamping branch 12, second clamping branch 13, first discharge branch 14, enhanced pull-down drive clamp circuit 15 respectively, second clamping branch 13 is connected with first discharge branch 14, enhanced pull-down drive clamp circuit 15 is connected with second clamping branch 13 and first discharge branch 14. Unlike two-stage open-loop comparator circuit of prior art, in the embodiment, fifth NMOS tube N5 and first NMOS tube N1 constitute first discharge branch 14.

[0034] Inverter INV is arranged between the first input end IN and the second input end INB of the two-stage open-loop comparator, the input end of the inverter INV is connected with the first input end IN, and the output end of the inverter INV is connected with the second input end INB. Thus, the input of the two-stage open-loop comparator is directly set as a level complementary input signal, the first input end IN receives a high level or low level signal output by a digital circuit inside a chip, and only one tube of the differential pair of eighth NMOS tube N8 and ninth NMOS tube N9 is in a conduction state when each kind of level input.

[0035] The first end of the first clamping branch 12 is connected with the power supply end VDD, and the second end is connected with the first-stage output node of the two-stage open-loop comparator circuit. The first clamping branch 12 includes a first clamping component, and in the embodiment, the first clamping component includes tenth PMOS tube P10, eleventh PMOS tube P11 and twelfth PMOS tube P12. The source of the tenth PMOS tube P10 is connected with the power supply end, the gate of the tenth PMOS tube P10 is connected with the drain of the tenth PMOS tube P10, and the drain of the tenth PMOS tube P10 is connected with the source of the eleventh PMOS tube P11. The source of the eleventh PMOS tube P11 is connected with the drain of the tenth PMOS tube P10, the gate of the eleventh PMOS tube P11 is connected with the drain of the eleventh PMOS tube P11, and the drain of the eleventh PMOS tube P11 is connected with the source of the twelfth PMOS tube. The source of the twelfth PMOS tube P12 is connected with the drain of the eleventh PMOS tube P11, the gate of the twelfth PMOS tube P12 is connected with the drain of the twelfth PMOS tube P12, and the drain of the twelfth PMOS tube P12 is connected with the gate of the ninth PMOS tube P9.

[0036] One end of the first discharge branch 14 is connected with the power supply end VDD, and the second end is connected with the second-stage output node of the two-stage open-loop comparator circuit 11. The first discharge branch 14 includes first NMOS tube N1 and fifth NMOS tube. The drain of the first NMOS tube N1 is connected with the second-stage output node, the gate of the first NMOS tube N1 is connected with the input end of the inverter INV and the first input end IN, and the source of the first NMOS tube N1 is connected with the drain of the fifth NMOS tube N5.

[0037] The first end of the second clamping branch 13 is connected with the power supply end VDD, and the second end is connected with the second-stage output node. The second clamping branch 13 comprises a second clamping component, and the second clamping component in the embodiment comprises a second PMOS tube P2. The source of the second PMOS tube P2 is connected with the power supply end, the gate of the second PMOS tube P2 is connected with the drain of the second PMOS tube P2, the drain of the second PMOS tube P2 is connected with the second-stage output node and the source of the first PMOS tube P1.

[0038] The enhanced pull-down driving clamping circuit 15 is connected with the first-stage output node and the second-stage output node, and comprises a second discharging branch 151 and a bias branch 152 for driving enhancement. The bias branch 152 for driving enhancement is connected with the second discharging branch 151.

[0039] The first end of the second discharging branch 151 is connected with the second-stage output node, and the second end is grounded. The second discharging branch 151 comprises a first PMOS tube P1 and a second NMOS tube N2. The source of the first PMOS tube P1 is connected with the second-stage output node and the second end of the second clamping branch 13, the gate of the first PMOS tube P1 is connected with the enhanced pull-down driving clamping circuit 15, and the drain of the first PMOS tube P1 is connected with the drain of the second NMOS tube N2. The gate of the second NMOS tube N2 is connected with the input end of the inverter INV and the first input end IN, and the source of the second NMOS tube N2 is grounded.

[0040] The driving enhanced bias branch 152 is connected with the first stage output node, the second stage output node and the second discharging branch 151. The driving enhanced bias branch 152 comprises a third PMOS P3, a fourth PMOS P4, a fifth PMOS P5, a sixth PMOS P6, a third NMOS N3 and a fourth NMOS N4. The source of the third PMOS P3 is connected with the power supply terminal, the gate of the third PMOS P3 is connected with the first stage output node, and the drain of the third PMOS P3 is connected with the gate of the second PMOS P2. The source of the fourth PMOS P4 is connected with the power supply terminal, the gate of the fourth PMOS P4 is connected with the drain of the fourth PMOS P4. The source of the fifth PMOS P5 is connected with the drain of the fourth PMOS P4, and the gate of the fifth PMOS P5 is connected with the drain of the fifth PMOS P5. The source of the sixth PMOS P6 is connected with the drain of the fifth PMOS P5, the gate of the sixth PMOS P6 is connected with the drain of the sixth PMOS P6, and the drain of the sixth PMOS P6 is connected with the gate of the first PMOS P1 and the drain of the third NMOS N3. The gate of the third NMOS N3 is connected with the input terminal of the inverter INV and the first input terminal IN, and the source of the third NMOS N3 is connected with the drain of the fourth NMOS N4. The source of the fourth NMOS N4 is connected with the drain of the third NMOS N3, the gate of the fourth NMOS N4 is connected with the gate of the sixth NMOS N6 in the two-stage open-loop comparator circuit, and the source of the fourth NMOS N4 is grounded. The fourth NMOS N4 is in the on state.

[0041] In combination Figure 3 When the first input terminal IN is at low level and the second input terminal INB is at high level, the ninth NMOS N9 is turned on, the first stage output node is at low level, and the first driving voltage of the second stage output node is the voltage of the power supply terminal VDD. For easy explanation, Figure 2The PMOS driving circuit of the embodiment is provided with an external PMOS tube P0 to be driven, the external PMOS tube P0 is an active switch large-size PMOS device, the source of the external PMOS tube P0 is connected with a power supply end VDD, the gate of the external PMOS tube P0 is connected with a second-stage output node, and the drain of the external PMOS tube P0 is connected with an external PAD. The first clamping branch 12 clamps the voltage of the first-stage output node, so that the voltage difference between the voltage of the node and the power supply end VDD is a relatively fixed voltage drop, the gate voltage of the ninth PMOS tube P9 is clamped, and the condition that the power supply end VDD increases so that the gate-source voltage of the ninth PMOS tube P9 exceeds the withstand voltage value and is damaged is prevented. It can be understood that the tenth PMOS tube P10, the eleventh PMOS tube P11 and the twelfth PMOS tube P12 are replaced by a clamping diode, which can have the same effect, but the clamping diode increases a layer of photomask in the manufacturing process of the chip, so that the cost is increased. By connecting the tenth PMOS tube P10, the eleventh PMOS tube P11 and the twelfth PMOS tube P12 in series, the current of the first clamping branch 12 can also be reduced.

[0042] When the first input terminal IN is high, the second input terminal INB is low, at this time the ninth NMOS tube N9 is closed, the first stage output node is high. At the same time, the first NMOS tube N1 of the first discharging branch 14 is turned on, and the first discharging branch 14 can start to work. In the enhanced pull-down driving clamp circuit 15, the second NMOS tube N2 is turned on, and the third NMOS tube N3 is turned on. The first stage output node in the bias branch 152 of the driving enhancement closes the third PMOS tube P3, at this time the low level obtained by subtracting the fixed voltage drop of the fourth PMOS tube P4, the fifth PMOS tube P5 and the sixth PMOS tube P6 from the power supply terminal VDD turns on the first PMOS tube P1, so that the second discharging branch 151 can start to work. Since the first input terminal IN is low, the second stage output node charges the gate capacitor of the external PMOS tube P0 to the voltage value of the power supply terminal VDD, so at this time the gate capacitor starts from the voltage value of the power supply terminal VDD and is discharged to the second preset value through the first discharging branch 14 and the second discharging branch 151. The second preset value is the voltage value required for the gate clamp of the external PMOS tube P0. In the embodiment, through the double pull-down driving control of the first discharging branch and the enhanced pull-down driving circuit, at this time the voltage value of the second stage output node is clamped at the voltage value of the power supply terminal VDD minus the gate-source voltage of the second PMOS tube P2, so that the gate voltage of the external PMOS tube P0 is clamped at the second driving voltage, and the second driving voltage is the voltage value of the power supply terminal VDD minus the gate-source voltage of the second PMOS tube P2, so that the external PMOS tube P0 works in the safe range of the gate-source voltage and will not be damaged due to the increase of the voltage value of the power supply terminal VDD, and the first discharging branch 14 and the second discharging branch 151 make the second stage output node double pull-down driven, so as to drive a larger size PMOS switch device. It should be noted that in the circuit design, the voltage of the power supply terminal VDD minus the gate-source voltage of the second PMOS tube P2 = the gate voltage of the first PMOS tube P1 + the threshold voltage (Vth) of the first PMOS tube P1, at this time the gate-source clamp voltage of the external PMOS tube P0 is mainly determined by the voltage drop of the second PMOS tube P2, so as to clamp the gate voltage of the external PMOS tube P0 at the voltage of the power supply terminal VDD minus the gate-source voltage of the second PMOS tube P2. The gate voltage of the first PMOS tube P1 is determined by the sum of the gate-source voltages of the fourth PMOS tube P4, the fifth PMOS tube P5 and the sixth PMOS tube P6. It can be understood that the second PMOS tube P2 of the second clamping branch, and the fourth PMOS tube P4, the fifth PMOS tube P5 and the sixth PMOS tube P6 in the enhanced pull-down driving clamp circuit 15 can be replaced by a clamping diode with equal voltage drop.

[0043] In actual application, the PMOS driving circuit 1 with the gate voltage clamping protection function can not be provided with the first clamping branch 12, and still can realize the pull-down driving of the second stage output point to realize the driving of the large-size PMOS switch device, but cannot protect the gate of the ninth PMOS P9.

[0044] The embodiment of the enable translation circuit with the gate voltage clamping protection function:

[0045] Different from the above embodiment, the embodiment is not used for the active switch large-size PMOS device, but is used for other functional modules (such as LDO modules and current bias modules) in the chip. These modules usually have an EN_CTRL enable control signal, and to adapt to the design requirement of low power consumption, small-size PMOS devices with gate clamping protection are inevitably applied as switch devices, and the EN_CTRL enable control signal is usually derived from a digital module in a low-voltage power supply domain, and is used for driving a functional module in a high-voltage power supply domain (for example, the low-voltage current domain is 5V and below, and the high-voltage current domain is between 5V and 100V), which requires a low-voltage to high-voltage enable translation circuit with clamping output to realize logic conversion.

[0046] With reference to Figure 4 The low-voltage to high-voltage enable translation circuit 2 with the gate voltage clamping protection function of the embodiment includes a two-stage open-loop comparator circuit 21 and a first clamping branch 22. The connection relationship between the two-stage open-loop comparator circuit 21 and the first clamping branch 22 of the embodiment is the same as that of the first embodiment, and the first clamping branch 22 is the same as that of the first embodiment. The difference between the two-stage open-loop comparator circuit 21 of the embodiment and the two-stage open-loop comparator circuit 11 of the first embodiment is that the second stage output node is not provided, that is, the ninth PMOS and the fifth NMOS in the first embodiment are not provided. The first input end is EN_IN, which receives the enable control signal in the chip, and the first stage output node is the EN_CTRL node.

[0047] For the convenience of description, Figure 4The internal function module 23 can be an LDO module or a current biasing module, etc. In the embodiment, the internal function module 23 is an LDO module. When the enable control signal received by the first input terminal EN_IN is low voltage domain low level, the low level with voltage clamping is outputted by the EN_CTRL node, the PMOS transistor P13 is enabled, and the high impedance node of the LDO module is set high. When the LDO module needs to work, the enable control signal received by the first input terminal EN_IN becomes low voltage domain high level, the EN_CTRL node outputs high voltage domain high level, the PMOS transistor P13 is enabled or cut off, thereby not affecting the work of the internal module. In addition, when the enable control signal received by the first input terminal EN_IN changes, the output waveform of the EN_CTRL node is basically consistent with the waveform of the OUT node in the accompanying drawings of the present application. Figure 2 The voltage drop between the OUT node and the power supply end VDD is also the sum of the gate-source voltages of the tenth PMOS transistor, the eleventh PMOS transistor and the twelfth PMOS transistor.

[0048] In summary, the enable translation circuit with gate voltage clamping protection can control the gate-source voltages of all the PMOS transistors in the internal circuit within the bearable voltage range, the first clamping circuit can clamp the first level output node of the two-stage open-loop comparator circuit, thereby being used for the enable control of the internal module of the chip with the enable control PMOS transistor, and ensuring the reliability of the internal module of the chip. On the basis of the first clamping circuit, the second clamping circuit, the first discharging branch and the enhanced pull-down driving clamping circuit can have strong driving capability and output characteristics with clamping, thereby being able to drive large-size PMOS switching devices.

Claims

1. A PMOS driving circuit with gate voltage clamping protection function, comprising a two-stage open-loop comparator circuit, characterized in that, Also includes: First clamping branch, second clamping branch, first discharge branch, enhanced pull-down drive clamping circuit; The first end of the first clamping branch is connected to the power supply terminal, and the second end is connected to the first output node of the two-stage open-loop comparator circuit. The first end of the second clamping branch is connected to the power supply terminal, and the second end is connected to the second-stage output node of the two-stage open-loop comparator circuit. The first end of the first discharge branch is connected to the second-stage output node, and the second end of the first discharge branch is grounded. The enhanced pull-down drive clamping circuit connects the first-stage output node and the second-stage output node; An inverter is provided between the first input terminal and the second input terminal of the two-stage open-loop comparator. The input terminal of the inverter is connected to the first input terminal, and the output terminal of the inverter is connected to the second input terminal. When the first input terminal receives a low-level signal, the first clamping branch clamps the voltage of the first-stage output node, and the second-stage output node outputs the first driving voltage to the gate of the external PMOS transistor. When the first input terminal receives a high-level signal, the second-stage output node and the enhanced pull-down drive clamping circuit control the gate capacitance of the external PMOS transistor to discharge to a second preset value, and the second clamping branch clamps the voltage of the second-stage output node to the second driving voltage.

2. The PMOS driving circuit with gate voltage clamping protection function as described in claim 1, characterized in that: The enhanced pull-down drive clamping circuit includes a second discharge branch and a drive enhancement bias branch. The first end of the second discharge branch is connected to the second-stage output node, and the second end is grounded; The bias branch for drive enhancement is connected to the first-stage output node, the second-stage output node, and the second discharge branch; When the first input terminal receives a high-level signal, the bias branch of the drive enhancement controls the first discharge branch and the second discharge branch to discharge the gate capacitance of the external PMOS transistor to the second preset value.

3. The PMOS driving circuit with gate voltage clamping protection function as described in claim 2, characterized in that: The first discharge branch includes a first NMOS transistor and a fifth NMOS transistor; the second clamping branch includes a first PMOS transistor and a second NMOS transistor; the drive-enhanced bias branch includes a third PMOS transistor, a first clamping component, a third NMOS transistor, and a fourth NMOS transistor. The drain of the first NMOS transistor is connected to the second-stage output node, the gate of the first NMOS transistor is connected to the input terminal of the inverter and the first input terminal, and the source of the first NMOS transistor is connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the two-stage open-loop comparator circuit, and the gate of the fifth NMOS transistor is grounded. The source of the first PMOS transistor is connected to the second stage output node and the second end of the second clamping branch, the gate of the first PMOS transistor is connected to the drive enhancement bias branch, and the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the input terminal of the inverter and the first input terminal, and the source of the second NMOS transistor is grounded. The source of the third PMOS transistor is connected to the power supply terminal, the gate of the third PMOS transistor is connected to the first stage output node, and the drain of the third PMOS transistor is connected to the gate of the second PMOS transistor. The first end of the first clamping component is connected to the power supply terminal, and the second end is connected to the third PMOS transistor. The gate of the third NMOS transistor is connected to the input terminal of the inverter and the first input terminal, and the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor. The source of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, the gate of the fourth NMOS transistor is connected to the two-stage open-loop comparator circuit, and the source of the fourth NMOS transistor is grounded; the fourth NMOS transistor is in the on state.

4. The PMOS driving circuit with gate voltage clamping protection function as described in claim 3, characterized in that: The first clamping assembly includes a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor connected in series; The source of the fourth PMOS transistor is connected to the power supply terminal, and the gate of the fourth PMOS transistor is connected to the drain of the fourth PMOS transistor. The source of the fifth PMOS transistor is connected to the drain of the fourth PMOS transistor, and the gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor. The source of the sixth PMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the sixth PMOS transistor is connected to the drain of the sixth PMOS transistor, and the drain of the sixth PMOS transistor is connected to the gate of the first PMOS transistor and the drain of the third NMOS transistor.

5. The PMOS driving circuit with gate voltage clamping protection function as described in claim 4, characterized in that: The second clamping branch includes a second PMOS transistor, the source of which is connected to the power supply terminal, the gate of which is connected to the drain of which is connected to the drain of which is connected to the second stage output node and the source of the first PMOS transistor.

6. The PMOS driving circuit with gate voltage clamping protection function as described in any one of claims 1 to 5, characterized in that: The two-stage open-loop comparator circuit includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a current source; The source of the seventh PMOS transistor is connected to the power supply terminal, the gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor and the drain of the seventh PMOS transistor, and the drain of the seventh PMOS transistor is connected to the drain of the eighth NMOS transistor. The gate of the eighth NMOS transistor is connected to the first input terminal and the input terminal of the inverter, and the source of the eighth NMOS transistor is connected to the drain of the seventh NMOS transistor. The source of the eighth PMOS transistor is connected to the power supply terminal, the gate of the eighth PMOS transistor is connected to the gate of the seventh PMOS transistor, and the drain of the eighth PMOS transistor is connected to the drain of the ninth NMOS transistor and the gate of the ninth PMOS transistor. The gate of the ninth NMOS transistor is connected to the output terminal of the inverter, and the source of the ninth NMOS transistor is connected to the drain of the seventh NMOS transistor. The first-stage output node is located at the drain of the eighth PMOS transistor; the second-stage output node is located at the drain of the ninth PMOS transistor. The gate of the seventh NMOS transistor is connected to the gate of the sixth NMOS transistor, and the source of the seventh NMOS transistor is grounded. The drain of the sixth NMOS transistor is connected to the gate of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded. The gate of the sixth NMOS transistor is connected to the first discharge branch and the enhanced pull-down drive clamping circuit; One end of the current source is connected to the drain and gate of the sixth NMOS transistor, and the other end of the current source is grounded. The current direction of the current source is to flow into the drain of the sixth NMOS transistor. The first end of the first clamping branch is connected to the power supply terminal, and the second end of the first clamping branch is connected to the gate of the ninth PMOS transistor.

7. The PMOS driving circuit with gate voltage clamping protection function as described in claim 6, characterized in that: The first clamping branch includes a second clamping component.

8. The PMOS driving circuit with gate voltage clamping protection function as described in claim 7, characterized in that: The second clamping assembly includes a tenth PMOS transistor, an eleventh PMOS transistor, and a twelfth PMOS transistor; The source of the tenth PMOS transistor is connected to the power supply terminal, the gate of the tenth PMOS transistor is connected to the drain of the tenth PMOS transistor, and the drain of the tenth PMOS transistor is connected to the source of the eleventh PMOS transistor. The source of the eleventh PMOS transistor is connected to the drain of the tenth PMOS transistor, the gate of the eleventh PMOS transistor is connected to the drain of the eleventh PMOS transistor, and the drain of the eleventh PMOS transistor is connected to the source of the twelfth PMOS transistor. The source of the twelfth PMOS transistor is connected to the drain of the eleventh PMOS transistor, the gate of the twelfth PMOS transistor is connected to the drain of the twelfth PMOS transistor, and the drain of the twelfth PMOS transistor is connected to the gate of the ninth PMOS transistor.

9. A PMOS driving circuit with gate voltage clamping protection function, comprising a two-stage open-loop comparator circuit, characterized in that, Also includes: Second clamping branch, first discharge branch, enhanced pull-down drive clamping circuit; The first end of the first discharge branch is connected to the power supply, and the second end is grounded. The first end of the second clamping branch is connected to the power supply terminal, and the second end is connected to the second-stage output node of the two-stage open-loop comparator circuit. The first end of the first discharge branch is connected to the second-stage output node, and the second end of the first discharge branch is grounded. The enhanced pull-down drive clamping circuit connects the first-stage output node and the second-stage output node; An inverter is connected between the first input terminal and the second input terminal of the two-stage open-loop comparator. The input terminal of the inverter is connected to the first input terminal, and the output terminal of the inverter is connected to the second input terminal. When the first input terminal receives a low-level signal, the second-stage output node outputs a first driving voltage to the gate of the external PMOS transistor; When the first input terminal receives a high-level signal, the second-stage output node and the enhanced pull-down drive clamping circuit control the gate capacitance of the external PMOS transistor to discharge to a second preset value, and the second clamping branch clamps the voltage of the second-stage output node to the second driving voltage.

10. An enable shift circuit with gate voltage clamping protection function, comprising a two-stage open-loop comparator circuit, characterized in that, Also includes: First clamping branch; The first end of the first clamping branch is connected to the power supply terminal, and the second end is connected to the first output node of the two-stage open-loop comparator circuit; the first output node is used to connect to the internal functional module, the internal functional module includes an enable control PMOS transistor, and the first output node is connected to the gate of the enable control PMOS transistor. An inverter is connected between the first input terminal and the second input terminal of the two-stage open-loop comparator. The input terminal of the inverter is connected to the first input terminal, and the output terminal of the inverter is connected to the second input terminal. When the enable control signal received by the first input terminal is a low level in the low-voltage power supply domain, the first-stage output node outputs a low level with voltage clamping, the enable control PMOS transistor is turned on, and the first clamping branch clamps the voltage of the first-stage output node. The enable control signal received by the first receiving end is a high level in the low-voltage power supply domain, and the first-stage output node outputs a high level in the high-voltage power supply domain, thus enabling the PMOS transistor to be turned off. The two-stage open-loop comparator circuit includes a seventh PMOS transistor, an eighth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a current source. The source of the seventh PMOS transistor is connected to the power supply terminal, the gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor and the drain of the seventh PMOS transistor, and the drain of the seventh PMOS transistor is connected to the drain of the eighth NMOS transistor. The gate of the eighth NMOS transistor is the first input terminal, and the source of the eighth NMOS transistor is connected to the drain of the seventh NMOS transistor. The source of the eighth PMOS transistor is connected to the power supply terminal, and the gate of the eighth PMOS transistor... The drain of the eighth PMOS transistor is connected to the gate of the seventh PMOS transistor, and the drain of the ninth NMOS transistor is connected to the drain of the ninth NMOS transistor. The gate of the ninth NMOS transistor is the second input terminal, and the source of the ninth NMOS transistor is connected to the drain of the seventh NMOS transistor. The gate of the seventh NMOS transistor is connected to the gate of the sixth NMOS transistor, and the source of the seventh NMOS transistor is grounded. The drain of the sixth NMOS transistor is connected to the gate of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded. One end of the current source is connected to the drain and gate of the sixth NMOS transistor, and the other end of the current source is grounded. The current direction of the current source is to flow into the drain of the sixth NMOS transistor.

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