A chip IO port and power port enhanced protection circuit

Abstract

The present invention discloses an enhanced protection circuit for the IO port and power port of a chip, which relates to the field of chip protection technology, and solves the problem that the existing chip protection circuit cannot simultaneously protect the IO port and the power port from ESD shock or microsecond-level shock. The enhanced protection circuit includes: a discharge branch, which is arranged between the IO port and the ground and between the power port and the ground, and is used to discharge current when the IO port or the power port is shocked; a control branch, including a primary control branch and a secondary control branch, the secondary control branch is used to control whether the primary control branch is turned on, and the primary control branch is used to control whether the discharge branch is turned on; a detection branch, which is used to trigger the control branch when it detects that the IO port and the power port are subjected to ESD shock or microsecond-level shock, and the control branch controls the discharge current of the discharge branch. The enhanced protection circuit provided by the present invention is used to discharge energy shocks from the IO port and the power port of the chip, and protect the internal circuit of the chip.

Description

Technical Field

[0001] The present invention relates to the field of chip protection technology, and in particular to an enhanced protection circuit for an IO port and a power port of a chip. Background Art

[0002] As the chip manufacturing process size continues to shrink, the maximum voltage that the CMOS circuit inside the chip can withstand is also decreasing. In harsh environments, the chip's IO ports and power ports will have nanosecond-level instantaneous ESD and microsecond-level surge impact discharge processes, causing chip damage.

[0003] Existing chip protection circuits only protect against ESD shocks or µs-level shocks on IO ports, but ignore shocks on power ports. When the power port is subjected to µs-level surges and overvoltage shocks, due to the limitation that the charging time of the RC in the chip is at the hundreds of nanoseconds, the existing chip protection circuit can only respond to nanosecond-level instantaneous ESD shocks for discharge and clamping. For µs-level surges and overvoltage shocks, the RC circuit is already saturated and cannot respond to trigger the protection circuit. As the voltage of µs-level surges and overvoltage shocks rises, it will cause permanent damage to the chip, and the robustness of the chip protection performance is poor. Summary of the Invention

[0004] The purpose of the present invention is to provide an enhanced protection circuit for the IO port and power port of a chip, which is used to solve the problem that the existing chip protection circuit cannot simultaneously protect the IO port and the power port from ESD impact and μs-level impact, resulting in poor chip protection robustness.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] The present invention provides an enhanced protection circuit for IO ports and power ports of a chip, comprising:

[0007] A discharge branch is provided between the IO port and the ground and between the power port and the ground, and is used to discharge current when the IO port or the power port is subjected to an impact; the impact includes an ESD impact or a microsecond impact;

[0008] A control branch, comprising a primary control branch and a secondary control branch, wherein the secondary control branch is used to control whether the primary control branch is conductive, and the primary control branch is used to control whether the discharge branch is conductive;

[0009] The detection branch includes a first detection branch and a second detection branch. The first detection branch is used to trigger the primary control branch when detecting that the IO port or the power port is subjected to an ESD impact, and the primary control branch controls the discharge branch to discharge the current of the ESD impact; the second detection branch is used to trigger the secondary control branch when detecting that the IO port or the power port is subjected to a us-level impact, and the secondary control branch controls the conduction of the primary control branch, and the primary control branch controls the discharge branch to discharge the current of the us-level impact.

[0010] Optionally, the discharge branch includes a first power tube, a second power tube and a third power tube, the first power tube is an NMOS tube, the second power tube and the third power tube are diodes; the drain of the first power tube is connected to the power port, the positive pole of the second power tube is connected to the negative pole of the third power tube, the first power tube is arranged between the power port and the ground, the second power tube is arranged between the power port and the IO port, and the third power tube is arranged between the IO port and the ground; the first power tube is used to discharge the ESD shock or µs-level shock current of the power port and the IO port, the second power tube is used to transmit the ESD shock current of the IO port to the first detection branch, and the third power tube is used to discharge the negative ESD shock current of the IO port.

[0011] Optionally, the primary control branch includes a first field effect transistor and a second field effect transistor, the first field effect transistor is a PMOS transistor, the second field effect transistor is an NMOS transistor, the first field effect transistor and the second field effect transistor are connected in series, and the first field effect transistor and the second field effect transistor cooperate to control whether the first power tube is turned on.

[0012] Optionally, the secondary control branch includes a current limiting resistor, a voltage dividing resistor and a transistor, the collector of the transistor is connected to the primary control branch, the current limiting resistor is connected in series with the base electrode of the transistor, the voltage dividing resistor is connected in parallel with the transistor, the voltage dividing resistor is connected in parallel with the current limiting resistor, and the voltage dividing resistor is used to provide a voltage dividing voltage to the transistor to turn on the transistor. When the transistor is turned on, the first field effect transistor is turned on and the second field effect transistor is turned off.

[0013] Optionally, the first detection branch includes a resistor and a capacitor, the resistor is connected in series with the capacitor, the series connection between the resistor and the capacitor is connected to the collector of the transistor, the resistor is connected in parallel with the first field effect transistor, the resistor is connected to the power port, and the capacitor is grounded; the resistor is used to provide a divided voltage to the first field effect transistor to make the first field effect transistor turn on.

[0014] Optionally, the second detection branch includes an IO detection branch and a power supply detection branch, the IO detection branch is connected to the IO port and the secondary control branch, the IO detection branch includes a first Zener diode and a first diode, the cathode of the first Zener diode is connected to the IO port, and the anode of the first Zener diode is connected to the anode of the first diode. When the IO port is subjected to a us-level impact, the first Zener diode reversely breaks down and turns on, triggering the secondary control branch to turn on, and the threshold voltage of the first Zener diode is greater than the peak value of the chip operating voltage.

[0015] Optionally, the power detection branch includes a second Zener diode and a second diode, the cathode of the second Zener diode is connected to the power port, and the anode of the second Zener diode is connected to the anode of the second diode. When the power port is subjected to a us-level impact, the second Zener diode reversely breaks down and turns on, triggering the secondary control branch to turn on; the threshold voltage of the second Zener diode is greater than the peak value of the chip operating voltage.

[0016] Optionally, when the IO port or the power port is subjected to ESD impact, the resistor and the capacitor are charged to turn on the first field effect transistor and the second field effect transistor, thereby driving the first power tube to turn on, thereby realizing ESD impact discharge current for the IO port or the power port.

[0017] Optionally, when the second detection branch detects a μs-level impact, a high level is provided to the base electrode of the transistor through the voltage divider resistor and the current limiting resistor, so that the gate of the first field effect transistor is at a low level and turned on, and the gate of the second field effect transistor is at a low level and turned off. At this time, the gate of the first power tube is at a high level and turned on.

[0018] Optionally, when the chip is working normally, the collector of the transistor is connected to the power supply via the resistor at a high level, controlling the first field effect transistor to be cut off and the second field effect transistor to be turned on. At this time, the gate of the first power tube is cut off at a low level.

[0019] Compared with the prior art, the present invention provides an enhanced protection circuit for the IO port and power port of a chip, including: a discharge branch, arranged between the IO port and the ground and between the power port and the ground, for discharging current when the IO port or the power port is impacted; the impact includes an ESD impact or a μs-level impact; a control branch, including a primary control branch and a secondary control branch, the secondary control branch is used to control whether the primary control branch is turned on, and the primary control branch is used to control whether the discharge branch is turned on; a detection branch, including a first detection branch and a second detection branch, the first detection branch is used to trigger the primary control branch when it detects that the IO port or the power port is impacted by ESD, and the primary control branch controls the discharge branch to discharge current to the ESD impact; the second detection branch is used to trigger the secondary control branch when it detects that the IO port or the power port is impacted by μs-level impact, the secondary control branch controls the primary control branch to be turned on, and the primary control branch controls the discharge branch to discharge current to the μs-level impact. The first detection branch is used to detect ESD shocks on the power port and IO port, and the second detection branch is used to detect μs-level shocks on the IO port and power port. When the detection branch detects ESD shocks or μs-level shocks, it triggers the control circuit to quickly turn on the discharge branches set between the power port and the ground and between the IO port and the ground, thereby discharging the overvoltage energy of the clamping shock, thereby protecting the internal circuit of the chip and enhancing the robustness of the chip protection performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0021] Figure 1 This is a structural diagram of the IO port and power port enhanced protection circuit of a chip provided by an embodiment of the present invention.

[0022] Reference numerals:

[0023] 10-discharge branch, 11-primary control branch, 12-secondary control branch, 13-first detection branch, 14-IO detection branch, 15-power supply detection branch. DETAILED DESCRIPTION

[0024] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0025] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0026] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0027] In the description of the present invention, it should be understood that the terms "up", "down", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0028] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0029] Electrostatic discharge (ESD) and surge-induced overvoltage currents are the main causes of integrated circuit failure within the chip. ESD shocks or surge shock discharges can occur at both the power port and the IO port of the chip, causing damage to the chip. Existing chip protection circuit designs generally set a number of Zener diodes and a number of diodes plus the threshold voltage of the power tube at the IO port as a preset locking voltage to discharge the µs-level shocks received by the IO port. This protection circuit cannot detect the µs-level shocks received by the power port and cannot discharge the ESD shocks. At the same time, multiple Zener diodes connected in series will result in weak adjustability of the clamping voltage, resulting in poor chip protection performance.

[0030] To address the above issues, the present invention provides an enhanced protection circuit for a chip's IO ports and power ports. This enhanced protection circuit incorporates detection branches at each chip's IO ports and power ports, each equipped with a Zener diode. This circuit rapidly conducts when subjected to a microsecond-level impact, triggering a discharge branch through a two-stage control branch to discharge and clamp the voltage, thereby protecting the chip's internal circuitry. This enhanced protection circuit protects both the chip's IO ports from ESD or microsecond-level impacts, as well as the power port from ESD or microsecond-level impacts, thereby enhancing the robustness of the chip's protection performance. A microsecond-level impact refers to a surge impact and overvoltage impact of the microsecond level, referred to herein as a microsecond-level impact. This will be described below with reference to the accompanying drawings.

[0031] Figure 1 The structure diagram of the IO port and power port enhanced protection circuit of a chip provided by an embodiment of the present invention is as follows: Figure 1 As shown, the enhanced protection circuit includes: a discharge branch 10, a primary control branch 11, a secondary control branch 12, a first detection branch 13, an IO detection branch 14, and a power detection branch 15. The discharge branch 10 is arranged between the IO port and the ground and between the power port and the ground. The primary control branch 11 is connected to the discharge branch 10, and the secondary control branch 12 is connected to the primary control branch 11. The first detection branch 13 is arranged between the power supply and the ground and is respectively connected to the primary control branch 11 and the secondary control branch 12. The power detection branch 15 is respectively connected to the power port and the secondary control branch 12. The IO detection branch 14 is respectively connected to the IO port and the secondary control branch 12.

[0032] The discharge branch 10 is used to discharge current when the IO port or the power port is impacted; the impact includes ESD impact or microsecond level impact;

[0033] The primary control branch 11 and the secondary control branch 12 constitute the control branch of the enhanced protection circuit. The secondary control branch 12 is used to control whether the primary control branch 11 is conductive, and the primary control branch 11 is used to control whether the discharge branch 10 is conductive.

[0034] The IO detection branch 14, the power supply detection branch 15 and the first detection branch 13 constitute the detection branch of the enhanced protection circuit. The first detection branch 13 is used to trigger the first-level control branch 11 when it detects that the IO port or the power supply port is subjected to ESD impact. The first-level control branch 11 controls the discharge branch 10 to discharge the ESD impact current; the power supply detection branch 15 is used to trigger the second-level control branch 12 when it detects that the power supply port is subjected to a us-level impact. The second-level control branch 12 controls the first-level control branch 11 to turn on, and the first-level control branch 11 controls the discharge branch 10 to discharge the us-level impact current; the IO detection branch 14 is used to trigger the second-level control branch 12 when it detects that the IO port is subjected to a us-level impact. The second-level control branch 12 controls the first-level control branch 11 to turn on, and the first-level control branch 11 controls the discharge branch 10 to discharge the us-level impact current.

[0035] In specific implementation, when the IO port or the power port is subjected to ESD impact, the first detection branch 13 detects the impact current and provides a turn-on voltage for the primary control branch 11, thereby driving the discharge branch 10 to discharge the current; when the power port is subjected to a us-level impact, the power detection branch 15 detects the impact current and provides a turn-on voltage for the secondary control branch 12, and the secondary control branch 12 provides a turn-on voltage for the primary control branch 11, thereby driving the discharge branch 10 to discharge the current; when the IO port is subjected to a us-level impact, the IO detection branch 14 detects the impact current and provides a turn-on voltage for the secondary control branch 12, and the secondary control branch 12 provides a turn-on voltage for the primary control branch 11, thereby driving the discharge branch 10 to discharge the current, thereby achieving protection of the internal circuit of the chip.

[0036] It can be seen from the structure and specific implementation process of the above-mentioned enhanced protection circuit that the first detection branch 13 detects ESD impacts on the power port and the IO port, the power detection branch 15 detects us-level impacts on the power port, and the IO detection branch 14 detects us-level impacts on the IO port. When the detection branch detects ESD impact or us-level impact, it triggers the control branch to quickly turn on the discharge branch set between the power port and the ground and the IO port and the ground to discharge the overvoltage energy of the clamping impact, thereby protecting the internal circuit of the chip and enhancing the robustness of the chip protection performance.

[0037] As a possible implementation, see Figure 1The discharge branch 10 includes a first power tube Q3, a second power tube D1, a third power tube D2, and a resistor R5. The first power tube Q3 is an NMOS tube, and the second power tube D1 and the third power tube D2 are diodes. The drain of the first power tube Q3 is connected to the power port, the cathode of the second power tube D1 is connected to the drain of the first power tube Q3, and the anode of the second power tube D1 is connected to the cathode of the third power tube D2. The first power tube Q3 is arranged between the power port and ground, the second power tube D1 is arranged between the power port and the IO port, and the third power tube D2 is arranged between the IO port and ground. The resistor R5 is connected in parallel with the first power tube Q3 and is connected to the primary control branch 11. The first power tube Q3 is used to discharge ESD shocks or microsecond-level shocks from the power port and the IO port. The second power tube D1 is used to transmit the ESD shock current from the IO port to the first detection branch. The third power tube D2 is used to discharge negative ESD shock current from the IO port.

[0038] The first power transistor Q3, located between VDD and GND, exhibits low impedance when conducting, effectively protecting the IO ports and power port from ESD and microsecond-level surges. The second power transistor D1 and the third power transistor D2 provide reverse isolation, with the second power transistor D1 preventing surge current from the power port from flowing to the IO ports.

[0039] As a possible implementation, see Figure 1 The primary control branch 11 includes a first field effect transistor Q1 and a second field effect transistor Q2. The first field effect transistor Q1 is a PMOS transistor, and the second field effect transistor Q2 is an NMOS transistor. The first field effect transistor Q1 and the second field effect transistor Q2 are connected in series. The connection between the source of the first field effect transistor Q1 and the drain of the second field effect transistor Q2 is connected to the gate of the first power transistor Q3 and the resistor R5.

[0040] The primary control branch 11 is used to control the on or off of the first power tube Q3 in the discharge branch 10. The first field-effect tube Q1 and the second field-effect tube Q2 cooperate to control whether the first power tube Q3 is on. Specifically, when the chip is working normally, the second field-effect tube Q2 is on and the first field-effect tube Q1 is off. At this time, the first power tube Q3 is off; when subjected to ESD impact, the first field-effect tube Q1 and the second field-effect tube Q2 are turned on together, and the first power tube Q3 is controlled to be turned on through the on-resistance voltage divider of Q1 and Q2; when subjected to a microsecond level impact, the first field-effect tube Q1 is turned on and the second field-effect tube Q2 is turned off. At this time, the first power tube Q3 is turned on; wherein the first field-effect tube Q1 is turned on when the gate is low and turned off when the gate is high, and the second field-effect tube Q2 is turned on when the gate is high and turned off when the gate is low.

[0041] As a possible implementation, see Figure 1The secondary control branch 12 includes a current limiting resistor R2, a voltage dividing resistor R3 and a transistor Q4. The connection between the gate of the first field effect transistor Q1 and the gate of the second field effect transistor is connected to the collector of the transistor Q4. The current limiting resistor R2 is connected in series with the base electrode of the transistor Q4. The voltage dividing resistor R3 is connected in parallel with the transistor Q4. The voltage dividing resistor R3 is connected in parallel with the current limiting resistor R2. The voltage dividing resistor R3 is used to provide a divided voltage to the transistor Q4 to turn on the transistor Q4. When the transistor Q4 is turned on, the first field effect transistor Q1 is turned on and the second field effect transistor Q2 is turned off.

[0042] Transistor Q4 can be selected from models such as 2N1070 and 2N1069. When the second detection branch detects a microsecond impact, the base electrode of transistor Q4 is provided with a high level through the voltage divider resistor R3 and the current limiting resistor R2, so that the gate of the first field effect transistor Q1 is at a low level and turned on, and the gate of the second field effect transistor is at a low level and turned off. At this time, the gate of the first power transistor Q3 is at a high level and turned on.

[0043] As a possible implementation, see Figure 1 The first detection branch 13 includes a resistor R4 and a capacitor C1. The resistor R4 and the capacitor C1 are connected in series. The connection point between the resistor R4 and the capacitor C1 is connected to the collector of the transistor Q4. The resistor R4 is connected in parallel with the first field effect transistor Q1. The resistor R4 is connected to the power port and the capacitor C1 is grounded. The resistor R4 is used to provide a divided voltage for the first field effect transistor Q1 to turn on the first field effect transistor Q1.

[0044] As a possible implementation, see Figure 1 The IO detection branch 14 includes a first Zener diode D3 and a first diode D4. The cathode of the first Zener diode D3 is connected to the IO port, and the anode of the first Zener diode D3 is connected to the anode of the first diode D4. When the IO port is subjected to a μs-level impact, the first Zener diode D3 reversely breaks down and turns on, triggering the secondary control branch 12 to turn on. The threshold voltage of the first Zener diode D3 is greater than the peak value of the chip operating voltage.

[0045] As a possible implementation, see Figure 1 The power detection branch 15 includes a second Zener diode D5 and a second diode D6. The cathode of the second Zener diode D5 is connected to the power port, and the anode of the second Zener diode D5 is connected to the anode of the second diode D6. When the power port is subjected to a us-level impact, the second Zener diode D5 reversely breaks down and turns on, triggering the secondary control branch 12 to turn on; the threshold voltage of the second Zener diode D5 is greater than the peak value of the chip operating voltage.

[0046] The first diode D4 and the second diode D6 have a reverse isolation function, which can prevent the current of the secondary control branch 12 from interfering with the IO port and the power port.

[0047] To avoid the situation where the impact duration encountered by the IO port or power port exceeds the charging time of R4 and C1, and the two Zener diodes have not yet broken down, it is necessary to match the design to make the two Zener diodes break down in advance before R4 and C1 saturate.

[0048] Combine Figure 1 The working process of the enhanced protection circuit of the present invention is explained as follows: when the chip is working normally, the first Zener diode D3 in the IO detection branch and the second Zener diode D5 in the power detection branch are reversely cut off, the base electrode of the transistor Q4 is at a low level and is not conducting, and the collector of the transistor Q4 is connected to the power supply VDD at a high level through the resistor R4, controlling the first field effect transistor Q1 to be cut off and the second field effect transistor Q2 to be turned on. At this time, the gate of the first power tube Q3 is at a low level and is not conducting. The enhanced protection circuit of the present invention does not affect the normal operation of the chip.

[0049] When the IO port of the chip encounters an ESD shock, the shock current flows through the second power tube D1 to the first detection branch 13, and is charged by the resistor R4 and the capacitor C1, so that the first field effect tube Q1 and the second field effect tube Q2 in the primary control branch 11 are turned on, thereby driving the first power tube Q3 in the discharge branch 10 to turn on, realizing the ESD shock discharge current of the IO port.

[0050] When the power port of the chip encounters an ESD shock, the shock current flows to the first detection branch 13, is charged through the resistor R4 and the capacitor C1, and turns on the first field effect transistor Q1 and the second field effect transistor Q2 in the primary control branch 11, thereby driving the first power transistor Q3 in the discharge branch 10 to turn on, realizing the ESD shock discharge current of the IO port.

[0051] When the chip's IO port experiences a µs surge that lasts longer than the charging time of R4 and C1, the gate and drain voltages of the first FET Q1 in the primary control branch 11 become equal to VDD, causing the device to shut down and unable to maintain the conduction of the first power transistor Q3 in the discharge branch 10. At this point, the overshoot voltage exceeds the reverse breakdown threshold of the first Zener diode D3 in the IO detection branch 14, causing D3 to conduct. This provides a high voltage level to the base electrode of the transistor Q4 via the first diode D4, the voltage divider resistor R3, and the current-limiting resistor R2, turning on the transistor Q4. This causes the gate of the first FET Q1 in the primary control branch 11 to be low, turning it on, and the gate of the second FET Q2 to be low, turning it off. At this point, the gate of the first power transistor Q3 in the discharge branch 10 remains high, allowing it to continue conducting, clamping the µs surge at the IO port and continuing to protect the chip's internal circuits.

[0052] When the power port of the chip experiences a μs surge that lasts longer than the charging time of R4 and C1, the gate voltage and drain voltage of the first field-effect transistor Q1 in the primary control branch 11 become equal to VDD, causing it to be cut off and unable to continue to maintain the conduction of the first power transistor Q3 in the discharge branch 10. At this time, the overshoot voltage exceeds the reverse breakdown threshold of the second Zener diode D5 in the power detection branch 15, causing D5 to turn on. A high level is provided to the base electrode of the transistor Q4 via the second diode D6, the voltage-dividing resistor R3, and the current-limiting resistor R2, causing the transistor Q4 to turn on. This causes the gate of the first field-effect transistor Q1 in the primary control branch 11 to be at a low level, turning it on, and the gate of the second field-effect transistor Q2 to be at a low level, turning it off. At this time, the gate of the first power transistor Q3 in the discharge branch 10 is at a high level, allowing it to continue to conduct, clamping the μs surge at the power port and continuing to protect the internal circuits of the chip.

[0053] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0054] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A chip IO port and power port enhanced protection circuit, characterized in that: include: A discharge branch is provided between the IO port and the ground and between the power port and the ground, and is used to discharge current when the IO port or the power port is subjected to an impact; the impact includes an ESD impact or a microsecond impact; A control branch, comprising a primary control branch and a secondary control branch, wherein the secondary control branch is used to control whether the primary control branch is conductive, and the primary control branch is used to control whether the discharge branch is conductive; The detection branch includes a first detection branch and a second detection branch, wherein the first detection branch is used to trigger the primary control branch when detecting that the IO port or the power port is subjected to an ESD impact, and the primary control branch controls the discharge branch to discharge current in response to the ESD impact; the second detection branch is used to trigger the secondary control branch when detecting that the IO port or the power port is subjected to a μs-level impact, and the secondary control branch controls the primary control branch to be turned on, and the primary control branch controls the discharge branch to discharge current in response to the μs-level impact; The discharge branch includes a first power tube, a second power tube and a third power tube, the first power tube is an NMOS tube, and the second power tube and the third power tube are diodes; the drain of the first power tube is connected to the power port, the positive electrode of the second power tube is connected to the negative electrode of the third power tube, the first power tube is arranged between the power port and the ground, the second power tube is arranged between the power port and the IO port, and the third power tube is arranged between the IO port and the ground; the primary control branch includes a first field effect tube and a second field effect tube, the first field effect tube is a PMOS tube, the second field effect tube is an NMOS tube, and the first field effect tube and the second field effect tube are connected in series; the secondary control branch includes a current limiting resistor, a voltage dividing resistor and a transistor, the collector of the transistor is connected to the primary control branch, the current limiting resistor is connected in series to the base electrode of the transistor, the voltage dividing resistor is connected in parallel with the transistor, and the voltage dividing resistor is connected in parallel with the current limiting resistor; the first detection branch includes a resistor and a capacitor, the resistor The resistor is connected in series with the capacitor, and the collector of the transistor is connected at the connection point of the resistor and the capacitor in series. The resistor is connected in parallel with the first field effect transistor, and the resistor is connected to the power port. The capacitor is grounded; the resistor is used to provide a divided voltage for the first field effect transistor to turn on the first field effect transistor; the second detection branch includes an IO detection branch and a power detection branch, and the IO detection branch is connected to the IO port and the secondary control branch. The IO detection branch includes a first Zener diode and a first diode, the cathode of the first Zener diode is connected to the IO port, and the anode of the first Zener diode is connected to the anode of the first diode. When the IO port is subjected to a us-level impact, the first Zener diode reversely breaks down and turns on, triggering the secondary control branch to turn on. The threshold voltage of the first Zener diode is greater than the peak value of the chip operating voltage; the power detection branch includes a second Zener diode and a second diode, the cathode of the second Zener diode is connected to the power port, and the anode of the second Zener diode is connected to the anode of the second diode.

2. The enhanced protection circuit according to claim 1, characterized in that: The first power tube is used to discharge the current of the ESD impact or μs-level impact of the power port and the IO port, the second power tube is used to transmit the current of the ESD impact of the IO port to the first detection branch, and the third power tube is used to discharge the current of the negative ESD impact of the IO port.

3. The enhanced protection circuit according to claim 1, characterized in that: The first field effect tube cooperates with the second field effect tube to control whether the first power tube is turned on.

4. The enhanced protection circuit according to claim 1, characterized in that: The voltage-dividing resistor is used to provide a divided voltage to the transistor to turn on the transistor. When the transistor is turned on, the first field-effect transistor is turned on and the second field-effect transistor is turned off.

5. The enhanced protection circuit according to claim 1, characterized in that: When the power port is subjected to a microsecond impact, the second Zener diode reversely breaks down and turns on, triggering the secondary control branch to turn on; the threshold voltage of the second Zener diode is greater than the peak value of the chip operating voltage.

6. The enhanced protection circuit according to claim 1, characterized in that: When the IO port or the power port is subjected to ESD impact, the resistor and the capacitor are charged to turn on the first field-effect transistor and the second field-effect transistor, thereby driving the first power tube to turn on, thereby achieving ESD impact discharge current for the IO port or the power port.

7. The enhanced protection circuit according to claim 1, characterized in that: When the second detection branch detects a μs-level impact, a high level is provided to the base electrode of the transistor through the voltage divider resistor and the current limiting resistor, so that the gate of the first field effect transistor is at a low level and turned on, and the gate of the second field effect transistor is at a low level and turned off. At this time, the gate of the first power tube is at a high level and turned on.

8. The enhanced protection circuit according to claim 1, characterized in that: When the chip works normally, the collector of the transistor is connected to the power supply through the resistor and is at a high level, which controls the first field effect tube to be turned off and the second field effect tube to be turned on. At this time, the gate of the first power tube is at a low level and is cut off.

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