Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: forming a groove in an initial stacked structure on both sides of a pseudo-gate structure, and the remaining initial stacked structure is used as a stacked structure; forming a sub-doping layer on a channel layer on the sidewall of the groove, and in the stacked structure, the sub-doping layers on adjacent channel layers are in contact to form an initial transition doping layer; doping ions in a partial thickness material on the surface of the initial transition doping layer, suitable for reducing the etching resistance of the initial transition doping layer; removing the initial transition doping layer doped with ions, and the remaining initial transition doping layer is used as a transition doping layer; forming a main doping layer between the transition doping layers on the opposite sidewalls of the groove, the ion doping concentration of the main doping layer is greater than the ion doping concentration of the transition doping layer, and the main doping layer is used to form a source-drain doping layer with the transition doping layer. The embodiments of the present invention improve the formation quality of the source-drain doping layer, reduce the defects inside the source-drain doping layer, and improve the performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration, and semiconductor process nodes are continuously decreasing in accordance with Moore's Law. Transistors, as the most basic semiconductor devices, are currently being widely used. Therefore, with the increase in component density and integration of semiconductor devices, in order to adapt to the reduction of process nodes, the channel length of transistors must be continuously shortened.

[0003] In order to better adapt to the requirements of device size reduction, semiconductor processes have gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a gate-all-around transistor, the gate surrounds the area where the channel is located from all sides. Compared with planar transistors, the gate of a gate-all-around transistor has a stronger control ability over the channel and can better suppress the short channel effect.

[0004] However, the performance of current devices still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the formation quality of the source-drain doping layer, reduce the defects inside the source-drain doping layer, and enhance the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, comprising a plurality of discrete device unit regions; the substrate comprising a substrate and a plurality of protrusions protruding from the substrate of the device unit region; an isolation layer, located on the substrate and surrounding the protrusions; a channel structure layer, located above the protrusions and spaced from the protrusions, the channel structure layer comprising one or more channel layers spaced in sequence; a plurality of gate structures, located on the isolation layer of the device unit region, the gate structures spanning the channel structure layer and surrounding the channel layer; a source-drain doping layer; a gate structure layer comprising a plurality of gate structures ... gate structure; a gate structure layer comprising a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate structure; a gate An impurity layer is located on the protrusions on both sides of the gate structure and is in contact with the end of the channel structure layer along the extension direction; the source and drain doping layer includes: a transition doping layer, including a sub-doping layer located on an adjacent channel layer in the channel structure layer, and the sub-doping layers on the adjacent channel layers are in contact, and the sidewalls of the transition doping layer are smooth sidewalls; a main doping layer is located between the transition doping layers on the ends of the adjacent channel structure layers along the extension direction and is in contact with the transition doping layer, and the ion doping concentration of the main doping layer is higher than the ion doping concentration of the transition doping layer.

[0007] Accordingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a plurality of discrete device unit regions, the substrate comprising a substrate and a plurality of protruding portions protruding from the substrate of the device unit region; forming an initial stacked structure on the protruding portions, comprising a plurality of channel stacks stacked in sequence from bottom to top, each of the channel stacks comprising a sacrificial layer and a channel layer located on the sacrificial layer; forming a plurality of pseudo-gate structures across the initial stacked structure in the device unit region; forming grooves in the initial stacked structure on both sides of the pseudo-gate structure, and the remaining initial stacked structure is used as a stacked structure; forming a plurality of pseudo-gate structures on the sidewalls of the grooves ... A sub-doping layer is formed on the channel layer, and in the stacked structure, the sub-doping layers on adjacent channel layers are in contact to form an initial transition doping layer; ions are doped into a partial thickness material on the surface of the initial transition doping layer, and the doped ions are suitable for reducing the etching resistance of the initial transition doping layer; the initial transition doping layer doped with ions is removed, and the remaining initial transition doping layer is used as a transition doping layer; a main doping layer is formed between the transition doping layers on the opposite side walls of the groove, the ion doping concentration of the main doping layer is greater than the ion doping concentration of the transition doping layer, and the main doping layer is used to form a source-drain doping layer with the transition doping layer.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the method for forming a semiconductor structure provided by an embodiment of the present invention, the initial transition doping layer is formed, and ions are doped into a partial thickness material on the surface of the initial transition doping layer, which is suitable for reducing the etching resistance of the initial transition doping layer. In the process of doping ions, when the initial transition doping layer has an uneven surface, the ions are more easily doped and diffused to the protrusions on the surface of the initial transition doping layer than to the depressions on the surface of the initial transition doping layer, so that more doped ions can be distributed on the protrusions on the surface of the initial transition doping layer than to the depressions; accordingly, in the process of removing the initial transition doping layer doped with ions, the initial transition doping layer is more easily doped and diffused to the protrusions on the surface of the initial transition doping layer than to the depressions. Compared with the depressions on the surface of the transition doping layer, since the protrusions on the surface of the initial transition doping layer have more doping ions, the protrusions on the surface of the initial transition doping layer are easier to remove and the removal rate is faster. Therefore, after removing the initial transition doping layer doped with ions to form the transition doping layer, the transition doping layer can obtain a relatively smooth side wall surface, which is beneficial to providing a good interface state for forming the main doping layer, and is beneficial to improving the formation quality of the main doping layer and reducing the interface defects between the main doping layer and the transition doping layer, and correspondingly improving the formation quality of the source and drain doping layer, reducing the defects inside the source and drain doping layer, and improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;

[0011] Figure 2 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0012] Figures 3 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0013] As can be seen from the background technology, the performance of current devices still needs to be improved. The reason why the performance of devices needs to be improved is now analyzed in combination with a semiconductor structure.

[0014] Figure 1 It is a structural diagram of a semiconductor structure.

[0015] The semiconductor structure includes: a substrate 10, including a plurality of discrete device unit areas 10s; a plurality of protrusions 18, discretely disposed on the substrate 10 of the device unit area 10s; a channel structure layer 11, located on the protrusions 18, the channel structure layer 11 including a plurality of channel layers 12 spaced apart from bottom to top; a gate structure 13, spanning the channel structure layer 11 and covering the top of the channel structure layer 11, the gate structure 13 filling between adjacent channel layers 12 and surrounding the channel layer 12; a source-drain doping layer 14, located on both sides of the gate structure 13 and covering the sidewalls of the channel structure layer 11, and in the device unit area 10s, the source-drain doping layers 14 located on the ends of adjacent channel structure layers 11 are in contact with each other.

[0016] In the semiconductor structure, the source-drain doped layer 14 includes sub-source-drain doped layers 15 respectively located on the ends of each channel layer 12 along the extension direction, and in the same channel structure layer 11, the sub-source-drain doped layers 15 located on adjacent channel layers 12 are in contact with each other to form the source-drain doped layer 14, and in adjacent channel structure layers 11, the source-drain doped layers 14 located on the ends of adjacent channel structure layers 11 are in contact with each other.

[0017] The sub-source-drain doping layers 15 are formed by epitaxial growth based on the corresponding channel layer 12, and grain boundaries are formed between each sub-source-drain doping layer 15. The surface of the source-drain doping layer 14 formed by contacting each sub-source-drain doping layer 15 is usually uneven. In addition, the source-drain doping layers 14 located at the ends of adjacent channel structure layers 11 are in contact with each other, and grain boundaries are formed between the source-drain doping layers 14 located at the ends of adjacent channel structure layers 11. The source-drain doping layers 14 have more grain boundaries, which leads to defective interfaces that are easily formed in the source-drain doping layers 14, which easily reduces the stress in the source-drain doping layers 14, and thus easily reduces the performance of the device.

[0018] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure. After forming the initial transition doping layer, ions are doped into a partial thickness material on the surface of the initial transition doping layer, which is suitable for reducing the etching resistance of the initial transition doping layer. In the process of doping ions, when the initial transition doping layer has an uneven surface, the ions are more easily doped and diffused to the protrusions of the surface of the initial transition doping layer than to the depressions on the surface of the initial transition doping layer, so that more doped ions can be distributed on the protrusions of the surface of the initial transition doping layer than on the depressions; accordingly, when removing the initial transition doping layer doped with ions, In the process, compared with the depressions on the surface of the initial transition doping layer, since the protrusions on the surface of the initial transition doping layer have more doping ions, the protrusions on the surface of the initial transition doping layer are easier to remove and the removal rate is faster. Therefore, after removing the initial transition doping layer doped with ions to form the transition doping layer, the transition doping layer can obtain a smoother side wall surface, which is beneficial to providing a good interface state for forming the main doping layer, and is beneficial to improving the formation quality of the main doping layer and reducing the interface defects between the main doping layer and the transition doping layer, and correspondingly improving the formation quality of the source and drain doping layer, reducing the defects inside the source and drain doping layer, and improving the performance of the semiconductor structure.

[0019] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figure 2 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention. Figure 2 It is a cross-sectional view at the location of the channel structure layer along the extending direction of the channel structure layer.

[0020] like Figure 2 As shown, in this embodiment, the semiconductor structure includes: a substrate including a plurality of discrete device unit regions 100s; the substrate includes a substrate 100 and a plurality of protrusions 105 of the substrate 100 protruding from the device unit regions 100s; an isolation layer 110 (combined with reference Figure 5), located on the substrate 100 and surrounding the protrusion 105; a channel structure layer 300, located above the protrusion 105 and spaced apart from the protrusion 105, the channel structure layer 300 includes one or more channel layers 30 spaced apart in sequence; a plurality of gate structures 220, located on the isolation layer 110 of the device unit area 100s, the gate structure 220 spans the channel structure layer 300 and surrounds the channel layer 30; a source-drain doped layer 250, located on the protrusions 105 on both sides of the gate structure 220 and spaced apart from the end of the channel structure layer 300 along the extension direction; The source-drain doping layer 250 includes: a transition doping layer 180, including a sub-doping layer 40 located on an adjacent channel layer 30 in the channel structure layer 300, and the sub-doping layers on the adjacent channel layers are in contact with each other, and the sidewalls of the transition doping layer 180 are smooth sidewalls; a main doping layer 230, located between the transition doping layers 180 on the ends of the adjacent channel structure layers 300 along the extension direction and in contact with the transition doping layer 180, and the ion doping concentration of the main doping layer 230 is higher than the ion doping concentration of the transition doping layer 180.

[0021] The main doping layer 230 is formed after the transition doping layer 180. The sidewalls of the transition doping layer 180 are smooth sidewalls, which are beneficial to providing a good interface state for forming the main doping layer 230, and are beneficial to improving the formation quality of the main doping layer 230 and reducing the interface defects between the main doping layer 230 and the transition doping layer 180, thereby improving the performance of the semiconductor structure.

[0022] The substrate is used to provide a process platform for forming a semiconductor structure. In this embodiment, the semiconductor structure is an all-around gate (GAA) transistor as an example for description. In other embodiments, the semiconductor structure can also be a forksheet transistor or a complementary field effect transistor (CFET).

[0023] The device unit region 100s is used to form a device unit, and a plurality of device unit regions 100s are separated from each other.

[0024] In this embodiment, the base includes a substrate 100 and a plurality of protrusions 105 protruding from the substrate 100 .

[0025] In this embodiment, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single crystal silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0026] In this embodiment, the protrusion 105 and the substrate 100 are an integrated structure, and the material of the protrusion 105 is the same as that of the substrate 100, both of which are silicon. In other embodiments, the material of the protrusion may be different from that of the substrate, and the material of the protrusion may be other suitable materials, such as one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

[0027] In this embodiment, the protrusion 105 is a fin-shaped structure extending in the transverse direction.

[0028] The channel structure layer 300 is used to provide a conductive channel of the field effect transistor. In this embodiment, the channel structure layer 300 is located above the protrusion 105. In this embodiment, the channel layer 30 extends in a lateral direction.

[0029] In this embodiment, there are multiple channel layers 30 , and the stacking direction of the multiple channel layers 30 arranged in sequence from bottom to top is perpendicular to the surface of the substrate 100 .

[0030] In this embodiment, the semiconductor structure is an NMOS transistor, and the material of the channel layer 30 is Si. In other embodiments, when the semiconductor structure is a PMOS transistor, in order to improve the performance of the PMOS transistor, SiGe channel technology can be used, and the material of the channel layer is SiGe. In other embodiments, the material of the channel layer can also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

[0031] In this embodiment, in the channel structure layer 400, the number of the channel layers 30 is plural. As an example, the number of the channel layers 30 is three. In other embodiments, the number of the channel layers may be other numbers, for example, one, two, four, etc.

[0032] The isolation layer 110 is used to isolate adjacent protrusions 105, and is also used to isolate the substrate 100 from the gate structure 220. In this embodiment, the isolation layer 110 is made of silicon oxide. The isolation layer 110 can also be other insulating materials, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon germanium oxide.

[0033] In this embodiment, the top surface of the isolation layer 110 is lower than the top surface of the protrusion 105, that is, the isolation layer 110 also exposes part of the side wall of the protrusion 105. In other embodiments, the top surface of the isolation layer may also be flush with the top surface of the protrusion.

[0034] When the device is operating, the gate structure 220 is used to control the opening and closing of the conductive channel.

[0035] In this embodiment, the gate structure 220 is located on the isolation layer 110 and crosses the channel structure layer 300 .

[0036] In this embodiment, the gate structure 220 is a metal gate structure. In this embodiment, the gate structure 220 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0037] The gate dielectric layer is used to achieve electrical isolation between the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3.

[0038] The material of the gate electrode layer includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni. In a specific implementation, the gate electrode layer may include a work function layer (not shown) and an electrode layer (not shown) located on the work function layer, and the work function layer is used to adjust the work function of the gate structure 220, thereby adjusting the threshold voltage of the field effect transistor.

[0039] In this embodiment, the portion of the gate structure 220 located between adjacent channel layers 30 or between the channel layer 30 and the substrate is referred to as the first portion 220 (1), and the portion of the gate structure 220 spanning the channel structure layer 300 is referred to as the second portion 220 (2).

[0040] In this embodiment, along the extension direction of the channel layer 30, the sidewall of the first portion 220(1) is retracted relative to the sidewall of the channel layer 30, and the sidewall of the second portion 220(2) is retracted relative to the sidewall of the channel layer 30. Specifically, the portion of the gate structure 220 located between adjacent channel layers 30 or between the channel layer 30 and the protrusion 105 is the first portion 220(1).

[0041] The semiconductor structure further includes an inner sidewall 150 located between adjacent channel layers 30 or between the channel layer 30 and the protrusion 105 , and the inner sidewall 150 covers the sidewall of the first portion 220 ( 1 ).

[0042] The inner sidewall 150 is used to achieve isolation between the source-drain doped layer 250 and the first portion 220 ( 1 ), and also increases the distance between the first portion 220 ( 1 ) and the source-drain doped layer 250 , which is beneficial to reducing the parasitic capacitance between the gate structure 220 and the source-drain doped layer 250 .

[0043] In this embodiment, the material of the inner sidewall 150 is an insulating material to achieve isolation between the source-drain doped layer 250 and the gate structure 220. The material of the inner sidewall 150 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material. As an example, the material of the inner sidewall 150 is silicon nitride.

[0044] In this embodiment, the semiconductor structure further includes: a gate spacer 130 , which is located on the sidewall of the second portion and exposes the end of the channel structure layer 300 in the extending direction.

[0045] In this embodiment, the material of the gate spacer 130 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material, and the gate spacer 130 is a single-layer or stacked structure. As an example, the gate spacer 130 is a single-layer structure, and the material of the gate spacer 130 is silicon nitride.

[0046] The source-drain doped layer 250 is used as a source or a drain of a field effect transistor. When the field effect transistor is working, the source-drain doped layer 250 is used to provide a carrier source.

[0047] The transition doping layer 180 is used as a transition layer or an adhesion layer for forming the main doping layer 230 , so as to provide a good interface state for forming the main doping layer 230 .

[0048] The transition doping layer 180 includes a sub-doping layer 40 located on an adjacent channel layer 30 in the channel structure layer 300 , and the sub-doping layers 40 on the adjacent channel layers 30 are in contact with each other.

[0049] When forming a PMOS transistor, the transition doping layer 180 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe; when forming an NMOS transistor, the transition doping layer 180 includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC.

[0050] In this embodiment, the transition doping layer 180 is a U-shaped structure, and the transition doping layer 180 further includes a bottom doping layer 50 located on the protrusion 105 , and the bottom doping layer 50 is in contact with the sub-doping layer 40 . Specifically, the bottom doping layer 50 is embedded in the protrusion 105 .

[0051] In this embodiment, the sub-doping layer 40 includes a first stress layer doped with ions, and the bottom doping layer 50 includes a second stress layer doped with ions.

[0052] Specifically, when forming a PMOS transistor, the first stress layer and the second stress layer are doped with P-type ions, and the materials of the first stress layer and the second stress layer include Si or SiGe; when forming an NMOS transistor, the first stress layer and the second stress layer are doped with N-type ions, and the materials of the stress layers include Si or SiC.

[0053] In this embodiment, the transition doping layer 180 covers the sidewalls of the inner sidewall 150 .

[0054] The main doping layer 230 is formed after the transition doping layer 180. The sidewalls of the transition doping layer 180 are smooth sidewalls, which are beneficial to providing a good interface state for forming the main doping layer 230, and are beneficial to improving the formation quality of the main doping layer 230 and reducing the interface defects between the main doping layer 230 and the transition doping layer 180, thereby improving the performance of the semiconductor structure.

[0055] The main doping layer 230 is used as the main source of stress for the source-drain doping layer 250. Also, the main doping layer 230 is used as the main source of carriers provided by the source-drain doping layer 250, so the ion doping concentration of the main doping layer 230 is relatively high.

[0056] When forming an NMOS transistor, the material of the main doping layer 230 includes a third stress layer doped with N-type ions, and the material of the third stress layer is Si or SiC, thereby providing tensile stress to the channel region of the NMOS transistor, which is beneficial to improving the carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions or Sb ions. When forming a PMOS transistor, the material of the main doping layer 230 includes a third stress layer doped with P-type ions, and the material of the third stress layer is Si or SiGe, thereby providing compressive stress to the channel region of the PMOS transistor, which is beneficial to improving the carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions or In ions.

[0057] In this embodiment, the source-drain doping layer 250 further includes: a cap doping layer 240 located on the top of the main doping layer 230 , and the ion doping concentration of the cap doping layer 240 is lower than the ion doping concentration of the main doping layer 230 .

[0058] The ion doping concentration of the cap doping layer 240 is lower than that of the main doping layer 230, and is used to reduce the out-diffusion of the doped ions in the main doping layer 230 during the heat treatment process during the formation of the semiconductor structure. In addition, the cap doping layer 240 is also used to contact the source and drain plugs and serve as a buffer layer when forming the source and drain plugs.

[0059] In this embodiment, the cap doping layer 240 includes a fourth stress layer doped with ions, the material of the fourth stress layer is the same as the material of the third stress layer, and the ion doping type in the cap doping layer 240 is the same as the ion doping type of the main doping layer 230 .

[0060] In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer (not shown), which is located on the isolation layer 110 and covers the source and drain doping layer 250 and the sidewalls of the gate spacer 130. The interlayer dielectric layer is used to isolate adjacent devices. The material of the interlayer dielectric layer can be an insulating material such as silicon oxide, silicon oxynitride, etc.

[0061] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 3 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0062] The method for forming the semiconductor structure of this embodiment is described in detail below with reference to the accompanying drawings.

[0063] refer to Figure 3 , shows a schematic diagram of a local three-dimensional structure, providing a substrate, including a plurality of discrete device unit areas 100s, the substrate including a substrate 100 and a plurality of protrusions 105 protruding from the substrate 100 in the device unit area 100s; an initial stacked structure 115 is formed on the protrusions 105, including a plurality of channel stacks 210 stacked in sequence from bottom to top, each of the channel stacks 210 including a sacrificial layer 20 and a channel layer 30 located on the sacrificial layer 20.

[0064] The substrate is used to provide a process platform for subsequent processes. In this embodiment, the formation of a gate-all-around (GAA) transistor is used as an example for explanation. In other embodiments, the formation method can also be used to form a forksheet transistor or a complementary field effect transistor (CFET).

[0065] The device unit region 100s is used to form a device unit, and a plurality of device unit regions 100s are separated from each other.

[0066] In this embodiment, the base includes a substrate 100 and a plurality of protrusions 105 protruding from the substrate 100 ; the initial stacked structure 115 is located on the protrusions 105 .

[0067] In this embodiment, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single crystal silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0068] In this embodiment, the protrusion 105 and the substrate 100 are an integrated structure, and the material of the protrusion 105 is the same as that of the substrate 100, both of which are silicon. In other embodiments, the material of the protrusion may be different from that of the substrate, and the material of the protrusion may be other suitable materials, such as one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

[0069] In this embodiment, the protrusion 105 is along the X direction (eg Figure 3 ) extended fin structure.

[0070] As an example, the initial stacked structure 115 is a fin structure extending along the X direction.

[0071] In the initial stacked structure 115, the number of the channel stacks 210 is multiple, and the stacking direction of the multiple channel stacks 210 (eg Figure 4 The Z direction is perpendicular to the surface of the substrate 100.

[0072] The channel stack 210 provides a process basis for the subsequent formation of a suspended and spaced channel layer 30. Specifically, the channel layer 30 is used to provide a conductive channel of the field effect transistor, and the sacrificial layer 20 is used to support the channel layer 30, thereby providing a process basis for the subsequent realization of the spaced and suspended arrangement of the channel layer 30, and the sacrificial layer 20 is also used to occupy a space position for the subsequent formation of a gate structure.

[0073] In this embodiment, an NMOS transistor is formed, the material of the channel layer 30 is Si, and the material of the sacrificial layer 20 is SiGe. In the subsequent process of removing the sacrificial layer 20, the etching selectivity of SiGe and Si is relatively high, so by setting the material of the sacrificial layer 20 to SiGe and the material of the channel layer 30 to Si, the effect of the removal process of the sacrificial layer 20 on the channel layer 30 can be effectively reduced, thereby improving the quality of the channel layer 30, which is beneficial to improving the device performance. In other embodiments, when forming a PMOS transistor, in order to improve the performance of the PMOS transistor, SiGe channel technology can be used, the material of the channel layer is SiGe, and the material of the sacrificial layer is Si. In some other embodiments, the material of the channel layer can also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium.

[0074] In this embodiment, in the initial stacked structure 115, the number of the channel stacks 210 is multiple. As an example, the number of the channel stacks 210 is three. In other embodiments, the number of the channel stacks 210 can also be other numbers, such as one, two, four, etc.

[0075] In this embodiment, an isolation layer 110 surrounding the protrusion 105 is further formed on the substrate 100 .

[0076] The isolation layer 110 is used to isolate adjacent protrusions 105, and is also used to isolate the substrate 100 from a gate structure formed subsequently. In this embodiment, the material of the isolation layer 110 is silicon oxide. The isolation layer 110 can also be other insulating materials, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon germanium oxide.

[0077] In this embodiment, the top surface of the isolation layer 110 is lower than the top surface of the protrusion 105, that is, the isolation layer 110 also exposes part of the side wall of the protrusion 105. In other embodiments, the top surface of the isolation layer may also be flush with the top surface of the protrusion.

[0078] refer to Figure 4 , shows a partial three-dimensional schematic diagram, in which a plurality of dummy gate structures 120 spanning the initial stacked structure 115 are formed in the device unit region 100s.

[0079] Specifically, the dummy gate structure 120 is formed on the isolation layer 110 and crosses the initial stacked structure 115; the dummy gate structure 120 covers a portion of the top and a portion of the sidewall of the initial stacked structure 115. The dummy gate structure 120 extends along the Y direction, which is perpendicular to the X direction.

[0080] The dummy gate structure 120 is used to pre-occupy a space position for the subsequent formation of a gate structure.

[0081] The dummy gate structure 120 may be a stacked structure or a single-layer structure. In the present embodiment, the dummy gate structure 120 is a stacked structure, including a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) located on the dummy gate oxide layer. Specifically, the dummy gate structure 120 is a polysilicon gate structure, the material of the dummy gate oxide layer may be silicon oxide or silicon oxynitride, and the material of the dummy gate layer may be polysilicon.

[0082] In this embodiment, after forming the dummy gate structure 120 , the method for forming the semiconductor structure further includes: forming a gate spacer 130 on the sidewall of the dummy gate structure 120 .

[0083] The gate spacer 130 is used together with the dummy gate structure 120 as an etching mask for the subsequent etching process of forming grooves to define the formation position of the source and drain doping layers. The gate spacer 130 is also used to protect the sidewalls of the dummy gate structure 120 and the subsequent gate structure.

[0084] In this embodiment, the material of the gate spacer 130 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material, and the gate spacer 130 is a single-layer or stacked structure. As an example, the gate spacer 130 is a single-layer structure, and the material of the gate spacer 130 is silicon nitride.

[0085] refer to Figure 5 and Figure 6 , Figure 5 For a stereogram, Figure 6 for Figure 5 In the cross-sectional view along the xx direction, grooves 140 are formed in the initial stacked structure 115 on both sides of the dummy gate structure 120 , and the remaining initial stacked structure 115 is used as the stacked structure 200 .

[0086] The groove 140 is used to provide a space for forming a source-drain doped layer. The sidewall of the groove 140 exposes the stacked structure 200, so as to facilitate the subsequent etching of a portion of the thickness of the sacrificial layer 20 along the extension direction of the channel layer 30, and to facilitate the subsequent formation of a source-drain doped layer on the channel layer 30 exposed by the sidewall of the groove 140 through an epitaxial process.

[0087] In this embodiment, the groove 140 is formed in the initial stacked structure 115 and the protrusion 105 on both sides of the dummy gate structure 120. Specifically, the groove 140 is located in the initial stacked structure 115 on both sides of the dummy gate structure 120 and in the protrusion 105 exposed by the isolation layer 110.

[0088] In this embodiment, an anisotropic etching process (for example, an anisotropic dry etching process) is used to etch the initial stacked structure 115 on both sides of the pseudo gate structure 120 and the gate sidewall 130 and the partial thickness of the raised portion 105, which is beneficial to improving the cross-sectional morphology quality of the groove 140.

[0089] It should be noted that, in this embodiment, after forming the groove 140, the formation method further includes: etching a portion of the thickness of the sacrificial layer 20 along the extension direction of the channel layer 30 to form a groove (not shown), which is surrounded by the channel layer 30 and the protruding portion 105, and the remaining sacrificial layer 20, or is surrounded by the adjacent channel layer 30 and the remaining sacrificial layer 20; forming an inner spacer 150 in the groove.

[0090] The groove is used to provide a space for forming the inner wall.

[0091] In this embodiment, a steam etching process is used to etch the sacrificial layer 20 with a thickness of the side wall of the groove 140 along the extension direction of the channel layer 30. The steam etching process is an isotropic etching process, so that the sacrificial layer 20 can be etched along the lateral direction (i.e., the X direction or the extension direction of the channel layer 30), and the steam etching process is easy to achieve a large etching selectivity, which is conducive to reducing the difficulty of etching the sacrificial layer 20 and reducing the probability of damage to other film layer structures (for example: the channel layer 30).

[0092] In this embodiment, the material of the sacrificial layer 20 is SiGe, the material of the channel layer 30 is Si, and the sacrificial layer 20 on the sidewall of the groove 140 is steam-etched by HCl vapor. The etching rate of HCl vapor on SiGe material is much greater than the etching rate on Si material, which can effectively reduce the probability of damage to the channel layer 30.

[0093] In other embodiments, when the material of the channel layer is SiGe and the material of the sacrificial layer is Si, a dry etching process may be used to etch the sacrificial layer on the sidewall of the groove along the extension direction of the channel layer.

[0094] Subsequently, a source-drain doped layer is formed on the channel layer 30 on the side wall of the groove 140, and a gate structure is formed at the position of the pseudo-gate structure 120 and the sacrificial layer 20. The inner side wall 150 is used to achieve isolation between the source-drain doped layer and the gate structure, and also increases the distance between the gate structure and the source-drain doped layer, which is beneficial to reducing the parasitic capacitance between the gate structure and the source-drain doped layer.

[0095] In this embodiment, the material of the inner sidewall 150 is an insulating material to achieve isolation between the source-drain doping layer and the gate structure. In this embodiment, the material of the inner sidewall 150 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material. As an example, the material of the inner sidewall 150 is silicon nitride.

[0096] refer to Figure 7 A sub-doping layer 40 is formed on the channel layer 30 on the sidewall of the groove 140, and in the stacked structure 200, the sub-doping layers 40 on adjacent channel layers 30 are in contact with each other to form an initial transition doping layer 160. The initial transition doping layer 160 is used to form a transition doping layer after subsequent ion doping and etching processes.

[0097] In this embodiment, the initial transition doping layer 160 further includes a bottom doping layer 50 formed on the sidewall and bottom of the groove 140 and on the protruding portion 105 , and the bottom doping layer 50 is in contact with the sub-doping layer 40 .

[0098] In this embodiment, an epitaxial process is used to form a first stress layer on the channel layer 30 on the side wall of the groove 140, and a second stress layer is formed on the protruding portion 105 exposed by the groove 140, and in the process of forming the first stress layer and the second stress layer, ions are self-doped in situ, the first stress layer doped with ions is used as the sub-doping layer 40, and the second stress layer doped with ions is used as the bottom doping layer 50.

[0099] In this embodiment, when a PMOS transistor is formed, the first stress layer and the second stress layer are doped with P-type ions, and the materials of the first stress layer and the second stress layer include Si or SiGe; when an NMOS transistor is formed, the first stress layer and the second stress layer are doped with N-type ions, and the materials of the stress layers include Si or SiC.

[0100] In this embodiment, during the process of forming the sub-doping layer 40 , the sub-doping layers 40 on adjacent channel layers 30 in the stacked structure 200 are in contact with each other and cover the sidewalls of the inner spacer 150 .

[0101] In the process of forming the sub-doped layer 40, epitaxial growth is performed based on each channel layer 30 on the side wall of the groove 140. As the volume of the sub-doped layer 40 on each channel layer 30 continues to increase, the sub-doped layers 40 on the ends of adjacent channel layers 30 can gradually contact each other. Accordingly, in each of the stacked structures 200, after the sub-doped layers 40 on adjacent channel layers 30 contact each other, the side wall surface of the initial transitional doped layer 16 formed is usually not a flush or smooth surface, and the surface of the initial transitional doped layer 160 has depressions and protrusions.

[0102] refer to Figure 8 , ions are doped into a partial thickness material on the surface of the initial transition doping layer 160 , and the doped ions are suitable for reducing the etching resistance of the initial transition doping layer 160 .

[0103] The doped ions are suitable for reducing the etching resistance of the initial transition doped layer 160. During the process of doping ions, when the initial transition doped layer 160 has an uneven surface, ions are more easily doped and diffused to the protrusions on the surface of the initial transition doped layer 160 compared with the depressions on the surface of the initial transition doped layer 160, so that more doped ions can be distributed on the protrusions on the surface of the initial transition doped layer 160 than on the depressions; accordingly, during the process of removing the initial transition doped layer 160 doped with ions, compared with the depressions on the surface of the initial transition doped layer 160, since the protrusions on the surface of the initial transition doped layer 160 have more doped ions, the protrusions on the surface of the initial transition doped layer 160 are easier to remove and the removal rate is faster, so that after the initial transition doped layer 160 doped with ions is removed to form a transition doped layer, the transition doped layer is easy to obtain a smoother side wall surface.

[0104] In this embodiment, the ions doped in the partial thickness material on the surface of the initial transition doping layer 160 include any one or more of Si, C, Ga, B, As, Sb and P.

[0105] In this embodiment, doping ions in a partial thickness of the surface material of the initial transition doping layer 160 includes one or more ion implantation processes. The ion implantation process can easily accurately control the depth, position and doping concentration of ion doping by adjusting process parameters such as implantation angle, implantation energy and implantation dose.

[0106] It should be noted that, in this embodiment, the formation method further includes: after forming the initial transition doping layer 160 and before doping ions into a partial thickness material on the surface of the initial transition doping layer 160 , forming a masking layer 165 on the initial transition doping layer 160 .

[0107] The masking layer 165 is used as a masking layer for ion doping of the initial transition doping layer 160. Specifically, the masking layer 165 is used as a masking layer for ion implantation of the initial transition doping layer 160 to reduce the channel effect.

[0108] Specifically, the material of the masking layer 165 is an amorphous material. In this embodiment, the material of the masking layer 165 includes: one or more of SiO, SiN, SiON, SiC and SiOCN. As an example, the material of the masking layer 165 is silicon oxide.

[0109] It should be noted that the thickness of the masking layer 165 should not be too small or too large. If the thickness of the masking layer 165 is too small, it is easy to affect the masking effect of the masking layer 165 on ions or implantation; if the thickness of the masking layer 165 is too large, it is easy to affect the uniformity and depth of ion implantation, and it is also easy to cause the masking layer 165 on the initial transition doping layer 160 located on the opposite side walls of the groove 140 to contact each other, and it is also easy to increase the time and difficulty of subsequent removal of the masking layer 165. For this reason, in this embodiment, the thickness of the masking layer 165 is 1nm to 10nm.

[0110] refer to Fig. 9 In this embodiment, the formation method further includes: after doping ions into a partial thickness material on the surface of the initial transition doping layer 160 , heat treating 170 the initial transition doping layer 160 .

[0111] The transition doping layer 160 is subjected to a heat treatment 170 to repair ion implantation damage in the transition doping layer 160 and to increase the diffusion rate of ions doped in the partial thickness material on the surface of the transition doping layer 160 .

[0112] Among them, compared with the recessed parts on the surface of the initial transition doping layer 160, the protruding parts on the surface of the initial transition doping layer 160 are doped with more ions, and the ions are more easily diffused to the protruding parts on the surface of the initial transition doping layer 160, and the ion diffusion rate on the protruding parts on the surface of the initial transition doping layer 160 is faster. Therefore, after heat treatment 170, more doped ions can be distributed on the protruding parts on the surface of the initial transition doping layer 160 than on the recessed parts. Accordingly, in the subsequent process of removing the initial transition doping layer 160 doped with ions, it is beneficial to further improve the rate at which the protruding parts on the surface of the initial transition doping layer 160 are removed.

[0113] In this embodiment, an annealing process (eg, a rapid thermal annealing process) is used to perform the heat treatment.

[0114] refer to Fig.10 After ions are doped into a portion of the thickness of the surface material of the initial transition doping layer 160 , the masking layer 165 is removed. Specifically, after the heat treatment 170 is performed, the masking layer 165 is removed.

[0115] The masking layer 165 is removed to expose the surface of the initial transition doping layer 160 , so that the initial transition doping layer 160 doped with ions can be removed later.

[0116] In this embodiment, an isotropic etching process is used to remove the masking layer 165. The isotropic etching process includes one or both of a wet etching process and an isotropic dry etching process. As an example, a wet etching process is used to remove the masking layer 165. Specifically, the material of the masking layer 165 is silicon oxide, and a diluted hydrofluoric acid (DHF) solution is used to perform the wet etching process.

[0117] refer to Fig.11 , the initial transition doping layer 160 doped with ions is removed, and the remaining initial transition doping layer 160 is used as the transition doping layer 180 .

[0118] The protrusions on the surface of the initial transition doping layer 160 can be distributed with more doping ions than the depressions, and the doping ions are suitable for reducing the etching resistance of the initial transition doping layer 160; accordingly, in the process of removing the initial transition doping layer 160 doped with ions, compared with the depressions on the surface of the initial transition doping layer 160, since the protrusions on the surface of the initial transition doping layer 160 have more doping ions, the protrusions on the surface of the initial transition doping layer 160 are easier to remove and the removal rate is faster. Therefore, after the initial transition doping layer 160 doped with ions is removed to form the transition doping layer 180, the transition doping layer 180 can obtain a relatively smooth side wall surface, which is beneficial to provide a good interface state for the subsequent formation of the main doping layer on the side wall of the transition doping layer 180, which is beneficial to improve the formation quality of the main doping layer and reduce the interface defects between the main doping layer and the transition doping layer 180, thereby improving the performance of the semiconductor structure.

[0119] In this embodiment, an isotropic etching process is used to remove the initial transition doped layer 160 doped with ions. The isotropic etching process includes one or both of a wet etching process and an isotropic dry etching process. As an example, a wet etching process is used to remove the initial transition doped layer 160 doped with ions. The wet etching process is an isotropic etching process, and is easy to achieve a high etching selectivity, and the process operation is simple and the cost is low.

[0120] In this embodiment, after removing the initial transition doping layer 160 doped with ions, the side walls of each sub-doping layer 40 in the formed transition doping layer 180 are flush, which is beneficial to further improve the smoothness of the side walls of the transition doping layer 180 and further provide a good interface state for forming the main doping layer.

[0121] refer to Fig.12A main doping layer 230 is formed between the transition doping layers 180 on opposite side walls of the groove 140 , the ion doping concentration of the main doping layer 230 is greater than the ion doping concentration of the transition doping layer 180 , and the main doping layer 230 is used to form a source-drain doping layer 250 with the transition doping layer 180 .

[0122] The source-drain doped layer 250 is used as a source or a drain of a field effect transistor.

[0123] In this embodiment, the side wall surface of the transition doping layer 180 is highly smooth, thereby providing a good interface state for forming the main doping layer 230 on the side wall of the transition doping layer 180, which is beneficial to improving the formation quality of the main doping layer 230 and reducing the interface defects between the main doping layer 230 and the transition doping layer 180, thereby improving the performance of the semiconductor structure.

[0124] The main doping layer 230 is used as the main source of stress for the source-drain doping layer 250. Also, the main doping layer 230 is used as the main source of carriers provided by the source-drain doping layer 250, so the ion doping concentration of the main doping layer 230 is relatively high.

[0125] In this embodiment, an epitaxial process is adopted to form the third stress layer, and ions are self-doped in situ during the process of forming the third stress layer. The ion-doped third stress layer is used as the main doping layer 230 .

[0126] When forming an NMOS transistor, the material of the main doping layer 230 includes a third stress layer doped with N-type ions, and the material of the third stress layer is Si or SiC, thereby providing tensile stress for the channel region of the NMOS transistor, which is beneficial to improving the carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions or Sb ions.

[0127] When forming a PMOS transistor, the material of the main doping layer 230 includes a third stress layer doped with P-type ions, and the material of the third stress layer is Si or SiGe, thereby providing compressive stress for the channel region of the PMOS transistor, which is beneficial to improving the carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions or In ions.

[0128] In this embodiment, the formation method also includes: after forming the main doping layer 230, forming a cap doping layer 240 on the top of the main doping layer 230, the ion doping concentration of the cap doping layer 240 is lower than the ion doping concentration of the main doping layer 230, and the cap doping layer 240, the main doping layer 230 and the transition doping layer 180 constitute the source and drain doping layer 250.

[0129] The ion doping concentration of the cap doping layer 240 is lower than that of the main doping layer 230, and is used to reduce the out-diffusion of the doped ions in the main doping layer 230 during the subsequent heat treatment. In addition, the cap doping layer 240 is also used to contact the subsequent source and drain plugs and serve as a buffer layer when forming the source and drain plugs.

[0130] In this embodiment, the cap doping layer 240 includes a fourth stress layer doped with ions, the material of the fourth stress layer is the same as the material of the third stress layer, and the ion doping type in the cap doping layer 240 is the same as the ion doping type of the main doping layer 230 .

[0131] For a detailed description of the process steps for forming the cap doping layer 240 , please refer to the detailed description of forming the main doping layer 230 , which will not be repeated here.

[0132] Combined with reference Fig.13 The formation method further includes: after forming the source-drain doping layer 250, removing the dummy gate structure 120 to form a gate opening (not shown) to expose the stacked structure 200; removing the sacrificial layer 20 in the stacked structure 200 to form a through groove (not shown), the through groove is surrounded by the channel layer 30 and the protrusion 105, or, is surrounded by the adjacent channel layer 30; filling the gate structure 260 in the through groove and the gate opening.

[0133] The gate opening is used to provide a space for forming a gate structure. The gate opening exposes the channel stack 210 so that the sacrificial layer 20 can be removed through the gate opening. The through groove and the gate opening together provide a space for forming a gate structure. The through groove is connected to the gate opening.

[0134] The sacrificial layer 20 is removed after the source-drain doping layer 250 is formed. Therefore, after the sacrificial layer 20 is removed, both ends of the channel layer 30 are connected to the source-drain doping layer 250 in the lateral direction (i.e., the extension direction of the channel layer 30), and are suspended in the gate opening so that the gate structure can surround the channel layer 30. In this embodiment, after the sacrificial layer 20 is removed, one or more spaced channel layers 30 are used to form a channel structure layer 300.

[0135] In this embodiment, a steam etching process is used to remove the sacrificial layer 20. Specifically, the material of the channel layer 30 is Si, the material of the sacrificial layer 20 is SiGe, and the sacrificial layer 20 is removed by HCl vapor.

[0136] When the device is working, the gate structure 220 is used to control the opening and closing of the conductive channel. In this embodiment, the gate structure 220 is a metal gate structure. In this embodiment, the gate structure 220 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0137] The gate dielectric layer is used to achieve electrical isolation between the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3.

[0138] In a specific implementation, the gate electrode layer may include a work function layer (not shown) and an electrode layer located on the work function layer, and the work function layer is used to adjust the work function of the gate structure 220, thereby adjusting the threshold voltage of the field effect transistor. The material of the gate electrode layer includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni.

[0139] It should be noted that after forming the source-drain doped layer 250 and before removing the dummy gate structure 120 to form a gate opening, the formation method generally further includes: forming an interlayer dielectric layer (not shown) on the isolation layer 110 to cover the source-drain doped layer 250 and the sidewalls of the gate spacer 130, and the interlayer dielectric layer exposes the top surface of the dummy gate structure 120. The interlayer dielectric layer is used to isolate adjacent devices. The material of the interlayer dielectric layer can be an insulating material such as silicon oxide, silicon oxynitride, etc.

[0140] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate including a plurality of discrete device unit regions; The base comprises a substrate and a plurality of protrusions protruding from the substrate of the device unit area; an isolation layer, located on the substrate and surrounding the protrusion; A channel structure layer, located above the protrusion and spaced apart from the protrusion, the channel structure layer comprising one or more channel layers spaced apart from each other in sequence; A plurality of gate structures are located on the isolation layer of the device unit region, and the gate structures span the channel structure layer and surround the channel layer; Source-drain doping layers are located on the raised portions on both sides of the gate structure and are in contact with the end portions of the channel structure layer along the extension direction; the source-drain doping layers include: a transition doping layer, including a sub-doping layer located on an adjacent channel layer in the channel structure layer, and the sub-doping layers on the adjacent channel layers are in contact, and the sidewalls of the transition doping layers are smooth sidewalls; a main doping layer is located between the transition doping layers on the ends of the adjacent channel structure layers along the extension direction and is in contact with the transition doping layers, and the ion doping concentration of the main doping layer is higher than the ion doping concentration of the transition doping layer.

2. The semiconductor structure according to claim 1, wherein: The portion of the gate structure located between adjacent channel layers or between the channel layer and the protrusion is taken as the first portion, and the portion of the gate structure spanning across the channel structure layer is taken as the second portion; Along the extension direction of the channel layer, the sidewall of the first portion is retracted relative to the sidewall of the channel layer, and the sidewall of the second portion is retracted relative to the sidewall of the channel layer; The semiconductor structure further includes: an inner sidewall located between adjacent channel layers or between a channel layer and a protruding portion, and the inner sidewall covers a sidewall of the first portion; A gate spacer, located on the sidewall of the second portion and exposing an end portion of the channel structure layer in an extending direction; The transition doping layer covers the sidewalls of the inner sidewall.

3. The semiconductor structure according to claim 1, wherein: The transition doping layer is a U-shaped structure, and the transition doping layer further includes a bottom doping layer located on the protruding portion, and the bottom doping layer is in contact with the sub-doping layer.

4. The semiconductor structure according to claim 1, wherein: The source-drain doping layer further includes: a cap doping layer located on the top of the main doping layer, and the ion doping concentration of the cap doping layer is lower than the ion doping concentration of the main doping layer.

5. The semiconductor structure according to claim 1, wherein: When forming a PMOS transistor, the transition doping layer and the main doping layer include a stress layer doped with P-type ions, and the material of the stress layer includes Si or SiGe; when forming an NMOS transistor, the transition doping layer and the main doping layer include a stress layer doped with N-type ions, and the material of the stress layer includes Si or SiC.

6. The semiconductor structure according to claim 1, wherein: The materials of the substrate and the protrusions include: one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium; The material of the channel layer includes one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium.

7. The semiconductor structure according to claim 1, wherein: The gate structure comprises a gate dielectric layer and a gate electrode layer located on the gate dielectric layer; The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni.

8. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, including a plurality of discrete device unit regions, the substrate including a substrate and a plurality of protrusions protruding from the substrate of the device unit region; an initial stacked structure is formed on the protrusions, including a plurality of channel stacks stacked sequentially from bottom to top, each of the channel stacks including a sacrificial layer and a channel layer located on the sacrificial layer; forming a plurality of dummy gate structures across the initial stacked structure in the device unit region; forming grooves in the initial stacked structure on both sides of the dummy gate structure, and the remaining initial stacked structure is used as a stacked structure; forming a sub-doping layer on the channel layer on the sidewall of the groove, and in the stacked structure, the sub-doping layers on adjacent channel layers are in contact with each other to form an initial transition doping layer; doping ions in a partial thickness material on the surface of the initial transition doping layer, wherein the doping ions are suitable for reducing the etching resistance of the initial transition doping layer; removing the initial transition doping layer doped with ions, and using the remaining initial transition doping layer as a transition doping layer; A main doping layer is formed between the transition doping layers on opposite side walls of the groove, the ion doping concentration of the main doping layer is greater than the ion doping concentration of the transition doping layer, and the main doping layer is used to form a source-drain doping layer with the transition doping layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: Doping ions in a partial thickness material of the surface of the initial transition doping layer includes one or more ion implantation processes.

10. The method for forming a semiconductor structure according to claim 8 or 9, characterized in that: The method for forming a semiconductor structure further includes: after forming the initial transition doping layer and before doping ions into a partial thickness material on the surface of the initial transition doping layer, forming a masking layer on the initial transition doping layer; After doping ions into a partial thickness material of the surface of the initial transition doping layer and before removing the initial transition doping layer doped with ions, the masking layer is removed.

11. The method for forming a semiconductor structure according to claim 10, wherein: The material of the masking layer includes one or more of SiO, SiN, SiON, SiC and SiOCN.

12. The method for forming a semiconductor structure according to claim 10, wherein: The thickness of the masking layer is 1 nm to 10 nm.

13. The method for forming a semiconductor structure according to claim 8, wherein: The ions doped in the partial thickness material on the surface of the initial transition doping layer include any one or more of Si, C, Ga, B, As, Sb and P.

14. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming a semiconductor structure further includes: after doping ions into a partial thickness material on the surface of the initial transition doping layer, and before removing the initial transition doping layer doped with ions, heat treating the initial transition doping layer.

15. The method for forming a semiconductor structure according to claim 8, wherein: In the step of providing a substrate, an isolation layer surrounding the protrusion is also formed on the substrate; The dummy gate structure is formed on the isolation layer and spans across the initial stacked structure; In the step of forming the groove, the groove is formed in the initial stacked structure and the protruding portion on both sides of the dummy gate structure; In the step of forming the initial transition doping layer, the initial transition doping layer further includes a bottom doping layer formed on the sidewall and the bottom of the groove and on the protruding portion, and the bottom doping layer is in contact with the sub-doping layer.

16. The method for forming a semiconductor structure according to claim 8, wherein: The initial transition doping layer doped with ions is removed by an isotropic etching process.

17. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the semiconductor structure also includes: after forming the main doping layer, forming a cap doping layer on top of the main doping layer, the ion doping concentration of the cap doping layer is lower than the ion doping concentration of the main doping layer, and the cap doping layer, the main doping layer and the transition doping layer constitute the source and drain doping layer.

18. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming a semiconductor structure further comprises: after forming the dummy gate structure and before forming the groove, forming a gate spacer on a sidewall of the dummy gate structure; After forming the groove and before forming the sub-doping layer on the channel layer on the sidewall of the groove, etching a portion of the sacrificial layer along the extension direction of the channel layer to form a groove surrounded by the channel layer, the protruding portion, and the remaining sacrificial layer, or surrounded by the adjacent channel layer and the remaining sacrificial layer; forming an inner side wall in the groove; In the process of forming the sub-doping layers, the sub-doping layers on adjacent channel layers in the stacked structure are in contact with each other and cover the sidewalls of the inner spacer.

19. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the semiconductor structure also includes: after forming the source-drain doping layer, removing the dummy gate structure to form a gate opening to expose the stacked structure; removing the sacrificial layer in the stacked structure to form a through groove, wherein the through groove is surrounded by the channel layer and the protruding portion, or is surrounded by an adjacent channel layer; and filling the gate structure in the through groove and the gate opening.

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