A low mismatch complementary charge pump for charge pump phase-locked loop

Abstract

The present invention relates to a low mismatch complementary charge pump used in a charge pump phase-locked loop, comprising two sets of complementary charge pump circuits CH1 and CH2, a DN current fast shutdown compensation circuit, an UP current fast shutdown compensation circuit, an output filter circuit and a dynamic current compensation circuit; the charge pump circuit CH1 is used to provide a current mirrored with the UP current to the output filter circuit; the charge pump circuit CH2 is used to provide a current mirrored with the DN current to the output filter circuit; the DN current fast shutdown compensation circuit is used to quickly shut down the DN current of the charge pump circuit CH1 and the charge pump circuit CH2; the UP current fast shutdown compensation circuit is used to quickly shut down the UP current of the charge pump circuit CH1 and the charge pump circuit CH2; the output filter circuit is used to filter out the output current burrs of the charge pump circuit CH1 and the charge pump circuit CH2; the dynamic current compensation circuit dynamically compensates the output current of the charge pump circuit CH1 and the charge pump circuit CH2 through negative feedback. The circuit is conducive to reducing the mismatch of the UP current and the DN current of the charge pump circuit.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to a low mismatch complementary charge pump used in a charge pump phase-locked loop. Background Art

[0002] In the phase-locked loop, the function of the charge pump is to linearly convert the voltage pulse signals UP and DN output by the PFD, whose pulse width is proportional to the phase error, into charge and discharge current pulses Iup and Idn. The basic principle diagram of a typical charge pump is shown in the figure below. Figure 1 However, due to non-ideal factors such as charge-discharge current mismatch, leakage current, clock feedthrough, charge injection, and charge sharing caused by switching, the actual charge pump circuit cannot fully achieve the performance of the ideal charge pump. The charge pump dynamic current mismatch curve is shown in Figure 2 In order to ensure the linearity of the phase-locked loop transmission characteristics, the transmission characteristics of the PFD and charge pump combination are usually required to be as linear as possible. Specifically for the charge pump, its charge and discharge currents Iup and Idn are required to be as equal as possible in static state, and the speed of establishment and shutdown should be as consistent as possible in dynamic state.

[0003] In order to reduce or eliminate the current mismatch of the charge pump, many technologies have been invented. Increasing the channel length of the current source tube can reduce the current mismatch caused by the channel length modulation effect, but this comes at the expense of area. Figure 3 This is a charge pump structure diagram of a common-source common-gate current mirror structure, but it eliminates current mismatch at the expense of reducing the output dynamic range. The wide operating range of the PLL requires a wide dynamic range of the charge pump.

[0004] Figure 4 The figure shows a charge pump structure using an error amplifier and its output current matching curve. The structure uses a unity gain op amp clamp to keep the input voltage consistent with the bias drain reference voltage, thereby significantly improving the dynamic current matching performance of the charge pump. In fact, the structure mainly adjusts one current to match another current, rather than flattening the current response over the entire range.

[0005] Figure 5The figure shows a dynamic negative feedback charge pump structure proposed by TH Lin et al. ([1] TH Lin et al., "Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-N PLLs," IEEE Trans.Circuits Syst.I, vol.56, no.25, pp.877–885, May 2009). This structure compensates for the influence of the channel length modulation effect by changing the resistance of the introduced parallel field effect transistor. However, its dynamic adjustment range is limited, and the current mismatch between Iup and Idn still exists. Its output current matching curve is shown in Figure 6 shown. Summary of the invention

[0006] The object of the present invention is to provide a low mismatch complementary charge pump used in a charge pump phase-locked loop, which circuit is beneficial to reducing the mismatch between the UP current and the DN current of the charge pump circuit.

[0007] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: a low mismatch complementary charge pump used in a charge pump phase-locked loop, including two sets of complementary charge pump circuits CH1 and CH2, a DN current fast shutdown compensation circuit, an UP current fast shutdown compensation circuit, an output filter circuit and a dynamic current compensation circuit; the charge pump circuit CH1 is connected to input signals UPP, UPN, DNP and DNN, the charge pump circuit CH2 is connected to input signals UPP, UPN, DNP and DNN, the input end of the charge pump circuit CH1 connected to the input signal UPP is connected to the input end of the charge pump circuit CH2 connected to the input signal UPP The input end of the charge pump circuit CH1 connected to the input end of the input signal DNN is connected to the input end of the charge pump circuit CH2 connected to the input signal DNN, the output end OUTP of the charge pump circuit CH1 is connected to the input end of the output filter circuit, and the output end OUTN of the charge pump circuit CH2 is connected to the input end of the output filter circuit; the output filter circuit is connected to the circuit output end VCON; the UP current fast shutdown compensation circuit is connected to the charge pump circuit CH1 and CH2; the DN current fast shutdown compensation circuit is connected to the charge pump circuit CH1 and CH2; the dynamic current compensation circuit is connected to the signal input ends of the charge pump circuits CH1 and CH2;

[0008] The charge pump circuit CH1 is used to provide a current mirrored with the UP current to the output filter circuit; the charge pump circuit CH2 is used to provide a current mirrored with the DN current to the output filter circuit; the DN current fast shutdown compensation circuit is used to quickly shut down the DN current of the charge pump circuit CH1 and the charge pump circuit CH2; the UP current fast shutdown compensation circuit is used to quickly shut down the UP current of the charge pump circuit CH1 and the charge pump circuit CH2; the output filter circuit is used to filter out the output current glitches of the charge pump circuit CH1 and the charge pump circuit CH2; the dynamic current compensation circuit dynamically compensates the output current of the charge pump circuit CH1 and the charge pump circuit CH2 through negative feedback.

[0009] Further, the charge pump circuit CH1 includes: a reference current source PBIAS, a rail-to-rail input operational amplifier A1, a capacitor C1, a capacitor C2, a capacitor C3, a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M6, a PMOS tube M21, an NMOS tube M7, an NMOS tube M16, an NMOS tube M17, an NMOS tube M18, and an NMOS tube M20; wherein one end of the reference current source PBIAS is respectively connected to the gate and drain of the PMOS tube M1, the gate of the PMOS tube M2, the gate of the PMOS tube M3, and one end of the capacitor C1; the reference current source PBIAS is respectively connected to the gate and drain of the PMOS tube M1, the gate of the PMOS tube M2, the gate of the PMOS tube M3, and one end of the capacitor C1; The other end of the current source PBIAS is respectively connected to the source of the NMOS tube M18, the source of the NMOS tube M19, the source of the NMOS tube M20, the drain of the PMOS tube M21, one end of the capacitor C2 and the external ground wire GND; the positive input end of the rail-to-rail input amplifier A1 is respectively connected to the drain of the PMOS tube M2, the drain of the NMOS tube M16 and one end of the capacitor C3, the negative input end of the rail-to-rail input amplifier A1 is respectively connected to the drain of the PMOS tube M3, the gate of the PMOS tube M5, the drain of the NMOS tube M17, the gate of the NMOS tube M19, the resistor R1 and the capacitor C7, the rail-to-rail input amplifier A1 The output end is connected to the gate of NMOS tube M16, the gate of NMOS tube M17, the other end of capacitor C2 and the other end of capacitor C3; the source of PMOS tube M1, the source of PMOS tube M4, the source of PMOS tube M5, the source of PMOS tube M6, the drain of NMOS tube M7, the other end of capacitor C1 and the external power supply VDD are connected; the source of PMOS tube M2 is connected to the drain of PMOS tube M4 and the drain of PMOS tube M5; the source of PMOS tube M3 is connected to the drain of PMOS tube M6, the drain of PMOS tube M11, the source of NMOS tube M7, the drain of NMOS tube M8, and the drain of NMOS tube M9. The source of the OS transistor M10 is connected to the node A; the gate of the PMOS transistor M4 is connected to the external ground line GND; the gate of the PMOS transistor M6 is connected to the input port UPN, the gate of the NMOS transistor M7 is connected to the gate of the NMOS transistor M10 is connected to the input port UPP; the source of the NMOS transistor M16 is connected to the drain of the NMOS transistor M18 and the drain of the NMOS transistor M19; the source of the NMOS transistor M17 is connected to the drain of the NMOS transistor M20, the drain of the NMOS transistor M25, the source of the PMOS transistor M21, the source of the PMOS transistor M24, the drain of the PMOS transistor M22, and one end of the capacitor C8 are connected to the node B;

[0010] The charge pump circuit CH2 includes: a reference current source NBIAS, a rail-to-rail input operational amplifier A2, a capacitor C4, a capacitor C5, a capacitor C6, a PMOS tube M11, a PMOS tube M12, a PMOS tube M14, a PMOS tube M15, a PMOS tube M24, an NMOS tube M10, an NMOS tube M25, an NMOS tube M27, an NMOS tube M28, an NMOS tube M29, and an NMOS tube M30; wherein one end of the reference current source NBIAS is respectively connected to the gate of the NMOS tube M28, the gate of the NMOS tube M29, the gate and the drain of the NMOS tube M30, and one end of the capacitor C5; the other end of the reference current source NBIAS is respectively connected to the NMOS The drain of the PMOS tube M10, the source of the PMOS tube M11, the source of the PMOS tube M13, the source of the PMOS tube M14, one end of the capacitor C4 and the external power supply VDD are connected; the positive input end of the rail-to-rail input amplifier A2 is respectively connected to the drain of the PMOS tube M15, the drain of the NMOS tube M29, and one end of the capacitor C6, the negative input end of the rail-to-rail input amplifier A2 is respectively connected to the drain of the PMOS tube M12, the gate of the PMOS tube M13, the drain of the NMOS tube M28, the gate of the NMOS tube M26, and one end of the resistor R2, the output end of the rail-to-rail input amplifier A2 is respectively connected to the gate of the PMOS tube M12, the gate of the PMOS tube M15, the other end of the capacitor C4, the The other end of C6 is connected; the gate of PMOS tube M11 is connected to the gate of PMOS tube M6, the input end of delay1, and the input port UPN; the drain of PMOS tube M11 is connected to the source of PMOS tube M3, the drain of PMOS tube M6, the source of PMOS tube M12, the source of NMOS tube M7, the drain of NMOS tube M8, and the source of NMOS tube M10 at node A; the gate of PMOS tube M14 is connected to the external ground line GND; the drain of PMOS tube M14 is connected to the drain of PMOS tube M13; the source of PMOS tube M24 is connected to the source of PMOS tube M21, the drain of PMOS tube M22, the source of NMOS tube M17, and the source of NMOS tube M10; The drain of the MOS tube M20, the drain of the NMOS tube M25, the source of the NMOS tube M28, and one end of the capacitor C8 are connected; the gate of the PMOS tube M24 is connected to the gate of the PMOS tube M21 and the input port DNN; the drain of the PMOS tube M24 is connected to the source of the NMOS tube M25, the source of the NMOS tube M26, the source of the NMOS tube M27, the source of the NMOS tube M30, the other end of the capacitor C5, and the external ground line GND; the gate of the NMOS tube M10 is connected to the gate of the NMOS tube M7 and the input port UPP; the gate of the NMOS tube M25 is connected to the gate of the NMOS tube M20, the input end of the delay delay2, and the input port DNP;The gate of the NMOS tube M27 is connected to the external power supply VDD, and the drain of the NMOS tube M27 is connected to the drain of the NMOS tube M26 and the source of the NMOS tube M29;

[0011] The DN current fast shutdown compensation circuit includes: a delay delay2, an inverter INV2, a capacitor C8, a PMOS tube M22, and a PMOS tube M23; wherein the input end of the delay delay2 is connected to the gate of the PMOS tube M22, the gate of the NMOS tube M20, the gate of the NMOS tube M25, and the input port DNP; the output end of the delay delay2 is connected to the input end of the inverter INV2, and the output end of the inverter INV2 is connected to the gate of the PMOS tube M23; one end of the capacitor C8 is connected to the drain of the PMOS tube M22, the source of the PMOS tube M21, the source of the PMOS tube M24, the drain of the NMOS tube M20, and the drain of the NMOS tube M25 at a node B, and the other end of the capacitor C8 is connected to an external ground line GND; the source of the PMOS tube M22 is connected to the drain of the PMOS tube M23, and the source of the PMOS tube M23 is connected to an external power supply VDD;

[0012] The UP current fast shutdown compensation circuit includes: a delay delay1, an inverter INV1, an NMOS tube M8, and an NMOS tube M9; wherein the input end of the delay delay1 is connected to the gate of the NMOS tube M8, the gate of the PMOS tube M6, the gate of the PMOS tube M11, and the input port UPN; the output end of the delay delay1 is connected to the input end of the inverter INV1, and the output end of the inverter INV is connected to the gate of the NMOS tube M9; the source of the NMOS tube M9 is connected to the external ground line GND, and the drain of the NMOS tube M9 is connected to the source of the NMOS tube M8; the drain of the NMOS tube M8 is connected to the source of the PMOS tube M3, the drain of the PMOS tube M6, the drain of the PMOS tube M11, the source of the NMOS tube M7, and the source of the NMOS tube M10;

[0013] The output filter circuit includes: a resistor R1, a resistor R2, and a capacitor C7; wherein one end of the resistor R1 and one end of the capacitor C7 are connected to the OUTP node, one end of the resistor R2 and the other end of the capacitor C7 are connected to the OUTN node, and the other end of the resistor R1 is connected to the other end of the resistor R2 and leads to the output terminal VCON;

[0014] The dynamic current compensation circuit includes: a PMOS tube M5, a PMOS tube M13, an NMOS tube M19, and an NMOS tube M26; wherein the gate of the PMOS tube M5 and the gate of the NMOS tube M19 are connected to the OUTP node, the source of the PMOS tube M5 is connected to the source of the PMOS tube M4 and the external power supply VDD, the drain of the PMOS tube M5 is connected to the source of the PMOS tube M2 and the drain of the PMOS tube M4; the source of the NMOS tube M19 is connected to the source of the NMOS tube M18 and the external ground line GND, the drain of the PMOS tube M19 is connected to the NMOS tube M4. The source of the S tube M16 is connected to the drain of the NMOS tube M18; the gate of the PMOS tube M13 and the gate of the NMOS tube M26 are connected to the OUTN node, the source of the PMOS tube M13 is connected to the source of the PMOS tube M14 and the external power supply VDD, the drain of the PMOS tube M13 is connected to the drain of the PMOS tube M14 and the source of the PMOS tube M15; the source of the NMOS tube M26 is connected to the source of the NMOS tube M27 and the external ground line GND, and the drain of the NMOS tube M26 is connected to the drain of the NMOS tube M27 and the source of the NMOS tube M29.

[0015] Furthermore, the PMOS tube M1, PMOS tube M2, and PMOS tube M3 in the charge pump circuit CH1 form a current mirror, and the PMOS tube M1, PMOS tube M2, and PMOS tube M3 have the same width-to-length ratio. The rail-to-rail input operational amplifier A1 uses negative feedback to make the drain bias reference potentials of the PMOS tube M2, PMOS tube M3, NMOS tube M16, and NMOS tube M17 equal, thereby ensuring that the charging current of the charge pump circuit CH1, that is, the leakage current Iup1 of the PMOS tube M3, and the discharging current, that is, the leakage current Idn1 of the NMOS tube M17, accurately track the leakage current I2 of the PMOS tube M2 and the leakage current I16 of the NMOS tube M16. Since I2 is always equal to I16, Iup1=Idn1, thereby achieving accurate replication of the charging and discharging currents of the charge pump circuit CH1.

[0016] Furthermore, in the charge pump circuit CH2, the NMOS tubes M28, M9 and M30 form a current mirror, and the NMOS tubes M28, M9 and M30 have the same width-to-length ratio. The rail-to-rail input operational amplifier A2 uses negative feedback to make the drain bias reference potentials of the NMOS tubes M28, M29, M12 and M15 equal, thereby ensuring that the charging current of the charge pump circuit CH2, i.e., the leakage current Iup2 of the PMOS tube M12, and the discharging current, i.e., the leakage current Idn2 of the NMOS tube M28, accurately track the leakage current I15 of the PMOS tube M15 and the leakage current I29 of the NMOS tube M29. Since I15 is always equal to I29, Iup2=Idn2, thereby achieving accurate replication of the charging and discharging currents of the charge pump circuit CH2.

[0017] Furthermore, the signal of the input terminal UPN is opposite to the signal of the input terminal UPP, and the signal of the input terminal DNN is opposite to the signal of the input terminal DNP; in the DN current fast shutdown compensation circuit, the PMOS tube M22 is placed on the DN current discharge path node B to form a path with the PMOS tube M23 and the external power supply; the NMOS tube M23 is turned on for a delay time by delaying delay2 and the inverter INV2, and when the input signal DNP jumps to a valid low potential, the PMOS tube M22 and the PMOS tube M23 are turned on at the same time to raise the potential of the node B, and the DN current is quickly turned off, wherein the DN current IDN=Idn1+Idn2; after the DN current is completely turned off, the NMOS tube M9 is turned off when the delay time ends, and the NMOS tube M8 is turned off at the same time, thereby reducing the circuit leakage current and reducing the introduction of unnecessary noise; the capacitor C8 is used to compensate for the mismatch caused by the NMOS tube speed being faster than the PMOS tube speed.

[0018] Furthermore, in the UP current fast shutdown compensation circuit, the NMOS tube M8 is placed on the UP current discharge path node A to form a path with the NMOS tube M9 and the external ground line GND; the PMOS tube M9 is turned on for a delay time by delaying delay1 and the inverter INV1, and when the input signal UPN jumps to a valid high potential, the NMOS tubes M8 and M9 are turned on at the same time to pull down the potential of the node A, and quickly shut down the UP current, wherein the UP current IUP=Iup1+Iup2; after the UP current is completely shut down, the NMOS tube M9 is turned off when the delay time ends, and the NMOS tube M8 is turned off at the same time, thereby reducing the circuit leakage current and reducing the introduction of unnecessary noise.

[0019] Furthermore, in the dynamic current compensation circuit, the on-resistance of the NMOS tube M19, the NMOS tube M26, the PMOS tube M5 and the PMOS tube M13 will change with the change of the output voltage VCON, and the channel length modulation effect of the upper and lower current mirrors will be compensated by negative feedback; when the output voltage VCON rises, due to the channel length modulation effect of the transistor, the DN current rises with the increase of the output voltage VCON, the gate voltage of the NMOS tube M19 and the NMOS tube M26 rises, the on-resistance decreases, and the source voltage of the NMOS tube M16 and the NMOS tube M29 is pulled down; since the NMOS tube M16 and the NMOS tube M2 9 is a mirror image of the reference current source PBIAS and the reference current source NBIAS. In order to suppress the increase of the drain current caused by the increase of the source voltage of the NMOS tube M16 and the NMOS tube M29, the gate voltage of the NMOS tube M16 and the NMOS tube M29 is reduced accordingly, thereby causing the mirror current of M17 and M28 to decrease, and the DN current decreases accordingly; the output voltage VCON decreases in the same way; however, since the on-resistance of the PMOS tube M4, the PMOS tube M14, the NMOS tube M18, and the NMOS tube M27 is small, the dynamic adjustment range is limited, so the dynamic current compensation circuit is used for the overall circuit to roughly adjust the mismatch suppression.

[0020] Furthermore, the rail-to-rail input operational amplifier is used to provide negative feedback compensation, mainly to adjust one current to match another current, rather than to flatten the current response in the entire range; the rail-to-rail input operational amplifier A1 in the feedback loop of the charge pump circuit CH1 actively controls the bias voltages of the NMOS tubes M16 and M17 so that Idn1 follows the output trend of Iup1 and decreases as the output voltage VCON increases; the rail-to-rail input operational amplifier A2 in the feedback loop of the charge pump circuit CH2 actively controls the bias voltages of the PMOS tubes M12 and M15 so that Iup2 follows the output trend of Idn2 and increases as the output voltage VCON increases; the output filter circuit couples the output of the charge pump circuit CH1 with the output of the charge pump circuit CH2, and finally flattens the output current characteristics by superimposing the characteristics of the two opposite output current inclinations.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] 1. The present invention designs two sets of complementary charge pump circuits with different biases. Each charge pump circuit uses a rail-to-rail input operational amplifier to adjust one current to match another current, thereby reducing the mismatch between the UP current and the DN current of the charge pump circuit. At the same time, by superimposing the characteristics of two opposite output current tilts, the shortcomings of the single operational amplifier structure that the charging current and the discharge current change with the output voltage are overcome, and the linearity of the charge pump circuit is improved; and a dynamic current compensation circuit is designed to broaden the output voltage range under a certain current matching accuracy.

[0023] 2. The present invention uses a transmission gate with a complementary structure as the switch of the charge pump, which effectively avoids the mismatch caused by the inherent mismatch between different types of switch tubes. At the same time, the fast shutdown circuit used only works for a period of time when the switch is not completely turned off, reducing the circuit leakage current and avoiding the circuit mismatch caused by unnecessary noise introduction. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is the basic schematic diagram of a typical charge pump;

[0025] Figure 2 is a charge pump dynamic current mismatch curve for a typical charge pump;

[0026] Figure 3 It is a charge pump structure diagram of a common source and common gate current mirror structure;

[0027] Figure 4 It is a charge pump structure using an error amplifier and its charge / discharge current matching curve diagram;

[0028] Figure 5 It is a dynamic negative feedback charge pump structure diagram;

[0029] Figure 6 yes Figure 5 The charge / discharge current matching curve diagram of the dynamic negative feedback charge pump shown;

[0030] Figure 7 is a circuit schematic diagram of a low mismatch complementary charge pump according to an embodiment of the present invention;

[0031] Figure 8 It is a charge / discharge current matching simulation characteristic curve diagram of the low mismatch complementary charge pump according to the embodiment of the present invention. DETAILED DESCRIPTION

[0032] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0033] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0034] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0035] like Figure 7-8 As shown, this embodiment provides a low mismatch complementary charge pump for use in a charge pump phase-locked loop, including two sets of complementary charge pump circuits CH1 and CH2, a DN current fast shutdown compensation circuit 3, an UP current fast shutdown compensation circuit 4, an output filter circuit 5, and a dynamic current compensation circuit 6. The charge pump circuit CH1 is connected to input signals UPP, UPN, DNP, and DNN, and the charge pump circuit CH2 is connected to input signals UPP, UPN, DNP, and DNN. The input end of the charge pump circuit CH1 connected to the input signal UPP is connected to the input end of the charge pump circuit CH2 connected to the input signal UPP, and the input end of the charge pump circuit CH1 connected to the input signal DNN is connected to the input end of the charge pump circuit CH2 connected to the input signal DNN. The output end OUTP of the charge pump circuit CH1 is connected to the input end of the output filter circuit 5, and the output end OUTN of the charge pump circuit CH2 is connected to the input end of the output filter circuit 5. The output filter circuit 5 is connected to the circuit output end VCON. The UP current fast shutdown compensation circuit 4 is connected to the charge pump circuits CH1 and CH2. The DN current fast shutdown compensation circuit 3 is connected to the charge pump circuits CH1 and CH2. The dynamic current compensation circuit 6 is connected to the signal input terminals of the charge pump circuits CH1 and CH2.

[0036] The charge pump circuit CH1 is used to provide a current mirrored with the UP current to the output filter circuit 5. The charge pump circuit CH2 is used to provide a current mirrored with the DN current to the output filter circuit 5. The DN current fast shutdown compensation circuit 3 is used to quickly shut down the DN current of the charge pump circuit CH1 and the charge pump circuit CH2. The UP current fast shutdown compensation circuit 4 is used to quickly shut down the UP current of the charge pump circuit CH1 and the charge pump circuit CH2. The output filter circuit 5 is used to filter out the output current glitches of the charge pump circuit CH1 and the charge pump circuit CH2. The dynamic current compensation circuit 6 dynamically compensates the output current of the charge pump circuit CH1 and the charge pump circuit CH2 through negative feedback.

[0037] Specifically, the charge pump circuit CH1 includes: a reference current source PBIAS, a rail-to-rail input amplifier A1, a capacitor C1, a capacitor C2, a capacitor C3, a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M6, a PMOS tube M21, an NMOS tube M7, an NMOS tube M16, an NMOS tube M17, an NMOS tube M18, and an NMOS tube M20. Among them, one end of the reference current source PBIAS is respectively connected to the gate and drain of the PMOS tube M1, the gate of the PMOS tube M2, the gate of the PMOS tube M3, and one end of the capacitor C1. The other end of the reference current source PBIAS is respectively connected to the source of the NMOS tube M18, the source of the NMOS tube M19, the source of the NMOS tube M20, the drain of the PMOS tube M21, one end of the capacitor C2, and the external ground line GND. The positive input terminal of the rail-to-rail input amplifier A1 is respectively connected to the drain of the PMOS tube M2, the drain of the NMOS tube M16 and one end of the capacitor C3, the negative input terminal of the rail-to-rail input amplifier A1 is respectively connected to the drain of the PMOS tube M3, the gate of the PMOS tube M5, the drain of the NMOS tube M17, the gate of the NMOS tube M19, the resistor R1 and the capacitor C7, and the output terminal of the rail-to-rail input amplifier A1 is connected to the gate of the NMOS tube M16, the gate of the NMOS tube M17, the other end of the capacitor C2 and the other end of the capacitor C3. The source of the PMOS tube M1, the source of the PMOS tube M4, the source of the PMOS tube M5, the source of the PMOS tube M6, the drain of the NMOS tube M7, the other end of the capacitor C1 are connected to the external power supply VDD. The source of the PMOS tube M2 is connected to the drain of the PMOS tube M4 and the drain of the PMOS tube M5. The source of the PMOS tube M3 is connected to the drain of the PMOS tube M6, the drain of the PMOS tube M11, the source of the NMOS tube M7, the drain of the NMOS tube M8, and the source of the NMOS tube M10 at the node A. The gate of the PMOS tube M4 is connected to the external ground line GND. The gate of the PMOS tube M6 is connected to the input port UPN, the gate of the NMOS tube M7 is connected to the gate of the NMOS tube M10 is connected to the input port UPP. The source of the NMOS tube M16 is connected to the drain of the NMOS tube M18 and the drain of the NMOS tube M19. The source of the NMOS tube M17 is connected to the drain of the NMOS tube M20, the drain of the NMOS tube M25, the source of the PMOS tube M21, the source of the PMOS tube M24, the drain of the PMOS tube M22, and one end of the capacitor C8 at the node B.

[0038] The charge pump circuit CH2 includes: a reference current source NBIAS, a rail-to-rail input amplifier A2, a capacitor C4, a capacitor C5, a capacitor C6, a PMOS tube M11, a PMOS tube M12, a PMOS tube M14, a PMOS tube M15, a PMOS tube M24, an NMOS tube M10, an NMOS tube M25, an NMOS tube M27, an NMOS tube M28, an NMOS tube M29, and an NMOS tube M30. Among them, one end of the reference current source NBIAS is respectively connected to the gate of the NMOS tube M28, the gate of the NMOS tube M29, the gate and the drain of the NMOS tube M30, and one end of the capacitor C5. The other end of the reference current source NBIAS is respectively connected to the drain of the NMOS tube M10, the source of the PMOS tube M11, the source of the PMOS tube M13, the source of the PMOS tube M14, one end of the capacitor C4, and the external power supply VDD. The positive input terminal of the rail-to-rail input amplifier A2 is respectively connected to the drain of the PMOS tube M15, the drain of the NMOS tube M29, and one end of the capacitor C6. The negative input terminal of the rail-to-rail input amplifier A2 is respectively connected to the drain of the PMOS tube M12, the gate of the PMOS tube M13, the drain of the NMOS tube M28, the gate of the NMOS tube M26, and one end of the resistor R2. The output terminal of the rail-to-rail input amplifier A2 is connected to the gate of the PMOS tube M12, the gate of the PMOS tube M15, the other end of the capacitor C4, and the other end of the capacitor C6. The gate of the PMOS tube M11 is connected to the gate of the PMOS tube M6, the input end of the delay delay1, and the input port UPN. The drain of the PMOS tube M11 is connected to the source of the PMOS tube M3, the drain of the PMOS tube M6, the source of the PMOS tube M12, the source of the NMOS tube M7, the drain of the NMOS tube M8, and the source of the NMOS tube M10 at the node A. The gate of the PMOS tube M14 is connected to the external ground line GND. The drain of the PMOS tube M14 is connected to the drain of the PMOS tube M13. The source of the PMOS tube M24 is connected to the source of the PMOS tube M21, the drain of the PMOS tube M22, the source of the NMOS tube M17, the drain of the NMOS tube M20, the drain of the NMOS tube M25, the source of the NMOS tube M28, and one end of the capacitor C8. The gate of the PMOS tube M24 is connected to the gate of the PMOS tube M21 and the input port DNN. The drain of the PMOS tube M24 is connected to the source of the NMOS tube M25, the source of the NMOS tube M26, the source of the NMOS tube M27, the source of the NMOS tube M30, the other end of the capacitor C5, and the external ground line GND. The gate of the NMOS tube M10 is connected to the gate of the NMOS tube M7 and the input port UPP. The gate of the NMOS transistor M25 is connected to the gate of the NMOS transistor M20, the input end of the delay 2, and the input port DNP.The gate of the NMOS tube M27 is connected to the external power supply VDD, and the drain of the NMOS tube M27 is connected to the drain of the NMOS tube M26 and the source of the NMOS tube M29.

[0039] The DN current fast shutdown compensation circuit 3 includes: delay delay2, inverter INV2, capacitor C8, PMOS tube M22, and PMOS tube M23. Among them, the input end of delay delay2 is connected to the gate of PMOS tube M22, the gate of NMOS tube M20, the gate of NMOS tube M25, and the input port DNP. The output end of delay delay2 is connected to the input end of inverter INV2, and the output end of inverter INV2 is connected to the gate of PMOS tube M23. One end of capacitor C8 is connected to the drain of PMOS tube M22, the source of PMOS tube M21, the source of PMOS tube M24, the drain of NMOS tube M20, and the drain of NMOS tube M25 at node B, and the other end of capacitor C8 is connected to the external ground line GND. The source of PMOS tube M22 is connected to the drain of PMOS tube M23, and the source of PMOS tube M23 is connected to the external power supply VDD.

[0040] The UP current fast shutdown compensation circuit 4 includes: delay delay1, inverter INV1, NMOS tube M8, and NMOS tube M9. Among them, the input end of delay delay1 is connected to the gate of NMOS tube M8, the gate of PMOS tube M6, the gate of PMOS tube M11, and the input port UPN. The output end of delay delay1 is connected to the input end of inverter INV1, and the output end of inverter INV is connected to the gate of NMOS tube M9. The source of NMOS tube M9 is connected to the external ground line GND, and the drain of NMOS tube M9 is connected to the source of NMOS tube M8. The drain of NMOS tube M8 is connected to the source of PMOS tube M3, the drain of PMOS tube M6, the drain of PMOS tube M11, the source of NMOS tube M7, and the source of NMOS tube M10.

[0041] The output filter circuit 5 includes: a resistor R1, a resistor R2, and a capacitor C7. One end of the resistor R1 and one end of the capacitor C7 are connected to the OUTP node, one end of the resistor R2 and the other end of the capacitor C7 are connected to the OUTN node, and the other end of the resistor R1 is connected to the other end of the resistor R2 and leads to the output terminal VCON.

[0042] The dynamic current compensation circuit 6 includes: a PMOS tube M5, a PMOS tube M13, an NMOS tube M19, and an NMOS tube M26. Among them, the gate of the PMOS tube M5 and the gate of the NMOS tube M19 are connected to the OUTP node, the source of the PMOS tube M5 is connected to the source of the PMOS tube M4 and the external power supply VDD, and the drain of the PMOS tube M5 is connected to the source of the PMOS tube M2 and the drain of the PMOS tube M4. The source of the NMOS tube M19 is connected to the source of the NMOS tube M18 and the external ground line GND, and the drain of the PMOS tube M19 is connected to the source of the NMOS tube M16 and the drain of the NMOS tube M18. The gate of the PMOS tube M13 and the gate of the NMOS tube M26 are connected to the OUTN node, the source of the PMOS tube M13 is connected to the source of the PMOS tube M14 and the external power supply VDD, the drain of the PMOS tube M13 is connected to the drain of the PMOS tube M14 and the source of the PMOS tube M15. The source of the NMOS tube M26 is connected to the source of the NMOS tube M27 and the external ground line GND, and the drain of the NMOS tube M26 is connected to the drain of the NMOS tube M27 and the source of the NMOS tube M29.

[0043] In the charge pump circuit CH1, the PMOS tubes M1, M2 and M3 form a current mirror, and the PMOS tubes M1, M2 and M3 have the same width-to-length ratio. The rail-to-rail input operational amplifier A1 uses negative feedback to make the drain bias reference potentials of the PMOS tubes M2, M3, NMOS tubes M16 and M17 equal, thereby ensuring that the charging current of the charge pump circuit CH1, i.e., the leakage current Iup1 of the PMOS tube M3, and the discharging current, i.e., the leakage current Idn1 of the NMOS tube M17, accurately track the leakage current I2 of the PMOS tube M2 and the leakage current I16 of the NMOS tube M16. Since I2 is always equal to I16, Iup1=Idn1, thereby achieving accurate replication of the charging and discharging currents of the charge pump circuit CH1.

[0044] In the charge pump circuit CH2, the NMOS tubes M28, M9 and M30 form a current mirror, and the NMOS tubes M28, M9 and M30 have the same width-to-length ratio. The rail-to-rail input operational amplifier A2 uses negative feedback to make the drain bias reference potentials of the NMOS tubes M28, M29, PMOS tubes M12 and M15 equal, thereby ensuring that the charging current of the charge pump circuit CH2, i.e., the leakage current Iup2 of the PMOS tube M12, and the discharging current, i.e., the leakage current Idn2 of the NMOS tube M28, accurately track the leakage current I15 of the PMOS tube M15 and the leakage current I29 of the NMOS tube M29. Since I15 is always equal to I29, Iup2=Idn2, thereby achieving accurate replication of the charging and discharging currents of the charge pump circuit CH2.

[0045] The signal at the input terminal UPN is opposite to the signal at the input terminal UPP, and the signal at the input terminal DNN is opposite to the signal at the input terminal DNP. In the DN current fast shutdown compensation circuit 3, the PMOS tube M22 is placed on the DN current discharge path node B to form a path with the PMOS tube M23 and an external power supply. The NMOS tube M23 is turned on for a delay time by delaying delay2 and the inverter INV2. When the input signal DNP jumps to a valid low potential, the PMOS tube M22 and the PMOS tube M23 are turned on at the same time to raise the potential of the node B, and the DN current is quickly turned off, wherein the DN current IDN=Idn1+Idn2. After the DN current is completely turned off, wait until the delay time ends, the NMOS tube M9 is turned off, and the NMOS tube M8 is turned off at the same time, thereby reducing the circuit leakage current and reducing the introduction of unnecessary noise. Capacitor C8 is used to compensate for the mismatch caused by the NMOS tube speed being faster than the PMOS tube speed.

[0046] In the UP current fast shutdown compensation circuit 4, the NMOS tube M8 is placed on the UP current discharge path node A and forms a path with the NMOS tube M9 and the external ground line GND. The PMOS tube M9 is turned on for a delay time by delay1 and the inverter INV1. When the input signal UPN jumps to a valid high potential, the NMOS tubes M8 and M9 are turned on at the same time to pull down the potential of the node A, and quickly turn off the UP current, wherein the UP current IUP=Iup1+Iup2. After the UP current is completely turned off, the NMOS tube M9 is turned off when the delay time is over, and the NMOS tube M8 is turned off at the same time, thereby reducing the circuit leakage current and reducing the introduction of unnecessary noise.

[0047] In the dynamic current compensation circuit 6, the on-resistance of the NMOS tube M19, the NMOS tube M26, the PMOS tube M5 and the PMOS tube M13 will change with the change of the output voltage VCON, and the channel length modulation effect of the upper and lower current mirrors will be compensated by the negative feedback. When the output voltage VCON rises, due to the channel length modulation effect of the transistor, the DN current rises with the increase of the output voltage VCON, the gate voltage of the NMOS tube M19 and the NMOS tube M26 rises, the on-resistance decreases, and the source voltage of the NMOS tube M16 and the NMOS tube M29 is pulled down. Since the NMOS tube M16 and the NMOS tube M29 are mirrored by the reference current source PBIAS and the reference current source NBIAS, in order to suppress the increase of the drain current caused by the increase of the source voltage of the NMOS tube M16 and the NMOS tube M29, the gate voltage of the NMOS tube M16 and the NMOS tube M29 is reduced accordingly, thereby causing the mirror current of M17 and M28 to decrease, and the DN current is reduced accordingly. The same is true for the decrease of the output voltage VCON. However, since the on-resistance of the PMOS tube M4 , the PMOS tube M14 , the NMOS tube M18 , and the NMOS tube M27 is relatively small, the dynamic adjustment range is limited, so the dynamic current compensation circuit 6 is used for coarse adjustment of the overall circuit to suppress mismatch.

[0048] Rail-to-rail input op amps are used to provide negative feedback compensation, mainly to adjust one current to match another current, rather than to flatten the current response over the entire range. The rail-to-rail input op amp A1 in the feedback loop of the charge pump circuit CH1 actively controls the bias voltages of the NMOS tubes M16 and M17 so that Idn1 follows the output trend of Iup1 and decreases as the output voltage VCON rises. The rail-to-rail input op amp A2 in the feedback loop of the charge pump circuit CH2 actively controls the bias voltages of the PMOS tubes M12 and M15 so that Iup2 follows the output trend of Idn2 and increases as the output voltage VCON rises. Although the difference between the currents can be significantly reduced, the change of the current with the output voltage VCON still exists. The output filter circuit 5 couples the output of the charge pump circuit CH1 with the output of the charge pump circuit CH2, and finally flattens the output current characteristics by superimposing the characteristics of the two opposite output current inclinations.

[0049] The above is only a preferred embodiment of the present invention, and does not limit the present invention in other forms. Any technician familiar with the profession may use the above disclosed technical content to change or modify it into an equivalent embodiment with equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the technical solution of the present invention still belongs to the protection scope of the technical solution of the present invention.

Claims

1. A low mismatch complementary charge pump for use in a charge pump phase-locked loop, characterized in that: The invention comprises two sets of complementary charge pump circuits CH1 and CH2, a DN current fast shutdown compensation circuit (3), an UP current fast shutdown compensation circuit (4), an output filter circuit (5) and a dynamic current compensation circuit (6); the charge pump circuit CH1 is connected to input signals UPP, UPN, DNP and DNN, the charge pump circuit CH2 is connected to input signals UPP, UPN, DNP and DNN, the input end of the charge pump circuit CH1 connected to the input signal UPP is connected to the input end of the charge pump circuit CH2 connected to the input signal UPP, and the charge pump circuit CH1 is connected to the input end of the input signal DNN. The input end is connected to the input end of the charge pump circuit CH2 connected to the input signal DNN, the output end OUTP of the charge pump circuit CH1 is connected to the input end of the output filter circuit (5), and the output end OUTN of the charge pump circuit CH2 is connected to the input end of the output filter circuit (5); the output filter circuit (5) is connected to the circuit output end VCON; the UP current fast shutdown compensation circuit (4) is connected to the charge pump circuits CH1 and CH2; the DN current fast shutdown compensation circuit (3) is connected to the charge pump circuits CH1 and CH2; the dynamic current compensation circuit (6) is connected to the signal input ends of the charge pump circuits CH1 and CH2; The charge pump circuit CH1 is used to provide a current mirrored with the UP current to the output filter circuit (5); the charge pump circuit CH2 is used to provide a current mirrored with the DN current to the output filter circuit (5); the DN current fast shutdown compensation circuit (3) is used to quickly shut down the DN current of the charge pump circuit CH1 and the charge pump circuit CH2; the UP current fast shutdown compensation circuit (4) is used to quickly shut down the UP current of the charge pump circuit CH1 and the charge pump circuit CH2; the output filter circuit (5) is used to filter out output current glitches of the charge pump circuit CH1 and the charge pump circuit CH2; The dynamic current compensation circuit (6) dynamically compensates the output currents of the charge pump circuit CH1 and the charge pump circuit CH2 through negative feedback; The charge pump circuit CH1 includes: a reference current source PBIAS, a rail-to-rail input operational amplifier A1, a capacitor C1, a capacitor C2, a capacitor C3, a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M6, a PMOS tube M21, an NMOS tube M7, an NMOS tube M16, an NMOS tube M17, an NMOS tube M18, and an NMOS tube M20; wherein one end of the reference current source PBIAS is respectively connected to the gate and drain of the PMOS tube M1, the gate of the PMOS tube M2, the gate of the PMOS tube M3, and one end of the capacitor C1; the reference current source The other end of PBIAS is respectively connected to the source of NMOS tube M18, the source of NMOS tube M19, the source of NMOS tube M20, the drain of PMOS tube M21, one end of capacitor C2 and the external ground wire GND; the positive input end of the rail-to-rail input amplifier A1 is respectively connected to the drain of PMOS tube M2, the drain of NMOS tube M16 and one end of capacitor C3, the negative input end of the rail-to-rail input amplifier A1 is respectively connected to the drain of PMOS tube M3, the gate of PMOS tube M5, the drain of NMOS tube M17, the gate of NMOS tube M19, resistor R1 and capacitor C7, the ... The output end is connected to the gate of NMOS tube M16, the gate of NMOS tube M17, the other end of capacitor C2 and the other end of capacitor C3; the source of PMOS tube M1, the source of PMOS tube M4, the source of PMOS tube M5, the source of PMOS tube M6, the drain of NMOS tube M7, the other end of capacitor C1 and the external power supply VDD are connected; the source of PMOS tube M2 is connected to the drain of PMOS tube M4 and the drain of PMOS tube M5; the source of PMOS tube M3 is connected to the drain of PMOS tube M6, the drain of PMOS tube M11, the source of NMOS tube M7, the drain of NMOS tube M8, NMOS The source of the S transistor M10 is connected to the node A; the gate of the PMOS transistor M4 is connected to the external ground line GND; the gate of the PMOS transistor M6 is connected to the input port UPN, the gate of the NMOS transistor M7 is connected to the gate of the NMOS transistor M10 is connected to the input port UPP; the source of the NMOS transistor M16 is connected to the drain of the NMOS transistor M18 and the drain of the NMOS transistor M19; the source of the NMOS transistor M17 is connected to the drain of the NMOS transistor M20, the drain of the NMOS transistor M25, the source of the PMOS transistor M21, the source of the PMOS transistor M24, the drain of the PMOS transistor M22, and one end of the capacitor C8 are connected to the node B; The charge pump circuit CH2 includes: a reference current source NBIAS, a rail-to-rail input operational amplifier A2, a capacitor C4, a capacitor C5, a capacitor C6, a PMOS tube M11, a PMOS tube M12, a PMOS tube M14, a PMOS tube M15, a PMOS tube M24, an NMOS tube M10, an NMOS tube M25, an NMOS tube M27, an NMOS tube M28, an NMOS tube M29, and an NMOS tube M30; wherein one end of the reference current source NBIAS is respectively connected to the gate of the NMOS tube M28, the gate of the NMOS tube M29, the gate and the drain of the NMOS tube M30, and one end of the capacitor C5; the other end of the reference current source NBIAS is respectively connected to the NMOS The drain of the PMOS tube M10, the source of the PMOS tube M11, the source of the PMOS tube M13, the source of the PMOS tube M14, one end of the capacitor C4 and the external power supply VDD are connected; the positive input end of the rail-to-rail input amplifier A2 is respectively connected to the drain of the PMOS tube M15, the drain of the NMOS tube M29, and one end of the capacitor C6, the negative input end of the rail-to-rail input amplifier A2 is respectively connected to the drain of the PMOS tube M12, the gate of the PMOS tube M13, the drain of the NMOS tube M28, the gate of the NMOS tube M26, and one end of the resistor R2, the output end of the rail-to-rail input amplifier A2 is respectively connected to the gate of the PMOS tube M12, the gate of the PMOS tube M15, the other end of the capacitor C4, the The other end of C6 is connected; the gate of PMOS tube M11 is connected to the gate of PMOS tube M6, the input end of delay1, and the input port UPN; the drain of PMOS tube M11 is connected to the source of PMOS tube M3, the drain of PMOS tube M6, the source of PMOS tube M12, the source of NMOS tube M7, the drain of NMOS tube M8, and the source of NMOS tube M10 at node A; the gate of PMOS tube M14 is connected to the external ground line GND; the drain of PMOS tube M14 is connected to the drain of PMOS tube M13; the source of PMOS tube M24 is connected to the source of PMOS tube M21, the drain of PMOS tube M22, the source of NMOS tube M17, and the source of NMOS tube M10; The drain of the MOS tube M20, the drain of the NMOS tube M25, the source of the NMOS tube M28, and one end of the capacitor C8 are connected; the gate of the PMOS tube M24 is connected to the gate of the PMOS tube M21 and the input port DNN; the drain of the PMOS tube M24 is connected to the source of the NMOS tube M25, the source of the NMOS tube M26, the source of the NMOS tube M27, the source of the NMOS tube M30, the other end of the capacitor C5, and the external ground line GND; the gate of the NMOS tube M10 is connected to the gate of the NMOS tube M7 and the input port UPP; the gate of the NMOS tube M25 is connected to the gate of the NMOS tube M20, the input end of the delay delay2, and the input port DNP;The gate of the NMOS tube M27 is connected to the external power supply VDD, and the drain of the NMOS tube M27 is connected to the drain of the NMOS tube M26 and the source of the NMOS tube M29; The DN current fast shutdown compensation circuit (3) comprises: a delay delay2, an inverter INV2, a capacitor C8, a PMOS tube M22, and a PMOS tube M23; wherein the input end of the delay delay2 is connected to the gate of the PMOS tube M22, the gate of the NMOS tube M20, the gate of the NMOS tube M25, and the input port DNP; the output end of the delay delay2 is connected to the input end of the inverter INV2, and the output end of the inverter INV2 is connected to the gate of the PMOS tube M23; one end of the capacitor C8 is connected to the drain of the PMOS tube M22, the source of the PMOS tube M21, the source of the PMOS tube M24, the drain of the NMOS tube M20, and the drain of the NMOS tube M25 at a node B, and the other end of the capacitor C8 is connected to an external ground line GND; the source of the PMOS tube M22 is connected to the drain of the PMOS tube M23, and the source of the PMOS tube M23 is connected to an external power supply VDD; The UP current fast shutdown compensation circuit (4) comprises: a delay delay1, an inverter INV1, an NMOS tube M8, and an NMOS tube M9; wherein the input end of the delay delay1 is connected to the gate of the NMOS tube M8, the gate of the PMOS tube M6, the gate of the PMOS tube M11, and the input port UPN; the output end of the delay delay1 is connected to the input end of the inverter INV1, and the output end of the inverter INV is connected to the gate of the NMOS tube M9; the source of the NMOS tube M9 is connected to the external ground line GND, and the drain of the NMOS tube M9 is connected to the source of the NMOS tube M8; the drain of the NMOS tube M8 is connected to the source of the PMOS tube M3, the drain of the PMOS tube M6, the drain of the PMOS tube M11, the source of the NMOS tube M7, and the source of the NMOS tube M10; The output filter circuit (5) comprises: a resistor R1, a resistor R2, and a capacitor C7; wherein one end of the resistor R1 and one end of the capacitor C7 are connected to an OUTP node, one end of the resistor R2 and the other end of the capacitor C7 are connected to an OUTN node, and the other end of the resistor R1 is connected to the other end of the resistor R2 and leads to an output terminal VCON; The dynamic current compensation circuit (6) comprises: a PMOS tube M5, a PMOS tube M13, an NMOS tube M19, and an NMOS tube M26; wherein the gate of the PMOS tube M5 and the gate of the NMOS tube M19 are connected to the OUTP node, the source of the PMOS tube M5 is connected to the source of the PMOS tube M4 and the external power supply VDD, the drain of the PMOS tube M5 is connected to the source of the PMOS tube M2 and the drain of the PMOS tube M4; the source of the NMOS tube M19 is connected to the source of the NMOS tube M18 and the external ground line GND, the drain of the PMOS tube M19 is connected to the NM The source of the OS transistor M16 is connected to the drain of the NMOS transistor M18; the gate of the PMOS transistor M13 and the gate of the NMOS transistor M26 are connected to the OUTN node, the source of the PMOS transistor M13 is connected to the source of the PMOS transistor M14 and the external power supply VDD, the drain of the PMOS transistor M13 is connected to the drain of the PMOS transistor M14 and the source of the PMOS transistor M15; the source of the NMOS transistor M26 is connected to the source of the NMOS transistor M27 and the external ground line GND, the drain of the NMOS transistor M26 is connected to the drain of the NMOS transistor M27 and the source of the NMOS transistor M29; In the charge pump circuit CH1, the PMOS tube M1, the PMOS tube M2, and the PMOS tube M3 form a current mirror, and the PMOS tube M1, the PMOS tube M2, and the PMOS tube M3 have the same width-to-length ratio. The rail-to-rail input operational amplifier A1 uses negative feedback to make the drain bias reference potentials of the PMOS tube M2, the PMOS tube M3, the NMOS tube M16, and the NMOS tube M17 equal, thereby ensuring that the charging current of the charge pump circuit CH1, that is, the leakage current Iup1 of the PMOS tube M3, and the discharging current, that is, the leakage current Idn1 of the NMOS tube M17, accurately track the leakage current I2 of the PMOS tube M2 and the leakage current I16 of the NMOS tube M16. Since I2 is always equal to I16, Iup1=Idn1, thereby realizing accurate replication of the charging and discharging currents of the charge pump circuit CH1; In the charge pump circuit CH2, the NMOS tubes M28, M29 and M30 form a current mirror, and the NMOS tubes M28, M29 and M30 have the same width-to-length ratio. The rail-to-rail input operational amplifier A2 uses negative feedback to make the drain bias reference potentials of the NMOS tubes M28, M29, PMOS tubes M12 and PMOS tubes M15 equal, thereby ensuring that the charging current of the charge pump circuit CH2, i.e., the leakage current Iup2 of the PMOS tube M12, and the discharging current, i.e., the leakage current Idn2 of the NMOS tube M28, accurately track the leakage current I15 of the PMOS tube M15 and the leakage current I29 of the NMOS tube M29. Since I15 is always equal to I29, Iup2=Idn2, thereby achieving accurate replication of the charging and discharging currents of the charge pump circuit CH2.

2. A low mismatch complementary charge pump for a charge pump phase-locked loop according to claim 1, characterized in that: The signal at the input terminal UPN is opposite to the signal at the input terminal UPP, and the signal at the input terminal DNN is opposite to the signal at the input terminal DNP; in the DN current fast shutdown compensation circuit (3), the PMOS tube M22 is placed on the DN current discharge path node B to form a path with the PMOS tube M23 and an external power supply; By delaying delay2 and the inverter INV2, the NMOS tube M23 is turned on for a delay time. When the input signal DNP jumps to a valid low potential, the PMOS tubes M22 and M23 are turned on at the same time to raise the potential of the node B, and quickly turn off the DN current, wherein the DN current IDN=Idn1+Idn2; after the DN current is completely turned off, when the delay time is over, the NMOS tube M9 is turned off, and the NMOS tube M8 is turned off at the same time, thereby reducing the circuit leakage current and the introduction of unnecessary noise; the capacitor C8 is used to compensate for the mismatch caused by the NMOS tube speed being faster than the PMOS tube speed.

3. A low mismatch complementary charge pump for a charge pump phase-locked loop according to claim 1, characterized in that: In the UP current fast shutdown compensation circuit (4), the NMOS tube M8 is placed on the UP current discharge path node A and forms a path with the NMOS tube M9 and the external ground line GND; the PMOS tube M9 is turned on for a delay time by delay1 and the inverter INV1, and when the input signal UPN jumps to an effective high potential, the NMOS tubes M8 and M9 are turned on at the same time to pull down the potential of the node A, and quickly shut down the UP current, wherein the UP current IUP=Iup1+Iup2; after the UP current is completely shut down, the NMOS tube M9 is turned off when the delay time ends, and the NMOS tube M8 is turned off at the same time, thereby reducing the circuit leakage current and reducing the introduction of unnecessary noise.

4. A low mismatch complementary charge pump for a charge pump phase-locked loop according to claim 1, characterized in that: In the dynamic current compensation circuit (6), the on-resistance of the NMOS tube M19, the NMOS tube M26, the PMOS tube M5 and the PMOS tube M13 will change with the change of the output voltage VCON, and compensate the channel length modulation effect of the upper and lower current mirrors through negative feedback. When the output voltage VCON rises, due to the channel length modulation effect of the transistor, the DN current rises with the increase of the output voltage VCON, the gate voltage of the NMOS tube M19 and the NMOS tube M26 rises, the on-resistance decreases, and the source voltage of the NMOS tube M16 and the NMOS tube M29 is lowered. Since the NMOS tube M16 and the NMOS tube M29 are composed of The reference current source PBIAS and the reference current source NBIAS are mirrored. In order to suppress the increase of the drain current caused by the increase of the source voltage of the NMOS tube M16 and the NMOS tube M29, the gate voltage of the NMOS tube M16 and the NMOS tube M29 is reduced accordingly, thereby causing the mirror current of M17 and M28 to decrease, and the DN current to decrease accordingly; the output voltage VCON decreases in the same way; however, since the on-resistance of the PMOS tube M4, the PMOS tube M14, the NMOS tube M18, and the NMOS tube M27 is small, the dynamic adjustment range is limited, so the dynamic current compensation circuit (6) is used for the overall circuit to roughly adjust the mismatch suppression.

5. A low mismatch complementary charge pump for a charge pump phase-locked loop according to claim 1, characterized in that: The rail-to-rail input operational amplifier is used to provide negative feedback compensation, mainly to adjust one current to match another current, rather than to flatten the current response over the entire range; the rail-to-rail input operational amplifier A1 in the feedback loop of the charge pump circuit CH1 actively controls the bias voltages of the NMOS transistors M16 and M17 so that Idn1 follows the output trend of Iup1 and decreases as the output voltage VCON increases; the rail-to-rail input operational amplifier A2 in the feedback loop of the charge pump circuit CH2 actively controls the bias voltages of the PMOS transistors M12 and M15 so that Iup2 follows the output trend of Idn2 and increases as the output voltage VCON increases; the output filter circuit (5) couples the output of the charge pump circuit CH1 with the output of the charge pump circuit CH2, and finally flattens the output current characteristics by superimposing the characteristics of the two opposite output current inclinations.

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