Pixel unit, CMOS image sensor, electronic device and preparation method

Abstract

The present invention provides a pixel unit, a CMOS image sensor, an electronic device and a preparation method. The pixel unit includes a photosensitivity control unit, a reset transistor and a gain control transistor. At least one of the reset transistor and the gain transistor has a buried gate structure, which is at least located between the source and the drain of the corresponding transistor and extends into the substrate to form a buried channel. The present invention can increase the gain control capacitance by preparing a buried gate structure, effectively realize dual conversion gain control, and is particularly suitable for improving the dynamic range of the image sensor under high light. Based on the design of the present invention, the layout of the pixel unit elements can be combined, so that both high conversion gain and low conversion gain are effectively improved. The present invention realizes the increase of gain capacitance without the need for external capacitors, saves device space, and reduces the mutual influence between components. Electrical lead-out can also be achieved through the top gate, the process is simple, and the device can be prepared without adding complex process steps.

Description

Technical Field

[0001] The present invention belongs to the technical field of image sensor manufacturing, and in particular relates to a CMOS image sensor pixel unit, a CMOS image sensor including the pixel unit, an electronic device and a manufacturing method thereof. Background Art

[0002] Image sensors use the photoelectric conversion function of photoelectric devices to convert the light image on the photosensitive surface into an electrical signal that is proportional to the light image. Depending on the components, they can be divided into two categories: CCD (charge coupled device) and CMOS (metal oxide semiconductor device). With the continuous development of CMOS image sensor (CIS) design and manufacturing technology, CMOS image sensors have gradually replaced CCD image sensors and become the mainstream. Among them, CMOS image sensors can be divided into two categories: FSI (FrontSide Illumination) and BSI (Back Side Illumination).

[0003] Dynamic range is a key factor in the imaging quality of image sensors. A large dynamic range can output scene image information within a wider range of light intensity and present richer image details. Normally, the dynamic range of image sensor output is about 60-70db. In general natural environment applications, the dynamic range required to capture image information of highlights and shadows at the same time is about 100db. In image sensor design, the image sensor high dynamic range (HDR) is usually achieved by reading multiple frames of images and synthesizing multiple frames. In addition, some sensors will design a dual conversion gain mode (DCG) to use different gains in different application environments. For example, in low-light scenes, the pixel circuit of the image sensor operates in a high conversion gain mode; in high-light scenes, the pixel circuit of the image sensor operates in a low conversion gain mode.

[0004] However, in the high dynamic range implementation method using multi-frame synthesis, there is a time difference in the multi-frame reading process, and the final synthesized image will have a tailing phenomenon, and the circuit reading noise is large. In addition, the gain capacitance of the existing gain control unit is difficult to effectively increase. The smaller gain capacitance limits the function of the gain control unit, limits the dynamic range of the device, and is difficult to continue to reduce the low gain part. In addition, there is also a method of increasing the gain capacitance by setting the device capacitance, but this method introduces device capacitance, increases the influence between signals, and has high process difficulty. As a result, it is difficult to effectively improve the dynamic range of existing image sensors.

[0005] Therefore, it is necessary to provide a CMOS image sensor pixel unit, a CMOS image sensor, an electronic device and a manufacturing method to solve the above problems in the prior art. Summary of the invention

[0006] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a pixel unit, a CMOS image sensor, an electronic device and a preparation method, which are used to solve the problems in the prior art that the dynamic range of the image sensor is difficult to effectively improve, the gain capacitance is difficult to effectively increase, and the external device capacitance easily causes interference between signals and the process is complicated.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a CMOS image sensor pixel unit, the pixel unit comprising:

[0008] A photosensitive control unit, comprising a photosensitive element and a transfer transistor, wherein the transfer transistor is connected to the photosensitive element and a floating diffusion point respectively, the photosensitive element generates charges in response to incident light, and the transfer transistor transfers the charges;

[0009] a reset transistor connected to a first voltage source;

[0010] a gain control transistor connected between the reset transistor and the floating diffusion;

[0011] At least one of the reset transistor and the gain transistor has a buried gate structure, and the buried gate structure is at least located between the source and the drain of the corresponding transistor and extends into the substrate to form a buried channel.

[0012] Optionally, the buried gate structure includes a plurality of buried gate units arranged at intervals, so as to correspondingly form a plurality of buried channel units in the substrate.

[0013] Optionally, the buried gate structure includes a connecting portion and an extending main portion, the connecting portion is connected to a source and a drain of the transistor, and the extending main portion is connected to the connecting portion and extends downward into the substrate.

[0014] Optionally, a cross-sectional shape of the buried gate structure includes at least one of a square, a circle, an S-shape, a U-shape, a field shape and a ring shape.

[0015] Optionally, the depth of the buried gate structure is greater than the depth of the source and drain of the corresponding transistor; and / or, the depth of the buried gate structure is between 400-500nm, and the depth of the source and drain of the transistor corresponding to the buried gate structure is between 300-400nm; and / or, the sum of the distances between the buried gate structure and the source and drain on both sides is greater than 200nm.

[0016] Optionally, the pixel unit includes four photosensitive control units having a shared structure, the transfer transistor is arranged at a preset inclination angle at a corner corresponding to the photosensitive element, and the four transfer transistors are arranged opposite to each other to form an opening, wherein the reset transistor is arranged along the same direction on one side of the gain control transistor and is correspondingly located between the photosensitive elements in adjacent rows.

[0017] Optionally, the pixel unit also includes at least one of a source follower transistor and a row selection transistor, wherein the source follower transistor is arranged at the center of the opening, and when the source follower transistor and the row selection transistor are formed, the row selection transistor is arranged along the same direction on one side of the source follower transistor and is correspondingly located between the photosensitive elements of adjacent columns.

[0018] Optionally, the buried gate structure includes a first buried gate structure corresponding to the reset transistor and a second buried gate structure corresponding to the gain control transistor, and the setting of the buried gate structure includes: in the same pixel unit, the first buried gate structure and the second buried gate structure are symmetrically arranged about the column direction edge line; and, in adjacent pixel units, the first buried gate structure and the adjacent second buried gate structure are symmetrically arranged about the column direction axis.

[0019] Optionally, the pixel unit further includes a top gate, which is connected to the buried gate structure and arranged correspondingly up and down.

[0020] Optionally, the top gate is located between the source and drain of the corresponding transistor to form a MOS device, and the electrical extraction of the transistor is achieved from the top gate.

[0021] The present invention further provides an image sensor, wherein the CMOS image sensor comprises a plurality of CMOS image sensor pixel units arranged in rows and columns as described in any one of the above solutions.

[0022] The present invention also provides an electronic device, comprising the CMOS image sensor as described in any one of the above solutions.

[0023] The present invention also provides a method for preparing a pixel unit of a CMOS image sensor, wherein the pixel unit of the CMOS image sensor provided by the present invention is preferably prepared based on the preparation method provided by the present invention, and of course, other methods can also be used for preparation. The preparation method of the pixel unit of the CMOS image sensor comprises the following steps:

[0024] Providing a substrate, the substrate comprising a photosensitivity control unit area, a reset transistor area and a gain control transistor area;

[0025] A buried gate structure is prepared corresponding to at least one of the reset transistor region and the gain transistor region, wherein the buried gate structure is at least located between a source region and a drain region of the corresponding transistor and extends into the substrate to form a buried channel;

[0026] A photosensitive element, a transfer transistor and a floating diffusion point are prepared in the photosensitive control unit area; a reset transistor is prepared in the reset transistor area; and a gain control transistor is prepared in the gain control transistor area; wherein the transfer transistor is connected to the photosensitive element and the floating diffusion point respectively, the gain control transistor is connected between the floating diffusion point and the reset transistor, and the other end of the reset transistor is connected to a first voltage source.

[0027] Optionally, the step of preparing the buried gate structure includes:

[0028] A groove is prepared in the substrate by an etching process, and the groove is filled to form the buried gate structure.

[0029] Optionally, the preparation method includes the step of preparing four photosensitive control units having a shared structure to form the pixel unit, the transfer transistor is arranged at a preset inclination angle at a corner corresponding to the photosensitive element, and the four transfer transistors are arranged opposite to each other to form an opening, wherein the reset transistor is arranged on one side of the gain control transistor along the same direction.

[0030] Optionally, the pixel unit also includes at least one of a source follower transistor and a row selection transistor, wherein the source follower transistor is arranged at the center of the opening, and when the source follower transistor and the row selection transistor are formed, the row selection transistor is arranged along the same direction on one side of the source follower transistor and is correspondingly located between the photosensitive elements of adjacent columns.

[0031] Optionally, the preparation method also includes the step of preparing a top gate, wherein the top gate is connected to the buried gate structure and is arranged correspondingly up and down, and the top gate and the gate of the transfer transistor, the gate of the reset transistor and the gate of the gain control transistor are prepared based on the same process.

[0032] Optionally, the preparation method also includes the step of preparing a top interconnect structure, wherein the top interconnect structure is electrically connected to the top gate, and the top gate is located between the source and drain of the corresponding transistor to form a MOS device, so as to realize electrical extraction of the corresponding transistor from the top gate based on the top interconnect structure.

[0033] As described above, the pixel unit, CMOS image sensor, electronic device and preparation method of the present invention can increase the gain capacitance in the gain control process by preparing a buried gate structure, effectively realize the dual conversion gain control of the sensor, and improve the dynamic range of the image sensor. In addition, based on the design of the present invention, the layout of the pixel unit elements can be combined to effectively improve both the high conversion gain and the low conversion gain. The present invention optimizes the physical structure of the low gain node on the basis of the original dual gain product, thereby greatly reducing the low gain value, and with the high gain configuration, the pixel can provide a higher dynamic range. The present invention achieves an increase in gain capacitance without the need for external capacitance, saves device space, and reduces the mutual influence between components. Based on the design of the present invention, electrical extraction can be achieved through the top gate, the preparation process is simple, and the preparation of the device can be achieved without adding too many additional complex process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Shown is a system framework diagram of the image sensor structure provided in an embodiment of the present invention.

[0035] Figure 2 Shown is a process flow chart for preparing a pixel unit according to an embodiment of the present invention.

[0036] Figure 3 Shown is a schematic diagram of providing a substrate in the preparation of a pixel unit according to an embodiment of the present invention.

[0037] Figure 4 It is a schematic diagram showing the preparation of a buried gate structure first in the preparation of a pixel unit according to an embodiment of the present invention.

[0038] Figure 5 It is a schematic diagram showing the formation of the source and drain of the transistor first in the preparation of the pixel unit according to an embodiment of the present invention.

[0039] Figure 6 It is a schematic diagram showing the formation of a buried gate structure and a transistor source and drain in the preparation of a pixel unit according to an embodiment of the present invention.

[0040] Figure 7 It is a schematic diagram showing the formation of a top gate after forming a buried gate structure in the preparation of a pixel unit according to an embodiment of the present invention.

[0041] Figure 8 It is a schematic diagram showing the formation of a transistor source and drain after forming a top gate in the preparation of a pixel unit according to an embodiment of the present invention.

[0042] Fig. 9 Shown is a cross-sectional schematic diagram of a buried gate structure in a pixel unit according to an embodiment of the present invention.

[0043] Fig.10It is a cross-sectional schematic diagram showing another buried gate structure in a pixel unit according to an embodiment of the present invention.

[0044] Fig.11 FIG. 4 is a cross-sectional schematic diagram showing another buried gate structure in a pixel unit according to an embodiment of the present invention.

[0045] Fig.12 Shown is a schematic diagram of a pixel circuit based on the pixel unit design of the present invention.

[0046] Fig.13 Shown is a schematic diagram of a pixel unit layout based on the pixel unit design of the present invention.

[0047] Fig.14 Shown is a partial schematic diagram of a pixel array arrangement based on the pixel unit design of the present invention.

[0048] Fig.15 Shown is a schematic diagram of the operation of an image sensor based on the pixel unit design of the present invention.

[0049] Component number description

[0050] 101 Substrate

[0051] 101a Photosensitive control unit area

[0052] 101b Reset transistor area

[0053] 101c Gain Control Transistor Area

[0054] 102 Photodiode

[0055] 103 first doping region

[0056] 104 second doping region

[0057] 105 Third doping region

[0058] 106 first gate control region

[0059] 107 Second gate control region

[0060] 108 first buried gate structure

[0061] 108a First buried gate cell

[0062] 108b Connection

[0063] 108c Extended main body

[0064] 109 Second buried gate structure

[0065] 109a Second buried gate unit

[0066] 110 Reset transistor gate

[0067] 111 Gain transistor gate

[0068] 112 Pass transistor gate

[0069] Steps S1 to S3 DETAILED DESCRIPTION

[0070] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0071] For the convenience of description, spatial relationship words such as "under", "below", "below", "below", "above", "on", etc. may be used here to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship words are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers; "located between..." includes the area between the two and can also be in contact with the two; "between..." used in the present invention includes two endpoint values. In the context of the present application, the structure described as a first feature "above" a second feature can include an embodiment in which the first and second features are formed in direct contact, and can also include an embodiment in which another feature is formed between the first and second features, so that the first and second features may not be in direct contact.

[0072] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0073] The contents proposed by the present invention are described in detail below in conjunction with the various drawings provided for this patent.

[0074] Embodiment 1:

[0075] Figure 1 The following is a basic structural diagram of an image sensor system. Figure 1 As shown in , the image sensor includes a readout circuit and a control circuit connected to a pixel array, and a functional logic unit is connected to the readout circuit to perform logical control on the reading of the pixel circuit; the readout circuit and the control circuit are connected to a status register to realize the reading control of the pixel array. The pixel array includes a plurality of pixel units arranged in rows (R1, R2, R3...Ry) and columns (C1, C2, C3...Cx), and the pixel signals output by the pixel array are output to the readout circuit via column lines. In one embodiment, after each pixel unit acquires image data, the image data is read out by a readout circuit of a readout mode specified by a status register, and then transmitted to the functional logic unit. In a specific application, the readout circuit may include an analog-to-digital conversion (ADC) circuit, an amplification circuit and others. In certain application embodiments, the status register may include a programmed selection system to determine whether the readout system is read out through a rolling exposure mode (rolling shutter) or a global exposure mode (global shutter). The functional logic unit may only store image data or image data applied or processed by image effects. In one application example, the readout circuit may read out image data along a readout column line (such as Figure 1 The control circuit may read out image data one row at a time (as shown), or may read out image data in various other ways. The operation of the control circuit may be determined by the current setting of the status register. For example, the control circuit generates a shutter signal for controlling image acquisition. In some application examples, the shutter signal may be a global exposure signal so that all pixels of the pixel array simultaneously acquire their image data through a single acquisition window. In some other application examples, the shutter signal may be a rolling exposure signal, and each pixel row is continuously read through the acquisition window.

[0076] Figure 2-11 It shows a process flow chart of the preparation of the pixel unit of the CMOS image sensor of the present invention and a schematic diagram of the structure obtained in each step of the preparation process, Figure 6 and Figure 8 The following are structural diagrams of two pixel unit examples obtained by the present invention. Fig.12 Shown is a circuit connection diagram of a pixel unit designed based on the present invention. Figure 13-14 The schematic diagram of the structure of the layout of each component in a pixel unit designed according to the present invention is shown. The schematic diagram of the operation of an image sensor based on the pixel unit design according to the present invention is shown.

[0077] Please refer to Figure 6 and Figure 8As shown, the present invention provides a CMOS image sensor pixel unit. The pixel unit at least includes: a photosensitive control unit, a reset transistor, a gain control transistor and a buried gate structure, the photosensitive control unit includes a photosensitive element and a transmission transistor, at least one of the reset transistor and the gain transistor has the buried gate structure, and the buried gate structure is at least located between the source and the drain of the corresponding transistor and extends into the substrate to form a buried channel. Through the above-mentioned design of the present invention, based on the introduction of the buried gate structure, it is possible to solve the problems in the prior art that the dynamic range of the image sensor is difficult to effectively improve, the gain capacitance is difficult to continue to increase, and the external device capacitance is easy to cause influence between signals and the process is complicated, and based on the design of the buried gate structure, the overall performance of the image sensor can be improved.

[0078] The CMOS image sensor pixel unit of the present invention will be described in detail below with reference to the accompanying drawings.

[0079] See also Figure 6 and Figure 8 As shown, the substrate 101 of the pixel unit includes a photosensitive control unit area 101a, a reset transistor area 101b and a gain control transistor area 101c, wherein the photosensitive control unit area 101a further includes a photosensitive element area and a transmission transistor area (not shown in the figure). It should be noted that the substrate 101 may also have other structural areas in addition to the above-mentioned areas. The positional relationship of the above-mentioned areas or other areas in the substrate 101 is not limited to the figure. The positional relationship of each area shown in the figure is only to schematically indicate the existence of each area and the related connection method. It does not strictly represent the actual positional relationship of each element in a pixel unit. It can also be other layout methods. As long as the layout method of each transistor in the pixel unit that can achieve the effect of the present invention is within the protection scope of the present invention. In addition, the elements in each area can be connected and operated using existing electrical connection methods.

[0080] Specifically, the substrate 101 can be any structure used to prepare various functional areas in the field of CMOS image sensors. It can be a structure composed of a single material layer, such as a silicon substrate, and the components in each area are prepared in the silicon substrate. The substrate 101 can also be a stacked structure composed of two or more material layers, and each area is prepared in any required layer. In addition, the substrate 101 can also be a structure with n-type doping or p-type doping to meet functional requirements.

[0081] Please continue reading Figure 6 and Figure 8As shown, the pixel unit of the present invention includes a photosensitive control unit, which is prepared in the photosensitive control unit area 101a, and the photosensitive control unit includes a photosensitive element and a transfer transistor (TX) connected to each other, and the transfer transistor is also connected to a floating diffusion point (FD). The photosensitive element responds to incident light to generate charge, and the transfer transistor is used to transfer the charge, wherein the gate of the transfer transistor is connected to a transmission signal line and responds to a transmission signal Vtx, and after the photosensitive element (such as a photodiode PD) completes the integration process, the accumulated charge is transferred to the floating diffusion point.

[0082] Specifically, in one example, Figure 6 and Figure 8 As shown, a photodiode 102 is prepared in the substrate 101 as a photosensitive element. In addition, a first doped region 103 is also prepared in the substrate 101. On the one hand, the first doped region 103 serves as the floating diffusion point, and on the other hand, the first doped region 103, the photodiode 102 and the transfer transistor gate 112 together constitute the transfer transistor (TX) to transfer the charge generated by the photosensitive element to the floating diffusion point based on the transfer transistor. In an optional example, the first doped region 103 is an n-type doped region, and the photodiode 102 can be an n-type and p-type doped region stacked up and down, or a pinned-photodiode. Of course, the arrangement of components in the photosensitive control unit area can also be other commonly used methods in the art, and is not limited to this.

[0083] Please continue reading Figure 6 and Figure 8 As shown, the pixel unit of the present invention also includes an electrically connected reset transistor (RST) and a gain control transistor (DCG), which are respectively prepared in the reset transistor area 101b and the gain control transistor area 101c. One end (such as the drain) of the reset transistor is connected to a first voltage source, and the gate is connected and responds to the reset signal Vrst, which can be used to reset the floating diffusion point according to the reset signal. In one example, the first voltage source is a variable voltage, and of course, it can also be a power supply voltage Vdd, which can be set according to the actual circuit design. The gain control transistor is electrically connected between the other end (such as the source) of the reset transistor and the floating diffusion point, and the gate is connected and responds to the gain control signal Vdcg, and can be converted between high and low gains to improve the dynamic range of the image sensor.

[0084] Specifically, in one example, Figure 6 and Figure 8As shown, a gain control transistor gate 111 is prepared in the gain control transistor region 101c, a reset transistor gate 110 is prepared in the reset transistor region 101b, and a second doping region 104 is prepared across the gain control transistor region 101c and the reset transistor region 101b, and the second doping region 104 serves as the source of the reset transistor and the drain of the gain control transistor at the same time. A third doping region 105 is also prepared in the reset transistor region 101b, and the third doping region 105 serves as the drain of the reset transistor. In addition, in this example, the first doping region 103 can also serve as the source of the gain control transistor at the same time. Of course, the arrangement of the components of the reset transistor region 101b and the gain control transistor region 101c can also be other commonly used methods in the art, and is not limited to this.

[0085] In an optional example, the second doping region 104 and the third doping region 105 are both n-type doping regions, so that each transistor in the pixel unit forms an n-type MOS transistor. Of course, p-type doping can also be performed on different transistors.

[0086] Please continue reading Figure 6 and Figure 8 As shown, in the design of the pixel unit of the present invention, at least one of the reset transistor and the gain transistor has a buried gate structure, and the buried gate structure is at least located between the source and drain of the corresponding transistor and extends downward into the substrate, which can form a buried channel. Of course, it can also extend to other feasible areas, such as extending in other directions in the substrate. Among them, the buried gate structure can be located only at the position corresponding to the reset transistor, and can also be located only at the position corresponding to the gain control transistor. Of course, the buried gate structure can also be set at the positions corresponding to both. In one example, as shown in the figure, it is shown that the position corresponding to the reset transistor has a first buried gate structure 108, and the position corresponding to the gain control transistor has a second buried gate structure 109.

[0087] The buried gate structure extends downward into the substrate. In one example, it can be considered to extend downward from the upper surface of the substrate, and the source and drain of each transistor are also prepared by ion implantation from the upper surface. Thus, an electron channel can be formed around the buried gate structure in the substrate during operation, and a buried channel surrounding the buried gate structure can be obtained. Based on the buried channel, parasitic capacitance can be increased, thereby increasing the gain capacitance of the dual conversion gain control unit, reducing the low gain part under high light, and improving the dynamic range of the image sensor.

[0088] As an example, Figure 8As shown, the pixel unit further includes a top gate, which is connected to the buried gate structure and arranged correspondingly up and down. In one example, the top gate includes at least one of a reset transistor gate 110 and a gain control transistor gate 111. In a specific optional example, the top gate includes both the reset transistor gate 110 and the gain control transistor gate 111, and the buried gate structure includes a first buried gate structure 108 and a second buried gate structure 109, the first buried gate structure 108 is connected to the reset transistor gate 110 and arranged correspondingly up and down, and the second buried gate structure 109 is connected to the gain transistor gate 111 and arranged correspondingly up and down.

[0089] It should be noted that the upper and lower correspondence here refers to the top gate being located on the buried gate structure and having a contact area, and does not limit the area of ​​the contact between the two. In one example, at the interface where the two contact, the top gate covers the buried gate structure. In a further optional example, the top gate covers the area between the source and drain of the corresponding transistor, forming the gate of a traditional MOS transistor, that is, it can work as the gate of a MOS tube during transistor operation.

[0090] In one example, when the top gate exists, the top gate is located between the source and drain of the corresponding transistor to form a MOS device, and the electrical extraction of the transistor is realized from the top gate. For example, there is a reset transistor gate 110 and a gain control transistor gate 111, and in the circuit wiring arrangement, the reset transistor gate 110 and the gain control transistor gate 111 are connected by wiring arrangement to realize the control of the corresponding transistor.

[0091] In this example, the top gate is used as the device gate of the MOS transistor, and the existing pixel unit preparation process and the existing pixel circuit connection lead-out method can be used to complete the image sensor function, so that the introduced buried gate structure can be flexibly configured, including its position and shape, so as to more effectively increase the gain capacitance and improve the overall performance of the sensor. Of course, in other examples, such as Figure 6 As shown, the top gate may not be prepared, and the buried gate structure serves as the gate of the MOS device and has the function of increasing the gain control capacitance. The existing method may be used to realize electrical extraction from the buried gate structure.

[0092] See also Figure 9-11 As shown, the design solution of the present invention can have a variety of buried gate structure design methods.

[0093] In one example, if Fig. 9As shown, the buried gate structure is arranged in a strip shape between the source and drain of the transistor to form a conductive buried channel with the source and drain on both sides, and the buried channel surrounds the buried gate structure. In a further example, in the cross-sectional direction, the front and rear ends of the buried gate structure penetrate the active area and are flush with the ends of the source and drain.

[0094] Specifically, the cross-sectional shape of the buried gate structure is not limited to the above-mentioned strip shape, and its cross-sectional shape includes at least one of square, circular, S-shaped, U-shaped, field-shaped and ring-shaped, but is not limited thereto, and may also be an irregular shape.

[0095] In another example, Fig.10 As shown, the buried gate structure includes a connecting portion and an extended main portion, the connecting portion is connected to the source and drain of the transistor, and the extended main portion is connected to the connecting portion and extends downward into the substrate to form the buried channel. The figure takes the first buried gate structure 108 as an example for illustration, including a connected connecting portion 108b and an extended main portion 108c, the connecting portion 108b is connected to the source and drain of the transistor to facilitate the formation of a buried channel, and the extended main portion 108c extends downward into the substrate to facilitate increasing the channel length. In addition, in one example, at least the front and rear ends of the extended main portion 108c may be flush with the source and drain, Fig.10 The misalignment condition is shown.

[0096] The depth of the connecting portion and the extending main body portion can be designed according to actual needs. For example, in one example, the depth of the connecting portion is less than the depth of the extending main body portion. In addition, the cross-sectional shapes of the connecting portion and the extending main body portion can be designed according to actual needs without excessive restrictions.

[0097] In another example, Fig.11 As shown, the buried gate structure includes a plurality of buried gate units arranged at intervals, and the buried gate units can form a plurality of buried channel units in the substrate, thereby obtaining a buried channel as a whole to further increase the gain control capacitance. For example, in the example in the figure, the first buried gate structure 108 includes a plurality of first buried gate units 108a, and the second buried gate structure 109 includes a plurality of second buried gate units 109a, and the figure shows three buried gate units as an example. The shape of each buried gate structure unit and the adjacent spacing can be set according to actual needs.

[0098] See also Figure 6 and Fig. 9As shown, as an example, the depth d1 of the buried gate structure is greater than the depth d2 of the source and drain of the corresponding transistor, wherein the source and drain depths are equal. In another example, the depth of the buried gate structure is between 400-500nm, such as 420nm, 450nm, 460nm, 480nm. In addition, the depth of the source and drain of the transistor corresponding to the buried gate structure is between 300-400nm, such as 320nm, 350nm, 360nm, 380nm. In addition, in an example, the sum of the spacings between the buried gate structure and the source and drain on both sides is greater than 200nm, for example, the sum of the distance w1 between the drain and the distance w2 between the source (w1+w2) is greater than 200nm, such as 300nm, 400nm; further, w1 may be greater than 100nm, w2 may be greater than 100nm, such as 150nm each, which is conducive to preventing short circuits. The above characteristics may all be satisfied in the device setting, and of course the design may also be made according to actual needs.

[0099] Also, see Figure 12-14 As shown, a circuit connection method of a pixel unit of the present invention and a layout method of a pixel unit are provided, wherein the pixel unit includes four photosensitive control units with a shared structure, respectively including photosensitive elements PD0, PD1, PD2, PD3 and corresponding transmission transistors TX0, TX1, TX2, TX3, forming four photosensitive pixels connected to a floating diffusion point FD. The reset transistor RST is reset, and after the exposure is completed, the pixel signal is amplified by the source follower transistor SF and selected by the row selection transistor RS to be output to the column line. In this example diagram, the pixel circuit also includes a conversion gain control transistor DCG to realize the conversion between high and low gain of the pixel circuit, thereby improving the dynamic range of the image sensor.

[0100] In one example, see Fig.13 As shown, the transfer transistor is arranged at a preset inclination angle at the corner of the corresponding photosensitive element, for example, the preset inclination angle is 45°. Further, it can be that the cross-sectional shape of the PD is a square, and the transfer transistor is arranged parallel to its diagonal direction. In addition, in one example, the four photosensitive control units are arranged opposite to each other to form an opening, which can be considered as four regularly arranged transfer transistors forming a regular shape and symmetrical opening. In an optional example, as shown in the figure, the floating diffusion point is divided into two parts and is respectively arranged on the left and right sides. For example, photodiodes PD1 and PD2 share a floating diffusion point, and photodiodes PD0 and PD3 share another floating diffusion point.

[0101] Among them, in the pixel unit with four photosensitive control units having a shared structure, the reset transistor is arranged on one side of the gain control transistor and arranged along the same direction, correspondingly located between the photosensitive elements in adjacent rows. Here, those skilled in the art can understand that being located between the photosensitive elements does not strictly correspond to being located between the elements, but can be understood as being between the pixel unit row and the pixel unit column to which the corresponding photosensitive element belongs.

[0102] For example, see Figure 13-14 As shown, the reset transistor (RST) 202 is arranged on one side of the gain control transistor (DCG) 204 and arranged in the same direction, such as along the x direction. In this example, the row direction of the pixel array is defined as the x direction, and the column direction is defined as the y direction. Optionally, the x and y directions are perpendicular to each other. In addition, the figure also shows a first buried gate structure 201 corresponding to the reset transistor and a second buried gate structure 203 corresponding to the gain control transistor. For specific structures, please refer to Figure 8 Specifically, in a further example, the reset transistor 202 and the gain control transistor 204 are arranged between the photodiodes PD1 and PD2 in adjacent rows, and the photodiodes PD1 and PD2 are arranged axially symmetrically about the line connecting the centers of the reset transistor 202 and the gain control transistor 204 (along the x direction), and similarly, the photodiodes PD0 and PD3 are also symmetrical about the line.

[0103] Please continue reading Figure 13-14 As shown, the pixel unit also includes at least one of a source follower transistor (SF) and a row selection transistor (RS), and the figure takes the example of including both as an example. Among them, the source follower transistor SF is arranged at the center of the opening, and the center here can be understood as four transfer transistors (or photodiodes) symmetrically arranged about the center of the source follower transistor, and the distance from the center of the source follower transistor to the center of each transfer transistor (or photodiode) is the same. In addition, when both are included, the row selection transistor is arranged on one side of the source follower transistor and arranged along the same direction, such as the y direction, corresponding to the photosensitive elements located between adjacent columns. In one example, as Fig.11 The source follower transistor is shown located in the center of the line connecting the floating diffusion points of the two parts.

[0104] In one example, see Figure 13-14 As shown, the reset transistor and the gain control transistor of the pixel unit share the source / drain configuration. For further information, see Figure 6 and Figure 8 In one example, see Fig.14 As shown, the reset transistor is located between photodiodes in two adjacent rows in adjacent pixel units.

[0105] Among them, the layout of each element in the above pixel unit in this example can effectively reduce the metal size in the rewiring layer. For example, the metal wiring between the gate of the source follower transistor and the floating diffusion point can be effectively reduced, thereby reducing the parasitic capacitance formed there, which is beneficial to improve the dynamic range of the image sensor in the high gain mode. However, it is difficult to effectively improve the low gain mode. The above layout combined with the design of the buried gate structure of the present invention can effectively increase the gain capacitance based on the buried gate structure, so that the image sensor can effectively work in two modes.

[0106] In an optional example, in the same pixel unit, the first buried gate structure corresponding to the reset transistor (such as the corresponding reset transistor 303) and the second buried gate structure corresponding to the gain control transistor (such as the corresponding gain control transistor 301) are symmetrically arranged about the y-direction edge line (such as the dotted line k2), wherein the y-direction edge line can be the central axis of the boundary area between the left and right adjacent pixel units. In another optional example, in adjacent pixel units, the first buried gate structure corresponding to the reset transistor (such as the corresponding reset transistor 302) and the second buried gate structure corresponding to the adjacent gain control transistor (such as the corresponding gain control transistor 301) are symmetrically arranged about the y-direction axis (such as the dotted line k1), wherein the y-direction axis can be the symmetry axis of the left and right photodiodes. The symmetrically arranged buried gate structure is conducive to improving the overall stability of the sensor.

[0107] See also Fig.15 As shown, a schematic diagram of the operation of a sensor based on the pixel unit of the present invention is provided.

[0108] During the operation, during the reset phase T1, the gate voltage of the reset transistor RST and the gate voltage of the conversion gain control transistor DCG are both set to a high level. At this time, the reset transistor RST and the conversion gain control transistor DCG are both turned on to reset the photodiode PD and the floating diffusion point FD. During the exposure process, the photodiode PD responds to the incident light and generates charges. During the low conversion gain reference voltage output phase T2, the gate voltage of the reset transistor RST is set to a low level, the reset transistor RST is turned off, the gate voltage of the conversion gain control transistor DCG is set to a high level, the conversion gain control transistor DCG is turned on, the capacitance value between the floating diffusion point FD and the first voltage source VDD increases due to the gain control capacitor C, the gate voltage of the row selection transistor RS is set to a high level, the row selection transistor RS is turned on, and the pixel circuit outputs the reference voltage VL0 when the conversion gain is low. During the high conversion gain reference voltage output stage T3, the gate voltage of the reset transistor RST is set to a low level, the reset transistor RST is turned off, the gate voltage of the conversion gain control transistor DCG is set to a low level, the conversion gain control transistor DCG is turned off, the gate voltage of the row selection transistor RS is set to a high level, the row selection transistor RS is turned on, and the pixel circuit outputs the reference voltage VH0 when the conversion gain is high.

[0109] Embodiment 2:

[0110] The present invention also provides a CMOS image sensor, comprising a pixel array, wherein the pixel array comprises a plurality of CMOS image sensor pixel units arranged in rows and columns as described in any one of the above schemes, and the CMOS image sensor may be a front-illuminated (FSI) image sensor or a back-illuminated (BSI) image sensor.

[0111] Embodiment three:

[0112] The present invention also provides an electronic device, comprising a CMOS image sensor as described in any one of the above solutions. The electronic device may be a security camera, an automotive electronic camera, a mobile phone camera, a drone, a machine vision, an existing camera, and other devices, but is not limited to the above devices.

[0113] Embodiment 4:

[0114] like Figure 2-11As shown, the present invention also provides a method for preparing a pixel unit of a CMOS image sensor, wherein the pixel unit of the CMOS image sensor provided in the first embodiment of the present invention is preferably prepared based on the preparation method provided in the fourth embodiment, and of course, other methods may also be used for preparation. The structure and characteristics of the relevant material layers in the preparation method of this embodiment can refer to the description of the pixel unit in the first embodiment, and will not be repeated here.

[0115] like Figure 2 As shown, the method for preparing the pixel unit of the CMOS image sensor comprises the following steps:

[0116] S1, providing a substrate, wherein the substrate includes a photosensitivity control unit region, a reset transistor region and a gain control transistor region;

[0117] S2, preparing a buried gate structure corresponding to at least one of the reset transistor region and the gain transistor region, wherein the buried gate structure is at least located between a source region and a drain region of the corresponding transistor and extends into the substrate to form a buried channel;

[0118] S3, preparing a photosensitive element, a transfer transistor and a floating diffusion point in the photosensitive control unit area; preparing a reset transistor in the reset transistor area; preparing a gain control transistor in the gain control transistor area; wherein the transfer transistor is connected to the photosensitive element and the floating diffusion point respectively, the gain control transistor is connected between the floating diffusion point and the reset transistor, and the other end of the reset transistor is connected to a first voltage source.

[0119] The method for preparing a pixel unit of a CMOS image sensor of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 2-11 A schematic diagram of the structure obtained by each step in the preparation of the pixel unit of the CMOS image sensor of this embodiment. In addition, it should be noted that the above sequence does not strictly represent the preparation sequence of the pixel unit of the CMOS image sensor protected by the present invention, and those skilled in the art may change it according to the actual process steps, for example, the photosensitive element may be prepared before the buried gate structure is prepared. Figure 2 Only the steps for preparing a pixel unit of a CMOS image sensor in one example of the present invention are shown.

[0120] First, if Figure 2 S1 and Figure 3 As shown, step S1 is performed to provide a substrate 101, wherein the substrate 101 includes a photosensitivity control unit area 101a, a reset transistor area 101b and a gain control transistor area 101c. The description of the substrate 101 and each area can refer to the description of the pixel unit structure in the first embodiment.

[0121] Then, if Figure 2S2 and Figure 4 As shown, step S2 is performed to prepare a buried gate structure corresponding to at least one of the reset transistor region and the gain transistor region, wherein the buried gate structure is at least located between the source region and the drain region of the corresponding transistor and extends into the substrate to form a buried channel.

[0122] In one example, a first buried gate structure 108 corresponding to the reset transistor and a second buried gate structure 109 corresponding to the gain control transistor are prepared at the same time. In addition, each well region may be prepared in the substrate before the buried gate structure is prepared, and an isolation structure may be prepared as required. In addition, the photodiode 102 may be prepared before the buried gate structure is prepared, the photodiode and the well region may be prepared at the same stage, or after the buried gate structure is prepared, depending on actual settings.

[0123] As an example, the step of preparing the buried gate structure includes: preparing a groove at a corresponding position of the substrate 101 by a photolithography-etching process, and filling the groove to form the buried gate structure. Among them, the groove can be filled by an existing physical and chemical vapor deposition or chemical vapor deposition process. The method is simple and has no additional complex steps. It is easy to implement, compatible with existing semiconductor manufacturing processes, does not require additional process development, and does not affect other designs that increase parasitic capacitance.

[0124] Finally, if Figure 2 S3 and Figure 5-8 As shown, a photosensitive element, a source and a drain of a transfer transistor, and a floating diffusion point are prepared in the photosensitive control unit area 101a; a source and a drain of a reset transistor are prepared in the reset transistor area; and a source and a drain of a gain control transistor are prepared in the gain control transistor area.

[0125] Specifically, each element and each doping region can be prepared by using an existing preparation method. The transfer transistor is connected to the photosensitive element and the floating diffusion point respectively, the photosensitive element generates charge in response to incident light, the transfer transistor transmits the charge, the gain control transistor is connected between the source of the reset transistor and the floating diffusion point, and the drain of the reset transistor is connected to the first voltage source.

[0126] Among them, it should be noted that Figure 4 and Figure 6 The process shown is a process of first preparing a buried gate structure; Figure 5 and Figure 6 The schematic diagram shows that the source and drain of the transistor are prepared first and then the buried gate structure is prepared.

[0127] As an example, see Figure 7-8As shown, the preparation method also includes the step of preparing a top gate, wherein the top gate is connected to the buried gate structure and is arranged correspondingly up and down, and the top gate and the gate of the transfer transistor, the gate of the reset transistor and the gate of the gain control transistor are prepared based on the same process.

[0128] Specifically, in one example, Figure 7 As shown, after the buried gate structure is prepared, the gates of each transistor are prepared first, such as Figure 8 As shown, the gates at the corresponding positions of the reset transistor and the gain control transistor are used as the top gate. That is, the top gate can be prepared by the existing gate preparation process of the reset transistor and the gain control transistor, so there is no need to add a mask plate, there is no need to improve the mask plate, and it can be prepared at the same time as other transistor gates, which is equivalent to inserting only one step of preparing the buried gate structure as a whole. The process is simple and can significantly improve the device performance. Among them, it can be considered that the area between the source and the drain of the reset transistor is defined as the first gate control area 106, and the area between the source and the drain of the gain control transistor is defined as the second gate control area 107, and the top gate is correspondingly located in the above two areas.

[0129] In a further example, the preparation method also includes the step of preparing a top interconnect structure, wherein the top gate is located between the source and drain of the corresponding transistor to form a MOS device, and the top interconnect structure is electrically connected to the top gate to realize electrical extraction of the corresponding transistor from the top gate based on the top interconnect structure, and the top interconnect structure can be prepared using existing wiring processes, such as including a dielectric layer and a metal interconnect layer.

[0130] As an example, the preparation method includes the step of preparing four photosensitive control units having a shared structure to form the pixel unit, the transfer transistor is arranged at a preset inclination angle at the corner corresponding to the photosensitive element, and the four transfer transistors are arranged opposite to each other to form an opening, wherein the reset transistor is arranged along the same direction on one side of the gain control transistor and is correspondingly located between the photosensitive elements in adjacent rows.

[0131] As an example, the pixel unit also includes at least one of a source follower transistor and a row selection transistor, wherein the source follower transistor is arranged at the center of the opening, and when the source follower transistor and the row selection transistor are formed, the row selection transistor is arranged along the same direction on one side of the source follower transistor and is correspondingly located between the photosensitive elements of adjacent columns.

[0132] As an example, the buried gate structure includes a first buried gate structure corresponding to the reset transistor and a second buried gate structure corresponding to the gain control transistor, and the setting of the buried gate structure includes: in the same pixel unit, the first buried gate structure and the second buried gate structure are symmetrically arranged about the column direction edge line; and, in adjacent pixel units, the first buried gate structure and the adjacent second buried gate structure are symmetrically arranged about the column direction axis.

[0133] As an example, the buried gate structure includes a plurality of buried gate units arranged at intervals to correspondingly form a plurality of buried channel units in the substrate.

[0134] As an example, the buried gate structure includes a connecting portion and an extending main portion, the connecting portion is connected to a source and a drain of the transistor, and the extending main portion is connected to the connecting portion and extends downward into the substrate.

[0135] As an example, the cross-sectional shape of the buried gate structure includes at least one of a square, a circle, an S-shape, a U-shape, a field shape, and a ring shape.

[0136] As an example, the depth of the buried gate structure is greater than the depth of the source and drain of the corresponding transistor.

[0137] As an example, the depth of the buried gate structure is between 400-500 nm, and the depth of the source and drain of the transistor corresponding to the buried gate structure is between 300-400 nm.

[0138] As an example, the sum of the distances between the buried gate structure and the source and drain electrodes on both sides is greater than 200 nm.

[0139] In summary, the pixel unit, CMOS image sensor, electronic device and preparation method of the present invention can increase the gain capacitance in the gain control process by preparing a buried gate structure, effectively realize the dual conversion gain control of the sensor, and are particularly suitable for high light conditions to improve the dynamic range of the image sensor. In addition, based on the design of the present invention, the layout of the pixel unit components can be combined so that both the high conversion gain and the low conversion gain are effectively improved. The present invention achieves an increase in the gain capacitance without the need for an external capacitor, saves device space, and reduces the mutual influence between the components. Based on the design of the present invention, electrical lead-out can be achieved through the top gate, the preparation process is simple, and the preparation of the device can be achieved without adding too many additional complex process steps. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0140] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A CMOS image sensor pixel unit, characterized in that: The pixel unit comprises: A photosensitive control unit, comprising a photosensitive element and a transfer transistor, wherein the transfer transistor is connected to the photosensitive element and a floating diffusion point respectively, the photosensitive element generates charges in response to incident light, and the transfer transistor transfers the charges; a reset transistor connected to a first voltage source; a gain control transistor connected between the reset transistor and the floating diffusion; Among them, at least one of the reset transistor and the gain control transistor has a buried gate structure, and the buried gate structure is at least located between the source and the drain of the corresponding transistor and extends into the substrate; the buried gate structure in the substrate forms an electron channel when working, and obtains a buried channel surrounding the buried gate structure, which is used to increase the gain capacitance of the dual conversion gain control unit by increasing the parasitic capacitance, reduce the low gain part under high light, and improve the dynamic range of the image sensor; in the reset stage, the gate voltages of the reset transistor and the gain control transistor are both configured to a high level and turned on; in the low conversion gain output stage, the reset transistor is turned off, and the gain control transistor is turned on, increasing the capacitance value corresponding to the floating diffusion point; in the high conversion gain output stage, the reset transistor and the gain control transistor are both turned off, and the reference voltage at high conversion gain is output.

2. The CMOS image sensor pixel unit according to claim 1, characterized in that: The buried gate structure includes a plurality of buried gate units arranged at intervals, so as to form a plurality of buried channel units correspondingly in the substrate.

3. The CMOS image sensor pixel unit according to claim 1, characterized in that: The buried gate structure includes a connecting portion and an extending main portion, wherein the connecting portion is connected to a source and a drain of a transistor, and the extending main portion is connected to the connecting portion and extends downward into the substrate.

4. The CMOS image sensor pixel unit according to claim 1, characterized in that: The pixel unit includes four photosensitive control units with a shared structure, the transfer transistor is arranged at a preset tilt angle at the corner corresponding to the photosensitive element, and the four transfer transistors are arranged opposite to each other to form an opening, wherein the reset transistor is arranged along the same direction on one side of the gain control transistor and is correspondingly located between the photosensitive elements in adjacent rows.

5. The CMOS image sensor pixel unit according to claim 4, characterized in that: The pixel unit also includes at least one of a source follower transistor and a row selection transistor, wherein the source follower transistor is arranged at the center of the opening, and when the source follower transistor and the row selection transistor are formed, the row selection transistor is arranged along the same direction on one side of the source follower transistor and is correspondingly located between the photosensitive elements of adjacent columns.

6. The CMOS image sensor pixel unit according to claim 1, characterized in that: The buried gate structure includes a first buried gate structure corresponding to the reset transistor and a second buried gate structure corresponding to the gain control transistor, wherein the buried gate structure is arranged in the following manners: in the same pixel unit, the first buried gate structure and the second buried gate structure are symmetrically arranged about a column direction edge line; and, in adjacent pixel units, the first buried gate structure and the adjacent second buried gate structure are symmetrically arranged about a column direction axis. At least one of the following, wherein the column direction edge line is the central axis of a boundary area between left and right adjacent pixel units, and the column direction axis is the symmetry axis of left and right adjacent phototransistors.

7. The CMOS image sensor pixel unit according to claim 1, characterized in that: The cross-sectional shape of the buried gate structure includes at least one of square, circular, S-shaped, U-shaped, field-shaped and ring-shaped.

8. The CMOS image sensor pixel unit according to claim 1, characterized in that: The depth of the buried gate structure is greater than the depth of the source and drain of the corresponding transistor; and / or the depth of the buried gate structure is between 400-500nm, and the depth of the source and drain of the transistor corresponding to the buried gate structure is between 300-400nm; and / or the sum of the distances between the buried gate structure and the source and drain on both sides is greater than 200nm.

9. The CMOS image sensor pixel unit according to any one of claims 1 to 8, characterized in that: The pixel unit further includes a top gate connected to the buried gate structure and arranged correspondingly up and down.

10. The CMOS image sensor pixel unit according to claim 9, characterized in that: The top gate is located between the source and drain of the corresponding transistor to form a MOS device, and the electrical extraction of the transistor is realized from the top gate.

11. A CMOS image sensor, characterized in that: The CMOS image sensor comprises a plurality of CMOS image sensor pixel units as claimed in any one of claims 1 to 10 arranged in rows and columns.

12. An electronic device, characterized in that: Comprising the CMOS image sensor as claimed in claim 11.

13. A method for preparing a pixel unit of a CMOS image sensor, applied to the pixel unit of a CMOS image sensor as claimed in any one of claims 1 to 10, characterized in that: The preparation method comprises the following steps: Providing a substrate, the substrate comprising a photosensitivity control unit area, a reset transistor area and a gain control transistor area; A buried gate structure is prepared corresponding to at least one of the reset transistor region and the gain control transistor region, wherein the buried gate structure is at least located between the source region and the drain region of the corresponding transistor and extends into the substrate to form a buried channel; A photosensitive element, a transfer transistor and a floating diffusion point are prepared in the photosensitive control unit area; a reset transistor is prepared in the reset transistor area; and a gain control transistor is prepared in the gain control transistor area; wherein the transfer transistor is connected to the photosensitive element and the floating diffusion point respectively, the gain control transistor is connected between the floating diffusion point and the reset transistor, and the other end of the reset transistor is connected to a first voltage source.

14. The method for preparing a pixel unit of a CMOS image sensor according to claim 13, characterized in that: The steps of preparing the buried gate structure include: A groove is prepared in the substrate by an etching process, and the groove is filled to form the buried gate structure.

15. The method for preparing a pixel unit of a CMOS image sensor according to claim 13, characterized in that: The preparation method also includes the step of preparing at least one of a source follower transistor and a row selection transistor, wherein the pixel unit has four photosensitive control units with a shared structure, the transfer transistor is arranged at a preset inclination angle at the corner corresponding to the photosensitive element, and the four transfer transistors are arranged opposite to each other to form an opening, and the reset transistor is arranged on one side of the gain control transistor along the same direction; the source follower transistor is arranged at the center of the opening, and when the source follower transistor and the row selection transistor are formed, the row selection transistor is arranged on one side of the source follower transistor along the same direction and is correspondingly located between the photosensitive elements in adjacent columns.

16. The method for preparing a pixel unit of a CMOS image sensor according to any one of claims 13 to 15, characterized in that: The preparation method also includes the step of preparing a top gate, wherein the top gate is connected to the buried gate structure and is arranged correspondingly up and down, and the top gate and the gate of the transfer transistor, the gate of the reset transistor and the gate of the gain control transistor are prepared based on the same process.

17. The method for preparing a pixel unit of a CMOS image sensor according to claim 16, characterized in that: The preparation method also includes the step of preparing a top interconnect structure, wherein the top interconnect structure is electrically connected to the top gate, and the top gate is located between the source and drain of the corresponding transistor to form a MOS device, so as to realize electrical extraction of the transistor from the top gate based on the top interconnect structure.

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