Input signal correction device

Abstract

The present invention provides an input signal correction device capable of reducing power consumption. The input signal correction device (10) of the present invention comprises an input circuit (12) operating at an operating frequency f, an expansion circuit (13), a degeneration circuit (14), a separation circuit (16), a restoration circuit (17), a delay adjustment circuit (18), an unequalizing circuit (15) operating at an operating frequency f / 2, and an adding circuit (19). The expansion circuit (13) doubles the period of the input signals of R and B to output a preprocessed signal. The degeneration circuit (14) degenerates the input signal of G. The de-averaging circuit (15) corrects the pre-processed signals from the expansion circuit (13) and the degeneration circuit (14) to output a correction signal, the separation circuit (16) makes the period of the correction signals of R and B become 1 / 2 to output a differential signal, the restoration circuit (17) makes the period of the correction signal of G become 1 / 2 and outputs the same differential signal in both periods, the delay adjustment circuit (18) delays the input signal to output a delayed signal, and the addition circuit (19) adds the delayed signal to the differential signal to output an output signal.

Description

Technical Field

[0001] The present invention relates to an input signal correction device for correcting input signals of a display panel with uneven numbers of R, G, and B sub-pixels. Background Art

[0002] Conventionally, LCD, OLED, and micro-LED display panels have been known to have a so-called pixel arrangement structure ("PENTILE" is a registered trademark) in which the number of R, G, and B sub-pixels is uneven, as described in Patent Document 1. Display panels with this structure can maintain high resolution with a small number of sub-pixels and have recently been widely used in smartphone displays and other applications.

[0003] like Figure 6 As shown, in the display panel 1 having the RGBG pixel structure, the first pixel P1 includes a sub-pixel P of R. 1R and G sub-pixel P 1G , the second pixel P2 includes a sub-pixel P of B 2B and G sub-pixel P 2G , the (2k+1)th (k is an integer greater than 1) pixel P (2k+1) Sub-pixel P including R (2k+1)R and G sub-pixel P (2k+1)G , the (2k+2)th pixel P (2k+2) Sub-pixel P including B (2k+2)B and G sub-pixel P (2k+2)G In order to correct the input image signal by software and output it to the panel body to eliminate the unevenness (reduce the unevenness) even if the panel body of the display panel 1 has unevenness as hardware, the display panel 1 may have the following features: Figure 7 Input signal correction device 2 as shown.

[0004] The input signal correction device 2 includes: an input circuit 3, which operates at an operating frequency f and receives input signals (image signals) of R, G, and B; an expansion circuit 4, which operates at an operating frequency f and doubles the period of the input signal Ri associated with the R sub-pixel and the input signal Bi associated with the B sub-pixel among the input signals of R, G, and B input to the input circuit 3, thereby outputting pre-processed signals RiA and BiA; a delay circuit 5, which operates at an operating frequency f and delays the input signal Gi associated with the G sub-pixel among the input signals of R, G, and B input to the input circuit 3, thereby outputting a pre-processed signal GiA substantially simultaneously with the output of the pre-processed signals RiA and BiA from the expansion circuit 4; and a de-uniformity circuit 6, which operates at an operating frequency f and corrects the pre-processed signals RiA, BiA, and GiA. Output correction signals ΔRo, ΔBo, ΔGo; a delay adjustment circuit 7, which operates at an operating frequency f, delays the input signals Ri, Bi, Gi to output delay signals RiD, BiD, GiD; an addition circuit 8, which adds the delay signals RiD, BiD, GiD to the correction signals ΔRo, ΔBo, ΔGo to output output signals Ro, Bo, Go (Ro = RiD + ΔRo, Bo = BiD + ΔBo, Go = GiD + ΔGo); and a clock circuit 9, which generates a clock signal of the operating frequency f that is input to the input circuit 3, the expansion circuit 4, the delay circuit 5, the de-uniformity circuit 6 and the delay adjustment circuit 7. As described in patent document 2, the unevenness of the panel body is corrected by inputting the output signals Ro, Bo, Go into the panel body instead of directly inputting the input signals Ri, Bi, Gi.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent No. 4647213

[0008] Patent Document 2: Japanese Patent No. 6220674 Summary of the Invention

[0009] Problems to be solved by the invention

[0010] Furthermore, while the nonuniformity correction performance of input signal correction devices has historically been crucial for technological competitiveness, in recent years, with the significant improvement in display panel performance, reducing power consumption has become a key differentiator. In particular, with the increasing size of displays and speed of processors in mobile devices such as smartphones, battery life is rapidly depleting, making reducing display panel power consumption a challenge.

[0011] The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide an input signal correction device capable of reducing power consumption.

[0012] Solutions for solving problems

[0013] In order to solve the above-mentioned problems, the present invention is an input signal correction device for correcting an input signal of a display panel in which the number of R, G, and B sub-pixels is uneven in the ratio of the number of a minority of sub-pixels to the number of a majority of sub-pixels = 1:N, wherein N is an integer greater than 2, and the input signal correction device is characterized in that it comprises: an input circuit that operates at an operating frequency f and receives input signals of R, G, and B; an expansion circuit that operates at an operating frequency f and causes a period of a first input signal associated with the minority of sub-pixels among the R, G, and B input signals input to the input circuit to become N times, thereby outputting a first pre-processed signal; and a reduction circuit that operates at an operating frequency f and causes a second input signal associated with the majority of sub-pixels among the R, G, and B input signals input to the input circuit to be reduced to 1 / N, thereby outputting a first pre-processed signal. outputting a second preprocessed signal substantially simultaneously; a correction circuit operating at an operating frequency of f / N, correcting the first preprocessed signal to output a first correction signal, and correcting the second preprocessed signal to output a second correction signal; a separation circuit operating at an operating frequency of f, causing the period of the first correction signal to become 1 / N, and outputting a first differential signal; a restoration circuit operating at an operating frequency of f, causing the period of the second correction signal to become 1 / N, and outputting the same second differential signal in N periods; a delay adjustment circuit operating at an operating frequency of f, delaying the first input signal to output a first delayed signal, and delaying the second input signal to output a second delayed signal; and an addition circuit adding the first delayed signal to the first differential signal, and adding the second delayed signal to the second differential signal.

[0014] The input signal correction device may also include: a clock circuit, which generates a clock signal of an operating frequency f that is input to the input circuit, the expansion circuit, the degeneration circuit, the separation circuit, the restoration circuit and the delay adjustment circuit; and a frequency dividing circuit, which divides the clock signal of the operating frequency f to generate a clock signal of an operating frequency f / N that is input to the correction circuit.

[0015] Alternatively, the present invention is an input signal correction device for correcting an input signal for a display panel in which the number of R, G, and B sub-pixels is non-uniform in the ratio of the number of a minority of sub-pixels to the number of a majority of sub-pixels = 1:N, wherein N is an integer greater than or equal to 2, and the input signal correction device is characterized in that it comprises: an input circuit that operates with a clock signal of a frequency f and receives input signals of R, G, and B; an expansion circuit that operates with the clock signal and multiplies the period of a first input signal associated with the minority of sub-pixels among the R, G, and B input signals input to the input circuit by N times, thereby outputting a first pre-processed signal; a degeneration circuit that operates with the clock signal and degenerates a second input signal associated with the majority of sub-pixels among the R, G, and B input signals input to the input circuit by 1 / N, thereby outputting a second pre-processed signal substantially simultaneously with the first pre-processed signal; the correction circuit, It operates with the clock signal and is input with a clock enable signal that switches the validity of the clock signal at a frequency of f / N. The correction circuit corrects the first preprocessed signal to output a first correction signal, and corrects the second preprocessed signal to output a second correction signal; a separation circuit operates with the clock signal to make the period of the first correction signal become 1 / N to output a first differential signal; a restoration circuit operates with the clock signal to make the period of the second correction signal become 1 / N, and outputs the same second differential signal in N periods; a delay adjustment circuit operates with the clock signal to delay the first input signal to output a first delayed signal, and delay the second input signal to output a second delayed signal; and an addition circuit adds the first delayed signal to the first differential signal, and adds the second delayed signal to the second differential signal.

[0016] The input signal correction device may include: a clock circuit that generates the clock signal; and a fast enable circuit that generates the clock enable signal based on the clock signal.

[0017] Furthermore, the correction circuit may correct the first preprocessed signal to reduce unevenness of the display panel and output the first correction signal, and correct the second preprocessed signal to reduce unevenness of the display panel and output the second correction signal.

[0018] Effects of the Invention

[0019] According to the input signal correction device according to the present invention, power consumption can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a block diagram showing an input signal correction device according to an embodiment of the present invention.

[0021] Figure 2 It shows that the application Figure 1 An explanatory diagram of a panel body of a display panel of an input signal correction device.

[0022] Figure 3 It shows Figure 1 An explanatory diagram of the outputs of the input circuit, expansion circuit, reduction circuit, de-averaging circuit, separation circuit, restoration circuit, and adding circuit of an input signal correction device.

[0023] Figure 4 This is a block diagram showing another input signal correction device according to an embodiment of the present invention.

[0024] Figure 5 It shows Figure 4 An explanatory diagram of the outputs of the input circuit, expansion circuit, reduction circuit, de-averaging circuit, separation circuit, restoration circuit, and adding circuit of an input signal correction device.

[0025] Figure 6 This is an explanatory diagram showing a panel body of a display panel having an RGBG pixel structure.

[0026] Figure 7 This is a block diagram showing a conventional input signal correction device. DETAILED DESCRIPTION

[0027] The embodiment of the present invention will be described using the accompanying drawings.

[0028] Figure 1 The input signal correction device according to this embodiment is shown. The input signal correction device 10 has a pixel structure of RGBG similar to the display panel 1. Figure 2 In the display panel 11 shown, a signal having a polarity opposite to that of a pre-acquired unevenness signal is superimposed on an input image signal to eliminate unevenness in the panel body.

[0029] The panel body of the display panel 11 is formed by alternatingly arranging pixels composed of R sub-pixels and G sub-pixels and pixels composed of B sub-pixels and G sub-pixels in the horizontal and vertical directions. Specifically, the first pixel P1 includes R sub-pixels P 1R and G sub-pixel P 1G , the second pixel P2 includes a sub-pixel P of B 2B and G sub-pixel P 2G , the (2k+1)th pixel P (2k+1) Sub-pixel P including R (2k+1)R and G sub-pixel P (2k+1)G , the (2k+2)th pixel P (2k+2)Sub-pixel P including B (2k+2)B and sub-pixel P of G (2k+2)G .

[0030] In addition, the input signal correction device 10 includes an input circuit 12, an expansion circuit 13, a reduction circuit 14, a de-uniformity circuit 15, a separation circuit 16, a restoration circuit 17, a delay adjustment circuit 18, an addition circuit 19, a clock circuit 20, and a frequency division circuit 21.

[0031] The input circuit 12 operates at an operating frequency f, receives the input signals (image signals) of R, G, and B, and outputs the input signals of R, G, and B to the expansion circuit 13.

[0032] The expansion circuit 13 operates at an operating frequency f, and expands the periods of the input signals Ri related to the R sub-pixels and the input signals Bi related to the B sub-pixels among the input signals of R, G, and B input to the input circuit 12 to twice, and outputs preprocessing signals RiA and BiA.

[0033] That is, as Figure 3 shown, in the expansion circuit 13, for example, a signal R1 related to the R sub-pixel of the first pixel P1 is input in the first period, and there is no signal related to the R sub-pixel of the second pixel P2 in the second period and thus no input, and the preprocessing signal RiA obtained by expanding the signal R1 in the first period to two periods is generated in the expansion circuit 13. 1R In addition, in the expansion circuit 13, a signal B2 related to the B sub-pixel of the second pixel P2 is input in the second period, and in the expansion circuit 13, a preprocessing signal BiA obtained by adding a pseudo signal with no data in the first period to the signal B2 is generated.

[0034] The reduction circuit 14 operates at an operating frequency f, reduces the input signals Gi related to the G sub-pixels among the input signals of R, G, and B input to the input circuit 12, and outputs a preprocessing signal GiA substantially simultaneously with the output of the preprocessing signals RiA and BiA from the expansion circuit 13. Here, "reduction" means that by calculating the arithmetic mean, weighted mean, central value, etc. of the data of X pixels and transforming them into the data of Y pixels (Y < X), in the reduction circuit 14, a signal G1 related to the G sub-pixel of the first pixel P1 is input in the first period, and a signal G1 related to the G sub-pixel of the second pixel P2 is input in the second period 1G related, and in the second period, a signal G1 related to the G sub-pixel of the second pixel P2 is input 2G ​​​​​The correlated signal G2 is converted into a pre-processed signal GiA in the degeneration circuit 14 by arranging a signal (G1+G2) / 2 obtained by averaging the signals G1 and G2 in the second cycle and adding a pseudo signal in the first cycle.

[0036] The de-averaging circuit 15 operates at an operating frequency of f / 2, correcting the preprocessed signals RiA, BiA, and GiA to output correction signals ΔRo, ΔBo, and ΔGo. Specifically, the second cycle of the preprocessed signals RiA, BiA, and GiA, i.e., signals R1, B2, and (G1+G2) / 2, is input to the de-averaging circuit 15. The de-averaging circuit 15 corrects these signals R1, B2, and (G1+G2) / 2 based on correction data stored in the de-averaging circuit 15 to generate signals ΔRo1, ΔBo2, and ΔGo12 as correction signals ΔRo, ΔBo, and ΔGo. At this time, since the operating frequency of the de-averaging circuit 15 is f / 2, the signal lengths of the correction signals ΔRo1, ΔBo2, and ΔGo12 are doubled (equal to two cycles).

[0037] Separation circuit 16 operates at an operating frequency f, halving the periods of correction signals ΔRo and ΔBo, and outputs differential signals ΔRoR and ΔBoR. Specifically, separation circuit 16 receives signal ΔRo1 as correction signal ΔRo during its first period, and receives signal ΔBo2 as correction signal ΔBo during its second period. Separation circuit 16 adds a pseudo signal to the second period of signal ΔRo1 to generate signal ΔRoR1, which is the result of separating signal ΔRo1 into its first period. Separation circuit 16 also adds a pseudo signal to the first period of signal ΔBo2 to generate signal ΔBoR2, which is the result of separating signal ΔBo2 into its second period.

[0038] The restoration circuit 17 operates at an operating frequency f, halving the period of the correction signal ΔGo and outputting the same differential signal ΔGoR in both periods. That is, the restoration circuit 17 receives the signal ΔGo12 as the correction signal ΔGo in the first period, and the restoration circuit 17 also copies the signal ΔGo12 in the second period, thereby restoring the same two periods as the input signal Gi (the same as the period of the sub-pixel P of G of the first pixel P1). 1G The related signal and the G sub-pixel P of the second pixel P2 2G Related signal), generating signal ΔGoR12.

[0039] The delay adjustment circuit 18 operates at an operating frequency f, delaying the input signals Ri, Bi, Gi to output delayed signals RiD, BiD, GiD. In the delay adjustment circuit 18, when the signals R1, B2, G1 are input, signals RiD1, BiD2, GiD1 obtained by delaying the signals R1, B2, G1 are generated.

[0040] The adding circuit 19 adds the delayed signals RiD, BiD, GiD and the differential signals ΔRoR, ΔBoR, ΔGoR to output the output signals Ro, Bo, Go (Ro = RiD+ΔRoR, Bo = BiD+ΔBoR, Go = GiD+ΔGoR: in addition, the differential signals ΔRoR, ΔBoR, ΔGoR may be positive or negative.). In the adding circuit 19, the signal RiD1 is added to the signal ΔRoR1 to generate the signal Ro1, the signal BiD2 is added to the signal ΔBoR2 to generate the signal Bo2, the signal GiD1 is added to the signal ΔGoR12 to generate the signal Go1, and the signal GiD2 is added to the signal ΔGoR12 to generate the signal Go2.

[0041] The clock circuit 20 generates a clock signal of an operating frequency f that is input to the input circuit 12, the expansion circuit 13, the degeneration circuit 14, the separation circuit 16, the restoration circuit 17, and the delay adjustment circuit 18. The frequency division circuit 21 divides the clock signal of the operating frequency f by 2 to generate a clock signal of an operating frequency f / 2 that is input to the de-averaging circuit 15.

[0042] The input signal correction device 10 according to this embodiment includes: an input circuit 12 that operates at an operating frequency f and receives input signals of R, G, and B; an expansion circuit 13 that operates at an operating frequency f and doubles the period of the input signal Ri associated with the R sub-pixel and the input signal Bi associated with the B sub-pixel, among the R, G, and B input signals input to the input circuit 12, thereby outputting pre-processed signals RiA and BiA; a degeneration circuit 14 that operates at an operating frequency f and degenerates (averages) the input signal Gi associated with the G sub-pixel, among the R, G, and B input signals input to the input circuit 12, thereby outputting a pre-processed signal GiA substantially simultaneously with the pre-processed signals RiA and BiA output from the expansion circuit 13; and a de-averaging circuit 15 that operates at an operating frequency f / 2 and corrects the pre-processed signals RiA, BiA, and GiA to output a correction signal ΔRo. , ΔBo, ΔGo; a separation circuit 16, which operates at an operating frequency f, makes the period of the correction signals ΔRo, ΔBo become 1 / 2, and outputs differential signals ΔRoR, ΔBoR; a restoration circuit 17, which operates at an operating frequency f, makes the period of the correction signal ΔGo become 1 / 2, and outputs the same differential signal ΔGoR in both periods; a delay adjustment circuit 18, which operates at an operating frequency f, delays the input signals Ri, Bi, Gi to output delay signals RiD, BiD, GiD; and an addition circuit 19, which adds the delay signals RiD, BiD, GiD to the differential signals ΔRoR, ΔBoR, ΔGoR to output output signals Ro, Bo, Go. By utilizing the degeneration circuit 14 to degenerate the input signal Gi to 1 / 2, the operating frequency of the de-uniformity circuit 15 can be reduced to 1 / 2, thereby being able to reduce the power consumption required for de-uniformity (unevenness correction) to approximately half.

[0043] Figure 4 Another input signal correction device according to this embodiment is shown. This input signal correction device 30 superimposes a signal having a polarity opposite to that of a previously acquired unevenness signal on the input image signal of the display panel 11 to eliminate unevenness in the panel. Compared to the input signal correction device 10, this device has the same structure as the input signal correction device 10, except that the operation of the unevenness elimination circuit 15 is different and a clock enable circuit 31 is included instead of the frequency divider circuit 21.

[0044] In the input signal correction device 30 , the clock enable circuit 31 generates a clock enable signal for switching the clock signal at a frequency f / N based on the clock signal at a frequency f generated by the clock circuit 20 , and outputs the clock enable signal to the de-skew circuit 15 .

[0045] like Figure 5As shown, the de-rattling circuit 15 operates with a clock signal of frequency f generated by the clock circuit 20 and receives a clock enable signal generated by the clock enable circuit 31. Similar to the input signal correction device 10, the de-rattling circuit 15 receives the second cycle of the preprocessed signals RiA, BiA, and GiA, namely, signals R1, B2, and (G1+G2) / 2, when the clock enable signal is high (at this time, the clock signal is valid (enabled); when the clock enable signal is low, the clock signal is invalid (disabled). De-rattling circuit 15 corrects these signals R1, B2, and (G1+G2) / 2 based on the correction data stored in the de-rattling circuit 15 to generate signals ΔRo1, ΔBo2, and ΔGo12 as correction signals ΔRo, ΔBo, and ΔGo.

[0046] The input signal correction device 30 includes: an input circuit 12 that operates with a clock signal of a frequency f and receives R, G, and B input signals; an expansion circuit 13 that operates with a clock signal of a frequency f and doubles the period of an input signal Ri associated with an R sub-pixel and an input signal Bi associated with a B sub-pixel, among the R, G, and B input signals input to the input circuit 12, to thereby output pre-processed signals RiA and BiA; a decrement circuit 14 that operates with a clock signal of a frequency f and decrements an input signal Gi associated with a G sub-pixel, among the R, G, and B input signals input to the input circuit 12, to thereby output a pre-processed signal GiA substantially simultaneously with the pre-processed signals RiA and BiA output from the expansion circuit 13; and a de-crement circuit 15 that operates with a clock signal of a frequency f and receives a clock enable signal that switches the validity of the clock signal with a frequency f / 2. The de-crement circuit 15 corrects the pre-processed signals RiA, BiA, and GiA to output a correction signal. signals ΔRo, ΔBo, ΔGo; a separation circuit 16, which operates with a clock signal of frequency f, makes the period of the correction signal ΔRo, ΔBo 1 / 2, and outputs differential signals ΔRoR, ΔBoR; a restoration circuit 17, which operates with a clock signal of frequency f, makes the period of the correction signal ΔGo 1 / 2, and outputs the same differential signal ΔGoR in both periods; a delay adjustment circuit 18, which operates with a clock signal of frequency f, delays the input signals Ri, Bi, Gi, and outputs delayed signals RiD, BiD, GiD; and an addition circuit 19, which adds the delayed signals RiD, BiD, GiD to the differential signals ΔRoR, ΔBoR, ΔGoR, and outputs output signals Ro, Bo, Go. By using the degeneration circuit 14 to degenerate the input signal Gi to 1 / 2, and by inputting a clock enable signal to the de-equalizing circuit 15, the operation of the de-equalizing circuit 15 can be made equivalent to that of the input signal correction device 10, thereby reducing the power consumption required for de-equalizing.

[0047] While the embodiments for carrying out the present invention have been exemplified above, the embodiments of the present invention are not limited to the above-described embodiments, and appropriate changes and the like can be made without departing from the spirit of the present invention.

[0048] For example, the panel body of the display panel to which the input signal correction device is applied is not limited to having an RGBG pixel structure. The panel body may also have an RBGB pixel structure in which pixels including R sub-pixels and B sub-pixels are combined with pixels including G sub-pixels and B sub-pixels. It may also have an RBRG pixel structure in which pixels including R sub-pixels and B sub-pixels are combined with pixels including R sub-pixels and G sub-pixels.

[0049] In addition, the number of R, G, and B sub-pixels does not have to satisfy the number of minority sub-pixels: the number of majority sub-pixels = 1:2. For example, it can also be set to the number of minority sub-pixels: the number of majority sub-pixels = 1:3, and a degeneration circuit is used to degenerate the signal related to the majority sub-pixels to 1 / 3 instead of 1 / 2, and the frequency division circuit is set to a 3-frequency division circuit instead of a 2-frequency division circuit.

[0050] Furthermore, the correction of the input signal is not limited to the purpose of unevenness correction, and the input signal correction device according to the present invention can perform any correction.

[0051] Description of Reference Numerals

[0052] 10: Input signal correction device; 11: Display panel; 12: Input circuit; 13: Expansion circuit; 14: Reduction circuit; 15: De-unevening circuit (correction circuit); 16: Separation circuit; 17: Restoration circuit; 18: Delay adjustment circuit; 19: Addition circuit; 20: Clock circuit; 21: Frequency division circuit; 30: Input signal correction device; 31: Clock enable circuit.

Claims

1. An input signal correction device, which corrects an input signal for a display panel in which the number of R, G, and B sub-pixels is non-uniform in the ratio of the number of minority sub-pixels to the number of majority sub-pixels = 1:N, wherein: N is an integer greater than 2, and the input signal correction device is characterized in that it has: An input circuit operates at an operating frequency f and receives input signals of R, G, and B; an expansion circuit that operates at an operation frequency f to increase the period of a first input signal related to the small number of sub-pixels among the R, G, and B input signals input to the input circuit by N times to output a first pre-processed signal; A degeneration circuit operates at an operation frequency f, degenerating a second input signal related to the plurality of sub-pixels among the R, G, and B input signals input to the input circuit to 1 / N, thereby outputting a second pre-processed signal simultaneously with the first pre-processed signal, wherein degeneration means converting the data of X pixels into data of Y pixels by calculating an additive average, a weighted average, or a central value, wherein Y <X; a correction circuit operating at an operating frequency f / N, correcting the first preprocessed signal to output a first correction signal, and correcting the second preprocessed signal to output a second correction signal; A separation circuit operates at an operating frequency f so that the period of the first correction signal becomes 1 / N to output a first differential signal; A restoration circuit operates at an operating frequency f, so that the period of the second correction signal becomes 1 / N, and outputs the same second differential signal in N periods; a delay adjustment circuit that operates at an operating frequency f, delays the first input signal to output a first delayed signal, and delays the second input signal to output a second delayed signal; and An adding circuit that adds the first delayed signal to the first differential signal and adds the second delayed signal to the second differential signal.

2. The input signal correction device according to claim 1, characterized in that: Also available: a clock circuit that generates a clock signal of an operating frequency f that is input to the input circuit, the expansion circuit, the degeneration circuit, the separation circuit, the restoration circuit, and the delay adjustment circuit; as well as A frequency dividing circuit divides the clock signal of the operating frequency f to generate a clock signal of the operating frequency f / N to be input to the correction circuit.

3. An input signal correction device, which corrects the input signal of a display panel in which the number of R, G, and B sub-pixels is non-uniform in the ratio of the number of minority sub-pixels to the number of majority sub-pixels = 1:N, wherein: N is an integer greater than 2, and the input signal correction device is characterized in that it has: An input circuit operates with a clock signal of frequency f and is input with input signals of R, G, and B; an expansion circuit that operates with the clock signal to increase the period of a first input signal related to the small number of sub-pixels among the R, G, and B input signals input to the input circuit by N times to output a first pre-processed signal; A degeneration circuit operates with the clock signal to degenerate a second input signal related to the plurality of sub-pixels among the R, G, and B input signals input to the input circuit to 1 / N, thereby outputting a second pre-processed signal simultaneously with the first pre-processed signal, wherein degeneration means converting the data of X pixels into data of Y pixels by calculating an additive average, a weighted average, or a central value, wherein Y <X; a correction circuit that operates with the clock signal and receives a clock enable signal that switches the clock signal valid or invalid at a frequency of f / N, wherein the correction circuit corrects the first preprocessed signal to output a first correction signal, and corrects the second preprocessed signal to output a second correction signal; a separation circuit that operates with the clock signal to make the period of the first correction signal 1 / N to output a first differential signal; a restoration circuit that operates with the clock signal to make the period of the second correction signal become 1 / N and outputs the same second differential signal in N periods; a delay adjustment circuit that operates with the clock signal, delays the first input signal to output a first delayed signal, and delays the second input signal to output a second delayed signal; and An adding circuit that adds the first delayed signal to the first differential signal and adds the second delayed signal to the second differential signal.

4. The input signal correction device according to claim 3, characterized in that: Also available: a clock circuit that generates the clock signal; and A fast enable circuit generates the clock enable signal based on the clock signal.

5. The input signal correction device according to any one of claims 1 to 4, characterized in that: The correction circuit corrects the first preprocessed signal so as to reduce unevenness of the display panel and outputs the first correction signal, and corrects the second preprocessed signal so as to reduce unevenness of the display panel and outputs the second correction signal.

Images