Display panel testing equipment and mainboard and subboard used in the testing equipment

Abstract

The present application relates to a detection device for a display panel and a mainboard and a daughterboard used in the detection device. In one embodiment, a waveform driving unit as a signal output channel and a programmable logic device secondary control unit can be integrated into the daughterboard, and only a processor, a programmable logic device control center, a power supply, and a daughterboard slot are retained on the mainboard. The processor controls the programmable logic device control center through a data bus, and the programmable logic device control center is connected to the programmable logic device secondary control unit on the daughterboard by setting a parallel interface in the daughterboard slot. In this way, since the mainboard and the daughterboard in this solution can be connected in a pluggable manner, the total number of channels of the output signal of the detection device can be expanded by adding multiple daughterboards, and the actual detection requirements of the module to be detected can be met by replacing daughterboards with different performances. At the same time, when the signal output channel is damaged, only the corresponding daughterboard needs to be replaced, which greatly reduces the maintenance cost.

Description

Technical Field

[0001] The present disclosure relates to the field of panel detection, and in particular to a detection device for a display panel and a main board and a sub-board used in the detection device. Background Art

[0002] With the continuous development of liquid crystal display technology, the performance of liquid crystal display panels shipped every year is getting higher and higher, and the categories are increasing. Various technologies for testing display panels are also constantly being updated. Correspondingly, how to effectively perform factory testing on various display panels has become a major problem for display panel manufacturers.

[0003] During the production of display panels, after the module process is completed, a panel will be divided into small Cell units. At present, in the factory test of display panels, the Cell inspection machine is mainly used to light up the Cell unit on each panel module after the module Cell process is completed to prevent defective products from flowing into the subsequent production process and causing waste of resources. The Cell inspection machine is a device specially used for Cell unit detection on panel modules. However, the existing Cell inspection machine has a relatively simple design and a simple structure. The detection performance of each Cell inspection machine and the module it is applied to are fixed when it is designed. When a certain detection signal output channel fails or is damaged, the entire machine needs to be disassembled and repaired for maintenance, which is time-consuming and laborious. Even if the inspection machine does not fail, once the detection technology is updated or the production line of the existing module is replaced by a new module, the manufacturer has to abandon the existing Cell inspection machine and seek a Cell inspection machine that meets the new module requirements. This is undoubtedly a huge waste.

[0004] Therefore, there is an urgent need for a display panel testing device that can meet the manufacturers' various testing needs. Summary of the invention

[0005] The present disclosure provides a display panel detection device and a main board and a sub-board used in the detection device to solve the problem that the existing devices cannot meet the various detection requirements of manufacturers. The technical solution of the present disclosure is as follows:

[0006] According to a first aspect of an embodiment of the present disclosure, there is provided a detection device for a display panel, including:

[0007] A mainboard card comprises a processor, a programmable logic device control center, a power supply and a daughterboard slot arranged on the mainboard card.

[0008] The processor is connected in parallel with the programmable logic device control center via a data bus, and the programmable logic device control center receives data and instructions from the processor; the programmable logic device control center is connected in parallel with the daughter board slot via a data bus; the daughter board slot is provided with a parallel interface that can be connected to the daughter board.

[0009] The power supply is connected to the processor, the programmable logic device control center, and the daughter board slot.

[0010] A daughter board card comprises a programmable logic device secondary control unit and a first waveform driving unit.

[0011] The daughter board is pluggably connected to the main board via the parallel interface on the daughter board slot; the programmable logic device secondary control unit communicates with the programmable logic device control center via the parallel interface on the daughter board slot; the first waveform driving unit is connected to the programmable logic device secondary control unit for receiving and outputting signals.

[0012] In one embodiment, the first waveform driving unit includes a digital-to-analog converter, a current driving unit, a digital communication interface and a monitoring unit.

[0013] The output end of the digital-to-analog converter is connected to the input end of the current driving unit. The current driving unit is respectively connected to the digital communication interface and the monitoring unit. The digital communication interface is also connected to the monitoring unit.

[0014] The digital-to-analog converter is also connected to the secondary control unit of the programmable logic device, receives digital signals, converts them into analog signals, and transmits them to the current driving unit.

[0015] The current driving unit is used to output the processed analog signal.

[0016] The digital communication interface is used to receive the current result fed back by the current driving unit and the abnormal information fed back by the monitoring unit. The digital communication interface is also provided with a peripheral interface connected to the secondary control unit of the programmable logic device, and the current result and the abnormal information are sent to the secondary control unit of the programmable logic device through the peripheral interface.

[0017] The monitoring unit is used to monitor abnormal information of the output signal of the current driving unit.

[0018] In one embodiment, a signal synchronization line is provided between the main board and the daughter board, so as to enable the daughter board and the main board to output signals synchronously.

[0019] In one of the embodiments, an interrupt pin is provided between the programmable logic device secondary control unit and the first waveform driving unit. When the monitoring unit detects abnormal information, the first waveform driving unit sends an interrupt signal to the programmable logic device secondary control unit through the interrupt pin.

[0020] In one of the embodiments, an interrupt line is further provided between the main board and the daughter board, and the daughter board sends an interrupt signal to the main board via the interrupt line.

[0021] In one embodiment, a reset line is further provided between the main board and the daughter board. When an abnormal condition occurs in the daughter board, the main board sends a control instruction for performing a reset operation to the daughter board through the reset line.

[0022] In one of the embodiments, when the daughter card is inserted into the daughter card slot, the power supply provides a power signal to the daughter card via a parallel interface on the daughter card slot.

[0023] In one of the embodiments, the mainboard card is further provided with a second waveform driving unit, which is connected to the programmable logic device control center via a data bus, receives signals and instructions, and outputs signals.

[0024] According to a second aspect of an embodiment of the present disclosure, there is also provided a mainboard card of a detection device applied to a display panel, comprising: a processor, a programmable logic device control center, a power supply, and a daughter board slot.

[0025] The processor is connected in parallel with the programmable logic device control center via a data bus, and the programmable logic device control center receives data and instructions from the processor.

[0026] The programmable logic device control center is connected to the daughter board slot via a data bus.

[0027] The daughter board slot is provided with a parallel interface which can be connected to the daughter board.

[0028] The power supply is connected to the processor, the programmable logic device control center, and the daughter board slot.

[0029] According to a second aspect of an embodiment of the present disclosure, there is also provided a daughter card used in conjunction with a main board of the detection device applied to a display panel, comprising: a programmable logic device secondary control unit and a first waveform driving unit.

[0030] The daughter card is connected to the main card in a pluggable manner via a parallel interface on the daughter card slot.

[0031] The programmable logic device secondary control unit communicates with the programmable logic device control center via a parallel interface on the daughter card slot.

[0032] The first waveform driving unit is connected to the programmable logic device secondary control unit and is used for receiving signals and outputting signals.

[0033] In the technical solution provided by the embodiment of the present disclosure, the waveform output channel and the microprocessor are integrated into the daughter card through the split design of the main board and the daughter card, and the daughter card is connected to the main board in a pluggable manner. In this way, when the output channel fails, the daughter card where the failed channel is located can be pulled out, and the daughter card with the same function can be replaced, so as not to affect the use of the entire detection equipment. Moreover, there can be multiple daughter card slots and corresponding daughter cards on the main board, and the number of waveform output channels on each daughter card can also be designed according to needs. Therefore, whether the progress of detection technology brings about the improvement of detection performance, or the number of Cell units in the module to be detected changes, the new detection requirements can be met by replacing the corresponding daughter card. In addition, the main board and the daughter card can be used repeatedly according to actual detection needs, saving hardware resources and reducing equipment costs.

[0034] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic diagram of a detection device for a display panel according to an exemplary embodiment;

[0036] Figure 2 is a schematic diagram of the interior of a daughter board according to an exemplary embodiment;

[0037] Figure 3 is an internal schematic diagram of a first waveform driving unit on a daughter card according to an exemplary embodiment;

[0038] Figure 4 is a schematic diagram of a mainboard card according to an exemplary embodiment;

[0039] Figure 5 is a schematic diagram of the interior of a daughter board according to an exemplary embodiment;

[0040] Figure 6 is a schematic diagram of a mainboard card according to an exemplary embodiment;

[0041] Figure 7is a schematic diagram of a mainboard card according to an exemplary embodiment;

[0042] Figure 8 is a schematic diagram of a mainboard card according to an exemplary embodiment;

[0043] Fig. 9 FIG. 4 is a waveform output diagram generated by a first waveform driving unit according to an exemplary embodiment.

[0044] Reference numerals:

[0045] 10-main board; 11-processor; 12-programmable logic device control center; 13-power supply; 14-data bus; 15-daughter board slot; 16-parallel interface; 17-synchronization line; 18-interrupt line; 19-reset line; 20-daughter board; 21-programmable logic device secondary control unit; 22-first waveform driving unit; 23-interrupt pin; 32-second waveform driving unit; 221-digital-to-analog converter; 222-current driving unit; 223-digital communication interface; 224-monitoring unit; 225-peripheral interface. DETAILED DESCRIPTION

[0046] In order to enable ordinary persons in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings.

[0047] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described here can be implemented in an order other than those illustrated or described here. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are only examples of devices and methods consistent with some aspects of the present disclosure as detailed in the attached claims. The terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, product or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such a process, method, product or device. In the absence of more restrictions, it is not excluded that there are other identical or equivalent elements in the process, method, product or device including the elements. For example, if the words first, second, etc. are used to represent the name, they do not represent any specific order.

[0048] In the present disclosure, when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "connected" to another element or one element is "connected" to another element, it may be directly connected to the other element or there may be an intermediate element at the same time, and it should be understood in a broad sense, for example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0049] The terms "vertical", "horizontal", "left", "right", "up", "down", "front", "rear", "circumferential", "direction of travel" and similar expressions used in this document are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0050] Unless otherwise defined, the technical and scientific terms used herein may have the same meaning as those generally understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The terms "and / or", "and / or", "at least one of..." used herein include any and all combinations of one or more related listed items. It should be noted that the connection, connection, etc. described in the present disclosure may be a direct connection through an interface or pin between devices, or may be a connection through leads.

[0051] Figure 1 Schematic diagram of a detection device for display panel provided by the present disclosure ( Figure 1 The black solid dots in the middle represent daughter boards or daughter board slots not shown), and the detection device may include a main board 10 and a daughter board 20.

[0052] The main board 10 includes a processor 11, a programmable logic device control center 12, a power supply 13, a data bus 14, a sub-board slot 15, and a parallel interface 16 located in the sub-board slot 15. Figure 1 As shown, the main board card 10 may be provided with N daughter board slots, where N≥1.

[0053] The processor 11 is connected in parallel with the programmable logic device control center 12 via a data bus 14 , and the programmable logic device control center 12 receives data and instructions from the processor 11 .

[0054] The programmable logic device control center 12 is connected to the daughter card slot 15 via a data bus.

[0055] The daughter card slot 15 is provided with a parallel interface 16 that can be connected to the daughter card 20 .

[0056] The power supply 13 is connected to the processor 11 , the programmable logic device control center 12 , and the daughter card slot 15 .

[0057] Figure 2 FIG. 2 is an internal schematic diagram of a daughter card embodiment (the black solid dots in the figure represent the first waveform driving unit not shown), and the daughter card 20 includes a programmable logic device secondary control unit 21 and a first waveform driving unit 22. Figure 2 As shown, the number of the first waveform driving units 22 on the daughter board 20 can be N, where N≥1.

[0058] The daughter card 20 is pluggably connected to the main card 10 via the parallel interface 16 on the daughter card slot 15 .

[0059] The PLD secondary control unit 21 communicates with the PLD control center 12 via the parallel interface 16 on the daughter card slot 15 .

[0060] The first waveform driving unit 22 is connected to the programmable logic device secondary control unit 21 and can be used to receive and output signals.

[0061] In some embodiments, the processor 11 on the mainboard card 10 can be a device unit with data processing and logic operation capabilities, such as an MCU processor, a microcomputer, a large-scale integrated logic circuit, etc., wherein the MCU (Microcontroller Unit) processor can also be called a "single-chip microcomputer". In some application scenarios, the detection device can usually be connected to an external host computer, which can be an industrial computer, a personal PC, or other computer systems commonly used in the field. The processor 11 on the mainboard card 10 can interact with the host computer, receive data and instructions from the host computer, and feed data back to the host computer.

[0062] A programmable logic device is a semi-custom circuit in an integrated circuit, and its logic structure can be designed by manual programming to form a digital signal system. Those skilled in the art can understand that the programmable logic device control center 12 and the programmable logic device secondary control unit 21 used in the technical solution of the present disclosure are used in a conventional manner of programmable logic devices. In some embodiments provided by the present disclosure, programmable logic devices such as FPGA (Field-Programmable Gate Array) field programmable gate array, CPLD (Complex Programmable Logic Device) complex programmable logic device, PLD (Programmable Logic Device) programmable logic device, etc. can be used as the programmable logic device control center 12 or programmable logic device secondary control unit 21 in the technical solution provided by the present disclosure. For ease of description, some embodiments in this description uniformly use corresponding abbreviations in the field such as FPGA, CPLD, PLD, etc.

[0063] In some embodiments, the processor 11, programmable logic device control center 12, power supply 13, and daughter card slot 15 on the motherboard card 10 are usually arranged on a baseboard with a pre-designed basic circuit structure to ensure the normal operation of the basic functions of the motherboard card 10. It should be pointed out that in other embodiments, the external physical shape of the motherboard card 10 composed of the baseboard and other necessary shells can be any shape that does not affect the use of the functions of the motherboard card.

[0064] Those skilled in the art can understand that the shape and basic circuit form of the bottom plate are to enable normal connection and use between the various equipment units, so the bottom plate can be a reasonable shape such as a rectangle, a circle, an ellipse, etc. In some embodiments, the basic circuit can also include an external communication interface for the processor 11 to communicate with the host computer. This external interface can be an interface such as a network port, a USB, a serial interface, etc. that can communicate with the host computer to realize the basic function of the detection device interacting with the host computer.

[0065] In some other implementations, the programmable logic device control center 12 may be a programmable logic device such as FPGA, CPLD, PLD, etc. Similarly, the programmable logic device secondary control unit 21 may also be a programmable logic device such as FPGA, CPLD, PLD, etc. The programmable logic device control center 12 and the programmable logic device secondary control unit 21 may use different devices in the same detection device, for example, the programmable logic device control center 12 may use FPGA, and the programmable logic device secondary control unit 21 may use CPLD. Those skilled in the art will understand that the selection of a specific type of programmable logic device will not affect the functional implementation of the technical solution disclosed herein.

[0066] In the technical solution provided by the embodiment of the present disclosure, the signal output channel in the existing Cell inspection machine and other detection equipment is replaced by a waveform driving unit 22 with simple signal processing function and signal output function, and a programmable logic device secondary control unit 21 is integrated into a relatively independent daughter board 20 as a microprocessor and at least one waveform driving unit 22, so that the daughter board 20 has simple information processing function and signal output function, and the daughter board 20 can be connected in a pluggable manner through the daughter board slot 15 on the main board 10. When the first waveform driving unit 22 fails, the daughter board 20 where it is located can be unplugged and replaced with a daughter board with the same function, thereby eliminating the need to repair the main board 10. In this way, by using programmable logic devices on the main board card 10 and the daughter board card 20 respectively to realize hierarchical communication, the daughter board card 20 can synchronously receive signals and instructions from the main board card 10. Since there can be multiple daughter board slots 15 on the main board card 10, and the number of first waveform driving units 22 on each daughter board card 20 can also be designed according to needs, therefore, whether the advancement of detection technology has brought about an improvement in detection performance, or the number of Cell units to be detected has changed due to different modules to be detected, new detection requirements can be met by replacing the corresponding daughter board card 20.

[0067] Figure 3 1 is an internal schematic diagram of a first waveform driving unit on a daughter board in an exemplary embodiment. The first waveform driving unit 22 includes a digital-to-analog converter 221 , a current driving unit 222 , a digital communication interface 223 and a monitoring unit 224 .

[0068] The output end of the digital-to-analog converter 221 is connected to the input end of the current driving unit 222 . The current driving unit 222 is connected to the digital communication interface 223 and the monitoring unit 224 respectively. The digital communication interface 223 is also connected to the monitoring unit 224 .

[0069] The digital-to-analog converter 221 is also connected to the programmable logic device secondary control unit 21 , receives digital signals, converts them into analog signals, and transmits them to the current driving unit 222 .

[0070] The current driving unit 222 is used to output the processed analog signal.

[0071] The digital communication interface 223 is used to receive the current result fed back by the current driving unit 222 and the abnormal information fed back by the monitoring unit 224. The digital communication interface 223 is also provided with a peripheral interface 225 connected to the programmable logic device secondary control unit 21, and the current result and the abnormal information are sent to the programmable logic device secondary control unit 21 through the peripheral interface 225.

[0072] The monitoring unit 224 is used to monitor abnormal information of the output signal of the current driving unit 222 .

[0073] In some embodiments, the connection interface of the digital-to-analog converter 221 can be a simple parallel interface or a serial interface. The digital communication interface 223 is the main external communication interface of the first waveform driving unit 22, and can set alarm functions such as overvoltage, overcurrent, and overheating. The monitoring unit 224 mainly realizes the monitoring function of the output signal. Specifically, during the process of the current driving unit 222 outputting the signal, the monitoring unit 224 can monitor abnormal information including excessive voltage, excessive current, and excessive temperature, and send the abnormal information to the digital communication interface 223. The digital communication interface 223 generates alarm information and transmits the alarm information to the programmable logic device secondary control unit 21. The programmable logic device secondary control unit 21 can store these alarm information and send an interrupt signal to the programmable logic device control center 12 on the main board 10, thereby realizing the monitoring function of the output signal.

[0074] Figure 4 1 is a schematic diagram of a mainboard card in an exemplary embodiment. In some embodiments, a signal synchronization line 17 is provided between the mainboard card 10 and the daughterboard card 20 to enable the mainboard card 10 and the daughterboard card 20 to output signals synchronously. It should be noted that Figure 4 Only the signal synchronization line 17 between one daughter board 20 and the main board 10 is drawn, and the signal synchronization lines between other daughter boards 20 and the main board 10 are not shown.

[0075] Optionally, a signal synchronization line 17 is set between the programmable logic device control center 12 on the main board 10 and the programmable logic device secondary control unit 22 on the daughter board 20. When the programmable logic device control center 12 receives the instructions and signals from the processor 11, it transmits the instructions and signals to the programmable logic device secondary control unit 22 on the daughter board 20, and at the same time sends a frame synchronization signal SYNC to the programmable logic device secondary control unit 22 on the daughter board 20 through the signal synchronization line 17, so that all daughter boards 20 achieve frame synchronization. In this way, the signals and instructions sent by the main board 10 to the daughter board 20 can be executed synchronously to ensure that the daughter board can eventually output waveforms to each Cell unit of the module to be detected synchronously and stably.

[0076] Figure 5 2 is an internal schematic diagram of a daughter card in an exemplary embodiment. In some embodiments, an interrupt pin 23 is provided between the programmable logic device secondary control unit 21 and the first waveform driving unit 22. When the monitoring unit 224 inside the first waveform driving unit 22 detects abnormal information, the first waveform driving unit 22 sends an interrupt signal INT to the programmable logic device secondary control unit 21 through the interrupt pin 23. It should be noted that an interrupt pin 23 is provided between all first waveform driving units 22 and programmable logic device secondary control units 21. Figure 5 Only one of them is drawn.

[0077] Figure 6 1 is a schematic diagram of a mainboard card in an exemplary embodiment. In some embodiments, an interrupt line 18 is further provided between the mainboard card 10 and the daughterboard card 20, and the daughterboard card 20 sends an interrupt signal to the mainboard card 10 via the interrupt line 18. It should be noted that Figure 6 Only the interrupt line 18 between one daughter card 20 and the main card 10 is drawn, and the interrupt lines between other daughter cards 20 and the main card 10 are not shown.

[0078] Optionally, an interrupt line 18 is set between the PLD secondary control unit 21 of the daughter board 20 and the PLD control center 12 of the main board 10, and an interrupt pin int (not shown in the figure) is set between the processor 11 and the PLD control center 12. When the daughter board 20 has an abnormal condition, the PLD secondary control unit 21 on the daughter board 20 first receives the interrupt signal INT sent by the first waveform driving unit 22, and the PLD control secondary control unit 21 then sends the interrupt signal INT to the PLD control center 12 on the main board 10 through the interrupt line 18, and the PLD control center 12 then sends the received interrupt signal INT to the processor 11 through the interrupt pin int, and finally the processor 11 receives the interrupt signal INT from the daughter board 20, and then reads the alarm information stored in the PLD secondary control unit 21 on the corresponding daughter board 20 through the data bus 14. In this way, when the daughter board 20 has an abnormal condition, the abnormal monitoring function of the main board 10 on the daughter board 20 is realized by setting the interrupt line 18 and the corresponding interrupt pin int.

[0079] Figure 7 1 is a schematic diagram of a main board in an exemplary embodiment. In some embodiments, a reset line 19 is further provided between the main board 10 and the daughter board 20. When an abnormal condition occurs in the daughter board 20, the main board 10 sends a control instruction for a reset operation to the daughter board 20 through the reset line 19. It should be noted that Figure 7 Only the reset line 19 between one daughter card 20 and the main card 10 is drawn, and the reset lines between other daughter cards 20 and the main card 10 are not shown.

[0080] Optionally, a reset line 19 is provided between the PLD secondary control unit 21 of the daughter board 20 and the PLD control center 12 of the main board 10. When an abnormal condition occurs in the daughter board 20, the processor 11 sends a reset instruction to the PLD control center 12, and the PLD control center 12 then sends the reset instruction to the PLD secondary control unit 21 on the corresponding daughter board 20 through the reset line 19. The PLD secondary control unit 21 performs a reset operation after receiving the reset instruction.

[0081] In some other embodiments, when the daughter card 20 is inserted into the daughter card slot 15, the power supply 13 provides a power signal to the daughter card 20 through the parallel interface 16 on the daughter card slot 15. Optionally, the daughter card slot 15 is provided with a parallel interface 16 and the power supply 13 is connected by a preset basic circuit. When the daughter card 20 is inserted into the daughter card slot 15, the power supply 13 provides the required high and low levels for the first waveform driving unit 22 on the daughter card 20 through the parallel interface 16. Those skilled in the art can understand that the output of the waveform is essentially different levels at different times, so the power supply 13 is connected to the parallel interface 16 through a preset basic circuit to provide power signals to all daughter cards 20 synchronously and stably. The basic circuit refers to a circuit that connects the power supply 13 with the processor 11, the programmable logic device control center 12, and the parallel interface 16, so that the power supply 13 can supply power to the daughter card 20 inserted in the daughter card slot 15 through the parallel interface 16. The technical solution provided by the embodiment of the present disclosure is that the power supply 13 on the main board 10 uniformly provides a power signal to the first waveform driving unit 22 on the daughter board 20, ensuring the consistency of the final output waveforms of all daughter boards 20 and making the subsequent calibration of the output waveforms of the daughter boards 20 more convenient.

[0082] Figure 8 1 is a schematic diagram of a mainboard card in an exemplary embodiment. In some embodiments, the mainboard card 10 is further provided with a second waveform driving unit 32. The internal structure of the second waveform driving unit 32 is the same as that of the first waveform driving unit 22, and is directly connected to the programmable logic device control center 11 on the mainboard card 10 through a data bus 14. Figure 8 As shown, the number of the second waveform driving units 32 may be N, where N≥1. In the technical solution provided by the embodiment of the present disclosure, at least one second waveform driving unit 32 is directly provided on the main board 10, so that the main board 10 can not only detect the module to be detected by inserting the daughter board 20, but also retain the basic detection capability for itself.

[0083] According to a second aspect of an embodiment of the present disclosure, there is also provided a mainboard card of a detection device applied to a display panel, comprising:

[0084] Processor, programmable logic device control center, power supply, daughter card slot;

[0085] The programmable logic device control center is connected in parallel with the processor via a data bus to receive data and instructions from the processor;

[0086] The programmable logic device control center is connected to the daughter card slot via a data bus;

[0087] The power supply is connected to the processor, the programmable logic device control center, and the daughter card slot to provide power supply;

[0088] The daughter board slot is provided with a parallel interface which can be connected to the daughter board.

[0089] In the technical solution provided by the embodiment of the present disclosure, the mainboard card itself no longer needs to be equipped with a large number of waveform output units, nor does it need to lay out a large number of interfaces connected to the waveform output units. It is only necessary to retain the external interface of the programmable logic device control center on the mainboard card, which greatly reduces the burden of the circuit layout of the mainboard card of the detection equipment. At the same time, the processor no longer needs to be connected in parallel with a large number of waveform output units through pins, but only needs to be connected to the programmable logic device control center through a data bus, which adds more possibilities for the selection of processors for the detection equipment.

[0090] According to a second aspect of an embodiment of the present disclosure, there is also provided a daughter card used in conjunction with a main board of the detection device applied to a display panel, comprising: a programmable logic device secondary control unit and a first waveform driving unit.

[0091] The first waveform driving unit is connected to the programmable logic device secondary control unit and is used for receiving signals and outputting signals.

[0092] The first waveform driving unit includes a digital-to-analog converter, a current driving unit, a digital communication interface and a monitoring unit.

[0093] The output end of the digital-to-analog converter is connected to the input end of the current driving unit. The current driving unit is respectively connected to the digital communication interface and the monitoring unit. The digital communication interface is also connected to the monitoring unit.

[0094] The digital-to-analog converter is also connected to the secondary control unit of the programmable logic device, receives digital signals, converts them into analog signals, and transmits them to the current driving unit.

[0095] The current driving unit is used to process the received analog signal and output it to the module to be detected.

[0096] The digital communication interface is used to receive the current result fed back by the current driving unit and the abnormal information fed back by the monitoring unit. The digital communication interface is also provided with a peripheral interface connected to the secondary control unit of the programmable logic device, and the current result and the abnormal information are sent to the secondary control unit of the programmable logic device through the peripheral interface.

[0097] The monitoring unit is used to monitor abnormal information of the output signal of the current driving unit.

[0098] In the technical solution provided by the embodiment of the present disclosure, the daughter board has a programmable logic device secondary control unit as a microprocessor and at least one waveform driving unit, which has information processing function and signal output function. In this way, a more complex and more powerful waveform output unit can be used on the daughter board, which greatly improves the detection accuracy and efficiency.

[0099] In one embodiment, a main board card 10 may include: a processor 11, a programmable logic device control center 12, a power supply 13, a data bus 14, and a daughter board slot 15. The processor 11 is an MCU processor, the programmable logic device control center is an FPGA unit, and the number of the daughter board slots 15 is set to 12.

[0100] The daughter card 20 includes a programmable logic device secondary control unit 21 and a first waveform driving unit 22. The programmable logic device secondary control unit 21 is a CPLD unit, and the number of the first waveform driving units 22 is set to 8.

[0101] In the technical solution provided by the embodiment of the present disclosure, 12 daughter card slots are provided on the main board, and each daughter card is provided with 8 first waveform driving units. According to the number of daughter cards inserted into the main board, 8 to 96 signal output channels can be provided for the main board, and daughter cards with different performances can be replaced according to different detection performance requirements, which can flexibly meet various detection needs. At the same time, FPGA is selected as the programmable logic device control center of the main board, and a smaller CPLD is selected as the programmable logic device secondary control unit of the daughter card. On the one hand, FPGA can complete the instructions of the MCU processor with powerful signal processing and interaction capabilities, and on the other hand, it can pass the received signals and instructions to the next-level programmable logic device CPLD on the daughter card. After receiving the signals and instructions transmitted by FPGA, CPLD performs corresponding operations, and the first waveform driving unit performs waveform output according to the signals transmitted by CPLD. The powerful processing capability of FPGA ensures the execution of MCU processor instructions, and CPLD has low cost, small size but superior performance, effectively saves the internal space of the daughter card and also reduces the overall cost of the detection equipment.

[0102] Fig. 9It is a waveform output diagram generated by a first waveform driving unit in an embodiment of the present disclosure, with 10 orders, the voltage range of the output waveform is -40V to -5V, the duration of each value is 1ms, and 10ms is a cycle. When the detection device is operating normally, the first waveform driving unit 22 on the daughter board 20 is connected to the module to be detected, and the host computer transmits the set waveform information to the processor 11 on the main board 10. The processor 11 processes the waveform information and then sends a digital signal to the programmable logic device control center 12 through the data bus 14. The programmable logic device control center 12 further transmits the digital signal to the programmable logic device secondary control unit 21 on the daughter board 20. The programmable logic device secondary control unit 21 can simply process the received digital signal and send it to the first waveform driving unit 22. The digital-to-analog converter 221 on the first waveform driving unit 22 converts the digital signal into an analog signal and provides it to the current driving unit 222 of the next level, and the current driving unit 222 completes the final waveform output. It should be noted that the processes of receiving signals and outputting waveforms by all the first waveform driving units 22 in the daughter cards 20 inserted into the main card 10 are the same, and will not be described one by one here.

[0103] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the present application. It should be noted that those skilled in the art will easily think of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0105] It will be understood that the present disclosure is not limited to the exact construction that has been described and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. A display panel detection device, characterized in that: The detection equipment comprises: A mainboard card, the mainboard card comprising a processor, a programmable logic device control center, a power supply, and a daughterboard slot arranged on the mainboard card; The processor is connected in parallel with the programmable logic device control center via a data bus, and the programmable logic device control center receives data and instructions from the processor; the programmable logic device control center is connected in parallel with the daughter card slot via a data bus; the daughter card slot is provided with a parallel interface that can be connected to the daughter card; The power supply is connected to the processor, the programmable logic device control center, and the daughter card slot; A daughter board, the daughter board comprising a programmable logic device secondary control unit and a first waveform driving unit; The daughter card is pluggably connected to the main card via the parallel interface on the daughter card slot; the programmable logic device secondary control unit communicates with the programmable logic device control center via the parallel interface on the daughter card slot; the first waveform driving unit is connected to the programmable logic device secondary control unit for receiving and outputting signals; The first waveform driving unit internally includes a digital-to-analog converter, a current driving unit, a digital communication interface and a monitoring unit; The output end of the digital-to-analog converter is connected to the input end of the current driving unit, the current driving unit is connected to the digital communication interface and the monitoring unit respectively, and the digital communication interface is also connected to the monitoring unit; The digital-to-analog converter is also connected to the programmable logic device secondary control unit, receives digital signals, converts them into analog signals and transmits them to the current driving unit; The current driving unit is used to output the processed analog signal; The digital communication interface is used to receive the current result fed back by the current driving unit and the abnormal information fed back by the monitoring unit. The digital communication interface is also provided with a peripheral interface connected to the secondary control unit of the programmable logic device, and the current result and the abnormal information are sent to the secondary control unit of the programmable logic device through the peripheral interface; The monitoring unit is used to monitor abnormal information of the output signal of the current driving unit.

2. The detection device according to claim 1, characterized in that: A signal synchronization line is arranged between the main board and the daughter board, so as to enable the daughter board and the main board to realize synchronous signal output.

3. The detection device according to claim 1, characterized in that: An interrupt pin is provided between the programmable logic device secondary control unit and the first waveform driving unit. When the monitoring unit detects abnormal information, the first waveform driving unit sends an interrupt signal to the programmable logic device secondary control unit through the interrupt pin.

4. The detection device according to claim 1, characterized in that: An interrupt line is also provided between the main board and the daughter board, and the daughter board sends an interrupt signal to the main board via the interrupt line.

5. The detection device according to claim 1, characterized in that: A reset line is also provided between the main board and the daughter board. When an abnormal condition occurs in the daughter board, the main board sends a control instruction for a reset operation to the daughter board through the reset line.

6. The detection device according to claim 5, characterized in that: A reset line is further arranged between the main board and the daughter board, including: a reset line is arranged between the editable logic device secondary control unit of the daughter board and the editable logic device control center of the main board.

7. The detection device according to claim 1, characterized in that: When the daughter board is inserted into the daughter board slot, the power supply provides a power signal to the daughter board through a parallel interface on the daughter board slot.

8. The detection device according to claim 1, characterized in that: The mainboard card is also provided with a second waveform driving unit, which is connected to the programmable logic device control center via a data bus, receives signals and instructions, and outputs signals.

9. A mainboard card for a display panel detection device, characterized in that: include: Processor, programmable logic device control center, power supply, daughter card slot; The processor is connected in parallel with the programmable logic device control center via a data bus, and the programmable logic device control center receives data and instructions from the processor; The programmable logic device control center is connected in parallel with the daughter card slot via a data bus; The daughter card slot is provided with a parallel interface that can be connected to the daughter card; The power supply is connected to the processor, the programmable logic device control center, and the daughter card slot; The daughter card is pluggably connected to the main card via the parallel interface on the daughter card slot; the daughter card includes a programmable logic device secondary control unit and a first waveform driving unit, and the programmable logic device secondary control unit communicates with the programmable logic device control center via the parallel interface on the daughter card slot; The first waveform driving unit is connected to the programmable logic device secondary control unit and is used to receive signals and output signals; The first waveform driving unit internally includes a digital-to-analog converter, a current driving unit, a digital communication interface and a monitoring unit; The output end of the digital-to-analog converter is connected to the input end of the current driving unit, the current driving unit is connected to the digital communication interface and the monitoring unit respectively, and the digital communication interface is also connected to the monitoring unit; The digital-to-analog converter is also connected to the programmable logic device secondary control unit, receives digital signals, converts them into analog signals and transmits them to the current driving unit; The current driving unit is used to output the processed analog signal; The digital communication interface is used to receive the current result fed back by the current driving unit and the abnormal information fed back by the monitoring unit. The digital communication interface is also provided with a peripheral interface connected to the secondary control unit of the programmable logic device, and the current result and the abnormal information are sent to the secondary control unit of the programmable logic device through the peripheral interface; The monitoring unit is used to monitor abnormal information of the output signal of the current driving unit.

10. A daughter card used in conjunction with the main card of the detection device for display panel according to claim 9, characterized in that: include: A programmable logic device secondary control unit and a first waveform driving unit; The daughter card is pluggably connected to the main card via a parallel interface on the daughter card slot; The PLD secondary control unit communicates with the PLD control center via the parallel interface on the daughter card slot; The first waveform driving unit is connected to the programmable logic device secondary control unit and is used to receive signals and output signals; The first waveform driving unit internally includes a digital-to-analog converter, a current driving unit, a digital communication interface and a monitoring unit; The output end of the digital-to-analog converter is connected to the input end of the current driving unit, the current driving unit is connected to the digital communication interface and the monitoring unit respectively, and the digital communication interface is also connected to the monitoring unit; The digital-to-analog converter is also connected to the programmable logic device secondary control unit, receives digital signals, converts them into analog signals and transmits them to the current driving unit; The current driving unit is used to output the processed analog signal; The digital communication interface is used to receive the current result fed back by the current driving unit and the abnormal information fed back by the monitoring unit. The digital communication interface is also provided with a peripheral interface connected to the secondary control unit of the programmable logic device, and the current result and the abnormal information are sent to the secondary control unit of the programmable logic device through the peripheral interface; The monitoring unit is used to monitor abnormal information of the output signal of the current driving unit.

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