A high-speed waveguide detector and its fabrication method

Abstract

This invention discloses a high-speed waveguide detector, comprising: a first waveguide layer and an absorption layer, and further comprising: a second waveguide layer located between the first waveguide layer and the absorption layer. This invention also discloses a method for fabricating a high-speed waveguide detector. The structural design of this invention avoids the problem of easy breakdown in the edge region of traditional designs; under low bias voltage or 0V, the technical means proposed in this invention can make the electric field at the edge of the absorption region strong, enabling charge carriers to drift rapidly, thereby ensuring a sufficiently high bandwidth; the process flow is compatible with CMOS technology, and the process steps used are all conventional processes, suitable for large-scale mass production.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a high-speed waveguide detector and its fabrication method. Background Art

[0002] Ge detectors are detectors that can be integrated on silicon wafers. Ge is typically grown on silicon via CVD epitaxy. Due to the influence of the crystal lattice, the shape of Ge is approximately trapezoidal, resulting in extremely thin thickness at the edge of the Ge layer.

[0003] like Figure 1 As shown, when light enters from one side of the silicon waveguide layer 101 and couples to the Ge layer 102, photogenerated carriers are generated at the edges and center of the Ge layer 102. Generally, when forming a PIN junction, ion injection in the edge region should be avoided; otherwise, the edge region is extremely prone to breakdown due to its thinness. Therefore, as... Figure 1 In the structure shown, the top N-type doped region 103 is far from the edge of the Ge layer 102, and its width is smaller than that of the bottom region of the Ge layer 102. Therefore, the electric field in the edge region is weak, which makes it difficult for the photogenerated carriers in the edge region below the sloping edge to reach the saturation drift velocity, thus limiting the bandwidth of the detector.

[0004] To address the aforementioned technical problems, those skilled in the art typically increase the voltage between the N and P electrodes to strengthen the electric field in the edge region, thereby partially improving the bandwidth. However, this method has three drawbacks: First, the electric field in the absorption layer within the lower left and right corners of Ge layer 102 (within the dashed box) remains very weak, preventing the bandwidth from reaching a high level; second, increasing the operating voltage significantly increases the dark current of the detector; and third, in some applications that integrate a large number of high-speed detectors, the increased power consumption due to high bias voltage is substantial. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a high-speed waveguide detector and its fabrication method. To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or to define the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0006] The present invention adopts the following technical solution:

[0007] This invention provides a high-speed waveguide detector, comprising: a first waveguide layer and an absorption layer, and further comprising: a second waveguide layer located between the first waveguide layer and the absorption layer;

[0008] The width of the doped region in the second waveguide layer is smaller than the width of the bottom edge of the absorption layer;

[0009] The width of the top doped region of the absorption layer is greater than or equal to the width of the bottom edge of the absorption layer, or it is less than the width of the bottom edge of the absorption layer but greater than the width of the doped region of the second waveguide layer.

[0010] Furthermore, the doped regions of the first waveguide layer and the doped regions of the second waveguide layer partially overlap.

[0011] Furthermore, a doped layer is disposed on top of the absorption layer, and ions are implanted into the doped layer to form the top doped region of the absorption layer, or ions are directly implanted into the upper surface layer of the absorption layer to form the top doped region.

[0012] Furthermore, the material of the absorption layer is intrinsic Ge, N / P-type doped Ge, GeSi alloy, quantum dot material, semiconductor bulk material, or quantum hydrazine material; when the material of the absorption layer is N / P-type doped Ge, the doping concentration is less than the doping concentration at the top and bottom of the absorption layer.

[0013] Furthermore, the materials of the first waveguide layer and the second waveguide layer are materials that can be doped with P-type or N-type; the doping polarities of the first waveguide layer and the second waveguide layer are the same, both being P-type or N-type doped; the doping polarity of the top of the absorption layer is opposite to that of the first waveguide layer and the second waveguide layer.

[0014] This invention also provides a method for fabricating a high-speed waveguide detector, comprising:

[0015] A second waveguide layer is epitaxially grown on the first waveguide layer, and the second waveguide layer is ion-doped.

[0016] An absorption layer is epitaxially grown on the second waveguide layer, and ion doping is performed on the top of the absorption layer;

[0017] Wherein, the width of the doped region of the second waveguide layer is smaller than the width of the bottom edge of the absorption layer;

[0018] The width of the top doped region of the absorption layer is greater than or equal to the width of the bottom edge of the absorption layer, or it is less than the width of the bottom edge of the absorption layer but greater than the width of the doped region of the second waveguide layer.

[0019] Furthermore, the method further includes: ion doping the first waveguide layer; wherein the doped region of the first waveguide layer partially overlaps with the doped region of the second waveguide layer.

[0020] Furthermore, the process of performing ion doping on the top of the absorption layer involves epitaxially growing a doped layer on the top of the absorption layer, implanting ions into the doped layer to form the top doped region of the absorption layer, or directly implanting ions into the upper surface layer of the absorption layer to form the top doped region.

[0021] Furthermore, the material of the absorption layer is intrinsic Ge, N / P-type doped Ge, GeSi alloy, quantum dot material, semiconductor bulk material, or quantum hydrazine material; when the material of the absorption layer is N / P-type doped Ge, the doping concentration is less than the doping concentration at the top and bottom of the absorption layer.

[0022] Furthermore, the materials of the first waveguide layer and the second waveguide layer are materials that can be doped with P-type or N-type; the doping polarities of the first waveguide layer and the second waveguide layer are the same, both being P-type or N-type doped; the doping polarity of the top of the absorption layer is opposite to that of the first waveguide layer and the second waveguide layer.

[0023] The beneficial effects of this invention are as follows: the structural design of this invention avoids the problem of easy breakdown in the edge region of traditional designs; under low bias voltage or 0V, the technical means proposed in this invention can make the electric field of the edge part of the absorption region stronger, so that the charge carriers can drift rapidly, thereby ensuring a sufficiently high bandwidth; the process flow is compatible with CMOS process, and the process steps used are all conventional processes, which are suitable for large-scale mass production. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the structure of a Ge-on-silicon detector in the prior art;

[0026] Figure 2 This is a schematic diagram of the structure of a high-speed waveguide detector according to the present invention;

[0027] Figure 3 This is a schematic diagram when the width of the doped region at the top of the absorption layer is equal to the width of the bottom edge of the absorption layer.

[0028] Figure 4 This is a schematic diagram when the width of the doped region at the top of the absorption layer is greater than the width of the bottom edge of the absorption layer.

[0029] Figure 5This is a schematic diagram when the width of the top doped region of the absorption layer is smaller than the width of the bottom edge of the absorption layer, but larger than the width of the doped region of the second waveguide layer.

[0030] Figure 6 This is a schematic diagram of the shape of the intrinsic absorption layer;

[0031] Figure 7 This is a flowchart of a method for fabricating a high-speed waveguide detector according to the present invention. Detailed Implementation

[0032] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0033] like Figure 2-6 As shown, the present invention provides a high-speed waveguide detector, comprising: a first waveguide layer 1, a second waveguide layer 2 and an absorption layer 3, that is, the present invention has two waveguide layers, and the second waveguide layer 2 is located between the first waveguide layer 1 and the absorption layer 3.

[0034] The material of the absorption layer 3 is intrinsic Ge, N / P-type doped Ge, GeSi alloy, quantum dot material, bulk semiconductor material, or quantum hydrazine material, such as InGaAs quantum dot material or InP-based bulk semiconductor material. When the material of the absorption layer 3 is N-type or P-type doped Ge, the N-type or P-type doping concentration is less than the doping concentration at the top and bottom of the absorption layer 3. The doping concentration at the bottom of the absorption layer 3 refers to the doping concentration of the second waveguide layer 2. When the material of the absorption layer 3 is a GeSi alloy, the present invention does not limit the ratio of the two materials.

[0035] The materials of the first waveguide layer 1 and the second waveguide layer 2 can be P-type or N-type doped materials, such as silicon, GaAs, and InP.

[0036] The following explanation uses a silicon waveguide as an example, with P-type doping on both silicon waveguide layers and an absorption layer 3 being a Ge layer, which is N-type doped. In this design, the N-type and P-type doping can be interchanged without affecting the effectiveness of the invention.

[0037] The first waveguide layer 1 is made of silicon and is a P-type doped region to form the first doped region 101.

[0038] The second waveguide layer 2 is made of silicon and is a partially P-type doped region to form a second doped region 201. The width of the second doped region 201 is smaller than the width of the bottom edge of the absorption layer 3, that is, smaller than the width of the bottom edge of the Ge layer.

[0039] Above the second waveguide layer 2 is the absorption layer 3. For example... Figure 3 As shown, the width of the top doped region 301 of the absorption layer 3 is equal to the width of the bottom edge of the absorption layer 3, or as shown... Figure 4 As shown, the width of the top doped region 301 of the absorption layer 3 is greater than the width of the bottom edge of the absorption layer 3, or as... Figure 5 As shown, the width of the top doped region 301 of the absorption layer 3 is smaller than the width of the bottom edge of the absorption layer 3, but larger than the width of the second doped region 201.

[0040] The doped regions of the first waveguide layer and the doped regions of the second waveguide layer partially overlap, that is, the doped region 101 of the first layer and the doped region 201 of the second layer partially overlap. The overlapping part is the width of the doped region 201 of the second layer. This invention does not require the width of the doped region of the first silicon layer.

[0041] A doped layer is provided on the top of the absorption layer 3. The doped layer is formed by ion implantation to form the top doped region 301 of the absorption layer 3, or by ion implantation directly into the upper surface layer of the absorption layer 3 to form the top doped region 301.

[0042] The first waveguide layer 1 and the second waveguide layer 2 have the same doping polarity, both being P-type or N-type doping; the top doping polarity of the absorption layer 3 is opposite to that of the first waveguide layer 1 and the second waveguide layer 2.

[0043] Generally, a PIN junction has a built-in electric field, and when the bias voltage is 0V, Figure 1 The conventional structure shown has a built-in electric field in the central part of the absorption region, but the edge of the absorption region has no built-in electric field or a very weak built-in electric field. Therefore, its bandwidth is not high under 0V bias, generally much lower than that under 1V or 3V bias. However, if the detector structure design of this invention is adopted, under 0V bias, all or most of the regions in the absorption layer 3 have a strong built-in electric field, so the bandwidth under 0V bias will be significantly improved.

[0044] In particular, the shape of the absorption layer 3 is not limited to a trapezoid; it can be a polygon, a rectangle, a triangle, etc. Figure 6 As shown.

[0045] This invention adds a new waveguide layer, namely the second waveguide layer 2, to the waveguide detector design, and injects P-type or N-type ions into a portion of the upper part of the waveguide layer to form a second doped region 201. At the same time, ion implantation is performed in the center and edge of the top layer of the absorption layer 3 to form a top doped region 301. The width of each doped region is specified accordingly. By selecting the width of the relevant doped region, the electric field in all or most areas of the detector is strong under low bias or zero bias, which enables the charge carriers to drift rapidly, thereby ensuring a sufficiently high bandwidth and avoiding the problem of easy breakdown in the edge region of traditional designs.

[0046] like Figure 2-7 As shown, this invention also provides a method for fabricating a high-speed waveguide detector. Taking a silicon waveguide as an example, two silicon waveguide layers are P-type doped, and the absorption layer is a Ge layer, which is N-type doped. The N-type and P-type doping can be interchanged without affecting the effectiveness of this invention. The fabrication method of this invention specifically includes the following steps:

[0047] 101: Prepare the substrate.

[0048] 102: P-type ion doping is performed on the first waveguide layer 1.

[0049] 103: Etched waveguide.

[0050] 104: A second waveguide layer 2 is epitaxially grown on the first waveguide layer 1, so that the present invention has two waveguide layers, and the second waveguide layer 2 is located between the first waveguide layer 1 and the absorption layer 3.

[0051] 105: P-type ion doping is performed on the second waveguide layer 2.

[0052] The doped region of the first waveguide layer 1 partially overlaps with the doped region of the second waveguide layer 2. The overlapping part is the width of the doped region of the second waveguide layer 2. This invention does not require a specific width for the doped region of the first silicon layer.

[0053] The width of the doped region in the second waveguide layer 2 is smaller than the width of the bottom edge of the absorption layer 3, which is smaller than the width of the bottom edge of the Ge layer.

[0054] 106: An absorption layer 3 is epitaxially grown on the second waveguide layer 2.

[0055] 107: Epitaxial doped layer. This step is optional. After the doped layer is epitaxially grown on top of the absorption layer 3, ions are implanted into the doped layer to form the top doped region 301 of the absorption layer 3. If step 107 is not performed, step 108 can be performed directly on the upper surface of the absorption layer 3.

[0056] 108: N-type ion doping is performed on the top of the absorption layer 3 to form the top doped region 301.

[0057] like Figure 3 As shown, the width of the top doped region 301 of the absorption layer 3 is equal to the width of the bottom edge of the absorption layer 3, or as shown... Figure 4 As shown, the width of the top doped region 301 of the absorption layer 3 is greater than the width of the bottom edge of the absorption layer 3, or as... Figure 5 As shown, the width of the top doped region 301 of the absorption layer 3 is smaller than the width of the bottom edge of the absorption layer 3, but larger than the width of the second doped region 201.

[0058] 109: Top and bottom contact process.

[0059] 110: Subsequent processes.

[0060] The material of the absorption layer 3 is intrinsic Ge, N / P-type doped Ge, GeSi alloy, quantum dot material, bulk semiconductor material, or quantum hydrazine material, such as InGaAs quantum dot material or InP-based bulk semiconductor material. When the material of the absorption layer is N-type or P-type doped Ge, the N-type or P-type doping concentration is less than the doping concentration at the top and bottom of the absorption layer. The doping concentration at the bottom of the absorption layer refers to the doping concentration of the second waveguide layer. When the material of the absorption layer is a GeSi alloy, the present invention does not limit the ratio of the two materials.

[0061] The materials of the first waveguide layer 1 and the second waveguide layer 2 are materials that can be p-type or n-type doped, such as silicon, GaAs, and InP. The doping polarity of the first waveguide layer 1 and the second waveguide layer 2 is the same, that is, p-type doping or n-type doping; the doping polarity of the top of the absorbing layer 3 is opposite to that of the first waveguide layer 1 and the second waveguide layer 2.

[0062] In the fabrication method of this invention, a new waveguide layer, namely the second waveguide layer 2, is added, and P-type or N-type ions are injected into a portion of it to form a second doped region 201. At the same time, ion implantation is performed in the center and edge portions of the top layer of the absorption layer 3 to form a top doped region 301. The width of each doped region is specified accordingly. By selecting the width of the relevant doped region, the electric field in all or most areas inside the detector is strong under low bias or 0 bias, enabling the charge carriers to drift rapidly, thereby ensuring a sufficiently high bandwidth and avoiding the problem of easy breakdown in the edge region in traditional designs.

[0063] The manufacturing process provided by this invention, particularly for Ge detectors on silicon, is compatible with CMOS processes, and all process steps used are conventional, making it suitable for large-scale mass production.

[0064] Finally, the design and process provided by this invention are also applicable to other material systems, such as InP-based integrated chips.

[0065] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A high-speed waveguide detector, comprising: The first waveguide layer and the absorption layer are characterized in that they further include: a second waveguide layer located between the first waveguide layer and the absorption layer; The width of the doped region in the second waveguide layer is smaller than the width of the bottom edge of the absorption layer; The width of the top doped region of the absorption layer is greater than or equal to the width of the bottom edge of the absorption layer, or it is less than the width of the bottom edge of the absorption layer but greater than the width of the doped region of the second waveguide layer. The doped regions of the first waveguide layer and the doped regions of the second waveguide layer partially overlap.

2. The high-speed waveguide detector according to claim 1, characterized in that, A doped layer is disposed on top of the absorption layer. Ions are implanted into the doped layer to form the top doped region of the absorption layer, or ions are directly implanted into the upper surface layer of the absorption layer to form the top doped region.

3. A high-speed waveguide detector according to claim 2, characterized in that, The material of the absorption layer is intrinsic Ge, N / P type doped Ge, GeSi alloy, quantum dot material, semiconductor bulk material or quantum hydrazine material; When the material of the absorption layer is N / P type doped Ge, the doping concentration is less than the doping concentration at the top and bottom of the absorption layer.

4. A high-speed waveguide detector according to claim 3, characterized in that, The first waveguide layer and the second waveguide layer are made of materials that can be doped with P-type or N-type; the first waveguide layer and the second waveguide layer have the same doping polarity, both being P-type or N-type doped; the doping polarity of the top of the absorption layer is opposite to that of the first waveguide layer and the second waveguide layer.

5. A method for fabricating a high-speed waveguide detector, characterized in that, include: A second waveguide layer is epitaxially grown on the first waveguide layer, and the second waveguide layer is ion-doped. An absorption layer is epitaxially grown on the second waveguide layer, and ion doping is performed on the top of the absorption layer; Wherein, the width of the doped region of the second waveguide layer is smaller than the width of the bottom edge of the absorption layer; The width of the top doped region of the absorption layer is greater than or equal to the width of the bottom edge of the absorption layer, or it is less than the width of the bottom edge of the absorption layer but greater than the width of the doped region of the second waveguide layer. The doped regions of the first waveguide layer and the doped regions of the second waveguide layer partially overlap.

6. The method for fabricating a high-speed waveguide detector according to claim 5, characterized in that, The method also includes, prior to, ion doping of the first waveguide layer.

7. The method for fabricating a high-speed waveguide detector according to claim 6, characterized in that, The process of ion doping on the top of the absorption layer involves epitaxially growing a doped layer on the top of the absorption layer, implanting ions into the doped layer to form the top doped region of the absorption layer, or directly implanting ions into the upper surface layer of the absorption layer to form the top doped region.

8. The method for fabricating a high-speed waveguide detector according to claim 7, characterized in that, The material of the absorption layer is intrinsic Ge, N / P type doped Ge, GeSi alloy, quantum dot material, semiconductor bulk material or quantum hydrazine material; When the material of the absorption layer is N / P type doped Ge, the doping concentration is less than the doping concentration at the top and bottom of the absorption layer.

9. The method for fabricating a high-speed waveguide detector according to claim 8, characterized in that, The first waveguide layer and the second waveguide layer are made of materials that can be doped with P-type or N-type; the first waveguide layer and the second waveguide layer have the same doping polarity, both being P-type or N-type doped; the doping polarity of the top of the absorption layer is opposite to that of the first waveguide layer and the second waveguide layer.

Images