System on chip, control method and electronic device

Abstract

The application relates to a system on chip, a control method and electronic equipment, and belongs to the chip technical field.The system on chip comprises a working module, a control module and a clock module;the clock module is configured to provide a clock signal for the working module; and the control module is configured to control the clock module to stop providing the clock signal for the working module in the case that it is determined that the working module enters a sleep state.Through the above scheme, the control module is added to the system on chip, so that after the working module enters the sleep state, the control module sends a signal to the clock module, so that the clock corresponding to the working module in the clock module stops, the clock signal is no longer provided for the working module, and the power consumption caused by the sending of the clock signal is saved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a system-on-a-chip, a control method, and an electronic device. Background Technology

[0002] Wearable devices are widely used due to their rich functionality, good effects, and performance. However, because wearable devices are generally small in size, their power consumption is also small, and battery life is an important indicator of wearable devices. Therefore, the power consumption of wearable devices plays a crucial role in product quality.

[0003] In related technologies, power consumption is generally reduced through software configuration. For example, by configuring the working modules in the system through software, the working modules can automatically enter a sleep state when the task is completed, thereby reducing the power consumption caused by the working modules.

[0004] The aforementioned technologies still cannot meet the energy-saving requirements. Summary of the Invention

[0005] This application provides a system-on-a-chip, a control method, and an electronic device that can save power consumption in the system-on-a-chip. The technical solution is as follows:

[0006] On the one hand, a system-on-a-chip is provided, the system-on-a-chip including: a working module, a control module and a clock module;

[0007] The clock module is configured to provide a clock signal to the working module;

[0008] The control module is configured to control the clock module to stop providing the clock signal to the working module when it is determined that the working module has entered a sleep state.

[0009] On the other hand, a signal control method is provided.

[0010] Get the working status of the working module;

[0011] Based on the determination that the working module has entered the first state, the supply of the first clock signal to the working module is stopped;

[0012] In response to determining that the working module has received a first external signal, a second clock signal is provided to the working module.

[0013] On the other hand, an electronic device is provided, which is provided with a system-on-a-chip as described in the above aspects.

[0014] On the other hand, a chip is provided that includes a system-on-a-chip as described above.

[0015] In this embodiment, by adding a control module to the system-on-a-chip, after the working module enters a sleep state, the control module sends a signal to the clock module to stop one of the clocks corresponding to the working module, thereby no longer providing a clock signal to the working module, thus saving the power consumption caused by sending the clock signal. Attached Figure Description

[0016] Figure 1 This application shows a schematic diagram illustrating the structure of a system-on-a-chip according to an exemplary embodiment.

[0017] Figure 2 This illustration shows a schematic diagram illustrating a switching mode of an on-chip system's operating scenarios, as shown in an exemplary embodiment of this application.

[0018] Figure 3 This application shows a schematic diagram illustrating the structure of a control module according to an exemplary embodiment.

[0019] Figure 4 A schematic diagram of a first logic circuit is shown in an exemplary embodiment of this application;

[0020] Figure 5 A schematic diagram of a first logic circuit is shown in an exemplary embodiment of this application;

[0021] Figure 6 A schematic diagram of a second logic circuit is shown in an exemplary embodiment of this application;

[0022] Figure 7 A schematic diagram of an on-chip system is shown in one exemplary embodiment of this application;

[0023] Figure 8 A schematic diagram of a third logic circuit is shown in an exemplary embodiment of this application;

[0024] Figure 9 A schematic diagram of a third logic circuit is shown in an exemplary embodiment of this application;

[0025] Figure 10 A flowchart illustrating a control method in an exemplary embodiment of this application is shown;

[0026] Figure 11 A schematic diagram of an electronic device is shown in an exemplary embodiment of this application. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0028] In this document, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the relevant data involved in this application can be data authorized by the user or fully authorized by all parties.

[0029] Please refer to Figure 1 The diagram illustrates an exemplary embodiment of a system-on-a-chip. The system-on-a-chip includes a working module 11, a control module 12, and a clock module 13.

[0030] This working module 11 is a module used for processing business within the on-chip system. For example, this working module 11 is a digital signal processor (DSP), a network processor (NPU), a central processing unit (CPU), or an internal or external device on the chip. After completing its task or in an idle state, this working module 11 can enter a sleep state to save system power consumption.

[0031] In some embodiments, the system-on-a-chip includes multiple working modules 11. During the operation of the system-on-a-chip, the working modules 11 switch between each other, and the working modules 11 switch between an active state and a dormant state. For example, see... Figure 2 This system-on-a-chip (SoC) is used in True Wireless Stereo (TWS) wireless earbuds. When operating, this SoC functions as follows: Figure 2 The illustrated operating scenarios include: playback, recording, phone call, Keyword Sporting (KWS), Active Noise Control (ANC) mode, sleep mode, and power-off mode. When the wireless earbuds switch between these operating scenarios during operation, the operating module 11 within the earbuds also switches based on these modes. For example, when playback is paused, it switches from playback mode to sleep mode; after recording is completed, it switches from recording mode to power-off mode, and so on.

[0032] In some embodiments, the process of the on-chip system switching from any working scenario to sleep mode can be implemented through software configuration. That is, the working scenario of the on-chip system is detected by software configuration, and in response to the detection that the task in the current working scenario has been completed, the working module 11 corresponding to the working scenario is set to sleep state, thereby reducing the power consumption of the working module 11 in the on-chip system.

[0033] The clock module 13 is configured to provide a clock signal to the working module 11. In some embodiments, the clock module 13 includes multiple clock sources, each clock source being used to send a clock signal to a working module 11 in the system-on-chip to ensure that the working module 11 can operate normally. The control module 12 is configured to control the clock module 13 to stop providing the clock signal to the working module 11 when it is determined that the working module 11 has entered a sleep state.

[0034] In this embodiment of the application, by adding a control module 12 to the system on the chip, after the working module 11 enters a sleep state, the control module 12 sends a signal to the clock module 13, so that the clock corresponding to the working module 11 in the clock module 13 stops running, thereby no longer providing a clock signal to the working module 11, thus saving the power consumption caused by sending the clock signal.

[0035] In some embodiments, the control module 12 is further configured to, in response to a first external signal for the working module 11, control the clock module 13 to provide the clock signal to the working module 11 when the working module 11 is in a sleep state and / or the clock module 13 stops providing the clock signal to the working module 11; the working module 11 is configured to switch from a sleep state to an active state in response to the clock signal.

[0036] The first external signal can be a signal generated based on external data or control flow. Accordingly, the control module 12 determines whether the working module 11 is externally triggered or receives external stimulation. For example, the control module 12 can receive signals triggered by timer interrupts, audio device interrupts, power management module (PMM) wake-up interrupts, watchdog timer (WDT) interrupts, mailbox interrupts, voice wake-up interrupts, neural network interrupts, or central processing unit interrupts. Accordingly, the control module 12 detects the signals generated by the aforementioned interrupts, and in response to detecting the corresponding terminal, wakes up the clock source corresponding to the working module 11 so that it sends a clock signal to the working module 11, thereby waking up the working module 11 and enabling it to operate normally.

[0037] In this embodiment of the application, when the clock module 13 stops sending clock signals to the working module 11, the control module 12 detects the first external signal of the working module 11, so that when the working module 11 needs to work, even if the clock source corresponding to the working module 11 is suspended, the working module 11 can be woken up in time to ensure the normal operation of the system.

[0038] In some embodiments, the control module 12 includes a first logic circuit 121 and a second logic circuit 122. See also... Figure 3 The control module 12 is a logic circuit module, and the output terminal of the first logic circuit 121 is connected to the input terminal of the second logic circuit 122.

[0039] In some embodiments, the first logic circuit 121 is further configured to output a second indication signal to the second logic circuit 122 upon receiving a first external signal; the second logic circuit 122 is configured to generate and output a second control signal based on the second indication signal to instruct the clock module 13 to provide the clock signal to the working module 11.

[0040] The first logic circuit 121 is configured to output a first indication signal to the second logic circuit 122 when it receives a first status signal. The first status signal indicates that the working module 11 has entered a sleep state.

[0041] See Figure 4 The first logic circuit 121 includes an OR gate circuit 1211, a first signal input terminal 1212, and an external signal input terminal 1213. The first signal input terminal 1212 is used to input a signal indicating the activation state of the working module 11. The first signal input terminal 1212 is connected to the first input terminal of the OR gate circuit 1211. The external signal input terminal 1213 is connected to the second input terminal of the OR gate circuit 1211. The output terminal of the OR gate circuit 1211 is connected to the second logic circuit 122.

[0042] The OR gate 1211 can be any logic circuit capable of performing an OR operation; however, in this embodiment, the OR gate 1211 is not specifically limited. Additionally, the signal input to the first signal input terminal 1212 (pwaitmode) indicates the activation state of the working module 11. For example, if the working module 11 is in a sleep state, this signal is automatically pulled high, with a level of 1; if the working module 11 is operating normally, the signal input to the first signal input terminal 1212 is 0. The external signal input terminal 1213 is used to input an external interrupt source. If the working module 11 is in a sleep state, the clock source corresponding to the working module 11 has stopped and does not send a clock signal to the working module 11. When any external terminal source provides a first external signal, the first external signal activates the clock source of the working module 11.

[0043] In some embodiments, the first logic circuit 121 further includes inputs for enable signals. Accordingly, see [link to relevant documentation]. Figure 5 The first logic circuit 121 includes an OR gate circuit 1211, a first signal input terminal 1212, an external signal input terminal 1213, an external signal integrator 1214, a first enable signal input terminal 1215, a NOT gate circuit 1216, and a NAND gate circuit 1217.

[0044] The first enable signal input terminal 1215 is connected to the input terminal of the NOT gate circuit 1216, the output terminal of the NOT gate circuit 1216 is connected to the first input terminal of the NAND gate circuit 1217, the first signal input terminal 1212 is connected to the second input terminal of the NAND gate circuit 1217, the output terminal of the NAND gate is connected to the first input terminal of the OR gate circuit 1211, the external signal input terminal 1213 includes input interfaces for various external signals, all of which are connected to the external signal integrator 1214, the output terminal of the external signal integrator 1214 is connected to the second input segment of the OR gate circuit 1211, and the output terminal of the OR gate circuit 1211 is connected to the second logic circuit 122.

[0045] The first enable signal input terminal 1215 (Pos_sw_en_dsp) is generally configured to 0, indicating that the clock source of the working module 11 can be stopped. The output terminal (Audio_dsp_clken) of the OR gate circuit 1211 is used to output a signal indicating whether the clock source stops or continues to operate. When the first enable signal input terminal 1215 (Pos_sw_en_dsp) is configured to 0, if the working module 11 enters a sleep state, this signal is 0 in the absence of an external terminal, and the clock source of the working module 11 will be stopped. The logic table of the control logic of the first logic circuit 121 is shown in Table 1.

[0046] Table 1

[0047]

[0048] Referring to Table 1, when the first enable signal input terminal 1215 is 0, if the first signal input terminal 1212 is a high-level signal 1 and there is no external signal input (external signal is 0) (Case 1), based on Figure 5 The logic circuit shown can determine that the output signal is 0, meaning that the clock module 13 will stop sending clock signals to the working module 11. However, in the case where the first signal input terminal 1212 is a high-level signal 1, but there is an external signal input (the external signal is 1) (case 2), based on... Figure 5 The logic circuit shown can determine that the output signal is 1, that is, the clock module 13 will send a clock signal to the working module 11. If the first signal input terminal 1212 is a low-level signal 0, regardless of whether there is an external signal input (the external signal is 0 or 1) (case 3), based on Figure 5 The logic circuit shown can determine that the output signal is 1, that is, the clock module 13 will send a clock signal to the working module 11. When the first enable signal input terminal 1215 is 1, the clock module 13 will always output a clock signal to the working module 11, regardless of the input signals of the first signal and the external signal.

[0049] In this embodiment, the logic circuit in the control module 12 judges each input signal, thereby enabling the control module 12 to control the clock module 13, which can stop the clock and send clock signals in a timely manner, saving the energy consumed by sending clock signals. Furthermore, it can wake up the clock module 13 in a timely manner and send signals to the working module 11, ensuring the normal operation of the system.

[0050] The second logic circuit 122 is configured to generate and output a first control signal based on the first indication signal, so as to instruct the clock module 13 to stop providing the clock signal to the working module 11.

[0051] The second logic circuit 122 is electrically connected to the output of the first logic circuit 121 and is configured to control the clock module 13. In response to the first indication signal, the first control signal corresponding to the first indication signal is sent to the clock module 13, and the clock module 13 stops providing clock signals to the working module 11.

[0052] In some embodiments, see Figure 6The second logic circuit 122 includes a switch signal input terminal 1221 and an AND gate circuit 1222; the first input terminal of the AND gate circuit 1222 is connected to the output terminal of the OR gate circuit 1211 of the first logic circuit 121; the second input terminal of the AND gate circuit 1222 is connected to the switch signal input terminal 1221; and the output terminal of the AND gate circuit 1222 is connected to the clock module 13.

[0053] The switch signal input terminal 1221 (Pd_clk_en_audio) is used to indicate the main switch of the clock module 13, and the default value is 1. The output terminal (Audio_dsp_clken) of the OR gate circuit 1211 of the first logic circuit 121 is connected to one channel of the AND gate circuit 1222. The output terminal (Clk_dsp) of the AND gate circuit 1222 is used to supply a signal for controlling the clock signal to the clock module 13. In some embodiments, please refer to... Figure 6 The second logic circuit 122 also includes an enable control signal for the working module 11, indicating that the clock source for controlling the working module 11 is allowed. The logic table of the control logic of the second logic circuit 122 is shown in Table 2.

[0054] Table 2

[0055]

[0056] Referring to Table 2, when the first enable signal input terminal 1215 is 1, if the output of the OR gate 1211 of the first logic circuit 121 is a high-level signal 1, and the enable control signal of the working module 11 is a high-level signal 1 (Case 1), based on Figure 6 The logic circuit shown can determine that the output signal is 1, meaning that the clock module 13 will send a clock signal to the working module 11. However, when the switch signal input terminal 1221 is a high-level signal 1 and the working module 11 enable control signal is a low-level signal 0 (case 2), based on... Figure 6 The logic circuit shown can determine that when the output signal is 0, the clock module 13 will stop sending clock signals to the working module 11. If the switch signal input terminal 1221 is a low-level signal 0, the clock module 13 will turn off and stop sending clock signals to the working module 11.

[0057] In this embodiment, the logic circuit in the control module 12 judges each input signal, thereby enabling the control module 12 to control the clock module 13, which can stop the clock and send clock signals in a timely manner, saving the energy consumed by sending clock signals. Furthermore, it can wake up the clock module 13 in a timely manner and send signals to the working module 11, ensuring the normal operation of the system.

[0058] In some embodiments, see Figure 7The system-on-chip also includes a subsystem 10 and a power management module 20. The subsystem 10 includes one or more of the working modules 11. The subsystem 10 can be any subsystem 10 in the system-on-chip, such as an audio subsystem (Audio SS), a communication subsystem (Communication SS), an image processing subsystem, a modem subsystem, etc.

[0059] The power management module 20 is configured to supply power to the subsystem 10; the control module 12 is configured to control the power management module 20 to stop supplying power to the subsystem 10 when all the working modules 11 of the subsystem 10 have entered a sleep state.

[0060] The control module 12 can determine whether each working module 11 in the subsystem 10 is in a sleep state, and then determine whether the subsystem 10 is in a sleep state (idle), thereby adaptively cutting off the power supply and further reducing the power consumption of the subsystem 10.

[0061] In some embodiments, the control module 12 receives the operating status and clock enable status of each working module 11 of the subsystem 10, such as NPU, DMA, I2S, SPI, I2C, and Timer clock signals, as well as access signals from other modules of the subsystem 10, CPU sleep status signals, etc., determines whether the system is in an idle state, and outputs this status to the system power management module 20. The power module can then determine whether to supply power to this subsystem 10.

[0062] For example, if the CPU of subsystem 10 is in sleep mode, and the NPU, Direct Memory Access (DMA), Inter-IC Sound (I2S), Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I2C), and Timer have stopped working, the control module 12 performs logical analysis on these states and outputs a signal indicating whether subsystem 10 is in sleep mode. This signal triggers the power management module 20 of the on-chip system, thereby shutting down the power supply to subsystem 10.

[0063] In this embodiment, when all the working modules 11 of the subsystem 10 do not need to work, the power management module 20 is notified by the status detection module, so that the power management module 20 can cut off the power in time, thereby further saving power consumption.

[0064] In some embodiments, the control module 12 also starts a timer after determining that the subsystem 10 is in a sleep state, and triggers the power management module 20 to stop supplying power only when the timer reaches a preset duration, thus preventing the subsystem 10 from being unable to complete subsequent tasks due to a sudden break.

[0065] In some embodiments, the control module 12 is further configured to, when the subsystem 10 is in a power-down state, upon receiving a second external signal for the working module 11, control the power management module 20 to supply power to the subsystem 10; and control the clock module 13 to provide the clock signal to the working module 11.

[0066] The principle by which the power management module 20 is controlled by the control module 12 to supply power to the subsystem 10 is the same as the principle by which the clock module 13 is controlled by the control module 12 to provide clock signals to the working module 11, and will not be repeated here.

[0067] In this embodiment, the control module 12 detects external signals of the subsystem 10, enabling the subsystem 10 to be woken up in time when it is powered off, thereby enabling timely service processing. This reduces the power consumption of the on-chip system while ensuring its normal operation.

[0068] In some embodiments, the control module 12 further includes a third logic circuit; the third logic circuit is configured to generate and output a third control signal based on the second status signal when the second status signal is received, so as to instruct the power management module 20 to stop supplying power to the subsystem 10, wherein the second status signal indicates that all working modules 11 of the subsystem 10 have entered a sleep state.

[0069] In some embodiments, the third logic circuit is further configured to generate and output a fourth control signal based on the second external signal upon receiving the second external signal, so as to instruct the power management module 20 to supply power to the subsystem 10 and to provide the clock signal to the working module 11 in the subsystem 10.

[0070] In some embodiments, see Figure 8 The third logic circuit includes a second signal input terminal 1231, a third signal input terminal 1232, and an AND gate circuit 1233. The second signal input terminal 1231 is used to input a signal indicating the activation state of the working module 11 of the subsystem 10, and the third signal input terminal 1232 is used to input a signal indicating the activation state of the clock module 13. The status signal input terminal of the working module 11 is connected to the first input terminal of the AND gate circuit 1233. The clock status signal input terminal is connected to the second input terminal of the AND gate circuit 1233. The output terminal of the AND gate circuit 1233 is connected to the power management module 20.

[0071] The signal input at the second signal input terminal 1231 (pwaitmode) is used to indicate the activation status of multiple working modules 11. For example, if a working module 11 is in sleep mode, this signal is automatically pulled high, with a level of 1; if a working module 11 is operating normally, the signal input at the first signal input terminal 1212 is 0. The third signal input terminal 1232 (IP enable signal) is used to receive multiple module enable signals, generally clock-related enable signals, which are input to the control module 12 to indicate that the module has received a clock signal and whether the module can operate. The output terminal (Audio_sys_idle) of the AND gate circuit 12331222 is used to output a signal. When the input signal meets the logic condition of the third circuit, this signal is high, with a level of 1, indicating that the subsystem 10 can enter sleep mode, and all working modules 11 within the subsystem 10 have stopped working or are in sleep mode.

[0072] In some embodiments, see Figure 9 The third logic circuit also includes a selection signal input terminal 1234, a path selector 1235, and a configuration signal input terminal 1236; the configuration signal input terminal 1236 is connected to the first input terminal of the path selector 1235; the output terminal of the AND gate circuit 1233 is connected to the second input terminal of the path selector 1235; the selection signal input terminal 1234 is connected to the third input terminal of the path selector 1235; and the output terminal of the path selector 1235 is connected to the power management module 20.

[0073] The selection signal input terminal 1234 (Audio_sys_idle_mode_sel) is used to select whether the subsystem 10 enters a sleep state via hardware or software control. The configuration signal input terminal 1236 is used to input a software configuration signal; when the software configuration signal is 1, the subsystem 10 is allowed to enter a sleep state. In some embodiments, the third logic circuit also includes an enable signal input terminal (Dsp_idle_en), which is normally configured to be 1, indicating that the subsystem 10 is allowed to enter a sleep state. The logic table of the control logic of this third logic circuit is shown in Table 3.

[0074] Table 3

[0075]

[0076] Referring to Table 3, when a high-level signal 1 is input to the selection signal input terminal 1234, the path selector 1235 selects to control the power management module 20 through the control module 12. When a low-level signal 0 is input to the selection signal input terminal 1234, the path selector 1235 selects to control the power management module 20 through software configuration.

[0077] When a high-level signal 1 is input to signal input terminal 1234, and subsystem 10 is allowed to enter sleep mode, if the signal input to second signal input terminal 1231 is a high-level signal 1, and the signal input to third signal input terminal 1232 is a low-level signal 0, that is, when working module 11 is in sleep mode and no clock signal is sent to multiple modules (case 1), based on Figure 7 The logic circuit shown can determine that the output signal is 1, that is, the power management module 20 stops supplying power to the subsystem 10.

[0078] In this embodiment, when all the working modules 11 of the subsystem 10 do not need to work, the power management module 20 is notified by the status detection module, so that the power management module 20 can cut off the power in time, thereby further saving power consumption.

[0079] In this embodiment, by adding a control module to the system-on-a-chip, after the working module enters a sleep state, the control module sends a signal to the clock module to stop one of the clocks corresponding to the working module, thereby no longer providing a clock signal to the working module, thus saving the power consumption caused by sending the clock signal.

[0080] See Figure 10 The diagram illustrates a flowchart of a control method shown in an exemplary embodiment of this application.

[0081] The method includes:

[0082] Step S1001: The electronic device acquires the working status of the working module.

[0083] This operating state includes a first state and a second state. The module operates in the first state and ceases operation in the second state. For example, the first state is the operating state, and the second state is the sleep state.

[0084] Step S1002: Based on the determination that the working module has entered the first state, the electronic device stops providing the first clock signal to the working module.

[0085] The first state includes sleep state, power-off state, and abnormal state. In the first state, the working module stops working, and correspondingly, the electronic device does not provide the first clock signal to the working module.

[0086] Step S1003: In response to determining that the working module has received a first external signal, the electronic device provides a second clock signal to the working module.

[0087] The first external signal can be a stimulus signal provided by any terminal source, used to instruct the working module to activate. The second clock signal is used to activate the working module.

[0088] In some embodiments, the method further includes:

[0089] Based on the determination that the working module has entered the first state, the electronic device reduces the power supply to at least one subsystem associated with the working module.

[0090] In some embodiments, when the working module enters a first state, the electronic device stops supplying power to the working module, thereby reducing the power supply to at least one subsystem associated with the working module. In some embodiments, the electronic device stops supplying power to at least one subsystem associated with the working module, thereby reducing the power supply to at least one subsystem associated with the working module.

[0091] In this embodiment of the application, by reducing the power supply of at least one subsystem associated with the working module that enters the first state, the power consumption of the electronic device is reduced, thereby increasing the battery life of the electronic device.

[0092] In this embodiment, by acquiring the working state of the working module, after the working module enters the first state, the first clock signal is stopped from being provided to the working module. When the first external signal is received, the working module is woken up by the second clock signal so that it can work normally. In this way, the clock signal provided to the working module is adjusted in a timely manner based on the working state of the working module. While ensuring the normal operation of the working module, the power consumption of providing the clock signal can be reduced in a timely manner, thereby saving the power consumption of the electronic device.

[0093] See Figure 11 This illustration shows a schematic diagram of an electronic device provided in an exemplary embodiment. The electronic device 1100 can be a wearable device, such as a Bluetooth headset, watch, glasses, etc. Alternatively, the electronic device 1100 can be a terminal such as a smartphone, tablet computer, etc. The electronic device 1100 in this application may include one or more of the following components: processor 1110, memory 1120, and system-on-a-chip 1130130.

[0094] Processor 1110 may include one or more processing cores. Processor 1110 connects to various parts within the electronic device 1100 using various interfaces and lines, and performs various functions and processes data of the electronic device 1100 by running or executing instructions, programs, code sets, or instruction sets stored in memory 1120, and by calling data stored in memory 1120. Optionally, processor 1110 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). Processor 1110 may integrate one or more of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and modem. Specifically, the CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display on the screen; the NPU is used to implement Artificial Intelligence (AI) functions; and the modem is used for wireless communication. It is understandable that the aforementioned modem may not be integrated into the processor 1110, but may be implemented using a separate chip.

[0095] The memory 1120 may include random access memory (RAM) or read-only memory. Optionally, the memory 1120 may include a non-transitory computer-readable storage medium. The memory 1120 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 1120 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the various method embodiments described below, etc.; the data storage area may store data created based on the use of the electronic device 1100 (such as audio data, telephone directory, etc.).

[0096] The system-on-chip 1130 is electrically connected to other components in the electronic device 1100.

[0097] The electronic device 1100 may further include a display screen, which is a display component for displaying a user interface. Optionally, the display screen is a touch-enabled display screen, through which the user can use a finger, stylus, or any suitable object to perform touch operations on the display screen. The display screen is typically located on the front panel of the electronic device 1100. The display screen can be designed as a full-screen, curved screen, irregularly shaped screen, dual-sided screen, or foldable screen. The display screen can also be designed as a combination of a full-screen and a curved screen, or a combination of an irregularly shaped screen and a curved screen, etc., which are not limited in this embodiment.

[0098] In addition, those skilled in the art will understand that the structure of the electronic device 1100 shown in the above figures does not constitute a limitation on the electronic device 1100. The electronic device 1100 may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, the electronic device 1100 may also include components such as a microphone, speaker, radio frequency circuit, input unit, sensor, audio circuit, power supply, and Bluetooth module, which will not be described in detail here.

[0099] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0100] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A system on chip, characterized by The system-on-chip comprises a working module, a control module and a clock module; The clock module is configured to provide a clock signal for the working module; The control module is configured to control the clock module to stop providing the clock signal for the working module in a case where it is determined that the working module enters a sleep state; The control module comprises: A first logic circuit configured to output a first indication signal to a second logic circuit in a case where a first state signal is received, the first state signal indicating that the working module enters a sleep state; The second logic circuit is configured to generate and output a first control signal based on the first indication signal to instruct the clock module to stop providing the clock signal for the working module; The first logic circuit is further configured to output a second indication signal to the second logic circuit in a case where a first external signal is received; The second logic circuit is configured to generate and output a second control signal based on the second indication signal to instruct the clock module to provide the clock signal for the working module.

2. The system-on-chip of claim 1, wherein, The control module is further configured to control the clock module to provide the clock signal for the working module in response to a first external signal for the working module in a case where the working module is in a sleep state and / or the clock module stops providing the clock signal for the working module; The working module is configured to switch from a sleep state to an active state in response to the clock signal.

3. The system on chip of claim 1, wherein, The first logic circuit comprises an OR gate circuit, a first signal input terminal and an external signal input terminal, the first signal input terminal being configured to input a signal indicating an active state of the working module; The first signal input terminal is connected with a first input terminal of the OR gate circuit; The external signal input terminal is connected with a second input terminal of the OR gate circuit; An output terminal of the OR gate circuit is connected with the second logic circuit.

4. The system-on-chip of claim 3, wherein, The second logic circuit comprises a switch signal input terminal and an AND gate circuit; A first input terminal of the AND gate circuit is connected with an output terminal of the OR gate circuit of the first logic circuit; A second input terminal of the AND gate circuit is connected with the switch signal input terminal; An output terminal of the AND gate circuit is connected with the clock module.

5. The system on chip of claim 1, wherein, The system-on-chip further comprises a subsystem and a power management module, the subsystem comprising one or more working modules; The power management module is configured to supply power for the subsystem; The control module is configured to control the power management module to stop supplying power for the subsystem in a case where all working modules of the subsystem enter a sleep state.

6. The system on chip of claim 5, wherein, The control module is further configured to control the power management module to supply power for the subsystem based on a second external signal for the working module in a case where the subsystem is in a power-off state; and control the clock module to provide the clock signal for the working module.

7. The system-on-chip of claim 5, wherein, The control module further comprises a third logic circuit; The third logic circuit is configured to generate and output a third control signal based on a second state signal to instruct the power management module to stop supplying power to the subsystem, in a case that the second state signal is received, the second state signal indicating that all working modules of the subsystem enter a sleep state.

8. The system-on-chip of claim 7, wherein, The third logic circuit is further configured to generate and output a fourth control signal based on a second external signal to instruct the power management module to supply power to the subsystem and provide the clock signal to the working modules in the subsystem, in a case that the second external signal is received.

9. The system on chip of claim 7, wherein, The third logic circuit comprises a second signal input terminal for inputting a signal indicating an activation state of the working modules of the subsystem, a third signal input terminal for inputting a signal indicating an activation state of the clock module, and an AND gate circuit; The state signal input terminal of the working module is connected with a first input terminal of the AND gate circuit; The state signal input terminal of the clock module is connected with a second input terminal of the AND gate circuit; An output terminal of the AND gate circuit is connected with the power management module.

10. The system-on-chip of claim 9, wherein, The third logic circuit further comprises a selection signal input terminal, a path selector, and a configuration signal input terminal; The configuration signal input terminal is connected with a first input terminal of the path selector; An output terminal of the AND gate circuit is connected with a second input terminal of the path selector; A selection signal input terminal is connected with a third input terminal of the path selector; An output terminal of the path selector is connected with the power management module.

11. A signal control method characterized by comprising: The method comprises: acquiring a working state of a working module; stopping providing a first clock signal to the working module based on determining that the working module enters a first state; providing a second clock signal to the working module in response to determining that the working module receives a first external signal; The method further comprises: based on determining that the working module enters the first state, reducing power supply to at least one subsystem associated with the working module. The electronic device is provided with a system on chip as claimed in any one of claims 1-10. The method comprises: acquiring a working state of a working module; stopping providing a first clock signal to the working module based on determining that the working module enters a first state; 12. The method of claim 11, wherein, providing a second clock signal to the working module in response to determining that the working module receives a first external signal; The method further comprises:

13. An electronic device, comprising: based on determining that the working module enters the first state, reducing power supply to at least one subsystem associated with the working module. The electronic device is provided with a system on chip as claimed in any one of claims 1-10.

14. A chip, characterized by The chip comprises a system on chip as claimed in any of claims 1-10. The chip comprises a system on chip as claimed in any of claims 1-10.

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