A circuit architecture for single-hot transfer of an implementation circuit based on a ring network

Abstract

The application discloses a circuit architecture for realizing single-hot transfer of a circuit based on a ring network, comprising a region division unit, a hot spot unit and a processing unit, wherein the region division unit comprises an FPGA chip, the FPGA chip divides multiple space regions and performs octal coding on the space regions, the multiple space regions are distributed in a ring array, each space region corresponds to a processing unit, and the hot spot unit and the processing unit are correspondingly arranged; the region division unit, the hot spot unit and the processing unit are matched, the FPGA chip of the region division unit makes the circuit architecture more complex, even if the circuit architecture is cracked, the specific circuit meaning is difficult to understand, the information representation method based on the FPGA single-hot distribution is more difficult to crack, the probability of information leakage is reduced, and the security of the circuit is improved.

Description

Technical Field

[0001] This invention belongs to the field of circuit single hotspot transmission technology, specifically relating to a circuit architecture based on a ring network for realizing circuit single hotspot transmission. Background Technology

[0002] Research on circuit architectures for single-hotspot propagation originates from information representation using FPGA single-hotspots. Information representation methods based on FPGA single-hotspot distribution divide the FPGA chip's spatial region and constrain circuit layout to create temperature differences between different parts of the circuit during operation, thereby utilizing the location of the hotspots to achieve information representation.

[0003] Based on the information representation method of FPGA single hotspot distribution, an information representation method based on the transmission order of FPGA single hotspot is proposed, so that the lighting of hotspots in the heat distribution map has a certain transmission order to express information.

[0004] However, the circuit architecture used to achieve the single hotspot transmission sequence was too straightforward. It controlled the order in which the hotspots lit up by directly connecting the control module to the hotspot unit. Once the circuit architecture was cracked, the probability of information leakage was relatively high, posing certain security risks. Summary of the Invention

[0005] The purpose of this invention is to provide a circuit architecture for realizing single hotspot transmission based on a ring network. Through the cooperation of a region partitioning unit, a hotspot unit, and a processing unit, wherein the region partitioning unit is an FPGA chip, the circuit architecture is made more complex, so as to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A circuit architecture for single hotspot transmission based on a ring network includes a region partitioning unit, a hotspot unit, and a processing unit. The region partitioning unit includes an FPGA chip. The FPGA chip divides multiple spatial regions and encodes the spatial regions in octal. The multiple spatial regions are distributed in a ring array. Each spatial region corresponds to a processing unit, and the hotspot unit and the processing unit are configured in a corresponding manner.

[0008] Preferably, after the spatial region is divided, the FPGA chip arranges hotspot circuits and corresponding network nodes in each target spatial region, and designs the network node processing and control information in the data packet header so that the control information can be transmitted in the ring network.

[0009] Preferably, when the FPGA chip is arranging the hotspot circuit, it generates a temperature difference between the working space area and other space areas according to the control information, so that the generated heat distribution map is distinguishable and it is easy to observe the hotspots of the FPGA being transmitted in sequence.

[0010] Preferably, the control information is carried by a data packet and the complete control information transmission sequence is encoded in 8421 BCD code.

[0011] Preferably, the network node includes a header flit, a body flit, and a data packet. The header flit contains the node address of the starting hotspot, the body flit carries encoded information, and the data packet is transmitted through a ring network.

[0012] Preferably, after receiving the information according to the address, the network node transmits the data packet to the processing unit. After receiving the data packet, the processing unit, in addition to timing the lighting of the hotspot unit, also needs to send a new data packet to the ring network. The processing unit uses the next address data in the body-flit data as the transmission address of the new data packet, as part of the header-flit. At the same time, the body-flit data in the original data packet is shifted so that the new destination address is located in the highest bit of the data.

[0013] Preferably, the processing unit uses a synthesis tool to convert the circuit information into a bit stream file, configures it into the FPGA, detects the temperature of the FPGA chip using a thermal imager, observes the heat distribution map, and determines the content of the information based on the changes in hot spots.

[0014] Preferably, the hotspot unit observes the transmission order of a single hotspot using a thermal imager, and decodes it according to the decoding scheme based on the transmission order to obtain representation information.

[0015] The circuit architecture for single-hotspot propagation based on a ring network proposed in this invention has the following advantages compared with the prior art:

[0016] This invention utilizes the cooperation of a region partitioning unit, a hotspot unit, and a processing unit. The region partitioning unit, an FPGA chip, makes the circuit architecture more complex. Even if the circuit architecture is cracked, the specific circuit meaning is difficult to understand. Furthermore, the information representation method based on the FPGA single hotspot distribution is more difficult to crack, reducing the probability of information leakage and improving circuit security. Attached Figure Description

[0017] Figure 1 This is a circuit architecture diagram of the present invention;

[0018] Figure 2 This is a schematic diagram of the spatial region division layout of the present invention;

[0019] Figure 3 This is a schematic diagram of the hotspot transmission path of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The specific embodiments described herein are merely used to explain the present invention and are not intended to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] This invention provides, for example Figure 1-3 The circuit architecture shown is based on a ring network to realize single hot spot transmission. It includes a region division unit, a hot spot unit and a processing unit. The region division unit includes an FPGA chip. The FPGA chip divides multiple spatial regions and encodes the spatial regions in octal. The multiple spatial regions are distributed in a ring array. Each spatial region corresponds to a processing unit, and the hot spot unit and the processing unit are set in a corresponding manner.

[0022] After the spatial region of the FPGA chip is divided, network nodes are arranged for each region based on a ring topology. Then, the control information for lighting up hotspots is transmitted in the ring network, so that the hotspots in the heat distribution map are lit up in the transmission order to express specific information.

[0023] After the FPGA chip is divided into spatial regions, hotspot circuits and corresponding network nodes are arranged in each target spatial region. The network node processing and control information are designed in the data packet header, so that the control information can be transmitted in the ring network. This method makes the circuit architecture more complex. Even if the circuit architecture is cracked, the specific circuit meaning is difficult to understand. The information representation method based on the FPGA single hotspot distribution is also more difficult to crack, and the security is higher.

[0024] When FPGA chips are arranged with hotspot circuits, they generate temperature differences between the working space area and other space areas according to control information, so that the generated thermal distribution map is distinguishable and easy to observe the hotspots of the FPGA being passed in sequence, such as 01234567. Based on this, the hotspot unit observes the transmission order of a single hotspot through a thermal imager, and decodes it according to the decoding scheme according to the transmission order to obtain the representation information.

[0025] Control information is carried in data packets and the complete control information transmission sequence is encoded in 8421 BCD code.

[0026] A network node consists of a header flit, a body flit, and data packets. The header flit contains the node address of the starting hotspot, the body flit carries encoded information, and the data packets are transmitted through the ring network.

[0027] After receiving the information based on the address, the network node transmits the data packet to the processing unit. After receiving the data packet, the processing unit, in addition to timing and lighting up the hotspot unit, also needs to send a new data packet to the ring network. The processing unit uses the next address data in the body-flit data as the transmission address of the new data packet, as part of the header-flit. At the same time, it shifts the body-flit data in the original data packet so that the new destination address is located in the highest bit of the data.

[0028] The processing unit uses synthesis tools to convert circuit information into a bit stream file, configures it into the FPGA, and then uses a thermal imager to detect the temperature of the FPGA chip, observes the heat distribution map, and determines the content of the information based on the changes in hot spots.

[0029] The FPGA chip used is a Xilinx XC7A100T FPGA. Taking the implementation of multiply-accumulate operations based on DSP as a hotspot unit as an example, the specific implementation process of this invention is described below:

[0030] Similar to the information representation of the single hotspot transmission order through direct connection of the control module to the hotspot unit, in situations such as Figure 2 Based on the physical layout, in order to enable the DSP circuit to generate sufficient power consumption and ensure that the generated heat distribution map has good resolution, each hot spot unit is a one-dimensional discrete convolution operation with 16-bit input, and the input polynomial has 4 terms, resulting in seven 32-bit outputs.

[0031] Control information is carried in data packets, and the complete control information transmission sequence is encoded in 8421 BCD code. For example, 01234567 is encoded as 0000_0001_0010_0011_0100_0101_0110_0111. The header flit contains the node address of the starting hotspot (0000), and the body flit carries the encoded information. The data packets are transmitted through the ring network.

[0032] After receiving the information based on the address, the starting network node (000) transmits the data to the processing unit. Upon receiving the data packet, the processing unit, in addition to timing the activation of the hotspot units, also needs to send a new data packet to the ring network. The processing unit uses the next address data (0001) in the body-flit data as the transmission address of the new data packet, as part of the header-flit. Simultaneously, it shifts the body-flit data in the original data packet so that the new destination address is located in the highest bit of the data, i.e., 0001_0010_0011_0100_0101_0110_0111_0000. This method enables the transmission of control information, activating each hotspot sequentially.

[0033] Circuit information is converted into a bitstream file using a synthesis tool, configured into an FPGA, and then the temperature of the FPGA chip is detected using a thermal imager to observe the heat distribution map. The information content is determined based on changes in hot spots. This invention explores the hot spot transmission sequence from 0 to 7. Under the condition of adjusting the circuit voltage to 1V, the following results are obtained. Figure 3 As shown, the circuit architecture can effectively transmit 4×2 hotspots in the target order to obtain a custom information representation.

[0034] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A circuit architecture for implementing single hotspot propagation based on a ring network, comprising a region partitioning unit, a hotspot unit, and a processing unit, characterized in that: The region division unit includes an FPGA chip, which divides multiple spatial regions and encodes the spatial regions in octal. The multiple spatial regions are arranged in a ring array, and each spatial region corresponds to a processing unit. The hot spot unit and the processing unit are set in a corresponding manner. After the spatial region is divided, the FPGA chip arranges hotspot circuits and corresponding network nodes in each target spatial region, and designs the network node processing and control information in the data packet header so that the control information can be transmitted in the ring network. The network node includes a header flit, a body flit, and a data packet. The header flit contains the node address of the starting hotspot, the body flit carries encoded information, and the data packet is transmitted through a ring network. After receiving the information according to the address, the network node transmits the data packet to the processing unit. After receiving the data packet, the processing unit, in addition to timing and lighting up the hotspot unit, also needs to send a new data packet to the ring network. The processing unit uses the next address data in the body-flit data as the transmission address of the new data packet, as part of the header-flit. At the same time, it shifts the body-flit data in the original data packet so that the new destination address is located in the highest bit of the data.

2. The circuit architecture for single-hotspot propagation based on a ring network according to claim 1, characterized in that: When arranging hotspot circuits, the FPGA chip generates a temperature difference between the working space area and other space areas according to the control information, so that the generated heat distribution map is distinguishable and it is easy to observe the hotspots of the FPGA being transmitted in sequence.

3. The circuit architecture for single-hotspot propagation based on a ring network according to claim 2, characterized in that: The control information is carried by data packets and the complete control information transmission sequence is encoded in 8421 BCD code.

4. The circuit architecture for single-hotspot propagation based on a ring network according to claim 1, characterized in that: The processing unit uses a synthesis tool to convert circuit information into a bit stream file, configures it into the FPGA, and then uses a thermal imager to detect the temperature of the FPGA chip, observes the heat distribution map, and determines the content of the information based on the changes in hot spots.

5. The circuit architecture for single-hotspot propagation based on a ring network according to claim 1, characterized in that: The hotspot unit observes the transmission order of a single hotspot using a thermal imager, and decodes it according to the decoding scheme based on the transmission order to obtain representation information.

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