Driving circuit and control method thereof, and display panel

Abstract

The present invention discloses a driving circuit, a control method thereof, and a display panel. The driving circuit includes: at least one switching module, each switching module including: a first transistor and a threshold voltage adjustment unit, the first transistor being a vertical dual-gate transistor including a first gate, a second gate, a first electrode, and a second electrode; the threshold voltage adjustment unit including a first feedback subunit and / or a second feedback subunit; when the first transistor is turned off, the first electrode of the first transistor is connected to the second gate via the conductive first feedback subunit to improve the off-state performance of the first transistor; when the first transistor is turned on, the first gate of the first transistor is connected to the second gate via the conductive second feedback subunit to improve the on-state performance of the first transistor. Embodiments of the present invention can improve the output stability of the driving circuit and enhance the display effect.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a driving circuit and a control method thereof, and a display panel. Background Art

[0002] With the development of display technology, display panels are gradually developing in the direction of being light, thin, low power consumption and low cost. Taking the drive circuit as a scanning circuit as an example, in order to reduce the manufacturing cost of the display panel and achieve a narrow frame, GIP (Gate in Panel) technology is usually adopted in the manufacturing process of the display panel to directly integrate the drive circuit on the display panel. However, due to the influence of transistor threshold voltage offset and transistor leakage, the waveform of the drive signal output by the drive circuit will be distorted. For example, the distortion of the scanning signal will affect the opening and closing of the transistor in the pixel circuit, resulting in abnormal display of the display panel. In summary, the existing drive circuit has the problem of poor output stability. Summary of the Invention

[0003] The present invention provides a driving circuit and a control method thereof, and a display panel, so as to improve the output stability of the driving circuit and enhance the display effect.

[0004] In a first aspect, an embodiment of the present invention provides a driving circuit, comprising: at least one switch module, wherein any switch module comprises:

[0005] A first transistor, the first transistor is a vertical double-gate transistor, and the first transistor includes a first gate, a second gate, a first electrode, and a second electrode;

[0006] A threshold voltage adjustment unit, the threshold voltage adjustment unit includes a first feedback subunit and / or a second feedback subunit; the first feedback subunit is connected between the first electrode and the second gate of the first transistor, and is used to connect the first electrode of the first transistor to the second gate via the conductive first feedback subunit when the first transistor is turned off, so as to improve the off-state performance of the first transistor; the second feedback subunit is connected between the first gate and the second gate of the first transistor, and is used to connect the first gate of the first transistor to the second gate via the conductive second feedback subunit when the first transistor is turned on, so as to improve the on-state performance of the first transistor.

[0007] Optionally, the first feedback subunit includes a first feedback control terminal, and the second feedback subunit includes a second feedback control terminal;

[0008] The first feedback control terminal is electrically connected to the second electrode of the first transistor, and the second feedback control terminal is electrically connected to the first gate of the first transistor;

[0009] Alternatively, the first feedback control terminal is electrically connected to the second gate of the first transistor, and the second feedback control terminal is electrically connected to the first electrode of the first transistor or the first gate of the first transistor.

[0010] Optionally, the driving circuit further includes: an input control module, a first output module and a second output module;

[0011] The first output module is connected to the input control module, and the first output module outputs a first signal to the output end of the driving circuit according to the control of the input control module; the second output module is connected to the input control module, and the second output module outputs a second signal to the output end of the driving circuit according to the control of the input control module;

[0012] Wherein, at least one switch module includes a first switch module and / or a second switch module, the first output module includes the first switch module, and / or the second output module includes the second switch module.

[0013] Optionally, the first output module includes a first switch module, and the threshold voltage adjustment unit of the first switch module includes a first feedback subunit and / or a second feedback subunit;

[0014] In the first switch module, the first feedback control terminal is electrically connected to the second electrode of the first transistor, and / or the second feedback control terminal is electrically connected to the first gate of the first transistor;

[0015] Optionally, the second electrode of the first transistor in the first switch module is electrically connected to the output end of the driving circuit;

[0016] Optionally, the first electrode of the first transistor in the first switch module is electrically connected to the first potential signal line.

[0017] Optionally, the second output module includes a second switch module, and the threshold voltage adjustment unit of the second switch module includes a first feedback subunit and / or a second feedback subunit;

[0018] In the second switch module, the second electrode of the first transistor is electrically connected to the second potential signal line; the first feedback control terminal is electrically connected to the second gate of the first transistor, and / or the second feedback control terminal is electrically connected to the first electrode of the first transistor or the first gate of the first transistor;

[0019] or,

[0020] In the second switch module, the second electrode of the first transistor is electrically connected to the first clock signal line; the first feedback control terminal is electrically connected to the second gate of the first transistor, and / or the second feedback control terminal is electrically connected to the first electrode of the first transistor;

[0021] Optionally, the first electrode of the first transistor in the second switch module is electrically connected to the output end of the drive circuit.

[0022] Optionally, the input control module includes: a first input unit, a second input unit, a node potential control unit and a first node mutual control unit;

[0023] The control end of the first input unit is connected to the first clock signal, the input end of the first input unit is connected to the input signal, and the output end of the first input unit is electrically connected to the second output module; the first control end of the second input unit is connected to the input signal, the second control end of the second input unit is connected to the first clock signal, and the input end of the second input unit is connected to the first potential signal; the control end of the node potential control unit is electrically connected to the output end of the second input unit, the input end of the node potential control unit is connected to the second clock signal, and the output end of the node potential control unit is electrically connected to the first output module; the control end of the first node mutual control unit is electrically connected to the output end of the first input unit, the input end of the first node mutual control unit is connected to the first potential signal, and the output end of the first node mutual control unit is electrically connected to the first output module;

[0024] Alternatively, the input control module includes: a first input unit, a second input unit, a node potential control unit, and a first node mutual control unit;

[0025] The control end of the first input unit is connected to the input signal, the input end of the first input unit is connected to the second potential signal, and the output end of the first input unit is electrically connected to the second output module; the first control end of the second input unit is connected to the input signal, the second control end of the second input unit is connected to the first clock signal, and the input end of the second input unit is connected to the first potential signal; the control end of the node potential control unit is electrically connected to the output end of the second input unit, the input end of the node potential control unit is connected to the second clock signal, and the output end of the node potential control unit is electrically connected to the first output module; the control end of the first node mutual control unit is electrically connected to the output end of the first input unit, the input end of the first node mutual control unit is connected to the first potential signal, and the output end of the first node mutual control unit is electrically connected to the first output module.

[0026] Optionally, the first feedback subunit includes: a second transistor; the gate of the second transistor serves as the first feedback control terminal, the first electrode of the second transistor is electrically connected to the first electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the second gate of the first transistor;

[0027] The second feedback subunit includes: a third transistor; the gate of the third transistor serves as a second feedback control terminal, the first electrode of the third transistor is electrically connected to the first gate of the first transistor, and the second electrode of the third transistor is electrically connected to the second gate of the first transistor;

[0028] Optionally, the first transistor is an N-type transistor; when the first gate of the first transistor is connected to the second gate via the conductive second feedback subunit, the threshold voltage of the first transistor is negatively biased; when the first gate of the first transistor is connected to the first electrode via the conductive first feedback subunit, the threshold voltage of the first transistor is positively biased;

[0029] Optionally, the first transistor is a P-type transistor; when the first gate of the first transistor is connected to the second gate through the conductive second feedback sub-unit, the threshold voltage of the first transistor is positively biased; when the first gate of the first transistor is connected to the first pole through the conductive first feedback sub-unit, the threshold voltage of the first transistor is negatively biased.

[0030] Accordingly, an embodiment of the present invention further provides a control method for a driving circuit, wherein the driving circuit includes: at least one switching module, wherein any switching module includes: a first transistor and a threshold voltage adjustment unit; the first transistor is a vertical dual-gate transistor, and the first transistor includes a first gate, a second gate, a first electrode, and a second electrode; the threshold voltage adjustment unit includes a first feedback subunit and / or a second feedback subunit; the first feedback subunit is connected between the first electrode and the second gate of the first transistor; and the second feedback subunit is connected between the first gate and the second gate of the first transistor;

[0031] The control method of the driving circuit includes: a first operating mode and / or a second operating mode;

[0032] In the first working mode, the first transistor is controlled to be turned off, and the first feedback subunit is controlled to be turned on, so that the first electrode of the first transistor is connected to the second gate via the turned-on first feedback subunit, so as to improve the off-state performance of the first transistor;

[0033] In the second working mode, the first transistor is controlled to be turned on, and the second feedback subunit is controlled to be turned on, so that the first gate of the first transistor is connected to the second gate via the turned-on second feedback subunit, so as to improve the on-state performance of the first transistor.

[0034] Optionally, the drive circuit further includes: an input control module, a first output module, and a second output module; the first output module is connected to the input control module; the second output module is connected to the input control module; wherein, at least one switch module includes a first switch module and / or a second switch module, the first output module includes the first switch module, and / or the second output module includes the second switch module; and the control method includes:

[0035] The first output module outputs a first signal to the output end of the driving circuit according to the control of the input control module; at this time, the first switch module operates in the second operating mode, and / or the second switch module operates in the first operating mode;

[0036] The second output module outputs a second signal to the output end of the driving circuit according to the control of the input control module; at this time, the first switch module operates in the first operating mode, and / or the second switch module operates in the second operating mode;

[0037] Optionally, in the same switch module, when the first feedback subunit is turned on, the second feedback subunit is turned off; when the second feedback subunit is turned on, the first feedback subunit is turned off.

[0038] Correspondingly, an embodiment of the present invention further provides a display panel, characterized in that it includes the driving circuit provided by any embodiment of the present invention.

[0039] A driving circuit provided in an embodiment of the present invention is provided with at least one switching module, which includes a first transistor and a threshold voltage adjustment unit. The threshold voltage adjustment unit includes a first feedback subunit and / or a second feedback subunit. The first feedback subunit is connected between the second gate and the first electrode of the first transistor, and can adjust the threshold voltage of the first transistor when the first transistor is turned off, thereby ensuring that the first transistor is reliably turned off. And / or, the second feedback subunit is connected between the second gate and the first gate of the first transistor, and can adjust the threshold voltage of the first transistor when the first transistor is turned on, thereby ensuring that the first transistor is reliably turned on. The first transistor can serve as an output transistor in the driving circuit. By controlling the on-time period of the first feedback subunit and the second feedback subunit, the threshold voltage of the first transistor can be dynamically adjusted in different directions in different operating phases. This can effectively balance the different requirements for the reliability, output capacity, and threshold voltage of the output transistor of the driving circuit, thereby improving the output stability and process window of the driving circuit. Therefore, compared with the prior art, the embodiments of the present invention can improve the output stability of the driving circuit and enhance the display effect.

[0040] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 This is a schematic structural diagram of a switch module provided by an embodiment of the present invention;

[0043] Figure 2is a structural schematic diagram of a first transistor provided by an embodiment of the present invention;

[0044] Figure 3 is a characteristic diagram of a first transistor in a BSM-S mode provided by an embodiment of the present invention;

[0045] Figure 4 is a characteristic diagram of a first transistor in a BSM-G mode provided by an embodiment of the present invention;

[0046] Figure 5 is a schematic structural diagram of a driving circuit provided by an embodiment of the present invention;

[0047] Figure 6 1 is a driving timing diagram of a driving circuit provided by an embodiment of the present invention;

[0048] Figure 7 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0049] Figure 8 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0050] Figure 9 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0051] Figure 10 1 is a driving timing diagram of another driving circuit provided by an embodiment of the present invention;

[0052] Figure 11 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0053] Figure 12 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0054] Figure 13 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0055] Figure 14 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0056] Figure 15 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0057] Figure 16 This is a driving timing diagram of another driving circuit provided by an embodiment of the present invention;

[0058] Figure 17 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0059] Figure 18 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0060] Figure 19 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0061] Figure 20 This is a driving timing diagram of another driving circuit provided by an embodiment of the present invention;

[0062] Figure 21 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0063] Figure 22 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0064] Figure 23 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0065] Figure 24 This is a driving timing diagram of another driving circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0066] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0067] It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be implemented in sequences other than those illustrated or described herein. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0068] An embodiment of the present invention provides a driving circuit. The driving circuit includes at least one switch module. The switch module can serve as an output module in the driving circuit. Figure 1 Schematic diagram of a switch module provided by an embodiment of the present invention. Figure 1Any of the switch modules 100 includes: a first transistor M1 and a threshold voltage adjustment unit 110. The first transistor M1 is a vertical dual-gate transistor, and the first transistor M1 includes a first gate G1, a second gate G2, a first electrode S, and a second electrode D. The threshold voltage adjustment unit 110 includes a first feedback sub-unit 111 and / or a second feedback sub-unit 112 ( Figure 1 The threshold voltage adjustment unit 110 is exemplarily shown to include a first feedback sub-unit 111 and a second feedback sub-unit 112); the first feedback sub-unit 111 is connected between the first electrode S and the second gate G2 of the first transistor M1; and / or, the second feedback sub-unit 112 is connected between the first gate G1 and the second gate G2 of the first transistor M1.

[0069] Exemplarily, the first transistor M1 is turned on or off based on a control signal SC connected to its first gate G1. When the first transistor M1 is turned on, the input signal VIN of the switch module 100 passes through the first transistor M1 and is output as the output signal VOUT of the switch module 100. During the operation of the switch module 100, the threshold voltage adjustment unit 110 adjusts the characteristics of the first transistor M1 by adjusting the connection state of the second gate G2 of the first transistor M1. Specifically, the first feedback sub-unit 111 is configured to connect the first electrode S of the first transistor M1 to the second gate G2 via the conductive first feedback sub-unit 111 when the first transistor M1 is turned off, thereby improving the off-state performance of the first transistor M1. The second feedback sub-unit 112 is configured to connect the first gate G1 of the first transistor M1 to the second gate G2 via the conductive second feedback sub-unit 112 when the first transistor M1 is turned on, thereby improving the on-state performance of the first transistor M1.

[0070] The driving circuit provided in an embodiment of the present invention is provided with at least one switching module 100, which includes a first transistor M1 and a threshold voltage adjustment unit 110. The threshold voltage adjustment unit 110 includes a first feedback sub-unit 111 and / or a second feedback sub-unit 112. The first feedback sub-unit 111 is connected between the second gate G2 and the first electrode S of the first transistor M1, and can adjust the threshold voltage of the first transistor M1 when the first transistor M1 is turned off, thereby ensuring that the first transistor M1 is reliably turned off. And / or, the second feedback sub-unit 112 is connected between the second gate G2 and the first gate G1 of the first transistor M1, and can adjust the threshold voltage of the first transistor M1 when the first transistor M1 is turned on, thereby ensuring that the first transistor M1 is reliably turned on. The first transistor M1 can serve as the output transistor in the driver circuit. By controlling the conduction period of the first feedback sub-unit 111 and the second feedback sub-unit 112, the threshold voltage of the first transistor M1 can be dynamically adjusted in different directions at different operating stages. This effectively balances the different requirements for the reliability, output capacity, and threshold voltage of the output transistor of the driver circuit, thereby improving the output stability and process window of the driver circuit. Therefore, compared with the existing technology, the embodiments of the present invention can improve the output stability of the driver circuit and enhance the display effect.

[0071] First, combine Figure 2-4 , the threshold voltage variation characteristics of the first transistor are described. Figure 2 In one embodiment, the first transistor optionally includes: a second gate 610, a first insulating layer 620, an active layer, a second insulating layer 640, a first gate 650, a third insulating layer 660, and an electrode layer stacked from bottom to top. The active layer includes a first source / drain region 631, a channel region 632, and a second source / drain region 633; the electrode layer includes a first electrode 671 and a second electrode 672. The first electrode 671 contacts the first source / drain region 631 through an insulating layer via, and the second electrode 672 contacts the second source / drain region 633 through an insulating layer via. Because the first transistor M1 can have a symmetrical structure, the embodiment of the present invention does not distinguish between the source and drain regions of the first transistor M1, and collectively refers to them as source / drain regions. Furthermore, the first gate 650 can be either the top gate or the bottom gate (or bottom shield metal BSM) of the first transistor, and the second gate 610 can be the other of the bottom gate and the top gate of the first transistor. The top gate and the bottom gate are specifically determined by the gate placement position. If the first transistor is an N-type transistor, the active layer can be prepared using an oxide semiconductor material, and the first source and drain regions 631 and the second source and drain regions 633 are both N-type ion heavily doped regions; if the first transistor is a P-type transistor, the active layer can be prepared using a polysilicon material, and the first source and drain regions 631 and the second source and drain regions 633 are both P-type ion heavily doped regions.

[0072] Figure 3is a characteristic diagram of a first transistor in a BSM-S mode provided by an embodiment of the present invention; Figure 4 1 is a characteristic diagram of a first transistor in a BSM-G mode according to an embodiment of the present invention. The BSM-S mode indicates that the second gate 610 of the first transistor is shorted to its first electrode 671 , and the BSM-G mode indicates that the second gate 610 of the first transistor is shorted to its first gate 650 . Figure 3 and Figure 4 In FIG, for the N-type first transistor, the potential Vg of the first gate of the first transistor is used as the horizontal coordinate, and the current I_Drain flowing through the first transistor M1 is used as the vertical coordinate, and the characteristic curves of the first transistor M1 operating in the saturation region and the linear region under different connection modes are respectively given. Figure 3 and Figure 4 , with the current I_Drain flowing through the first transistor equal to 10 -7 A is the critical current value between the on-state and the off-state of the first transistor, and the current is greater than 10 -7 A can be considered that the transistor is in the on state, and the current in the on state can be called the on current. Taking the current value when Vg=10V as an example, compare Figure 3 and Figure 4 , it can be seen that the on-current of the first transistor in the BSM-S mode is slightly lower than that in the BSM-G mode. In other words, the threshold voltage of the first transistor, a four-terminal device, in the BSM-S mode is greater than that in the BSM-G mode. That is, when the second gate 610 of the first transistor is connected to the first electrode 671, its threshold voltage is positively biased; when the second gate 610 is connected to the first gate 650, its threshold voltage is negatively biased.

[0073] To verify the characteristics of the first transistor, the inventors measured the characteristic parameters of the first transistor under different connection modes and obtained Table 1. Table 1 is a comparison table of the characteristic parameters of the first transistor under different connection modes. During the test, the potential difference between the first gate and the first electrode of the first transistor was controlled at 10.1V.

[0074] Table 1

[0075] W / L=8 / 8 BSM-S BSM-G Vth1 0.30 -0.06 MOB 11.61 19.13 SS_SLOP 0.21 0.15 Ion 2.13E-05 4.01E-05

[0076] Specifically in Table 1, W / L represents the width-to-length ratio of the first transistor, Vth1 represents the threshold voltage of the first transistor, MOB represents the carrier mobility of the first transistor, SS_SLOP represents the subthreshold swing of the first transistor, and Ion represents the on-current of the first transistor (the driving current generated when it is turned on). According to Table 1, the threshold voltage of the first transistor in the BSM-G mode is less than the threshold voltage in the BSM-S mode, and the driving current in the BSM-G mode is approximately equal to twice the driving current in the BSM-S mode, and the mobility of the first transistor in the BSM-G mode is greater than the mobility in the BSM-S mode. Exemplarily, the first insulating layer 620 can be made of silicon oxide material, and its thickness can be set at The thinner the thickness of the first insulating layer 620 is, the higher the mobility of the first transistor is.

[0077] In summary, there are differences in the characteristics exhibited by the first transistor in the BSM-G mode and the BSM-S mode, which provides a basis for the dynamic adjustment of the characteristics of the first transistor. The threshold voltage adjustment idea of the first transistor is: in the conduction phase of the first transistor, the first transistor is adjusted to be connected to the BSM-G mode to improve the output capacity of the first transistor. In the BSM-G mode, for the N-type first transistor, its threshold voltage is negatively biased; for the P-type first transistor, its threshold voltage is positively biased. In the turn-off phase of the first transistor, the first transistor is adjusted to be connected to the BSM-S mode to ensure that the first transistor is reliably turned off under the condition that the voltage difference between the first gate and the first electrode remains unchanged at a predetermined voltage difference. In the BSM-S mode, for the N-type first transistor, its threshold voltage is positively biased; for the P-type first transistor, its threshold voltage is negatively biased.

[0078] The following description will be made in conjunction with specific embodiments by taking the first transistor N1 as an example where the first transistor N1 is an N-type transistor.

[0079] Figure 5 Schematic diagram of a driving circuit provided by an embodiment of the present invention. Figure 5 In one embodiment, the drive circuit may optionally be a scanning circuit. The drive circuit includes: an input control module 10, a first output module 20, and a second output module 30. The first output module 20 is connected to the input control module 10 and outputs a first signal to the output end of the drive circuit according to the control of the input control module 10; the second output module 30 is connected to the input control module 10 and outputs a second signal to the output end of the drive circuit according to the control of the input control module 10. The at least one switch module includes a first switch module 101, and the first output module 20 includes the first switch module 101.

[0080] Exemplarily, the first output end of the input control module 10 is electrically connected to the first output module 20 via the first node N1, and the second output end of the input control module 10 is electrically connected to the second output module 30 via the second node N2. The input control module 10 controls the potentials of the first node N1 and the second node N2 based on the first potential signal VGL, the second potential signal VGH, the first clock signal CLK1, the second clock signal CLK2, and the input signal SIN. Optionally, the first output module 20 can be electrically connected to a first signal line (which can be a DC potential signal line), and the first output module 20 controls whether the first potential signal VGL on the first signal line is output as the first signal based on the potential of the first node N1. Optionally, the second output module 30 can be electrically connected to a second signal line, and the second output module 30 controls whether the second potential signal VGH on the second signal line is output as the second signal based on the potential of the second node N2. The first potential signal VGL and the second potential signal VGH have opposite logic. Optionally, the first potential signal VGL can be a low potential signal, and the second potential signal VGH can be a high potential signal. Optionally, the first potential signal may be a high potential signal, and the second potential signal may be a low potential signal. The first clock signal CLK1 and the second clock signal CLK2 may have the same frequency but different phases. Optionally, the first clock signal CLK1 and the second clock signal CLK2 may have opposite phases.

[0081] Figure 6 This is a driving timing diagram of a driving circuit provided by an embodiment of the present invention, combined with Figure 5 and Figure 6 , the driving process of the driving circuit includes:

[0082] In the first output stage T01, the input control module 10 controls the potential VN1 of the first node N1 to be a first potential, for example, a low potential, and controls the potential VN2 of the second node N2 to be a second potential, for example, a high potential. The first potential and the second potential may be logically opposite. Optionally, the first potential may be a high potential and the second potential may be a low potential. The first output module 20 is turned off in response to the first potential of the first node N1 (for example, a low potential), that is, the first transistor M1 is turned off; the second output module 30 is turned on in response to the second potential of the second node N2 (for example, a high potential), and the second potential signal VGH is output as the second signal, and the drive signal GOUT is the second potential signal VGH (for example, a high potential). At this time, the first feedback subunit 111 is turned on and the second feedback subunit 112 is turned off, so that the second gate of the first transistor M1 is shorted to its first electrode, forming a BSM-S short-circuit mode. Taking the first transistor M1 as an N-type transistor as an example, the threshold voltage of the first transistor M1 is positively biased compared to V0 when the second gate is floating, and is expressed as a voltage V1, which can achieve the following beneficial effects:

[0083] On the one hand, the setting of the first feedback subunit 111 makes the threshold voltage Vth1 of the first transistor M1 positively biased when it is in the off state. Therefore, compared with not setting the first feedback subunit 111, the first transistor M1 is easier to turn off, which can effectively enhance the off-state performance of the first transistor M1.

[0084] Secondly, the first feedback sub-unit 111 causes the threshold voltage of the first transistor M1 to be positively biased in the off state, which can effectively increase the margin for negative threshold voltage deviation. Even if the threshold voltage of the first transistor M1 is negatively biased due to bias temperature stress (BTS) or other reasons during use, the positive bias adjustment function of the first feedback sub-unit 111 can correct the off-state threshold voltage of the first transistor M1 so that it can still be reliably turned off, preventing the device from being abnormally turned off, thereby improving the reliability of the drive circuit and ensuring the output performance of the drive circuit.

[0085] Thirdly, such a setting can improve the tolerable window of the negative bias of the threshold voltage of the first transistor M1 during preparation. The initial threshold voltage specification of the first transistor M1 can be appropriately negatively biased, which can improve the on-state performance of the first transistor M1 and reduce the requirements for process accuracy.

[0086] In the second output stage T02, the input control module 10 controls the potential VN1 of the first node N1 to be a second potential, for example, a high potential, and controls the potential VN2 of the second node N2 to be a first potential, for example, a low potential. The first output module 20 is turned on in response to the second potential of the first node N1 (for example, a high potential), that is, the first transistor M1 is turned on, and the first potential signal VGL is output as the first signal, and the drive signal GOUT is the first potential signal VGL, for example, a low potential. The second output module 30 is turned off in response to the first potential of the second node N2 (for example, a low potential). At this time, the first feedback subunit 111 is turned off and the second feedback subunit 112 is turned on, so that the second gate of the first transistor M1 is short-circuited with its first gate, forming a BSM-G short-circuit mode. Taking the first transistor M1 as an N-type transistor as an example, the threshold voltage of the first transistor M1 is negatively biased compared to V0 when the second gate is floating, which is expressed as a voltage V2, and the following beneficial effects can be achieved:

[0087] On the one hand, the setting of the second feedback sub-unit 112 makes the threshold voltage Vth1 of the first transistor M1 in the on state negatively biased. Compared with the case where the second feedback sub-unit 112 is not set, under the drive of the same first gate potential, a larger effective operating voltage (i.e., Vgs-Vth1, where Vgs is the potential difference between the first gate and the first electrode of the first transistor) and a larger equivalent mobility can be obtained, and the dual-channel effect of the dual-gate structure makes the output capacity of the first transistor M1, i.e., the driving current Ion, increase exponentially, which can effectively enhance the on-state performance of the first transistor M1.

[0088] Secondly, by adjusting the on-state threshold voltage of the first transistor M1 through the second feedback sub-unit 112, a greater driving capability can be obtained, without increasing the driving capability by changing the width-to-length ratio of the first transistor M1 or increasing the area of the first transistor M1, which is conducive to reducing the size of the device.

[0089] Thirdly, the second feedback sub-unit 112 causes the threshold voltage of the first transistor M1 to be negatively biased when in the on-state. This, through the dual effects of increased mobility and drive current, helps enhance the resistance to resistance-capacitance delay (Rc Delay) of the first transistor M1, allowing the output of the first transistor M1 to reach a preset value more quickly. Therefore, this configuration ensures that the first transistor M1 has a high driving capability and a fast response speed when in the on-state.

[0090] Fourthly, different types of transistors in the driver circuit typically have different threshold voltage requirements. For example, for the switching transistor in the input control module 10, it is generally desirable for its threshold voltage to be close to 0V to ensure better reliability; while for the output transistor in the output module, it is generally desirable for its threshold voltage to be biased negative to obtain greater drive capability. In this embodiment, the provision of the second feedback sub-unit 112 can make the on-state threshold voltage of the first transistor M1 biased negative, allowing the switching transistor and the output transistor to be manufactured entirely in the same process. During use, the threshold voltage of the output transistor can be adjusted through the feedback loop to meet the above requirements, without having to adjust the active region doping concentration and other processes to meet the requirements of different transistors, effectively simplifying the manufacturing process and steps of the driver circuit.

[0091] In summary, the threshold voltage adjustment unit constructs the switch module into a threshold voltage dynamic adjustment structure. When the first transistor M1 is turned on, it is fully turned on, which can improve the on-state performance of the first transistor M1 and maintain the stable output of the drive signal GOUT as much as possible; when the first transistor M1 is turned off, it is fully cut off, which can improve the off-state performance of the first transistor M1 and minimize the impact of leakage on the drive signal GOUT, thereby improving the output stability of the drive signal GOUT, so that the drive circuit can be applied to low refresh frequency scenarios, such as 1Hz or even 0.1Hz, which is conducive to achieving broadband refresh of the drive circuit (for example, a frequency greater than or equal to 0.1Hz and less than or equal to 144Hz).

[0092] The above embodiments exemplarily provide that the first output module 20 includes the first switch module 101, and the threshold voltage adjustment unit includes the first feedback sub-unit 111 and the second feedback sub-unit 112, but this is not intended to limit the present invention. In other embodiments, such as Figure 7 As shown, the threshold voltage adjustment unit may only include the first feedback sub-unit 111, so that the first feedback sub-unit 111 adjusts the off-state threshold voltage of the first transistor M1. Figure 8 As shown, the threshold voltage adjustment unit may include only the second feedback sub-unit 112, so that the second feedback sub-unit 112 adjusts the on-state threshold voltage of the first transistor M1. The specific configuration can be selected according to actual needs. For example, when the first transistor M1 needs to be in the on state for a long time, only the second feedback sub-unit 112 may be provided, or both the first feedback sub-unit 111 and the second feedback sub-unit 112 may be provided.

[0093] The above embodiments exemplify the scheme of constructing the first output module 20 as a threshold voltage dynamic adjustment structure, but it is not intended to limit the present invention. In other embodiments, the second output module 30 may optionally be constructed as a threshold voltage dynamic adjustment structure. Figure 9 In one embodiment, optionally, at least one switch module includes a second switch module 102 , and the second output module 30 includes the second switch module 102 .

[0094] Figure 10 This is a driving timing diagram of another driving circuit provided by an embodiment of the present invention, see Figure 9 and Figure 10 When the second output module 30 is constructed as a threshold voltage dynamic adjustment structure, the driving process of the driving circuit is the same as Figure 5 and Figure 6 The driving process is similar to that of FIG. 1 , but the difference lies in the adjustment direction of the threshold voltage of the first transistor M1.

[0095] Specifically, in the first output stage T01, the second output module 30 is turned on and outputs the second potential signal VGH as the second signal, and the drive signal GOUT is the second potential signal VGH (for example, which can be a high potential). Since the first transistor M1 is turned on at this time, the first feedback sub-unit 111 is turned off and the second feedback sub-unit 112 is turned on, so that the second gate of the first transistor M1 is short-circuited with the first gate. For example, if the first transistor M1 is an N-type transistor, the threshold voltage of the first transistor M1 is negatively biased to ensure that the first transistor M1 is reliably turned on, so that the second potential signal VGH is stably output.

[0096] In the second output phase T02, the second output module 30 is turned off, that is, the first transistor M1 is turned off. At this time, the first feedback sub-unit 111 is turned on, and the second feedback sub-unit 112 is turned off, so that the second gate of the first transistor M1 is short-circuited with its first electrode. For example, if the first transistor M1 is an N-type transistor, the threshold voltage of the first transistor M1 is positively biased to ensure that the first transistor M1 is reliably turned off, preventing the second potential signal VGH from affecting the normal output of the drive circuit.

[0097] The above embodiments exemplarily provide that the second output module 30 includes the first feedback subunit 111 and the second feedback subunit 112, but this is not intended to limit the present invention. Figure 11 As shown, the second output module 30 may only include the first feedback subunit 111, so that the first feedback subunit 111 adjusts the off-state threshold voltage of the first transistor M1. Figure 12 As shown, the second output module 30 may include only the second feedback sub-unit 112, so that the second feedback sub-unit 112 adjusts the on-state threshold voltage of the first transistor M1. The specific configuration can be selected according to actual needs. For example, when the first transistor M1 needs to be in the off state for a long time, only the first feedback sub-unit 111 may be provided, or both the first feedback sub-unit 111 and the second feedback sub-unit 112 may be provided.

[0098] In other embodiments, the first output module 20 and the second output module 30 may both be constructed as a threshold voltage dynamic adjustment structure to adjust the threshold voltages of the first output module 20 and the second output module 30 respectively according to their respective requirements.

[0099] Figure 13 This is a schematic diagram of the structure of another driving circuit provided by an embodiment of the present invention. Figure 13In one embodiment, the first output module 20 optionally includes a first switch module 101, and the second output module 30 includes a second switch module 102. Optionally, the second electrode of the first transistor in the first output module 20 is electrically connected to the first electrode of the first transistor in the second output module 30. Optionally, each of the first switch module 101 and the second switch module 102 is provided with a corresponding first feedback subunit 111 and / or second feedback subunit 112. This ensures dynamic adjustment of the threshold voltages of the two output modules of the driver circuit, ensuring stable output of the driver circuit at all operating stages.

[0100] Figure 14 This is a schematic diagram of the structure of another driving circuit provided by an embodiment of the present invention. Figure 14 In another embodiment, optionally, only the second feedback subunit 112 is provided in the first output module 20 (first switch module 101), and only the first feedback subunit 111 is provided in the second output module 30 (second switch module 102). Because the drive circuit needs to output a low potential for a long time, the first output module 20 is in the on state for a long time, while the second output module 30 is in the off state for a long time. Therefore, the second feedback subunit 112 can improve the on-state performance of the first output module 20 when the first output module 20 is on, ensuring that the first output module 20 stably outputs a low potential for a long time; the first feedback subunit 111 can improve the off-state performance of the second output module 30 when the second output module 30 is off, ensuring that the second output module 30 is reliably shut down for a long time. Therefore, this embodiment can meet the different threshold voltage adjustment requirements of the first output module 20 and the second output module 30 while ensuring a simple drive circuit structure.

[0101] On the basis of the above embodiments, optionally, the first feedback subunit 111 includes a first feedback control terminal. Optionally, the second feedback subunit 112 includes a second feedback control terminal. There are many ways to connect the first feedback control terminal and the second feedback control terminal in the circuit, for example, the first feedback control terminal is electrically connected to the output terminal of the driving circuit (or the second pole of the first transistor), and the second feedback control terminal is electrically connected to the first gate of the first transistor M1; or, the first feedback control terminal is electrically connected to the second gate of the first transistor, and the second feedback control terminal is electrically connected to the output terminal of the driving circuit (or the first pole of the first transistor) or the first gate of the first transistor. In this embodiment, the potential of the original node in the driving circuit is used as the control signal of the first feedback subunit 111 and the second feedback subunit 112. Without the introduction of additional signals, the threshold voltage of the first transistor M1 can be dynamically adjusted, which is conducive to simplifying the structure of the display panel and reducing power consumption.

[0102] Specifically, the connection mode between the first feedback subunit and the second feedback subunit is related to the arrangement positions of the two feedback subunits and the specific structure of the driving circuit, which will be described below in conjunction with several specific embodiments.

[0103] See also Figure 5 In one embodiment, the first output module 20 optionally includes a first switching module 101. Optionally, the first signal output by the first output module 20 is a first potential. The turn-on signal of the first transistor M1 is logically opposite to the first potential. Optionally, the first electrode of the first transistor M1 is electrically connected to a first potential signal line (capable of transmitting a first potential signal VGL), and the first signal output by the first output module 20 is a low potential signal VGL, which is the first potential signal. Optionally, the first feedback control terminal is electrically connected to the second electrode of the first transistor M1. Optionally, the first feedback control terminal is electrically connected to the output terminal GOUT of the drive circuit. Optionally, the second feedback control terminal is electrically connected to the first gate of the first transistor M1. Optionally, the second electrode of the first transistor M1 is electrically connected to the output terminal GOUT of the drive circuit. In this way, when the first node N1 is at a second potential (e.g., a high potential), the potential of the first node N1 controls the conduction of the first transistor M1 while also controlling the conduction of the second feedback sub-unit 112, thereby causing the first gate and the second gate of the first transistor M1 to be in a conductive state, thereby enhancing the on-state performance of the first transistor M1. At the same time, the first transistor M1 outputs the first potential signal VGL (e.g., a low potential) on the first signal line (which may be a first potential signal line) to the output terminal GOUT of the driving circuit, thereby controlling the first feedback sub-unit 111 to be turned off. When the second output module 30 outputs the second potential signal VGH (e.g., a high potential) on the second signal line as the second signal, the first node N1 is at the first potential (e.g., a low potential), controlling the first transistor M1 and the second feedback sub-unit 112 to be turned off; the driving signal GOUT is at the second potential (e.g., a high potential), controlling the first feedback sub-unit 111 to be turned on, thereby causing the first electrode and the second gate of the first transistor M1 to be in a conduction state, thereby enhancing the off-state performance of the first transistor M1.

[0104] See also Figure 9In another embodiment, optionally, the second output module 30 includes a second switch module 102. Optionally, the second signal output by the second output module 30 is a second potential. Optionally, in the second switch module 102, the second pole of the first transistor M1 is electrically connected to the second potential signal line (which can transmit the second potential signal VGH). Optionally, the potentials on the first potential signal line and the second potential signal line can be logically opposite. Optionally, the second signal output by the second output module 30 is a second potential signal VGH of the second potential signal. Optionally, the first feedback control terminal is electrically connected to the second gate of the first transistor M1. Optionally, the second feedback control terminal is electrically connected to the first pole of the first transistor M1. Optionally, the second feedback control terminal of the second feedback sub-unit 112 is electrically connected to the output terminal of the drive circuit. Optionally, the first pole of the first transistor M1 is electrically connected to the output terminal GOUT of the drive circuit. Thus, when the second node N2 is at the second potential (e.g., a high potential), the potential of the second node N2 controls the first transistor M1 to turn on. The first transistor M1 outputs the second potential signal VGH (e.g., a high potential) on the second potential signal line as the drive signal GOUT. The drive signal GOUT controls the second feedback sub-unit 112 to turn on, causing the first gate and the second gate of the first transistor M1 to be in a conductive state, thereby enhancing the on-state performance of the first transistor M1. At the same time, the conductive second feedback sub-unit 112 transmits the second potential (e.g., a high potential) of the first gate of the first transistor M1 to the second gate of the first transistor M1, connecting the first feedback control terminal of the first feedback sub-unit 111 to the second potential (e.g., a high potential). Since the first feedback control terminal and the first terminal of the first feedback sub-unit 111 (i.e., the terminal of the first feedback sub-unit 111 connected to the first electrode of the first transistor M1, or the terminal of the first feedback sub-unit 111 connected to the output terminal GOUT of the drive circuit) are both at the second potential (e.g., a high potential), the first feedback sub-unit 111 is turned off. When the first output module 20 outputs the first potential signal VGL (e.g., a low potential) on the first potential signal line as the first signal, the second output module 30 is turned off. At this time, the drive signal GOUT is at the first potential (e.g., a low potential), controlling the second feedback sub-unit 112 to turn off. Simultaneously, the first feedback control terminal is at the second potential (e.g., a high potential), and the first terminal of the first feedback sub-unit 111 is at the first potential (e.g., a low potential). The first feedback sub-unit 111 is turned on, causing the first electrode of the first transistor M1 to be in a conductive state via the conductive first feedback sub-unit 111 and the second gate, thereby enhancing the off-state performance of the first transistor M1.

[0105] See also Figure 12In another embodiment, optionally, when the second output module 30 is provided with a second feedback subunit 112, and the second signal output by the second output module 30 is a second potential signal VGH, the second feedback control terminal may also be connected to the first gate of the first transistor M1. Since the potential of the second node N2 controls the on-off switching of the first transistor M1, the change trend of the potential of the second node N2 is actually the same as the change trend of the drive signal GOUT. Therefore, connecting the second feedback control terminal to the second node N2 can also realize the function of dynamic threshold voltage adjustment.

[0106] The above embodiments exemplify the functional modules of the driving circuit. The specific structure that the driving circuit may have will be described below.

[0107] Figure 15 This is a schematic diagram of another driving circuit provided by an embodiment of the present invention, see Figure 15 Based on the above embodiments, optionally, the first feedback subunit 111 includes: a second transistor M2. Optionally, the gate of the second transistor M2 is electrically connected to the first feedback control terminal. Optionally, the gate of the second transistor M2 serves as the first feedback control terminal. Optionally, the first electrode of the second transistor M2 is electrically connected to the first electrode of the first transistor M1. Optionally, the second electrode of the second transistor M2 is electrically connected to the second gate of the first transistor M1. In this embodiment, the first feedback subunit 111 is configured to consist of a single transistor, which makes the structure of the first feedback subunit 111 simple and easy to implement.

[0108] Continue to see Figure 15 Based on the above embodiments, the second feedback sub-unit 112 optionally includes: a third transistor M3. Optionally, the gate of the third transistor M3 is electrically connected to the second feedback control terminal. Optionally, the gate of the third transistor M3 serves as the second feedback control terminal. Optionally, the first electrode of the third transistor M3 is electrically connected to the first gate of the first transistor M1. Optionally, the second electrode of the third transistor M3 is electrically connected to the second gate of the first transistor M1. In this embodiment, the second feedback sub-unit 112 is configured to consist of a single transistor, which makes the second feedback sub-unit 112 simple in structure and easy to implement.

[0109] Continue to see Figure 15 On the basis of the above embodiments, optionally, the input control module 10 includes: a first input unit 11 , a second input unit 12 , a node potential control unit 13 and a first node mutual control unit 14 .

[0110] The control end of the first input unit 11 is connected to the first clock signal CLK1 on the first clock signal line, the input end of the first input unit 11 is connected to the input signal SIN on the input signal line, and the output end of the first input unit 11 is electrically connected to the second output module 20; the first control end of the second input unit 12 is connected to the input signal SIN on the input signal line, the second control end of the second input unit 12 is connected to the first clock signal CLK1 on the first clock signal line, and the input end of the second input unit 12 is connected to the first potential signal VGL on the first potential signal line; the control end of the node potential control unit 13 is electrically connected to the output end of the second input unit 12, the input end of the node potential control unit 13 is connected to the second clock signal CLK2 on the second clock signal line, and the output end of the node potential control unit 13 is electrically connected to the first output module 20; the control end of the first node mutual control unit 14 is electrically connected to the output end of the first input unit 11, the input end of the first node mutual control unit 14 is connected to the first potential signal VGL on the first potential signal line, and the output end of the first node mutual control unit 14 is electrically connected to the first output module 20.

[0111] Optionally, the first input unit 11 is used to respond to the first clock signal CLK1 and output the input signal SIN to its output end. Optionally, the second input unit 12 is used to respond to the first clock signal CLK1 and output the first potential signal VGL to its output end, and respond to the input signal SIN and output the first potential signal VGL to its output end. Optionally, the node potential control unit 13 is used to respond to the signal at the output end of the second input unit 12 and output the second clock signal CLK2 to its output end. Optionally, the first node mutual control unit 14 is used to respond to the signal at the output end of the first input unit 11 and output the first potential signal VGL to its output end. Optionally, the first output module 20 is used to respond to the signal at the output end of the node potential control unit 13 and the signal at the output end of the first node mutual control unit 14 and output the signal on the first signal line to the output end of the drive circuit. Optionally, the second output module 30 is used to respond to the signal at the output end of the first input unit 11 and output the signal on the second signal line to the output end of the drive circuit.

[0112] Optionally, the first input unit 11 includes a transistor M4. Optionally, the second input unit 12 includes a transistor M5 and a transistor M6. Optionally, the node potential control unit 13 includes a transistor M7 and a capacitor C3. Optionally, the first node mutual control unit 14 includes a transistor M8.

[0113] Optionally, the input control module 10 further includes a protection unit 15. The protection unit 15 is configured to output the signal at the output end of the first input unit 11 to the second output module 30 in response to the second potential signal VGH of the second potential signal line being turned on. Optionally, the protection unit 15 includes a transistor M9.

[0114] Taking the first output module 20 as a threshold voltage dynamic adjustment structure and the second output module 30 including the transistor M01 as an example, the specific connection method of each component in the driving circuit is as follows:

[0115] The gate of transistor M4 is connected to the first clock signal CLK1, the first terminal is connected to the input signal SIN, and the second terminal is electrically connected to the first terminal of transistor M9. The gate of transistor M9 is connected to the second potential signal VGH, and the second terminal of transistor M9 is electrically connected to the gate of transistor M01. The first terminal of transistor M01 is connected to the second potential signal VGH, and the second terminal of transistor M01 is electrically connected to the output terminal of the drive circuit. In addition, the second output module 30 also includes a capacitor C2 connected between the gate and the second terminal of transistor M01. The gate of transistor M5 is connected to the input signal SIN, the first electrode is connected to the first potential signal VGL, and the second electrode is electrically connected to the second electrode of transistor M6; the gate of transistor M6 is connected to the first clock signal CLK1, the first electrode is connected to the first potential signal VGL, and the second electrode is electrically connected to the gate of transistor M7; the first electrode of transistor M7 is connected to the second clock signal CLK2, and the second electrode is electrically connected to the first output terminal of input control module 10; capacitor C3 is connected between the gate and the first electrode of transistor M7; the gate of transistor M8 is electrically connected to the second electrode of transistor M4, the first electrode is connected to the first potential signal VGL, and the second electrode is electrically connected to the second electrode of transistor M7. Optionally, the first output module 20 also includes a capacitor C1 connected between the first gate and the first electrode of the first transistor M1.

[0116] Figure 16 This is a driving timing diagram of another driving circuit provided by an embodiment of the present invention. Figure 15 and Figure 16 Each transistor is shown as an N-type transistor and the corresponding timing waveform is shown as an example. Figure 15 and Figure 16 , the control process of the drive circuit includes:

[0117] In the first stage T11, the input signal SIN and the second clock signal CLK2 are both at a first potential, for example, a low potential, and the first clock signal CLK1 is at a second potential, for example, a high potential. Transistors M4 and M9 are turned on, and the first potential of the input signal SIN (for example, a low potential) is transmitted to the second node N2 through transistors M4 and M9, controlling transistor M01 to turn off. Transistor M6 is turned on, transmitting the first potential signal VGL to the gate of transistor M7, controlling transistor M7 to turn off. The first node N1 maintains the high potential of the previous stage, controlling the first transistor M1 to turn on, and outputting the first potential signal VGL as the drive signal GOUT. The third transistor M3 is turned on, and the second transistor M2 is turned off, so that the second gate of the first transistor M1 is short-circuited with the first gate, and the threshold voltage of the first transistor M1 is negatively biased, thereby enhancing the on-state performance of the first transistor M1.

[0118] In the second stage T12, the input signal SIN and the second clock signal CLK2 are both at the second potential, for example, a high potential, and the first clock signal CLK1 is at the first potential, for example, a low potential. The transistor M4 is turned off, and the second node N2 maintains the first potential of the previous stage, for example, a low potential, and controls the transistor M01 to be turned off. The transistor M5 is turned on, transmitting the first potential signal VGL to the gate of the transistor M7, and controlling the transistor M7 to be turned off. The first node N1 maintains the second potential of the previous stage, for example, a high potential, and controls the first transistor M1 to be turned on, outputting the first potential signal VGL as the drive signal GOUT. The third transistor M3 is turned on, and the second transistor M2 is turned off, so that the second gate of the first transistor M1 is short-circuited with the first gate, and the threshold voltage of the first transistor M1 is negatively biased, thereby enhancing the on-state performance of the first transistor M1.

[0119] In the third phase T13, the input signal SIN and the first clock signal CLK1 are both at the second potential, for example, a high potential, and the second clock signal CLK2 is at the first potential, for example, a low potential. Transistors M4 and M9 are turned on, and the second potential of the input signal SIN (for example, a high potential) is transmitted to the second node N2 through transistors M4 and M9, controlling transistor M01 to turn on and output the second potential signal VGH as the drive signal GOUT. Transistors M5 and M6 are both turned on, and both transmit the first potential of the first potential signal VGL (for example, a low potential) to the gate of transistor M7, controlling transistor M7 to turn off. Transistor M8 is turned on, transmitting the first potential signal VGL to the first node N1, controlling the first transistor M1 to turn off. The third transistor M3 is turned off, and the second transistor M2 is turned on, causing the second gate of the first transistor M1 to be shorted to the first electrode, and the threshold voltage of the first transistor M1 to be positively biased, thereby enhancing the off-state performance of the first transistor M1.

[0120] In the fourth stage T14, the input signal SIN and the second clock signal CLK2 are both at the second potential, for example, a high potential, and the first clock signal CLK1 is at the first potential, for example, a low potential. The transistor M4 is turned off, the second node N2 maintains the second potential of the previous stage (for example, a high potential), the control transistor M01 is turned on, and the second potential signal VGH is output as the drive signal GOUT. The transistor M5 is turned on, and the first potential signal VGL is transmitted to the gate of the transistor M7, and the control transistor M7 is turned off. The transistor M8 is turned on, and the first potential signal VGL is transmitted to the first node N1, and the control transistor M1 is turned off. The third transistor M3 is turned off, and the second transistor M2 is turned on, so that the second gate of the first transistor M1 is shorted to the first electrode, and the threshold voltage of the first transistor M1 is forward biased, thereby enhancing the off-state performance of the first transistor M1.

[0121] In the fifth stage T15, the input signal SIN and the second clock signal CLK2 are both at a first potential, for example, a low potential, and the first clock signal CLK1 is at a second potential, for example, a high potential. Transistors M4 and M9 are turned on, and the first potential of the input signal SIN (for example, a low potential) is transmitted to the second node N2 through transistors M4 and M9, controlling transistor M01 to turn off. Transistor M6 is turned on, transmitting the first potential signal VGL to the gate of transistor M7, controlling transistor M7 to turn off. The first node N1 maintains the first potential of the previous stage (for example, a low potential), controlling the first transistor M1 to turn off. At this time, the drive signal GOUT maintains the second potential of the previous stage (for example, a high potential). The third transistor M3 is turned off, and the second transistor M2 is turned on, so that the second gate of the first transistor M1 is short-circuited to the first electrode, and the threshold voltage of the first transistor M1 is forward biased, enhancing the off-state performance of the first transistor M1.

[0122] In the sixth stage T16, the input signal SIN and the first clock signal CLK1 are both at a first potential, for example, a low potential, and the second clock signal CLK2 is at a second potential, for example, a high potential. Transistor M4 is turned off, the second node N2 maintains the first potential of the previous stage (for example, a low potential), and the control transistor M01 is turned off. Transistors M5 and M6 are both turned off. The second clock signal CLK2 jumps to a second potential (for example, a high potential). Due to the coupling effect of capacitor C3, the gate potential of transistor M7 jumps to a high potential. Transistor M7 is turned on, transmitting the second potential of the second clock signal CLK2 (for example, a high potential) to the first node N1, controlling the first transistor M1 to turn on and outputting the first potential signal VGL as the drive signal GOUT. The third transistor M3 is turned on, and the second transistor M2 is turned off, so that the second gate of the first transistor M1 is shorted to the first gate, and the threshold voltage of the first transistor M1 is negatively biased, thereby enhancing the on-state performance of the first transistor M1.

[0123] In the seventh stage T17, the input signal SIN and the second clock signal CLK2 are both at a first potential, for example, a low potential, and the first clock signal CLK1 is at a second potential, for example, a high potential. Transistors M4 and M9 are turned on, and the first potential of the input signal SIN (for example, a low potential) is transmitted to the second node N2 through transistors M4 and M9, controlling transistor M01 to turn off. Transistor M6 is turned on, transmitting the first potential signal VGL to the gate of transistor M7, controlling transistor M7 to turn off. The first node N1 maintains the second potential of the previous stage (for example, a high potential), controlling the first transistor M1 to turn on, and outputting the first potential signal VGL as the drive signal GOUT. The third transistor M3 is turned on, and the second transistor M2 is turned off, so that the second gate of the first transistor M1 is short-circuited with the first gate, and the threshold voltage of the first transistor M1 is negatively biased, thereby enhancing the on-state performance of the first transistor M1.

[0124] The subsequent stages repeat the sixth stage T16 and the seventh stage T17 until the input signal SIN jumps to the second potential (for example, it can be a high potential) again. In this embodiment, a shifted output of the input signal SIN is achieved. Since the sixth stage T16, whenever the second clock signal CLK2 jumps to the second potential (for example, it can be a high potential), the first node N1 is charged to the second potential (for example, it can be a high potential), which can ensure that the first transistor M1 is reliably turned on. Combined with the threshold voltage adjustment effect of the third transistor M3 on the first transistor M1, it can ensure that the drive circuit stably outputs the first potential (for example, it can be a low potential) for a long time. Therefore, the drive circuit can achieve stable low-frequency output. By adjusting the pulse width of the input signal SIN, a wide frequency output can be achieved, for example, 0.1Hz to 144Hz.

[0125] Figure 17 This is a structural diagram of another driving circuit provided by an embodiment of the present invention. Figure 17 The driving circuit shown is Figure 15 The differences are: Figure 17 In the embodiment, the second output module 30 is configured as a threshold voltage dynamic adjustment structure, and the first output module 20 includes a transistor M02. The driving timing can still be referred to Figure 16 The difference is that, for the second output module 30, the second transistor M2 is turned off when the drive signal GOUT is the second potential (for example, it can be a high potential), and is turned on when the drive signal GOUT is the first potential (for example, it can be a low potential); and the third transistor M3 is turned on when the drive signal GOUT is the second potential (for example, it can be a high potential), and is turned off when the drive signal GOUT is the first potential (for example, it can be a low potential).

[0126] Figure 18 This is a structural diagram of another driving circuit provided by an embodiment of the present invention. Figure 18 The driving circuit shown is Figure 15 The differences are: Figure 18 In the embodiment, the first output module 20 is a first switch module 101 including a first transistor M101; and the second output module 30 is a second switch module 102 including a first transistor M102. The driving timing can still be referred to Figure 16 The difference is that the second transistor M201 in the first output module 20 and the third transistor M302 in the second output module 30 are turned on at the same time, and the third transistor M301 in the first output module 20 and the second transistor M202 in the second output module 30 are turned on at the same time.

[0127] The above embodiments illustrate that the second output module outputs a second potential signal (a high potential signal) as the second signal, but this is not intended to limit the present invention. In other embodiments, the second output module may output a clock signal (e.g., the first clock signal CLK1) as the second signal, and the input control module may have other structures.

[0128] Figure 19 This is a schematic diagram of the structure of another driving circuit provided by an embodiment of the present invention. Figure 19 In one embodiment, optionally, the second output module 30 receives the first clock signal CLK1 . The input control module 10 includes: a first input unit 11 , a second input unit 12 , a node potential control unit 13 , and a first node mutual control unit 14 .

[0129] The control end of the first input unit 11 is connected to the input signal SIN on the input signal line, the input end of the first input unit 11 is connected to the second potential signal VGH on the second potential signal line, and the output end of the first input unit 11 is electrically connected to the second output module 30; the first control end of the second input unit 12 is connected to the input signal SIN on the input signal line, the second control end of the second input unit 12 is connected to the first clock signal CLK1 on the first clock signal line, and the input end of the second input unit 12 is connected to the first potential signal VGL on the first potential signal line; the control end of the node potential control unit 13 is electrically connected to the output end of the second input unit 12, the input end of the node potential control unit 13 is connected to the second clock signal CLK2 on the second clock signal line, and the output end of the node potential control unit 13 is electrically connected to the first output module 20; the control end of the first node mutual control unit 13 is electrically connected to the output end of the first input unit 11, the input end of the first node mutual control unit 13 is connected to the first potential signal VGL on the first potential signal line, and the output end of the first node mutual control unit 13 is electrically connected to the first output module 20.

[0130] Optionally, the first input unit 11 is configured to output the second potential signal VGH on the second potential signal line to its output end in response to the input signal SIN on the input signal line. Optionally, the second input unit 12 is configured to output the first potential signal VGL to its output end in response to the first clock signal CLK1, and to output the first potential signal VGL to its output end in response to the input signal SIN. Optionally, the node potential control unit 13 is configured to output the second clock signal CLK2 to its output end in response to the signal at the output end of the second input unit 12. Optionally, the first node mutual control unit 14 is configured to output the first potential signal VGL to its output end in response to the signal at the output end of the first input unit 11. Optionally, the first output module 20 is configured to output the signal on the first potential signal line to the output end of the drive circuit in response to the signals at the output end of the node potential control unit 13 and the output end of the first node mutual control unit 14. Optionally, the second output module 30 is configured to output the signal on the first clock signal line to the output end of the drive circuit in response to the signal at the output end of the first input unit 11.

[0131] Figure 19 The components of the input control module 10 are configured in the same manner as Figure 15 The specific difference is that the gate of the transistor M4 is connected to the input signal SIN, and the first electrode of the transistor M4 is connected to the second potential signal VGH.

[0132] Optionally, the input control module 10 may further include a second node potential mutual control unit 16, which is used to control the second node N2 to be a first potential (for example, a low potential) when the first node N1 is a second potential (for example, a high potential). Optionally, the control end of the second node potential mutual control unit 16 is electrically connected to the output end of the node potential control unit 13 and the output end of the first node mutual control unit 14, the input end of the second node potential mutual control unit 16 is connected to the first potential signal VGL, and the output end of the second node potential mutual control unit 16 is electrically connected to the second output module 30. Optionally, the second node potential mutual control unit 16 is used to respond to the signals at the output end of the node potential control unit 13 and the output end of the first node mutual control unit 14, and output the first potential signal VGL to its output end. Optionally, the second node potential mutual control unit 16 includes a transistor M10, the gate of the transistor M10 is electrically connected to the first node N1, the first electrode is connected to the first potential signal VGL, and the second electrode is electrically connected to the first electrode of the transistor M9.

[0133] Figure 20 This is a driving timing diagram of another driving circuit provided by an embodiment of the present invention. Figure 19 and Figure 20 Each transistor is shown as an N-type transistor and the corresponding timing waveform is shown as an example. Figure 19 and Figure 20 , the driving process of the driving circuit includes:

[0134] In the first stage T11, the input signal SIN and the second clock signal CLK2 are both at the first potential, for example, a low potential, and the first clock signal CLK1 is at the second potential, for example, a high potential. Transistor M4 is turned off. Transistor M6 is turned on, transmitting the first potential of the first potential signal VGL (for example, a low potential) to the gate of transistor M7, and controlling transistor M7 to turn off. The first node N1 maintains the second potential of the previous stage (for example, a high potential), controls the first transistor M1 to turn on, and outputs the first potential signal VGL as the drive signal GOUT. Transistor M10 is turned on, transmitting the first potential signal VGL to the second node N2, and controlling transistor M01 to turn off. The third transistor M3 is turned on, and the second transistor M2 is turned off, so that the second gate of the first transistor M1 is short-circuited with the first gate, and the threshold voltage of the first transistor M1 is negatively biased, thereby enhancing the on-state performance of the first transistor M1.

[0135] In the second stage T12, the input signal SIN and the second clock signal CLK2 are both at the second potential, for example, a high potential, and the first clock signal CLK1 is at the first potential, for example, a low potential. Transistors M4 and M9 are turned on, and the second potential signal VGH is transmitted to the second node N2 through transistors M4 and M9, controlling transistor M01 to turn on and output the first potential of the first clock signal CLK1 (for example, a low potential) as the drive signal GOUT. Transistor M5 is turned on, transmitting the first potential of the first potential signal VGL (for example, a low potential) to the gate of transistor M7, controlling transistor M7 to turn off. Transistor M8 is turned on, transmitting the first potential signal VGL to the first node N1, controlling the first transistor M1 to turn off. The third transistor M3 and the second transistor M2 are both turned off, without changing the threshold voltage of the first transistor M1.

[0136] In the third phase T13, the input signal SIN and the first clock signal CLK1 are both at the second potential, for example, a high potential, and the second clock signal CLK2 is at the first potential, for example, a low potential. Transistors M4 and M9 are turned on, and the second potential signal VGH is transmitted to the second node N2 through transistors M4 and M9, controlling transistor M01 to turn on and output the second potential of the first clock signal CLK1 (for example, a high potential) as the drive signal GOUT. Transistors M5 and M6 are both turned on, and each transmits the first potential of the first potential signal VGL (for example, a low potential) to the gate of transistor M7, controlling transistor M7 to turn off. Transistor M8 is turned on, transmitting the first potential of the first potential signal VGL (for example, a low potential) to the first node N1, controlling the first transistor M1 to turn off. The third transistor M3 is turned off, and the second transistor M2 is turned on, causing the second gate of the first transistor M1 to be shorted to the first electrode, and the threshold voltage of the first transistor M1 to be positively biased, thereby enhancing the off-state performance of the first transistor M1.

[0137] In the fourth stage T14, the input signal SIN and the second clock signal CLK2 are both at a second potential (e.g., a high potential), and the first clock signal CLK1 is at a first potential (e.g., a low potential). The switching states of the transistors are the same as in the second stage T12. Transistor M01 is turned on, outputting the first potential (e.g., a low potential) of the first clock signal CLK1 as the drive signal GOUT.

[0138] In the fifth stage T15, the input signal SIN and the first clock signal CLK1 are both at the second potential, for example, a high potential, and the second clock signal CLK2 is at the first potential, for example, a low potential. The switching states of the transistors are the same as in the third stage T13. Transistor M01 is turned on, outputting the high potential of the first clock signal CLK1 as the drive signal GOUT.

[0139] In the sixth stage T16, the input signal SIN and the first clock signal CLK1 are both at a first potential, for example, a low potential, and the second clock signal CLK2 is at a second potential, for example, a high potential. Transistor M4 is turned off. Transistors M5 and M6 are both turned off. The second clock signal CLK2 jumps to a high potential. Due to the coupling effect of capacitor C3, the gate potential of transistor M7 jumps to a second potential (for example, a high potential). Transistor M7 is turned on, transmitting the second potential (for example, a high potential) of the second clock signal CLK2 to the first node N1, controlling the first transistor M1 to turn on and outputting the first potential signal VGL as the drive signal GOUT. Transistor M10 is turned on, transmitting the first potential signal VGL to the second node N2, controlling transistor M01 to turn off. The third transistor M3 is turned on, and the second transistor M2 is turned off, causing the second gate of the first transistor M1 to be short-circuited to the first gate. The threshold voltage of the first transistor M1 is negatively biased, thereby enhancing the on-state performance of the first transistor M1.

[0140] In the seventh stage T17, the input signal SIN and the second clock signal CLK2 are both at the first potential, for example, a low potential, and the first clock signal CLK1 is at the second potential, for example, a high potential. The transistor M4 is turned off. The transistor M6 is turned on, transmitting the first potential signal VGL to the gate of the transistor M7, and controlling the transistor M7 to turn off. The potential of the first node N1 maintains the second potential of the previous stage (for example, a high potential), controlling the first transistor M1 to turn on, and outputting the first potential signal VGL as the drive signal GOUT. The transistor M10 is turned on, transmitting the first potential signal VGL to the second node N2, and controlling the transistor M01 to turn off. The third transistor M3 is turned on, and the second transistor M2 is turned off, so that the second gate of the first transistor M1 is short-circuited with the first gate, and the threshold voltage of the first transistor M1 is negatively biased, thereby enhancing the on-state performance of the first transistor M1.

[0141] The subsequent stages repeat the sixth stage T16 and the seventh stage T17 until the input signal SIN jumps to the second potential (for example, which can be a high potential) again. In this embodiment, during the stages in which the input signal SIN remains at the second potential (for example, which can be a high potential), the second potential signal VGH is transmitted to the second node N2 through the transistor M4 and the transistor M9, controlling the transistor M01 to turn on, so that the waveform of the drive signal GOUT is the same as the waveform of the first clock signal CLK1; in other stages, the first transistor M1 is turned on, and the drive signal GOUT remains at the first potential (for example, which can be a low potential). This embodiment realizes an output method in which the waveform of the drive signal GOUT is different from the waveform of the input signal SIN.

[0142] Figure 21 This is a structural diagram of another driving circuit provided by an embodiment of the present invention. Figure 21The driving circuit shown is Figure 19 The differences are: Figure 21 In the embodiment, the second output module 30 is set to a threshold voltage dynamic adjustment structure. Its driving timing can still refer to Figure 20 Optionally, in the second switch module, the second electrode of the first transistor is electrically connected to the first clock signal line (capable of transmitting the first clock signal CLK1).

[0143] Figure 22 This is a structural diagram of another driving circuit provided by an embodiment of the present invention. Figure 22 The driving circuit shown is Figure 19 The differences are: Figure 22 In the embodiment, the first output module 20 and the second output module 30 are both configured as a threshold voltage dynamic adjustment structure. The driving timing can still be referred to Figure 20 .

[0144] On the basis of the above-mentioned embodiments, optionally, each transistor in the driving circuit is set as an N-type transistor. Compared with the P-type transistor, it can reduce the product cost and provide GIP circuit support for the pixel circuit composed of the N-type transistor, which is conducive to the penetration of OLED panels into medium and large-sized displays; and it can also make use of the low leakage characteristics of the N-type transistor to enable the product to easily achieve broadband display.

[0145] The above embodiments exemplarily introduce the driving circuit composed of N-type transistors, but this is not intended to limit the present invention. In other embodiments, some or all of the transistors in the driving circuit can also be replaced with P-type transistors. Figure 23 , a driving circuit composed of P-type transistors is described.

[0146] Figure 23 This is a schematic diagram of the structure of another driving circuit provided by an embodiment of the present invention. Figure 23 The drive circuit includes: an input control module 10, a first output module 20 (a first switch module 101), and a second output module 30 (a second switch module 102). The input control module 10 includes a transistor M11, a transistor M12, a transistor M13, a transistor M14, a transistor M15, a transistor M16, a transistor M17, a transistor M18, and a capacitor C13. The structures of the first output module 20 and the second output module 30 are similar to those of the first output module 20 and the second output module 30. Figure 22 Similar to, except that, Figure 23 Each transistor in the transistor is a P-type transistor, the first electrode of the transistor M101 is connected to the second potential signal VGH (the first potential signal line can transmit a high potential signal), the second electrode of the transistor M102 is connected to the first potential signal VGL (the second potential signal line can transmit a low potential signal), and Figure 23One end of the capacitor C2 is electrically connected to the gate of the transistor M102, and the other end is connected to the fourth clock signal CLK4.

[0147] Optionally, transistor M11 is used to respond to the third clock signal CLK3 on the third clock signal line and output the input signal SIN on the input signal line to its second pole (the control end of the second output module 30, i.e., the second node N2). Optionally, transistor M13 is used to respond to the third clock signal CLK3 and output the first potential signal VGL to its second pole (the third node N3). Optionally, transistor M12 is used to respond to the signal of the second pole of transistor M11 and output the third clock signal CLK3 to the third node N3. Optionally, transistor M14 is used to respond to the potential of the third node N3 and transmit the second potential signal VGH to the first pole of transistor M15. Transistor M15 is used to respond to the fourth clock signal CLK4 and transmit the potential of its first pole to the second node N2. Optionally, transistor M16 is used to respond to the potential of the third node N3 and transmit the fourth clock signal CLK4 to its second pole. Capacitor C13 is used to couple the potential change of the second pole of transistor M16 to the gate of transistor M16. Optionally, the transistor M17 is configured to respond to the fourth clock signal CLK4 and transmit the potential of the second electrode of the transistor M16 to the control terminal (first node N1) of the first output module 20. Optionally, the transistor M18 is configured to respond to the potential of the second node N2 and transmit the second potential signal VGH to the first node N1. Optionally, the first output module 20 is configured to respond to the potential of the first node N1 and output the second potential signal VGH as the drive signal GOUT. Optionally, the second output module 30 is configured to respond to the potential of the second node N2 and output the first potential signal VGL as the drive signal GOUT. The third clock signal CLK3 and the fourth clock signal CLK4 may have the same frequency but different phases. Optionally, the third clock signal CLK3 and the fourth clock signal CLK4 have opposite phases.

[0148] Figure 24 This is a driving timing diagram of another driving circuit provided by an embodiment of the present invention. Figure 23 and Figure 24 Each transistor is drawn as a P-type transistor and the corresponding timing waveform is shown as an example. Figure 23 and Figure 24 , the driving process of the driving circuit includes:

[0149] In phase T21, the third clock signal CLK3 is at a first potential, such as a low potential, and the fourth clock signal CLK4 and the input signal SIN are at a second potential, such as a high potential. Transistors M11 and M13 are turned on, while transistors M15 and M17 are turned off. The high potential of the input signal SIN is transmitted to the second node N2 via transistor M11, causing transistors M12, M18, and the first transistor M102 in the second output module 30 to turn off. The first potential signal VGL is transmitted to the third node N3 via transistor M13, causing transistors M14 and M16 to turn on. Under the storage effect of capacitor C1, the first node N1 maintains the high potential of the previous phase, causing the first transistor M101 in the first output module 20 to turn off. Therefore, in phase T21, the drive signal GOUT maintains the low potential of the previous phase. At this time, for the first output module 20, the second transistor M201 is turned on, shorting the second gate of the first transistor M101 in the first output module 20 to the first electrode, causing the threshold voltage of the first transistor M101 to be negatively biased, thereby enhancing the off-state performance of the first transistor M101. For the second output module 30, the third transistor M302 is turned on, transmitting the high potential of the second node N2 to the second gate of the first transistor M102 in the second output module 30.

[0150] In stage T22, the fourth clock signal CLK4 is at a first potential, such as a low potential, and the third clock signal CLK3 and the input signal SIN are at a second potential, such as a high potential. Transistors M15 and M17 are turned on, while transistors M11 and M13 are turned off. Due to the storage function of capacitor C13, the third node N3 maintains the low potential of the previous stage, causing transistors M14 and M16 to turn on. The second potential signal VGH is transmitted to the second node N2 through transistors M14 and M15, causing transistors M12, M18, and the first transistor M102 in the second output module 30 to remain in an off state. The low potential of the fourth clock signal CLK4 is transmitted to the first node N1 through transistors M16 and M17, causing the first transistor M101 in the first output module 20 to turn on. The second potential signal VGH is output through the first transistor M101 in the first output module 20, and the drive signal GOUT becomes a high potential. At this time, for the first output module 20, the second transistor M201 is turned off and the third transistor M301 is turned on, shorting the second gate of the first transistor M101 to the first gate. The threshold voltage of the first transistor M101 is positively biased, thereby enhancing the on-state performance of the first transistor M101. For the second output module 30, the first and second electrodes of the second transistor M202 are both at a high potential. The third transistor M302 is turned off and the second transistor M202 is turned on. This shorts the second gate of the first transistor M102 in the second output module 30 to the first electrode. The threshold voltage of the first transistor M102 is negatively biased, thereby enhancing the off-state performance of the first transistor M102.

[0151] In stage T23, the third clock signal CLK3 is at a first potential, for example, a low potential, and the fourth clock signal CLK4 and the input signal SIN are at a second potential, for example, a high potential. Transistors M11 and M13 are turned on, and transistors M15 and M17 are turned off. The high potential of the input signal SIN is transmitted to the second node N2 via transistor M11; due to the storage effect of capacitor C1, the first node N1 maintains the low potential of the previous stage. Therefore, the first transistor M101 in the first output module 20 remains on, the first transistor M102 in the second output module 30 remains off, and the drive signal GOUT maintains a high potential. At this time, for the first output module 20, the second transistor M201 is turned off, and the third transistor M301 is turned on to enhance the on-state performance of the first transistor M101. For the second output module 30, the third transistor M302 is turned off and the second transistor M202 is turned on, so that the second gate of the first transistor M102 in the second output module 30 is short-circuited with the first electrode, and the threshold voltage of the first transistor M102 is negatively biased to enhance the off-state performance of the first transistor M102.

[0152] In stage T24, the third clock signal CLK3 is at a second potential, such as a high potential, and the fourth clock signal CLK4 and the input signal SIN are at a first potential, such as a low potential. Transistors M11 and M13 are turned off, while transistors M15 and M17 are turned on. Due to the storage function of capacitor C13, the third node N3 maintains the low potential of the previous stage, causing transistors M14 and M16 to turn on. The second potential signal VGH is transmitted to the second node N2 via transistors M14 and M15, causing transistors M12, M18, and the first transistor M102 in the second output module 30 to remain in an off state. The low potential of the fourth clock signal CLK4 is transmitted to the first node N1 via transistors M16 and M17, causing the first transistor M101 in the first output module 20 to turn on. The second potential signal VGH is output via the first transistor M101 in the first output module 20, and the drive signal GOUT remains at a high potential. At this time, for the first output module 20, the second transistor M201 is turned off and the third transistor M301 is turned on, thereby enhancing the on-state performance of the first transistor M101. For the second output module 30, the third transistor M302 is turned off and the second transistor M202 is turned on, so that the second gate of the first transistor M102 in the second output module 30 is short-circuited to the first electrode, and the threshold voltage of the first transistor M102 is negatively biased, thereby enhancing the off-state performance of the first transistor M102.

[0153] In phase T25, the fourth clock signal CLK4 is at a second potential, such as a high potential, while the third clock signal CLK3 and the input signal SIN are at a first potential, such as a low potential. Transistors M11 and M13 are turned on, while transistors M15 and M17 are turned off. The low potential of the input signal SIN is transmitted to the second node N2 via transistor M11, turning on transistors M12, M18, and the first transistor M102 in the second output module 30. The low potential of the third clock signal CLK3 is transmitted to the third node N3 via transistor M12, turning on transistors M14 and M16. However, since transistor M17 is turned off, the low potential of the third node N3 cannot be transmitted to the first node N1. The high potential of the second potential signal VGH is transmitted to the first node N1 via transistor M18, turning off the first transistor M101 in the first output module 20. The first potential signal VGL is output via the first transistor M102 in the second output module 30, causing the drive signal OUT1 to go low. At this time, for the first output module 20, the third transistor M301 is turned off and the second transistor M201 is turned on, shorting the second gate of the first transistor M101 to the first gate, causing the threshold voltage of the first transistor M101 to be negatively biased, thereby enhancing the off-state performance of the first transistor M101. For the second output module 30, the second transistor M202 is turned off and the third transistor M302 is turned on, shorting the second gate of the first transistor M102 to the first gate, causing the threshold voltage of the first transistor M102 to be positively biased, thereby enhancing the on-state performance of the first transistor M102.

[0154] In stage T26, the third clock signal CLK3 is at a second potential, such as a high potential, and the fourth clock signal CLK4 and the input signal SIN are at a first potential, such as a low potential. Transistors M15 and M17 are turned on. Due to the bootstrap effect of capacitor C2, as the fourth clock signal CLK4 becomes low, the potential of the second node N2 becomes lower than that in stage T25, causing transistors M12, transistor M18, and the first transistor M102 in the second output module 30 to remain on. The high potential of the third clock signal CLK3 is transmitted to the third node N3 via transistor M12. The second potential signal VGH is transmitted to the first node N1 via transistor M18, causing the first transistor M101 in the first output module 20 to remain off. Compared to the previous stage, although transistor M17 is turned on in this stage, since the potential of the third node N3 has become high, it does not pull down the potential of the first node N1, allowing the first node N1 to remain high. The first potential signal VGL is output through the first transistor M102 in the second output module 30, and the drive signal GOUT maintains a low potential. At this time, for the first output module 20, the third transistor M301 is turned off and the second transistor M201 is turned on to enhance the off-state performance of the first transistor M101. For the second output module 30, the second transistor M202 is turned off and the third transistor M302 is turned on to enhance the on-state performance of the first transistor M102.

[0155] The subsequent stages repeat the stages T25 and T26 until the input signal SIN changes to the second potential (eg, a high potential) again.

[0156] In summary, the embodiment of the present invention provides a driving circuit with a dynamic adjustment function, and proposes a solution to the balance requirement of threshold voltage-driving capability (effective operating voltage VGS)-reliability in different driving stages. By connecting the second gate of the four-terminal output tube device in the driving circuit to a threshold voltage adjustment unit to control the short-circuit mode between the second gate and the first pole and the first gate, threshold voltage adjustment in different directions can be achieved in different working stages, so that a single device has multiple characteristics, greatly reducing the difficulty of device process control and debugging, and can achieve broadband refresh while ensuring the stability of the circuit output. At the same time, the feedback subunit does not introduce additional control signals, which is conducive to reducing power consumption.

[0157] An embodiment of the present invention further provides a method for controlling a drive circuit, which is used to control a drive circuit as provided in any embodiment of the present invention, and has corresponding beneficial effects. The method for controlling the drive circuit includes: a first operating mode and / or a second operating mode;

[0158] In the first working mode, the first transistor is controlled to be turned off and the first feedback subunit is controlled to be turned on, so that the first electrode of the first transistor is connected to the second gate via the turned-on first feedback subunit to improve the off-state performance of the first transistor.

[0159] In the second working mode, the first transistor is controlled to be turned on, and the second feedback subunit is controlled to be turned on, so that the first gate of the first transistor is connected to the second gate via the turned-on second feedback subunit, so as to improve the on-state performance of the first transistor.

[0160] The control method for a drive circuit provided in an embodiment of the present invention adjusts the threshold voltage of the first transistor when the first transistor is turned off, thereby ensuring that the first transistor is reliably turned off. And / or, adjusts the threshold voltage of the first transistor when the first transistor is turned on, thereby ensuring that the first transistor is reliably turned on, via the second feedback subunit 112. By controlling the on-time periods of the first feedback subunit and the second feedback subunit, dynamic adjustment of the threshold voltage of the first transistor in different directions under different operating modes can be achieved, effectively balancing the different requirements for reliability, output capability, and threshold voltage of the output transistor of the drive circuit, thereby improving the output stability and process window of the drive circuit.

[0161] Based on the above embodiments, optionally, the driving circuit includes: an input control module, a first output module, and a second output module; the first output module is connected to the input control module; the second output module is connected to the input control module; wherein at least one switch module includes a first switch module and / or a second switch module, the first output module includes the first switch module, and / or the second output module includes the second switch module;

[0162] The control method includes:

[0163] The first output module outputs the first signal to the output end of the driving circuit according to the control of the input control module; at this time, the first switch module operates in the second operating mode, and / or the second switch module operates in the first operating mode.

[0164] The second output module outputs a second signal to the output end of the driving circuit according to the control of the input control module; at this time, the first switch module operates in the first operating mode, and / or the second switch module operates in the second operating mode.

[0165] Optionally, within the same switch module, when the first feedback subunit 111 is on, the second feedback subunit 112 is off; and when the second feedback subunit 112 is on, the first feedback subunit 111 is off. The first feedback subunit 111 and the second feedback subunit 112 may not be on at the same time. This ensures the threshold adjustment effect of the first transistor at each stage.

[0166] It should be noted that in each embodiment of the driving circuit, specific descriptions of the control methods are given for different driving circuits. These control methods can all be considered as the control methods of the driving circuit provided by the embodiments of the present invention, and repeated content will not be repeated here.

[0167] Embodiments of the present invention further provide a display panel including a drive circuit as provided in any embodiment of the present invention, which has corresponding beneficial effects. For example, the display panel can be an active matrix organic light-emitting diode panel or a micro-LED display panel. The drive circuit can be a scanning circuit or a shift register, and can adopt a dual-ended drive or single-ended drive structure, which is not limited here.

[0168] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0169] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A driving circuit, characterized in that: include: At least one switch module, any of the switch modules comprising: A first transistor, wherein the first transistor is a vertical double-gate transistor, and the first transistor includes a first gate, a second gate, a first electrode, and a second electrode; A threshold voltage adjustment unit, the threshold voltage adjustment unit including a first feedback subunit and / or a second feedback subunit; the first feedback subunit is connected between the first electrode and the second gate of the first transistor, and is used to connect the first electrode of the first transistor to the second gate via the first feedback subunit when the first transistor is turned off, so as to improve the off-state performance of the first transistor; the second feedback subunit is connected between the first gate and the second gate of the first transistor, and is used to connect the first gate of the first transistor to the second gate via the second feedback subunit when the first transistor is turned on, so as to improve the on-state performance of the first transistor.

2. The driving circuit according to claim 1, wherein: The first feedback subunit includes a first feedback control terminal, and the second feedback subunit includes a second feedback control terminal; The first feedback control terminal is electrically connected to the second electrode of the first transistor, and the second feedback control terminal is electrically connected to the first gate of the first transistor; Alternatively, the first feedback control terminal is electrically connected to the second gate of the first transistor, and the second feedback control terminal is electrically connected to the first electrode of the first transistor or the first gate of the first transistor.

3. The driving circuit according to claim 2, wherein: The driving circuit further includes: an input control module, a first output module and a second output module; The first output module is connected to the input control module, and outputs a first signal to the output end of the driving circuit according to the control of the input control module; the second output module is connected to the input control module, and outputs a second signal to the output end of the driving circuit according to the control of the input control module; The at least one switch module includes a first switch module and / or a second switch module, the first output module includes the first switch module, and / or the second output module includes the second switch module.

4. The driving circuit according to claim 3, wherein: The first output module includes the first switch module, and the threshold voltage adjustment unit of the first switch module includes the first feedback subunit and / or the second feedback subunit; In the first switch module, the first feedback control terminal is electrically connected to the second electrode of the first transistor, and / or the second feedback control terminal is electrically connected to the first gate of the first transistor.

5. The driving circuit according to claim 4, wherein: The second electrode of the first transistor in the first switch module is electrically connected to the output end of the driving circuit.

6. The driving circuit according to claim 4, wherein: The first electrode of the first transistor in the first switch module is electrically connected to the first potential signal line.

7. The driving circuit according to claim 3, wherein: The second output module includes the second switch module, and the threshold voltage adjustment unit of the second switch module includes the first feedback subunit and / or the second feedback subunit; In the second switch module, the second electrode of the first transistor is electrically connected to the second potential signal line; the first feedback control terminal is electrically connected to the second gate of the first transistor, and / or the second feedback control terminal is electrically connected to the first electrode of the first transistor or the first gate of the first transistor; or, In the second switch module, the second electrode of the first transistor is electrically connected to the first clock signal line; the first feedback control terminal is electrically connected to the second gate of the first transistor, and / or the second feedback control terminal is electrically connected to the first electrode of the first transistor.

8. The driving circuit according to claim 7, wherein: The first electrode of the first transistor in the second switch module is electrically connected to the output end of the driving circuit.

9. The driving circuit according to claim 3, wherein: The input control module includes: a first input unit, a second input unit, a node potential control unit and a first node mutual control unit; The control end of the first input unit is connected to a first clock signal, the input end of the first input unit is connected to an input signal, and the output end of the first input unit is electrically connected to the second output module; the first control end of the second input unit is connected to the input signal, the second control end of the second input unit is connected to the first clock signal, and the input end of the second input unit is connected to a first potential signal; the control end of the node potential control unit is electrically connected to the output end of the second input unit, the input end of the node potential control unit is connected to a second clock signal, and the output end of the node potential control unit is electrically connected to the first output module; the control end of the first node mutual control unit is electrically connected to the output end of the first input unit, the input end of the first node mutual control unit is connected to the first potential signal, and the output end of the first node mutual control unit is electrically connected to the first output module; Alternatively, the input control module includes: a first input unit, a second input unit, a node potential control unit and a first node mutual control unit; The control end of the first input unit is connected to the input signal, the input end of the first input unit is connected to the second potential signal, and the output end of the first input unit is electrically connected to the second output module; the first control end of the second input unit is connected to the input signal, the second control end of the second input unit is connected to the first clock signal, and the input end of the second input unit is connected to the first potential signal; the control end of the node potential control unit is electrically connected to the output end of the second input unit, the input end of the node potential control unit is connected to the second clock signal, and the output end of the node potential control unit is electrically connected to the first output module; the control end of the first node mutual control unit is electrically connected to the output end of the first input unit, the input end of the first node mutual control unit is connected to the first potential signal, and the output end of the first node mutual control unit is electrically connected to the first output module.

10. The driving circuit according to claim 2, wherein: The first feedback subunit includes: a second transistor; the gate of the second transistor serves as the first feedback control terminal, the first electrode of the second transistor is electrically connected to the first electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the second gate of the first transistor; The second feedback subunit includes: a third transistor; the gate of the third transistor serves as the second feedback control terminal, the first electrode of the third transistor is electrically connected to the first gate of the first transistor, and the second electrode of the third transistor is electrically connected to the second gate of the first transistor.

11. The driving circuit according to claim 10, wherein: The first transistor is an N-type transistor; when the first gate of the first transistor is connected to the second gate via the conductive second feedback subunit, the threshold voltage of the first transistor is negatively biased; when the first gate of the first transistor is connected to the first electrode via the conductive first feedback subunit, the threshold voltage of the first transistor is positively biased; Alternatively, the first transistor is a P-type transistor; when the first gate of the first transistor is connected to the second gate via the conductive second feedback sub-unit, the threshold voltage of the first transistor is positively biased; when the first gate of the first transistor is connected to the first electrode via the conductive first feedback sub-unit, the threshold voltage of the first transistor is negatively biased.

12. A control method for a driving circuit, characterized in that: The driving circuit includes: at least one switching module, any of the switching modules including: a first transistor and a threshold voltage adjustment unit; the first transistor is a vertical dual-gate transistor, the first transistor including a first gate, a second gate, a first electrode, and a second electrode; the threshold voltage adjustment unit includes a first feedback subunit and / or a second feedback subunit; the first feedback subunit is connected between the first electrode and the second gate of the first transistor; the second feedback subunit is connected between the first gate and the second gate of the first transistor; The control method includes: a first working mode and / or a second working mode; In the first operating mode, controlling the first transistor to be turned off and controlling the first feedback subunit to be turned on, so that the first electrode of the first transistor is connected to the second gate via the turned-on first feedback subunit, so as to improve the off-state performance of the first transistor; In the second working mode, the first transistor is controlled to be turned on, and the second feedback subunit is controlled to be turned on, so that the first gate of the first transistor is connected to the second gate through the turned-on second feedback subunit, so as to improve the on-state performance of the first transistor.

13. The control method of the driving circuit according to claim 12, characterized in that: The driving circuit further includes: an input control module, a first output module, and a second output module; the first output module is connected to the input control module; the second output module is connected to the input control module; wherein the at least one switch module includes a first switch module and / or a second switch module, the first output module includes the first switch module, and / or the second output module includes the second switch module; The control method includes: The first output module outputs a first signal to the output end of the driving circuit according to the control of the input control module; at this time, the first switch module operates in the second operating mode, and / or the second switch module operates in the first operating mode; The second output module outputs a second signal to the output end of the driving circuit according to the control of the input control module; at this time, the first switch module operates in the first operating mode, and / or the second switch module operates in the second operating mode.

14. The control method of the driving circuit according to claim 13, characterized in that: In the same switch module, when the first feedback subunit is turned on, the second feedback subunit is turned off; when the second feedback subunit is turned on, the first feedback subunit is turned off.

15. A display panel, characterized in that: The drive circuit comprises the drive circuit according to any one of claims 1 to 11.

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