Display panel, manufacturing method and display device

Abstract

The present application discloses a display panel, a preparation method and a display device, which relate to the field of display technology and can improve the influence of the edge of a semiconductor structure on the quality of a subsequent film layer, thereby improving the electrical performance of a transistor. A display panel comprises: a substrate layer; a first gate insulating layer, which is arranged on one side of the substrate layer, the first gate insulating layer having an opening, and a semiconductor structure is arranged in the opening; a second gate insulating layer, the first gate insulating layer is arranged between the substrate layer and the second gate insulating layer, and the second gate insulating layer covers the semiconductor structure and the first gate insulating layer.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel, a preparation method and a display device. Background Art

[0002] In the field of display technology, the driving circuit of the display pixel of the display panel includes a transistor, and the semiconductor structure usually serves as the channel of the transistor. Since multiple transistors are arranged in the display panel, the semiconductor structure is patterned during the preparation process of the display panel, and it is necessary to use an etching process or other processes to realize the patterned semiconductor structure.

[0003] However, in the process of patterning the semiconductor layer to obtain a semiconductor structure, a slope angle will be formed at the edge of the semiconductor structure. The slope angle will affect the coverage of the semiconductor structure by the subsequently prepared film layer. The edge of the semiconductor structure with a slope angle will affect the film quality of the subsequently prepared film layer, thereby affecting the electrical performance of the transistor. Summary of the invention

[0004] The embodiments of the present application provide a display panel, a manufacturing method and a display device, which can improve the influence of the edge of the semiconductor structure on the film quality of the subsequently prepared film layer, thereby improving the electrical performance of the transistor.

[0005] According to a first aspect of an embodiment of the present application, a display panel is provided, comprising:

[0006] substrate layer;

[0007] A first gate insulating layer, disposed on one side of the substrate layer, the first gate insulating layer having an opening, and a semiconductor structure is disposed in the opening;

[0008] A second gate insulating layer, wherein the first gate insulating layer is disposed between the substrate layer and the second gate insulating layer, and the second gate insulating layer covers the semiconductor structure and the first gate insulating layer.

[0009] In some embodiments, the second gate insulating layer includes a first region and a second region, the second region at least partially surrounds the first region, and an orthographic projection of the semiconductor structure on the second gate insulating layer falls into the first region;

[0010] A surface of the second gate insulating layer in the first region away from the substrate layer and a surface of the second gate insulating layer in the second region away from the substrate layer belong to the same plane.

[0011] In some embodiments, a thickness of a gate insulating layer corresponding to the first region is smaller than a thickness of a gate insulating layer corresponding to the second region, wherein the gate insulating layer includes the first gate insulating layer and the second gate insulating layer.

[0012] In some embodiments, the display panel further includes:

[0013] A gate structure, disposed on a side of the second gate insulating layer away from the substrate layer, wherein an orthographic projection of the gate structure on the substrate layer at least partially covers an orthographic projection of the semiconductor structure on the substrate layer;

[0014] The thickness of the gate insulating layer between the semiconductor structure and the gate structure is smaller than the thickness of the gate insulating layer corresponding to the second region.

[0015] In some embodiments, a surface of the first gate insulating layer away from the substrate layer and a surface of the semiconductor structure away from the substrate layer belong to the same plane; and / or,

[0016] The thickness of the semiconductor structure is the same as the thickness of the first gate insulating layer.

[0017] In some embodiments, the first gate insulating layer and the second gate insulating layer are obtained by at least two process steps.

[0018] In some embodiments, the opening is obtained by etching the first gate insulating layer corresponding to the first region;

[0019] or,

[0020] The process for preparing the semiconductor structure is prior to the process for preparing the first gate insulating layer.

[0021] In some embodiments, a surface of the first gate insulating layer away from the substrate layer and a surface of the semiconductor structure away from the substrate layer belong to the same plane and are obtained by etching the first gate insulating layer away from the substrate layer.

[0022] According to a second aspect of an embodiment of the present application, a method for manufacturing a display panel is provided, comprising:

[0023] A first gate insulating layer and a semiconductor structure are respectively prepared on one side of the substrate layer, wherein the first gate insulating layer has an opening, and the semiconductor structure is arranged in the opening;

[0024] A second gate insulating layer is provided so that the second gate insulating layer covers the semiconductor structure and the first gate insulating layer.

[0025] In some embodiments, providing a second gate insulating layer includes:

[0026] The second gate insulating layer is arranged so that a surface of the second gate insulating layer in the first region away from the substrate layer and a surface of the second gate insulating layer in the second region away from the substrate layer belong to the same plane, wherein the second region at least partially surrounds the first region, and an orthographic projection of the semiconductor structure on the second gate insulating layer falls into the first region.

[0027] In some embodiments, the step of separately preparing a first gate insulating layer and a semiconductor structure on one side of the substrate layer includes:

[0028] Disposing the semiconductor structure on one side of the substrate layer;

[0029] Disposing the first gate insulating layer on a side of the semiconductor structure away from the substrate layer;

[0030] The side of the first gate insulation layer away from the substrate layer is etched so that the surface of the first gate insulation layer away from the substrate layer and the surface of the semiconductor structure away from the substrate layer belong to the same plane, and / or so that the thickness of the semiconductor structure is the same as the thickness of the first gate insulation layer.

[0031] In some embodiments, the step of separately preparing a first gate insulating layer and a semiconductor structure on one side of the substrate layer includes:

[0032] Disposing the first gate insulating layer on one side of the substrate layer;

[0033] Etching the first gate insulating layer corresponding to the first region to obtain the opening;

[0034] The semiconductor structure is disposed in the opening.

[0035] In some embodiments, before providing the second gate insulating layer, the method further includes:

[0036] The side of the semiconductor structure away from the substrate layer is etched so that the surface of the first gate insulation layer away from the substrate layer and the surface of the semiconductor structure away from the substrate layer belong to the same plane.

[0037] In some embodiments, disposing the semiconductor structure in the opening includes:

[0038] The semiconductor structure having the same thickness as that of the first gate insulating layer is disposed in the opening.

[0039] In some embodiments, the method for preparing the display panel further includes:

[0040] A gate structure is arranged on a side of the second gate insulation layer away from the substrate layer, so that the orthographic projection of the gate structure on the substrate layer at least partially covers the orthographic projection of the semiconductor structure on the substrate layer, wherein the thickness of the gate insulation layer between the semiconductor structure and the gate structure is less than the thickness of the gate insulation layer in the second region.

[0041] According to a third aspect of the embodiments of the present application, a display device is provided, including:

[0042] A display panel as described in the first aspect.

[0043] The display panel provided in the embodiment of the present application divides the gate insulating layer into a first gate insulating layer and a second gate insulating layer, the first gate insulating layer includes an opening, and the semiconductor structure is arranged in the opening, which is equivalent to the semiconductor structure being embedded in the first gate insulating layer, and the second gate insulating layer covers the first gate insulating layer and the semiconductor structure. The first gate insulating layer and the second gate insulating layer are arranged in layers, and even if cracks are formed on the edge of the semiconductor structure on the first gate insulating layer, the cracks will not extend to the second gate insulating layer, and the second gate insulating layer corresponding to the edge of the semiconductor structure will not produce cracks, cracks or fissures caused by the slope angle of the semiconductor structure, and the second gate insulating layer is a complete film layer. If there are no cracks, cracks or fissures in the film layer of the second gate insulating layer, it will not cause defects in the film layer prepared subsequently, for example, it will not cause defects in the gate, and thus will not cause defects in display bright spots, which can greatly improve the uniformity of the gate performance of the transistors in the display panel, and thus improve the display uniformity of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic partial structural diagram of a display panel provided in an embodiment of the present application;

[0045] Figure 2 A schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present application;

[0046] Figure 3 A scanning electron microscope cross-sectional view of a display panel provided in an embodiment of the present application;

[0047] Figure 4 A schematic partial structural diagram of another display panel provided in an embodiment of the present application;

[0048] Figure 5 A schematic partial structural diagram of another display panel provided in an embodiment of the present application;

[0049] Figure 6 A schematic partial structural diagram of another display panel provided in an embodiment of the present application;

[0050] Figure 7A schematic flow chart of a method for preparing a display panel provided in an embodiment of the present application;

[0051] Figure 8 A schematic structural change flow chart of a method for manufacturing a display panel provided in an embodiment of the present application;

[0052] Fig. 9 A schematic structural change flow chart of a method for manufacturing a display panel provided in an embodiment of the present application;

[0053] Fig.10 A schematic structural diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to better understand the technical solutions provided by the embodiments of this specification, the technical solutions of the embodiments of this specification are described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0055] In this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. The term "more than two" includes two or more than two situations.

[0056] In the field of display technology, the driving circuit of the display pixel of the display panel includes a transistor, and the semiconductor structure is usually used as the channel of the transistor. Since a plurality of transistors are arranged in the display panel, the semiconductor structure is patterned during the preparation process of the display panel, and the patterned semiconductor structure needs to be realized by means of an etching process or other processes. However, in the process of patterning the semiconductor layer to obtain the semiconductor structure, a slope angle will be formed at the edge of the semiconductor structure, and the slope angle will affect the coverage of the semiconductor structure by the film layer prepared subsequently. The edge of the semiconductor structure with a slope angle will affect the film quality of the film layer prepared subsequently, and further affect the electrical performance of the transistor.

[0057] In view of this, the embodiments of the present application provide a display panel, a manufacturing method and a display device, which can improve the influence of the edge of the semiconductor structure on the film quality of the subsequently prepared film layer, thereby improving the electrical performance of the transistor.

[0058] According to a first aspect of an embodiment of the present application, a display panel is provided. Figure 1 This is a schematic partial structural diagram of a display panel provided in an embodiment of the present application. Figure 1 As shown, the display panel provided by the embodiment of the present application includes: a substrate layer 100, a first gate insulating layer 200, a semiconductor structure 300 and a second gate insulating layer 400; the substrate layer 100 can be a hard substrate, such as glass, and the substrate layer 100 can also be a flexible substrate, such as a polyimide material, which is not specifically limited in the embodiment of the present application; the semiconductor structure 300 can be used as a channel of a transistor in the display panel; the first gate insulating layer 200 and the second gate insulating layer 400 are used to insulate and isolate the semiconductor structure 300 from the gate structure, so as to achieve the switching performance of the channel of the transistor. Exemplarily, the materials of the first gate insulating layer 200 and the second gate insulating layer 400 can be the same or different. It should be noted that when the materials of the first gate insulating layer 200 and the second gate insulating layer 400 are the same, the second gate insulating layer 400 covers the first gate insulating layer 200 and is tightly attached to the first gate insulating layer 200, which may easily cause the boundary between the second gate insulating layer 400 and the first gate insulating layer 200 to be unclear or even invisible during the product film layer slice analysis. This is not specifically limited in the embodiments of the present application. The first gate insulating layer 200 and the second gate insulating layer 400 may include silicon oxide or silicon nitride, or may be a film layer stack of silicon oxide and silicon nitride, which is not specifically limited in the embodiments of the present application. The first gate insulating layer 200 is disposed on one side of the substrate layer 100, and the first gate insulating layer 200 has an opening 210, and a semiconductor structure 300 is disposed in the opening 210. The opening 210 is Figure 1 The first gate insulating layer 200 is disposed between the substrate layer 100 and the second gate insulating layer 400, and the second gate insulating layer 400 covers the semiconductor structure 300 and the first gate insulating layer 200. It can be understood that the first gate insulating layer 200 and the second gate insulating layer 400 wrap the semiconductor structure 300 to insulate the semiconductor structure 300 from other structures.

[0059] It should be noted that the display panel provided in the embodiment of the present application may be a liquid crystal display panel, an organic light emitting display panel, a laser display panel, etc., which is not specifically limited in the embodiment of the present application. The semiconductor structure 300 may be amorphous silicon, polycrystalline silicon or metal oxide, etc., and the transistor formed by the semiconductor structure 300 may be used to form a pixel driving circuit, a shift register circuit, a multiplexer circuit, etc. of the display panel, which is not specifically limited in the embodiment of the present application.

[0060] For example, OLED (Organic Light Emitting Diode) has become one of the hot spots in the current display research field due to its advantages such as low energy consumption, low production cost, self-luminescence, wide viewing angle and fast response speed. However, the OLED process is relatively complex, which will lead to poor display uniformity, especially low grayscale display uniformity, and there will be more serious mura (uneven brightness) and other phenomena. Improving the display uniformity of OLED products, including brightness uniformity, low grayscale uniformity, electrical uniformity and other issues, display uniformity is one of the key parameters. In the OLED display panel, a plurality of light-emitting pixels are included, each pixel includes a pixel circuit and a light-emitting device, the pixel circuit is used to drive the light-emitting device to emit light, the pixel circuit includes a storage capacitor and a plurality of TFTs (thin film transistors), and the pixel circuit structure of 7T1C (7 TFTs and 1 storage capacitor) is currently used more. Faced with users' higher requirements for product picture quality and display uniformity, R&D personnel need to start from the product itself and put forward higher requirements for the process manufacturing process. As the requirements for the image quality and display uniformity of display products become higher and higher, higher requirements are also placed on the electrical uniformity of TFT.

[0061] ELA (Excimer Laser Annealing) can convert a-Si (amorphous-Silicon) into P-Si (Poly-Silicon). As a semiconductor structure, polysilicon has a high mobility and high stability. However, due to the limitations of coating and etching process technology, it is easy to cause uneven display and heavy low grayscale mura when the gate insulation layer is plated after P-Si film formation. In severe cases, it is accompanied by cracks in the gate insulation layer, which can easily cause a short circuit between the gate and the source and drain, resulting in poor functionality. The presence of cracks or cracks in the gate insulation layer will cause the gate and the polysilicon semiconductor to short at the crack or crack position, resulting in poor display of bright spots.

[0062] For example, Figure 2 Schematic diagram of a pixel driving circuit provided in an embodiment of the present application. Figure 2 As shown, the pixel driving circuit adopts the 7T1C setting. Figure 2The pixel driving circuit shown is applied to an OLED display panel, and under the drive of an anode signal VDD, a cathode signal VSS, a scanning signal Gate, a data signal Vdata, an enable signal EM and a reset signal Reset, respectively controls the opening and closing of a reset transistor T1, a compensation transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7, thereby driving the light-emitting device OLED to emit light for displaying a picture. The storage capacitor Cst can be used to maintain the potential of the first potential point N1. Figure 2 The direction of the arrow indicates the current direction of the light emitting device OLED. When the transistor structure with cracks is used as the reset transistor T1 and the compensation transistor T2 of the pixel driving circuit, it is easy to cause the leakage of T1 and T2 to lower the potential of the first potential point N1, resulting in poor bright spots. The lower the grayscale, the higher the potential of N1, the greater the voltage difference between the source and drain of T1 and T2, the greater the leakage, and the more obvious the poor bright spots.

[0063] For example, Figure 3 This is a scanning electron microscope cross-sectional view of a display panel provided in an embodiment of the present application. Figure 3 As shown, under the current process, the gate insulating layer GI is prepared after the P-Si semiconductor, that is, the entire gate insulating layer GI covers the P-Si semiconductor. Due to the limitation of the process level, the gate insulating layer GI is directly formed on the P-Si semiconductor, which easily forms cracks at the edge of the P-Si semiconductor. The cracks make the film uniformity of the gate insulating layer GI worse. Continuing to prepare the gate on the gate insulating layer GI easily leads to poor uniformity of the gate, which will cause poor display bright spots at the corresponding position, resulting in poor display uniformity of the display panel and affecting the display effect. The generation of cracks is usually caused by the slope angle of P-Si. The larger the slope angle of P-Si, the easier it is for the gate insulating layer GI to generate cracks.

[0064] To solve the above problems, the slope angle of P-Si can be reduced. By reducing the slope angle of P-Si, the gate insulation layer GI can be coated with good coverage, and the occurrence rate of cracks on both sides of P-Si can be reduced, thereby improving the electrical uniformity of TFT, improving the picture quality and display uniformity; at the same time, the occurrence rate of bright spot defects can be reduced and the product yield can be improved. However, the slope angle cannot be reduced indefinitely, and the risk of cracks caused by the existence of the slope angle will always exist, and the bright spot defects cannot be completely improved.

[0065] In view of the above problems, the display panel provided in the embodiment of the present application divides the gate insulating layer into a first gate insulating layer 200 and a second gate insulating layer 400. The first gate insulating layer 200 includes an opening 210, and the semiconductor structure 300 is arranged in the opening 210, which is equivalent to the semiconductor structure 300 being embedded in the first gate insulating layer 200, and the second gate insulating layer 400 covering the first gate insulating layer 200 and the semiconductor structure 300. The first gate insulating layer 200 and the second gate insulating layer 400 are arranged in layers, and even if cracks are formed on the edge of the semiconductor structure 300 on the first gate insulating layer 200, the cracks will not extend to the second gate insulating layer 400, and the second gate insulating layer 400 corresponding to the edge of the semiconductor structure 300 will not generate cracks, cracks or fissures caused by the slope angle of the semiconductor structure 300, and the second gate insulating layer 400 is a complete film layer. If there are no cracks, fissures or fissures in the film layer of the second gate insulating layer 400, it will not cause defects in the subsequently prepared film layer, for example, it will not cause defects in the gate, and will not cause defects in display bright spots. It can greatly improve the uniformity of the gate performance of the transistors in the display panel, and thus improve the display uniformity of the display panel.

[0066] In some embodiments, the first gate insulating layer 200 and the second gate insulating layer 400 are obtained by at least two processes. The first gate insulating layer 200 and the second gate insulating layer 400 are prepared by different processes, so that the first gate insulating layer 200 and the second gate insulating layer 400 can be prepared separately, and the second gate insulating layer 400 is entirely covered on the first gate insulating layer 200 and the semiconductor structure 300, and the interface between the semiconductor structure 300 and the first gate insulating layer 200 can be covered. Even if there are cracks or cracks at the interface between the semiconductor structure 300 and the first gate insulating layer 200, due to different processes, the cracks or cracks will not extend to the second gate insulating layer 400, and the second gate insulating layer 400 can cover the cracks and cracks, and can provide a flat film quality foundation for subsequent film layers, and will not affect the performance of subsequent film layers, so as to eliminate the bad bright spots caused by the contact cracks between the semiconductor structure 300 and the gate insulating layer.

[0067] In some embodiments, reference Figure 1 The second gate insulating layer 400 includes a first region 410 and a second region 420, the second region 420 at least partially surrounds the first region 410, and the orthographic projection of the semiconductor structure 300 on the second gate insulating layer 400 falls into the first region 410. The opening 210 is obtained by etching the first gate insulating layer 200 corresponding to the first region 410. For example, refer to Figure 1 The opening 210 may be a gap penetrating the first gate insulating layer 200 .

[0068] For example, Figure 4This is a schematic partial structural diagram of another display panel provided in an embodiment of the present application. Figure 4 As shown, the opening 210 is a groove that does not penetrate the first gate insulating layer 200, and the opening of the groove is arranged away from the substrate layer 100. The opening 210 in the form of a groove can separate the semiconductor structure 300 from the substrate layer 100 to prevent the intrusion of impurity ions in the substrate layer 100. The etching time is also short, and the etching process is easy to implement.

[0069] It should be noted that, when the first gate insulating layer 200 is prepared first and the semiconductor structure 300 is prepared later, the semiconductor structure 300 needs to be etched after film formation, so that the semiconductor material outside the first region 410 can be removed, and the surface of the semiconductor structure can be smoothed by etching the semiconductor material. The upper surface of the semiconductor structure 300 can be set to be flush with the upper surface of the first gate insulating layer 200, so as to avoid the second gate insulating layer 400 covering the first gate insulating layer 200 and the semiconductor structure 300, causing the film layer of the second gate insulating layer 400 to bulge, thereby causing the film layer crack problem again.

[0070] Exemplary, reference Figure 1 , the surface of the first gate insulating layer 200 away from the substrate layer 100 and the surface of the semiconductor structure 300 away from the substrate layer 100 belong to the same plane, and the thickness of the semiconductor structure 300 is the same as that of the first gate insulating layer 200. This can avoid the problem of film bulges of the second gate insulating layer 400 and film cracks caused again after the second gate insulating layer 400 covers the first gate insulating layer 200 and the semiconductor structure 300. After the second gate insulating layer 400 is formed, the surface of the second gate insulating layer 400 away from the substrate layer 100 in the first region 410 and the surface of the second gate insulating layer 400 away from the substrate layer 100 in the second region 420 belong to the same plane. This can avoid causing cracks in the second gate insulating layer 400.

[0071] It should be noted that, since it is usually difficult to make the surface of the film layer absolutely flat, the surface of the first gate insulation layer 200 away from the substrate layer 100 and the surface of the semiconductor structure 300 away from the substrate layer 100 belong to the same plane, which means that the surface of the first gate insulation layer 200 away from the substrate layer 100 and the surface of the semiconductor structure 300 away from the substrate layer 100 are flush.

[0072] Exemplary, reference Figure 4The surface of the first gate insulating layer 200 away from the substrate layer 100 and the surface of the semiconductor structure 300 away from the substrate layer 100 belong to the same plane, the thickness of the semiconductor structure 300 is different from the thickness of the first gate insulating layer 200, and the thickness of the semiconductor structure 300 is less than the thickness of the first gate insulating layer 200, which can also avoid cracks in the second gate insulating layer 400.

[0073] It should be noted that a buffer layer may be provided between the first gate insulating layer 200 and the substrate layer 100 . The buffer layer may prevent impurity ions in the substrate layer 100 from penetrating into the semiconductor structure 300 . The material of the buffer layer may include a stack of silicon nitride and silicon oxide film layers.

[0074] In some embodiments, the process for preparing the semiconductor structure 300 is before the process for preparing the first gate insulating layer 200. Exemplarily, the semiconductor structure 300 is prepared first, and then the first gate insulating layer 200 is prepared. The first gate insulating layer 200 covers the side of the semiconductor structure 300 away from the substrate layer 100, and the first gate insulating layer 200 corresponding to the semiconductor structure 300 is relatively convex. The first gate insulating layer 200 on the semiconductor structure 300 can be etched away partially or entirely by etching, so that the surface of the first gate insulating layer 200 is flat.

[0075] Exemplary, reference Figure 1 , first prepare the semiconductor structure 300, and then prepare the first gate insulating layer 200. By etching the first gate insulating layer 200, it can be achieved that the surface of the first gate insulating layer 200 away from the substrate layer 100 and the surface of the semiconductor structure 300 away from the substrate layer 100 belong to the same plane, and the thickness of the semiconductor structure 300 is the same as the thickness of the first gate insulating layer 200.

[0076] For example, Figure 5 A schematic partial structural diagram of another display panel provided in an embodiment of the present application. Figure 5 As shown, the opening of the groove faces the substrate layer 100, and the thickness of the semiconductor structure 300 is less than the thickness of the first gate insulating layer 200. The surface of the first gate insulating layer 200 away from the substrate layer 100 can be etched flat by etching the side of the first gate insulating layer 200 away from the substrate layer 100, thereby not affecting the surface flatness of the second gate insulating layer 400, so as to improve the crack defect.

[0077] In some embodiments, the thickness of the first gate insulating layer 200 may be in the range of 50±1 nm, and the thickness of the second gate insulating layer 400 may be in the range of 120±2 nm, which is only for illustration and is not a specific limitation of the present application.

[0078] In some embodiments, a thickness of a gate insulating layer corresponding to the first region 410 is smaller than a thickness of a gate insulating layer corresponding to the second region 420 , wherein the gate insulating layer includes a first gate insulating layer 200 and a second gate insulating layer 400 .

[0079] In some embodiments, Figure 6 This is a schematic partial structural diagram of another display panel provided in an embodiment of the present application. Figure 6 As shown, the display panel further includes: a gate structure 500, a source electrode 601 and a drain electrode 602. The semiconductor structure 300, the gate structure 500, the source electrode 601 and the drain electrode 602 can constitute a thin film transistor. The gate structure 500 is disposed on a side of the second gate insulating layer 400 away from the substrate layer 100, and the orthographic projection of the gate structure 500 on the substrate layer 100 at least partially covers the orthographic projection of the semiconductor structure 300 on the substrate layer 100; the thickness of the gate insulating layer between the semiconductor structure 300 and the gate structure 500 is less than the thickness of the gate insulating layer corresponding to the second region 420.

[0080] Exemplary, reference Figure 6 The display panel may further include an organic insulating layer 700, an anode 801, a light-emitting layer 802, a cathode 803, a pixel defining structure 810, and an encapsulation layer 900. The anode 801, the light-emitting layer 802, and the cathode 803 may constitute a light-emitting device for active light-emitting display. The source electrode 601 of the thin film transistor is electrically connected to the anode 801, and the thin film transistor may drive the light-emitting device to emit light.

[0081] A second aspect of the embodiments of the present application provides a method for preparing a display panel. Figure 7 The following is a schematic flow chart of a method for manufacturing a display panel provided in an embodiment of the present application. Figure 7 As shown, the method for preparing a display panel provided in an embodiment of the present application includes:

[0082] S101: preparing a first gate insulating layer and a semiconductor structure on one side of a substrate layer, respectively, wherein the first gate insulating layer has an opening, and the semiconductor structure is arranged in the opening.

[0083] refer to Figure 1 , the semiconductor structure 300 is disposed in the opening 210 , which is equivalent to the semiconductor structure 300 being embedded in the first gate insulating layer 200 .

[0084] S102: Disposing a second gate insulating layer so that the second gate insulating layer covers the semiconductor structure and the first gate insulating layer.

[0085] refer to Figure 1, the second gate insulating layer 400 covers the first gate insulating layer 200 and the semiconductor structure 300. The first gate insulating layer 200 and the second gate insulating layer 400 are arranged in layers, and even if cracks are formed on the edge of the semiconductor structure 300 on the first gate insulating layer 200, the cracks will not extend to the second gate insulating layer 400, and the second gate insulating layer 400 corresponding to the edge of the semiconductor structure 300 will not produce cracks, cracks or fissures caused by the slope angle of the semiconductor structure 300, and the second gate insulating layer 400 is a complete film layer. If there are no cracks, cracks or fissures in the film layer of the second gate insulating layer 400, it will not cause defects in the film layer prepared subsequently, such as the gate defect, and thus will not cause poor display bright spots, which can greatly improve the gate performance uniformity of the transistors in the display panel, thereby improving the display uniformity of the display panel.

[0086] In the method for preparing a display panel provided in an embodiment of the present application, the first gate insulating layer 200 and the second gate insulating layer 400 are prepared by different process steps, so that the first gate insulating layer 200 and the second gate insulating layer 400 can be prepared separately. Then, the second gate insulating layer 400 is entirely covered on the first gate insulating layer 200 and the semiconductor structure 300, and the interface between the semiconductor structure 300 and the first gate insulating layer 200 can be covered. Even if there are cracks or fissures at the interface between the semiconductor structure 300 and the first gate insulating layer 200, due to different process steps, the cracks or fissures will not extend to the second gate insulating layer 400. The second gate insulating layer 400 can cover the cracks and fissures, and can provide a smooth film quality foundation for subsequent film layers, which will not affect the performance of subsequent film layers, so as to eliminate the defective bright spots caused by the contact cracks between the semiconductor structure 300 and the gate insulating layer.

[0087] In some implementations, step S102 may include:

[0088] The second gate insulating layer is arranged so that the surface of the second gate insulating layer in the first region away from the substrate layer and the surface of the second gate insulating layer in the second region away from the substrate layer belong to the same plane, wherein the second region at least partially surrounds the first region, and the orthographic projection of the semiconductor structure on the second gate insulating layer falls into the first region. After the second gate insulating layer 400 is formed, the surface of the second gate insulating layer 400 in the first region 410 away from the substrate layer 100 and the surface of the second gate insulating layer 400 in the second region 420 away from the substrate layer 100 belong to the same plane, which can avoid causing cracks in the second gate insulating layer 400.

[0089] In some embodiments, Figure 8 A schematic structural change flow chart of a method for manufacturing a display panel provided in an embodiment of the present application. Figure 8 As shown, step S101 may include:

[0090] S1011: a semiconductor structure 300 is provided on one side of the substrate layer 100. The formation process of the semiconductor structure 300 may include film formation, exposure, development, photoresist removal, and the like.

[0091] S1012: Disposing a first gate insulating layer 200 on a side of the semiconductor structure 300 away from the substrate layer 100;

[0092] S1013: etching the side of the first gate insulating layer 200 away from the substrate layer 100 so that the surface of the first gate insulating layer 200 away from the substrate layer 100 and the surface of the semiconductor structure 300 away from the substrate layer 100 are in the same plane

[0093] Step S1013 can also achieve that the thickness of the semiconductor structure 300 is the same as the thickness of the first gate insulating layer 200 .

[0094] For example, the display panel provided in the embodiment of the present application can first be plated with a first gate insulating layer 200 slightly thicker than the semiconductor structure 300, and then a mask etching process is added to etch the first gate insulating layer 200 covering the semiconductor structure 300 to form a relatively flat surface, and then a second gate insulating layer 400 is plated, which can have good coverage, effectively improve display uniformity and prevent defects caused by short gate and source and drain. The preparation method of the display panel provided in the embodiment of the present application improves the uniformity of the TFT characteristics in the display panel by improving the uniformity of the gate insulating layer, so that during the lighting process of the display panel, when the voltage settings are the same, the internal pixels of the display panel are displayed more uniformly, especially for mura-type defects caused by VTH (threshold voltage) offset. In addition, the bright spots caused by TFT leakage can also be improved to improve the yield. In the actual process, the slope angle of P-Si is basically greater than 70 degrees, and the uniformity is particularly poor, and the controllability is poor in the production process. After the current process improvement, the P-Si slope angle can be basically reduced to about 50 degrees, but the display uniformity is still relatively poor, and the mura situation is still severe; the improvement of the bright spot defect is limited. The method for preparing the display panel provided in the embodiment of the present application can achieve the blocking and covering of the cracks caused by the slope angle by separately preparing the first gate insulating layer 200 and the second gate insulating layer 400, regardless of the P-Si slope angle and the process capability, and can improve the uniformity and yield, improve the uniformity of the second gate insulating layer 400, improve the display uniformity, and reduce the functional defects caused by the short gate and source and drain.

[0095] In some embodiments, Fig. 9 A schematic structural change flow chart of a method for manufacturing a display panel provided in an embodiment of the present application. Fig. 9As shown, step S101 may include:

[0096] S1014 : disposing a first gate insulating layer 200 on one side of the substrate layer 100 .

[0097] S1015: etching the first gate insulating layer 200 corresponding to the first region 410 to obtain an opening 210;

[0098] S1016 : Disposing a semiconductor structure 300 in the opening 210 .

[0099] In some implementations, before step S102, the following steps may also be included:

[0100] The side of the semiconductor structure 300 away from the substrate layer 100 is etched so that the surface of the first gate insulating layer 200 away from the substrate layer 100 and the surface of the semiconductor structure 300 away from the substrate layer 100 belong to the same plane. The planarity of the surfaces of the semiconductor structure 300 and the first gate insulating layer 200 can be achieved by etching the semiconductor structure 300.

[0101] In some implementations, step S1016 may include:

[0102] A semiconductor structure 300 having the same thickness as that of the first gate insulating layer 210 is disposed in the opening 210 .

[0103] In some embodiments, the method for preparing a display panel may further include:

[0104] A gate structure 500 is arranged on a side of the second gate insulation layer 400 away from the substrate layer 100, so that the orthographic projection of the gate structure 500 on the substrate layer 100 at least partially covers the orthographic projection of the semiconductor structure 300 on the substrate layer 100, wherein the thickness of the gate insulation layer between the semiconductor structure 300 and the gate structure 500 is less than the thickness of the gate insulation layer in the second region 420.

[0105] According to a third aspect of the embodiments of the present application, a display device is provided. Fig.10 Schematic diagram of a display device provided in an embodiment of the present application. Fig.10 As shown, the display device provided in the embodiment of the present application includes: the display panel 1000 as described in the first aspect.

[0106] It should be noted that the display device provided in the embodiments of the present application can be any product or component with a display function, such as a smart phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0107] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0108] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

[0109] Although the preferred embodiments of this specification have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of this specification.

[0110] Obviously, those skilled in the art can make various changes and modifications to this specification without departing from the spirit and scope of this specification. Thus, if these modifications and variations of this specification fall within the scope of the claims of this specification and their equivalents, this specification is also intended to include these modifications and variations.

Claims

1. A display panel, characterized in that: include: substrate layer; A first gate insulating layer, disposed on one side of the substrate layer, the first gate insulating layer having an opening, and a semiconductor structure is disposed in the opening; a second gate insulating layer, wherein the first gate insulating layer is disposed between the substrate layer and the second gate insulating layer, and the second gate insulating layer covers the semiconductor structure and the first gate insulating layer; The surface of the first gate insulating layer away from the substrate layer and the surface of the semiconductor structure away from the substrate layer belong to the same plane; and / or, The thickness of the semiconductor structure is the same as the thickness of the first gate insulating layer.

2. The display panel according to claim 1, characterized in that: The second gate insulating layer includes a first region and a second region, the second region at least partially surrounds the first region, and the orthographic projection of the semiconductor structure on the second gate insulating layer falls into the first region; A surface of the second gate insulating layer in the first region away from the substrate layer and a surface of the second gate insulating layer in the second region away from the substrate layer belong to the same plane.

3. The display panel according to claim 2, characterized in that: A thickness of the gate insulating layer corresponding to the first region is smaller than a thickness of the gate insulating layer corresponding to the second region, wherein the gate insulating layer includes the first gate insulating layer and the second gate insulating layer.

4. The display panel according to claim 3, characterized in that: Also includes: A gate structure, disposed on a side of the second gate insulating layer away from the substrate layer, wherein an orthographic projection of the gate structure on the substrate layer at least partially covers an orthographic projection of the semiconductor structure on the substrate layer; The thickness of the gate insulating layer between the semiconductor structure and the gate structure is smaller than the thickness of the gate insulating layer corresponding to the second region.

5. The display panel according to claim 1, characterized in that: The first gate insulating layer and the second gate insulating layer are obtained through at least two process steps.

6. The display panel according to claim 2, characterized in that: The opening is obtained by etching the first gate insulating layer corresponding to the first region; or, The process for preparing the semiconductor structure is prior to the process for preparing the first gate insulating layer.

7. The display panel according to claim 1, characterized in that: The surface of the first gate insulating layer away from the substrate layer and the surface of the semiconductor structure away from the substrate layer belong to the same plane and are obtained by etching the side of the first gate insulating layer away from the substrate layer.

8. A method for preparing a display panel, characterized in that: include: A first gate insulating layer and a semiconductor structure are respectively prepared on one side of the substrate layer, wherein the first gate insulating layer has an opening, and the semiconductor structure is arranged in the opening; Disposing a second gate insulating layer so that the second gate insulating layer covers the semiconductor structure and the first gate insulating layer; The second gate insulating layer is provided, comprising: The second gate insulating layer is arranged so that a surface of the second gate insulating layer in the first region away from the substrate layer and a surface of the second gate insulating layer in the second region away from the substrate layer belong to the same plane, wherein the second region at least partially surrounds the first region, and an orthographic projection of the semiconductor structure on the second gate insulating layer falls into the first region; and / or a thickness of the semiconductor structure is the same as a thickness of the first gate insulating layer.

9. The method for preparing a display panel according to claim 8, characterized in that: The method of preparing a first gate insulating layer and a semiconductor structure on one side of the substrate layer respectively comprises: Disposing the semiconductor structure on one side of the substrate layer; Disposing the first gate insulating layer on a side of the semiconductor structure away from the substrate layer; The side of the first gate insulation layer away from the substrate layer is etched so that the surface of the first gate insulation layer away from the substrate layer and the surface of the semiconductor structure away from the substrate layer belong to the same plane, and / or so that the thickness of the semiconductor structure is the same as the thickness of the first gate insulation layer.

10. The method for preparing a display panel according to claim 8, characterized in that: The method of preparing a first gate insulating layer and a semiconductor structure on one side of the substrate layer respectively comprises: Disposing the first gate insulating layer on one side of the substrate layer; Etching the first gate insulating layer corresponding to the first region to obtain the opening; The semiconductor structure is disposed in the opening.

11. The method for preparing a display panel according to claim 10, characterized in that: Before providing the second gate insulating layer, the method further includes: The side of the semiconductor structure away from the substrate layer is etched so that the surface of the first gate insulating layer away from the substrate layer and the surface of the semiconductor structure away from the substrate layer belong to the same plane.

12. The method for preparing a display panel according to claim 10, characterized in that: The semiconductor structure is arranged in the opening, comprising: The semiconductor structure having the same thickness as that of the first gate insulating layer is disposed in the opening.

13. The method for preparing a display panel according to claim 8, characterized in that: Also includes: A gate structure is arranged on a side of the second gate insulation layer away from the substrate layer, so that the orthographic projection of the gate structure on the substrate layer at least partially covers the orthographic projection of the semiconductor structure on the substrate layer, wherein the thickness of the gate insulation layer between the semiconductor structure and the gate structure is less than the thickness of the gate insulation layer in the second region.

14. A display device, characterized in that: include: A display panel as claimed in any one of claims 1 to 7.

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