Data transmission circuit and image sensor

Abstract

The present invention provides a data transmission circuit and an image sensor, wherein the data transmission circuit comprises: a first data transmission module and a second data transmission module, wherein the first data transmission module comprises at least one data transmission unit; the data transmission unit comprises a data transmission line and a driving unit, wherein the driving unit is connected to the output end of the same counting position of all the counters in the image sensor through the data transmission line; the driving unit obtains the output of the counting position through the data transmission line, converts the output of the counting position into a current difference inside the driving unit, and converts the current difference into a voltage difference. The driving unit in the data transmission circuit provided by the present invention can quickly convert the output of the counting position into a current difference inside the driving unit, and immediately amplify and output, which can meet the requirements of high-resolution and high-frame-rate data transmission of the image sensor.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensor design and application, and in particular to a data transmission circuit and an image sensor. Background Art

[0002] CMOS Image Sensor (CIS) has been widely used in imaging fields such as video, monitoring, industrial manufacturing, automobiles, and home appliances. The mainstream readout circuit structure of CIS is a readout circuit based on a column-level single-slope analog-to-digital converter (ADC) to ensure that CIS has sufficient conversion accuracy and speed under reasonable power consumption. With the continuous improvement of CIS resolution and frame rate in applications, after the column ADC reads out the data at the same time, it is necessary to transmit these data from the column ADC through the data transmission circuit in a short time for further data processing. The data transmission circuit needs to transmit all column ADC data in a shorter row cycle, which has high requirements on the driving ability and frequency of the data transmission circuit. In a CIS with higher resolution, there are more parallel ADC columns. When the ADC data is merged into the bus for serial output, the bus parasitic capacitance and resistance time constant are relatively large, the power consumption consumed by the bus drive will be very large, and the maximum frequency of transmission will be limited.

[0003] The current technical solution, for example, a Chinese patent with the authorization publication number CN108184081B discloses a medium-to-high-speed data transmission readout circuit and readout channel for CMOS image sensors, which is composed of a sampling and holding circuit, a column ADC circuit, and a column LVDS output circuit by connecting a high-speed data transmission circuit after each column of pixels. The circuit converts the reset signal and the photogenerated signal output by each column of pixels into analog-to-digital signals through a pipeline sampling and holding circuit and a column ADC circuit, and then outputs them to the column LVDS circuit through a pipeline latch holding circuit to achieve high-speed data transmission. In the digital signal output stage, this method controls the enablement of each column tri-state gate through a multi-way selection circuit to output the column signal to the corresponding LVDS channel, which may cause a risk of column signal output delay, resulting in an increase in the column signal readout timing.

[0004] Therefore, the present application proposes a data transmission circuit and an image sensor, which can achieve a high-frequency transmission rate while having a high driving capability. Summary of the invention

[0005] The present invention provides a data transmission circuit and an image sensor to solve the technical problem that the maximum frequency of data transmission of an image sensor with a high resolution requirement cannot meet the actual demand.

[0006] In a first aspect, the present invention provides a data transmission circuit, which is applied to an image sensor, wherein the image sensor includes at least one counter, including: a first data transmission module and a second data transmission module, wherein the first data transmission module includes at least one data transmission unit; the data transmission unit includes a data transmission line and a driving unit, wherein the driving unit is connected to the output end of the same counting bit of all the counters in the image sensor through the data transmission line; the driving unit obtains the output of the counting bit through the data transmission line, converts the output of the counting bit into a current difference inside the driving unit, and converts the current difference into a voltage difference; the driving unit is also connected to the second data transmission module, wherein the second data transmission module is used to convert the voltage difference into a logic level signal, and the logic level signal is used to generate image information.

[0007] The beneficial effect is that the driving unit in the data transmission circuit provided by the present invention can quickly convert the output of the counting bit into the current difference inside the driving unit, and immediately amplify the output, which can meet the high-resolution and high-frame rate data transmission requirements of the image sensor.

[0008] Optionally, the data transmission line includes a first line and a second line, an input end of the driving unit is electrically connected to the first output end of the counting bit through the first line, another input end of the driving unit is electrically connected to the second output end of the same counting bit through the second line, and the directions of the signals output by the first output end and the second output end are opposite. Its beneficial effect is that: by electrically connecting one input end of the driving unit to the first output end of the counting bit through the first line, and electrically connecting the other input end of the driving unit to the second output end of the same counting bit through the second line, and the directions of the signals output by the first output end and the second output end are opposite, then when the counting bit is output, the two signals obtained by the driving unit must be different, so that the driving unit can respond quickly to the difference.

[0009] Optionally, the driving unit includes a first amplifying unit and a second amplifying unit, the first amplifying unit is connected to the first output end of the counting bit through the first line, the second amplifying unit is electrically connected to the second output end of the counting bit through the second line, the first output end is one of the positive phase output end or the negative phase output end of the counting bit, and the second output end is the other of the positive phase output end or the negative phase output end of the counting bit. The beneficial effect is that the first amplifying unit and the second amplifying unit respectively amplify the received signals to enhance the difference and obtain an accurate output result of the driving unit.

[0010] Optionally, when the first output end is the positive phase output end of the counting bit and the second output end is the negative phase output end of the counting bit, the first amplifying unit includes a first amplifier and a second amplifier, and the second amplifying unit includes a third amplifier, a fourth amplifier and a mirror unit; the first amplifier includes: a first P-type transistor, a second P-type transistor, a first N-type transistor and a second N-type transistor, the second amplifier includes: a third P-type transistor, a fourth P-type transistor and a third N-type transistor; the third amplifier includes: a fifth P-type transistor, a sixth P-type transistor, a fourth N-type transistor and a fifth N-type transistor, the fourth amplifier includes: a seventh P-type transistor, an eighth P-type transistor and a sixth N-type transistor, The mirror unit includes a seventh N-type transistor and an eighth N-type transistor; the source of the first P-type transistor is respectively connected to the first power supply, the source of the second P-type transistor, and the source of the third P-type transistor; the gate of the first P-type transistor is respectively connected to the gate of the second P-type transistor and the drain of the first P-type transistor; the drain of the first P-type transistor is connected to the drain of the first N-type transistor; the drain of the second P-type transistor is connected to the drain of the second N-type transistor; the gate of the third P-type transistor is connected to the gate of the fourth P-type transistor, and the drain of the third P-type transistor is respectively connected to one end of the first line, the drain of the third N-type transistor, the gate of the third N-type transistor, the first N-type transistor The gate of the fourth P-type transistor is connected to the drain of the eighth N-type transistor respectively; the source of the first N-type transistor is grounded; the gate of the second N-type transistor is used to receive a first bias voltage, the first bias voltage is used to provide a stable bias current to the driving unit, the source of the second N-type transistor is grounded; the source of the third N-type transistor is grounded; the source of the fifth P-type transistor is respectively connected to the second power supply, the source of the sixth P-type transistor, and the source of the seventh P-type transistor, the gate of the fifth P-type transistor is respectively connected to the gate of the sixth P-type transistor and the drain of the fifth P-type transistor, the drain of the fifth P-type transistor is connected to the drain of the fifth N-type transistor; the sixth P-type The drain of the transistor is connected to the drain of the fifth N-type transistor; the gate of the seventh P-type transistor is connected to the gate of the eighth P-type transistor, the drain of the seventh P-type transistor is respectively connected to one end of the second line, the drain of the sixth N-type transistor, the gate of the sixth N-type transistor, and the gate of the fourth N-type transistor; the drain of the eighth P-type transistor is respectively connected to the drain of the seventh N-type transistor, the gate of the seventh N-type transistor, and the gate of the eighth N-type transistor; the source of the fourth N-type transistor is grounded; the gate of the fifth N-type transistor is used to receive the second bias voltage, the source of the fifth N-type transistor is grounded; the source of the sixth N-type transistor is grounded; the source of the seventh N-type transistor is grounded;The source of the eighth N-type transistor is grounded. ;

[0011] Optionally, the first circuit includes at least one branch, and each of the branches on the first circuit is provided with a ninth N-type transistor and a tenth N-type transistor; the second circuit includes at least one branch, and each of the branches on the second circuit is provided with an eleventh N-type transistor and a twelfth N-type transistor respectively; the source of the ninth N-type transistor is grounded, the gate of the ninth N-type transistor is used to receive the positive phase output of the corresponding counting bit, and the drain of the ninth N-type transistor is connected to the source of the tenth N-type transistor; the gate of the tenth N-type transistor and the gate of the twelfth N-type transistor are both used to receive a column selection signal, and the column selection signal is used to sequentially control the corresponding The ninth N-type transistor and the eleventh N-type transistor on the branch are turned on or off; the drains of the tenth N-type transistor on all the branches of the first line are connected, and are also connected to the drain of the third P-type transistor and the drain of the third N-type transistor; the source of the eleventh N-type transistor is grounded, the gate of the eleventh N-type transistor is used to receive the inverted output of the corresponding counting bit, and the drain of the eleventh N-type transistor is connected to the source of the twelfth N-type transistor; the drains of the twelfth N-type transistor on all the branches of the second line are connected, and are also connected to the drain of the seventh P-type transistor and the drain of the sixth N-type transistor.

[0012] Optionally, the second data transmission module includes at least one signal shaping module, and each of the signal shaping modules is respectively connected to one of the driving units, and is used to perform two inversion processes on the voltage difference.

[0013] Optionally, the signal shaping module includes a first inverter and a second inverter, the input end of the first inverter is respectively connected to the drain of the fourth P-type transistor and the drain of the eighth N-type transistor, the input end of the first inverter is used to obtain the voltage difference, the input end of the second inverter is connected to the output end of the first inverter, and the output of the second inverter is used to generate the image information.

[0014] Optionally, the number of the data transmission units is set according to the number of counting bits of the counter, and the number of branches on the first line and the number of branches on the second line are set according to the number of counters.

[0015] Optionally, the number of the data transmission units is equal to the number of counting bits of the counter, and the number of branches on the first line and the number of branches on the second line are both equal to the number of the counter.

[0016] In a second aspect, the present invention provides an image sensor, comprising: a pixel array, an analog-to-digital converter, a data transmission circuit as described in any one of the first aspects, a ramp generator, a decoding drive module, and a timing control module; the pixel array is used to collect light signals and convert the light signals into electrical signals; the decoding drive module is connected to the pixel array, and is used to control the output of the pixel unit in each row of the pixel array; the analog-to-digital converter is respectively connected to the pixel units in a column of the pixel array and the ramp generator, and is used to output according to the output of the pixel unit and the output of the ramp generator; the data transmission circuit is used to convert the output of the analog-to-digital converter into a logic level signal; the timing control module is respectively connected to the decoding drive module, the ramp generator, and the analog-to-digital converter, and is used to control the working timing of the decoding drive module, the ramp generator, and the analog-to-digital converter.

[0017] The beneficial effect is that the image sensor provided by the present invention can meet the requirements for high frame rate data transmission of the image sensor through the rapid response of the data transmission circuit to the count bit output. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of a four-tube pixel unit circuit structure;

[0019] Figure 2 A schematic diagram of the working timing of a four-tube pixel unit;

[0020] Figure 3 It is a structural schematic diagram of an image sensor readout circuit;

[0021] Figure 4 A schematic diagram of the working timing of an image sensor readout circuit;

[0022] Figure 5 A schematic diagram of a data transmission circuit embodiment provided by the present invention;

[0023] Figure 6 A schematic diagram of another data transmission circuit embodiment provided by the present invention;

[0024] Figure 7 It is a schematic diagram of an embodiment of the working timing of the column selection signal of the driving unit provided by the present invention. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. Among them, in the description of the embodiments of the present application, the terms used in the following embodiments are only for the purpose of describing specific embodiments, and are not intended to be used as limitations on the present application. As used in the specification and the appended claims of the present application, the singular expressions "a", "the", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear indication to the contrary in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one or more (including two). The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist; for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in a "or" relationship.

[0026] References to "one embodiment" or "some embodiments" etc. described in this specification mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Thus, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways. The term "connection" includes direct connection and indirect connection, unless otherwise specified. "First" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0027] In the embodiments of the present application, the words "exemplarily" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present related concepts in a specific way.

[0028] Figure 1A CIS standard four-tube pixel unit circuit structure is shown, which is commonly used in row exposure CIS. It consists of a photodiode PD, a transfer transistor Mtg, a reset transistor Mrst, an amplifier transistor Msf, and a row selection transistor Msel. The photodiode PD is sensitive to light and generates photoelectrons proportional to the light intensity. The function of the transfer transistor Mtg is to transfer the photoelectrons in the photodiode PD. When the TX signal is at a high potential, the transfer transistor Mtg is turned on, and the photoelectrons in the photodiode PD are transferred to the floating node FD. The function of the reset transistor Mrst is to reset the potential of the floating node FD when the RX signal is at a high potential. When SEL is at a high potential, the row selection transistor Msel is turned on, and the amplifier transistor Msf, the row selection transistor Msel and the current source to the ground form a path. At this time, the amplifier transistor Msf follows the change of the potential of the floating node FD and is finally output by the output bus PIX_OUT.

[0029] Figure 2 for Figure 1 The working sequence of the four-tube pixel unit shown is divided into reset (Rst), exposure (Exp), and signal reading (Read). In the Rst stage, the TX signal and the RX signal are at a "high" potential, the transfer transistor Mtg and the reset transistor Mrst are both turned on, the floating point FD is reset and its potential is pulled up to the power supply voltage VDD. After that, the RX signal and the TX signal become "low" potentials, and the Exp stage is entered, and the floating point PD is sensitive to light and accumulates electrons. Then, the Read stage is entered, SEL is at a "high" potential, the RX signal is first at a "high" potential, and after resetting the potential of the floating point FD, the RX signal is pulled to a "low" potential again, and the TX signal remains at a "low" potential. At this time, the source follower transistor Msf is controlled by the floating point FD potential and outputs the reset potential VRST through the output bus PIX_OUT. After that, the TX signal is pulled to a "high" potential, and the electrons on the photodiode PD are transferred to the floating point FD. At this time, the source follower transistor Msf is controlled by the potential of the floating point FD and outputs the integration potential VSIG through the output bus PIX_OUT. The difference between VRST and VSIG is the analog voltage corresponding to the photoelectrons on the photodiode PD. The VRST and VSIG potentials are converted into digital quantities by the analog-to-digital converter (ADC) circuit and subtracted to obtain the actual digital quantity corresponding to the photoelectrons on the photodiode PD. If the ADC is 12 bits and the ADC reference voltage range is VREF, the final output is DOUT = (VRST-VSIG) × 2 12 / VREF.

[0030] Figure 3The schematic diagram of the CIS readout circuit includes a pixel array, an ADC, a ramp generator, a timing control module, a decoding drive module, and an output signal processing module. Figure 1 The ADC comprises a comparator and a counter. The pixel array is read out row by row, and the specific order is ROW(0), ROW(1), ... ROW(k-1), ROW(k). The k is a positive integer. Each column in the pixel array is connected to an output bus, and these output buses are PIX_OUT(0), PIX_OUT(1), ... PIX_OUT(n-1), PIX_OUT(n). The output ends of these output buses are connected to the ADC module. The ADC module consists of a comparator and a counter. The comparator compares the output pixel signal with the ramp signal RAMP, and the comparison result determines the size of the counter count value. The ADC module will also judge the above-mentioned VRST and VSIG potentials respectively, and convert the VRST-VSIG difference into a digital output.

[0031] Figure 4 for Figure 3 The working timing of the CIS readout circuit shown is Figure 2 The Read phase of the timing. Figure 4 In the timing shown, the Read phase is entered, SEL is pulled to a "high" potential, RX is a "high" potential, and the pixel unit is reset. RST_CM is the comparator reset control signal, and RST_CM is also pulled to a "high" potential to reset the comparators in all ADC modules. Then RX and RST_CM change from a "high" potential to a "low" potential, and the ADC module enters a normal working state. The working process of the ADC module consists of two processes: comparison and counting. First, when the ramp RAMP potential begins to decrease, the counter CNT starts counting until the comparator signal flips from a "low" potential to a "high" potential. The counter CNT stops counting and stores the current count value. To complete the analog-to-digital conversion of the pixel signal, the ADC module needs to perform the above operation twice, that is, as the benchmark of the ADC module, two ramps will be generated. The first ramp stage (that is, Figure 4 The ADC module will determine and store the reset potential VRST, and the counter CNT will count and store the count value CN1 corresponding to the t1 period during the t1 period; the second ramp stage (i.e. Figure 4 The ADC module will determine and store the reset potential VSIG, and the counter CNT will count and store the count value CN2 corresponding to the t2 period. Finally, the counter CNT will output the count difference ΔCN=CN2-CN1, which corresponds to the difference between VSIG and VRST.

[0032] In order to introduce the data transmission circuit provided by the present application in more detail, Figure 5 The counter used in the embodiment of the present application is a column counter. The data transmission circuit is applied to an image sensor including N+1 column counters, where N is an integer and is responsible for converting the data output by the column ADC into serial data. The column counter includes 12 counting bits, and the number of the data transmission units is equal to the number of counting bits of the column counter. Figure 5 The data transmission circuit shown includes: 12 data transmission lines, 12 driving units, these data transmission lines are respectively the first data transmission line, the second data transmission line, the twelfth data transmission line and 9 data transmission lines omitted and not shown, these driving units include the first driving unit SA_D0, the second driving unit SA_D1, and the twelfth driving unit SA_D11. The counting bits of each column counter are respectively the first counting bit D0, the second counting bit D1, the twelfth counting bit D11 and 9 counting bits omitted and not shown. The counting bits occupying the same counting position in the corresponding column counter are the same counting bits, the output end of the same counting bit is connected to the same data transmission line, and different data transmission lines are connected to the output ends of different counting bits. For example, the first counting bit D0 in each column counter is connected to the first data transmission line, and is connected to the first driving unit SA_D0 through the first data transmission line; the second counting bit D1 in each column counter is connected to the second data transmission line, and is connected to the second driving unit SA_D1 through the second data transmission line; the twelfth counting bit D11 in each column counter is connected to the twelfth data transmission line, and is connected to the twelfth driving unit SA_D11 through the twelfth data transmission line. The comparators of the ADC columns connect N+1 output buses (these output buses are as follows Figure 5 The output of the pixel unit corresponding to the output bus PIX_OUT(0), output bus PIX_OUT(1), output bus PIX_OUT(N-1), output bus PIX_OUT(N) and the omitted parts shown in the figure is compared with the ramp signal RAMP, and the column counter obtains the output of the comparator. The data of the count bit transmitted by each data transmission line is transmitted in sequence through the control of the corresponding driving unit for subsequent data processing to generate image information.

[0033] The driving unit mentioned in the above embodiment is a differential input, so each of the data transmission lines includes two lines, namely a first line and a second line, and the directions of the signals transmitted by the first line and the second line are opposite. Figure 6As shown, the data transmission line includes a first line 601 and a second line 602, the second data transmission module 604 includes a first inverter INV1 and a second inverter INV2, the driving unit 603 includes a first amplifying unit and a second amplifying unit, and the second data transmission module 604 includes a first inverter INV1 and a second inverter INV2. The first inverter INV1 and the second inverter INV2 are used to perform two inversion processes on the voltage difference to achieve the function of converting the analog signal into a digital signal.

[0034] Continue to refer to Figure 6 , the first amplifying unit includes a first amplifier and a second amplifier, and the second amplifying unit includes a third amplifier, a fourth amplifier and a mirror unit. The first amplifier includes: a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1 and a second N-type transistor N2, and the second amplifier includes: a third P-type transistor P3, a fourth P-type transistor P4 and a third N-type transistor N3. The third amplifier includes: a fifth P-type transistor P5, a sixth P-type transistor P6, a fourth N-type transistor N4 and a fifth N-type transistor N5, the fourth amplifier includes: a seventh P-type transistor P7, an eighth P-type transistor P8 and a sixth N-type transistor N6, and the mirror unit includes a seventh N-type transistor N7 and an eighth N-type transistor N8.

[0035] The source of the first P-type transistor P1 is respectively connected to the first power supply VDD1, the source of the second P-type transistor P2, and the source of the third P-type transistor P3; the gate of the first P-type transistor P1 is respectively connected to the gate of the second P-type transistor P2 and the drain of the first P-type transistor P1; the drain of the first P-type transistor P1 is connected to the drain of the first N-type transistor N1; the drain of the second P-type transistor P2 is connected to the drain of the second N-type transistor N2; the gate of the third P-type transistor P3 is connected to the gate of the fourth P-type transistor P4; The drain of the third P-type transistor P3 is respectively connected to one end of the first line 601, the drain of the third N-type transistor N3, the gate of the third N-type transistor N3, and the gate of the first N-type transistor N1; the drain of the fourth P-type transistor P4 is respectively connected to the drain of the eighth N-type transistor N8 and the input end of the first inverter INV1; the source of the first N-type transistor N1 is grounded; the gate of the second N-type transistor N2 is used to receive the first bias voltage VB1, and the source of the second N-type transistor N2 is grounded; the source of the third N-type transistor N3 is grounded.

[0036] The source of the fifth P-type transistor P5 is respectively connected to the second power supply VDD2, the source of the sixth P-type transistor P6, and the source of the seventh P-type transistor P7; the gate of the fifth P-type transistor P5 is respectively connected to the gate of the sixth P-type transistor P6 and the drain of the fifth P-type transistor P5; the drain of the fifth P-type transistor P5 is connected to the drain of the fifth N-type transistor N5; the drain of the sixth P-type transistor P6 is connected to the drain of the fifth N-type transistor N5; the gate of the seventh P-type transistor P7 is connected to the gate of the eighth P-type transistor P8, and the drain of the seventh P-type transistor P7 is respectively connected to the second line 602. The first bias voltage VB1 is connected to one end of the first N-type transistor N6, the drain of the sixth N-type transistor N6, the gate of the sixth N-type transistor N6, and the gate of the fourth N-type transistor N4; the drain of the eighth P-type transistor P8 is connected to the drain of the seventh N-type transistor N7, the gate of the seventh N-type transistor N7, and the gate of the eighth N-type transistor N8 respectively; the source of the fourth N-type transistor N4 is grounded; the gate of the fifth N-type transistor N5 is used to receive the second bias voltage VB2, and the source of the fifth N-type transistor N5 is grounded; the source of the sixth N-type transistor N6 is grounded; the source of the seventh N-type transistor is grounded; and the source of the eighth N-type transistor is grounded. In some embodiments, the first bias voltage VB1 is the same as the second bias voltage VB2.

[0037] The number of branches on the first line and the number of branches on the second line are set according to the number of counters. Optionally, the number of data transmission units is equal to the number of counting bits of the counter, and the number of branches on the first line and the number of branches on the second line are both equal to the number of counters. When the image sensor has N+1 column counters, the first line 601 includes N+1 branches, each of which is respectively provided with 2 N-type transistors, namely the ninth N-type transistor MS1 and the tenth N-type transistor MS2, and the second line 602 includes N+1 branches, each of which is respectively provided with 2 N-type transistors, namely the eleventh N-type transistor MS3 and the twelfth N-type transistor MS4. The source of the ninth N-type transistor MS1 is grounded, the gate of the ninth N-type transistor MS1 is used to receive the positive phase output D0(0) of the first counting bit D0 of the corresponding counter, and the drain of the ninth N-type transistor MS1 is connected to the source of the tenth N-type transistor MS2; the gate of the tenth N-type transistor MS2 and the gate of the twelfth N-type transistor MS4 are both used to receive the column selection signal (such as Figure 6The column selection signal COL_SEL(0), the column selection signal COL_SEL(1), and the column selection signal COL_SEL(N)) shown in the figure control the state of each column selection signal to sequentially control the conduction or disconnection of the ninth N-type transistor MS1 and the eleventh N-type transistor MS3 on the corresponding branch. Figure 7 As shown, when one of the above column selection signals is a high pulse, the remaining column selection signals are all low level. Figure 6 , when the column selection signal is a high pulse in sequence, the conduction of the ninth N-type transistor MS1 and the eleventh N-type transistor MS3 on the corresponding branch is controlled in sequence, and when the column selection signal is a low level, the ninth N-type transistor MS1 and the eleventh N-type transistor MS3 on the corresponding branch are disconnected. The drain of the tenth N-type transistor MS2 on the N+1 branches of the first line 601 is connected to each other, and is also connected to the drain of the third P-type transistor and the drain of the third N-type transistor N3. The source of the eleventh N-type transistor MS3 is grounded, and the gate of the eleventh N-type transistor MS3 is used to receive the inverted output D0_b(0) of the first counting bit D0 of the corresponding counter, and the drain of the eleventh N-type transistor MS3 is connected to the source of the twelfth N-type transistor MS4; the drain of the twelfth N-type transistor MS4 on the N+1 branches of the second line 602 is connected to each other, and is also connected to the drain of the seventh P-type transistor P7 and the drain of the sixth N-type transistor N6.

[0038] The seventh N-type transistor N7 and the eighth N-type transistor N8 function to mirror the current of the eighth P-type transistor P8 1:1 to the branch where the fourth P-type transistor P4 and the eighth P-type transistor N8 are located. The second N-type transistor N2 is a current source tube and is controlled by a fixed first bias voltage VB to provide a fixed bias current for the entire drive unit. When data transmission does not begin, all column selection signals are low, the ninth N-type transistor MS1 and the eleventh N-type transistor MS3 on the corresponding branches are disconnected, there is no current on the first line and the second line, the current IU on the third P-type transistor P3 is equal to the current IB on the sixth N-type transistor N6, and the static current size of each branch in the drive unit is determined by the current flowing through the second N-type transistor N2 and the width-to-length ratio of each transistor.

[0039] Reference Figure 6When the column selection signal COL_SEL(0) is high, the positive phase output D0(0) of the first counting bit D0 of the corresponding counter is high, and the negative phase output D0_b(0) of the first counting bit D0 of the corresponding counter is low, the branch where the ninth N-type transistor MS1 and the tenth N-type transistor MS2 are located is turned on, and the branch where the eleventh N-type transistor MS3 and the twelfth N-type transistor MS4 are located is turned off, and a current IS0_P will increase at one end IP of the first line, and the current will flow from the IP end through the ninth N-type transistor MS1 and the tenth N-type transistor MS2 to the ground GND. At this time, the potential of the IP terminal will be slightly lowered, so the potential of the node F between the first N-type transistor and the third N-type transistor will also be lowered, the current IU on the third P-type transistor P3 is slightly greater than the current IB on the third N-type transistor N3, and there is a current IS0_P that is equal to the difference between the current IU and the current IB, the first bias voltage VB input to the first amplifier remains unchanged, and the potential on the node F becomes lower, so that the potential on the node A between the drain of the second P-type transistor and the drain of the second N-type transistor is pulled down, so that the gate-source voltage of the third P-type transistor P3 is increased, the current IU on the third P-type transistor P3 will further increase, and the current IS0_P will continue to increase. At this time, the third P-type transistor P3 will pull up the potential of one end IP of the first circuit again, and finally reach a stable state. Because the mirror ratio of the third P-type transistor P3 and the fourth P-type transistor P4 is 1:1, the current on the third P-type transistor P3 is equal to the current on the fourth P-type transistor P4, and the current IU on the fourth P-type transistor P4 will also reach a stable value. At this time, since there is no current at one end IN of the second line, the current ID on the eighth N-type transistor N8 is smaller than the current IU flowing through the fourth P-type transistor P4, so that the output signal SAOUT of the driving unit will be pulled high, and finally driven by the first inverter INV1 and the second inverter INV2 to make the output logic level signal DOUT high.

[0040] Similarly, if the column selection signal COL_SEL(0) is high, the positive phase output D0(0) of the first counting bit D0 of the corresponding counter is low level, and the negative phase output D0_b(0) of the first counting bit D0 of the corresponding counter is high level, the branch where the ninth N-type transistor MS1 and the tenth N-type transistor MS2 are located is disconnected, and the branch where the eleventh N-type transistor MS3 and the twelfth N-type transistor MS4 are located is turned on, which will eventually make the current ID on the eighth N-type transistor N8 greater than the current IU flowing through the fourth P-type transistor P4, and the output signal SAOUT of the driving unit is low, and the corresponding logic level signal DOUT is also low. The above process is the data transmission of the 0th column of the first counting bit D0. By analogy, the transmission process of other bits is the same. Since the proposed driving unit only needs to judge the difference in the magnitude of the current at the input node, the response speed is relatively fast. If the driving of the first circuit and the second circuit is replaced by a voltage comparator, the parasitic resistance and parasitic capacitance at the nodes of one end IP of the first circuit and one end IN of the second circuit are relatively large, resulting in a relatively large time constant, and the voltage swing at one end IP of the first circuit and one end IN of the second circuit will be very small, so the response speed of the voltage comparator will be very slow. The advantage of the driving unit proposed in this application is that even if the parasitic resistance and parasitic capacitance at the input end are relatively large, the two input ends can be detected and amplified and output immediately as long as there is a certain current difference.

[0041] Therefore, the data transmission circuit proposed in this application can meet the requirements of CIS high-resolution and high-frame-rate data transmission.

[0042] Based on the data transmission circuit provided by the above embodiments, the present invention provides an image sensor, including: a pixel array, an analog-to-digital converter, a data transmission circuit as described in any of the above embodiments, a ramp generator, a decoding driving module, and a timing control module; the pixel array is used to collect light signals and convert the light signals into electrical signals; the decoding driving module is connected to the pixel array to control the output of the pixel unit in each row of the pixel array; the analog-to-digital converter is respectively connected to the pixel unit of a column in the pixel array and the ramp generator, and is used to output according to the output of the pixel unit and the output of the ramp generator; the data transmission circuit is used to convert the output of the analog-to-digital converter into a logic level signal; the timing control module is respectively connected to the decoding driving module, the ramp generator, and the analog-to-digital converter, and is used to control the working timing of the decoding driving module, the ramp generator, and the analog-to-digital converter. The image sensor provided by the present invention can meet the requirements for high frame rate data transmission of image sensors through the rapid response of the data transmission circuit to the count bit output.

[0043] The above is only a specific implementation of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited thereto, and any changes or replacements within the technical scope disclosed in the embodiment of the present application should be included in the protection scope of the embodiment of the present application. Therefore, the protection scope of the embodiment of the present application should be based on the protection scope of the claims.

Claims

1. A data transmission circuit, characterized in that: Applied to an image sensor, the image sensor includes at least one counter, including: a first data transmission module and a second data transmission module, the first data transmission module includes at least one data transmission unit; The data transmission unit comprises a data transmission line and a driving unit, wherein the driving unit is connected to the output ends of the same counting position of all the counters in the image sensor through the data transmission line; the data transmission line comprises a first line and a second line, an input end of the driving unit is electrically connected to the first output end of the counting position through the first line, and another input end of the driving unit is electrically connected to the second output end of the same counting position through the second line, and the directions of the signals output by the first output end and the second output end are opposite; The driving unit obtains the output of the counting bit through the data transmission line, converts the output of the counting bit into a current difference inside the driving unit, and converts the current difference into a voltage difference; the driving unit includes a first amplifying unit and a second amplifying unit, the first amplifying unit is connected to the first output end of the counting bit through the first line, the second amplifying unit is electrically connected to the second output end of the counting bit through the second line, the first output end is one of the positive phase output end or the negative phase output end of the counting bit, and the second output end is the other of the positive phase output end or the negative phase output end of the counting bit; The driving unit is further connected to the second data transmission module, and the second data transmission module is used to convert the voltage difference into a logic level signal, and the logic level signal is used to generate image information.

2. The data transmission circuit according to claim 1, characterized in that: When the first output end is the positive phase output end of the counting bit and the second output end is the negative phase output end of the counting bit, the first amplifying unit includes a first amplifier and a second amplifier, and the second amplifying unit includes a third amplifier, a fourth amplifier and a mirror unit; The first amplifier includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor; the second amplifier includes: a third P-type transistor, a fourth P-type transistor, and a third N-type transistor; the third amplifier includes: a fifth P-type transistor, a sixth P-type transistor, a fourth N-type transistor, and a fifth N-type transistor; the fourth amplifier includes: a seventh P-type transistor, an eighth P-type transistor, and a sixth N-type transistor; the mirror unit includes a seventh N-type transistor and an eighth N-type transistor; The source of the first P-type transistor is respectively connected to the first power supply, the source of the second P-type transistor, and the source of the third P-type transistor; the gate of the first P-type transistor is respectively connected to the gate of the second P-type transistor and the drain of the first P-type transistor; the drain of the first P-type transistor is connected to the drain of the first N-type transistor; the drain of the second P-type transistor is connected to the drain of the second N-type transistor; the gate of the third P-type transistor is connected to the gate of the fourth P-type transistor; the drain of the third P-type transistor is respectively connected to one end of the first line, the drain of the third N-type transistor, the gate of the third N-type transistor, and the gate of the first N-type transistor; the drain of the fourth P-type transistor is respectively connected to the drain of the eighth N-type transistor; the source of the first N-type transistor is grounded; the gate of the second N-type transistor is used to receive a first bias voltage, and the first bias voltage is used to provide a stable bias current to the driving unit; the source of the second N-type transistor is grounded; the source of the third N-type transistor is grounded; the source of the third N-type transistor is grounded; The source of the fifth P-type transistor is respectively connected to the second power supply, the source of the sixth P-type transistor, and the source of the seventh P-type transistor; the gate of the fifth P-type transistor is respectively connected to the gate of the sixth P-type transistor and the drain of the fifth P-type transistor; the drain of the fifth P-type transistor is connected to the drain of the fifth N-type transistor; the drain of the sixth P-type transistor is connected to the drain of the fifth N-type transistor; the gate of the seventh P-type transistor is connected to the gate of the eighth P-type transistor; the drain of the seventh P-type transistor is respectively connected to one end of the second line, The drain of the sixth N-type transistor, the gate of the sixth N-type transistor, and the gate of the fourth N-type transistor; the drain of the eighth P-type transistor are respectively connected to the drain of the seventh N-type transistor, the gate of the seventh N-type transistor, and the gate of the eighth N-type transistor; the source of the fourth N-type transistor is grounded; the gate of the fifth N-type transistor is used to receive a second bias voltage, and the source of the fifth N-type transistor is grounded; the source of the sixth N-type transistor is grounded; the source of the seventh N-type transistor is grounded; the source of the eighth N-type transistor is grounded.

3. The data transmission circuit according to claim 2, characterized in that: The first circuit includes at least one branch, and each branch on the first circuit is provided with a ninth N-type transistor and a tenth N-type transistor; the second circuit includes at least one branch, and each branch on the second circuit is provided with an eleventh N-type transistor and a twelfth N-type transistor respectively; The source of the ninth N-type transistor is grounded, the gate of the ninth N-type transistor is used to receive the positive phase output of the corresponding counting bit, and the drain of the ninth N-type transistor is connected to the source of the tenth N-type transistor; the gate of the tenth N-type transistor and the gate of the twelfth N-type transistor are both used to receive a column selection signal, and the column selection signal is used to sequentially control the conduction or disconnection of the ninth N-type transistor and the eleventh N-type transistor on the corresponding branch; The drains of the tenth N-type transistor on all the branches of the first circuit are connected, and are also connected to the drain of the third P-type transistor and the drain of the third N-type transistor; the source of the eleventh N-type transistor is grounded, the gate of the eleventh N-type transistor is used to receive the inverted output of the corresponding counting bit, and the drain of the eleventh N-type transistor is connected to the source of the twelfth N-type transistor; the drains of the twelfth N-type transistor on all the branches of the second circuit are connected, and are also connected to the drain of the seventh P-type transistor and the drain of the sixth N-type transistor.

4. The data transmission circuit according to claim 1, characterized in that: The second data transmission module includes at least one signal shaping module, and each of the signal shaping modules is connected to one of the driving units, respectively, and is used to perform two inversion processes on the voltage difference.

5. The data transmission circuit according to claim 4, characterized in that: The signal shaping module includes a first inverter and a second inverter, the input end of the first inverter is respectively connected to the drain of the fourth P-type transistor and the drain of the eighth N-type transistor, the input end of the first inverter is used to obtain the voltage difference, the input end of the second inverter is connected to the output end of the first inverter, and the output of the second inverter is used to generate the image information.

6. The data transmission circuit according to claim 5, characterized in that: The number of the data transmission units is set according to the number of count bits of the counter, and the number of branches on the first line and the number of branches on the second line are set according to the number of counters.

7. The data transmission circuit according to claim 6, characterized in that: The number of the data transmission units is equal to the number of counting bits of the counter, and the number of branches on the first line and the number of branches on the second line are both equal to the number of the counter.

8. An image sensor, characterized in that: include: A pixel array, an analog-to-digital converter, a data transmission circuit according to any one of claims 1 to 7, a ramp generator, a decoding drive module, and a timing control module; The pixel array is used to collect light signals and convert the light signals into electrical signals; The decoding driving module is connected to the pixel array and is used to control the output of the pixel unit of each row in the pixel array; The analog-to-digital converter is respectively connected to a pixel unit of a column in the pixel array and the ramp generator, and is used for outputting according to the output of the pixel unit and the output of the ramp generator; The data transmission circuit is used to convert the output of the analog-to-digital converter into a logic level signal; The timing control module is respectively connected to the decoding driving module, the ramp generator, and the analog-to-digital converter, and is used to control the working timing of the decoding driving module, the ramp generator, and the analog-to-digital converter.

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