A method for planarizing thin films of microsystems

Abstract

The present invention discloses a method for planarizing thin films in microsystems, comprising: providing a semiconductor substrate with a patterned thin film formed thereon; forming a planar layer on the patterned thin film and patterning the patterned thin film; polishing the planar layer to a predetermined thickness using a multi-zone polishing head; polishing for no more than 3 minutes; and cleaning the polished planar layer in a chemical mechanical planarization device. The method makes it easier to control the thickness of thin films produced, and the resulting films exhibit improved flatness and stability.

Description

Technical Field

[0001] The present invention relates to the field of microsystem technology, and in particular to a microsystem thin film planarization method. Background Art

[0002] Capacitive microphones typically work by applying sound waves to a thin film of a capacitor. The vibration of the film changes the distance between the upper and lower plates, thereby changing the capacitance and generating a corresponding detection signal. The distance between the upper and lower substrates (the thickness of the sacrificial layer) and the surface flatness (the surface smoothness of the sacrificial layer) between the capacitors are particularly important for the sensitivity of the detection signal. The prior art method for manufacturing such a capacitive microphone is as follows: a standard silicon wafer is thermally oxidized to form a silicon dioxide film; silicon nitride, polysilicon, and silicon nitride are then deposited on the silicon dioxide film to form a patterned film; two planarization layers are then deposited and chemical-mechanical planarization (CMP) is performed on the planarization layers to form a sacrificial layer; upper and lower electrodes are then formed; and finally, the sacrificial layer is released to form the capacitor structure. During the polishing process of the two deposited planarization layers, a thickness of up to 2-3 μm of silicon dioxide must be removed, far exceeding the thickness required for IC (Integrated Circuit) thin film processes, and the remaining silicon dioxide thickness must be kept within the required thickness range. Furthermore, the manufacturing process also requires that the central region of the sacrificial layer have a minimal step difference after CMP. However, CMP is a highly sophisticated planarization method that achieves high-precision surface planarization through a balance of chemical and mechanical processes. High points are removed faster than low points, achieving global planarization. The removal rate is measured in angstroms, with a typical oxide removal rate of 2000-5000 angstroms. However, the micro-electro-mechanical system (MEMS) thick film process requires at least 2µm of removal, which results in polishing times exceeding four minutes. The resulting accumulation of heat within the wafer intensifies chemical reactions, making it difficult to maintain a stable balance between chemical reaction and mechanical removal over such a long period. Due to the active chemical reactions, some low-profile areas will experience extensive chemical erosion, resulting in poor intra-wafer non-uniformity (WIWNU). It is also difficult to control the thickness within the specified range. Furthermore, MEMS generally have large pattern pitches, and prolonged polishing will cause butterfly defects to continue to grow, making it difficult to effectively ensure the flatness of the central region.

[0003] In summary, it can be seen that the planarization methods currently used in the fabrication process of microsystem thin films make it difficult to control the thickness, flatness and stability of the sacrificial layer thin films. Summary of the Invention

[0004] In view of the above problems, the present invention proposes a microsystem thin film planarization method, which makes it easier to control the thickness of the thin film during fabrication, and the obtained thin film has better flatness and stability.

[0005] In the first aspect, the present application provides the following technical solutions through an embodiment:

[0006] A microsystem thin film planarization method, comprising:

[0007] A semiconductor substrate having a patterned thin film formed thereon is provided; a flat layer is formed on the patterned thin film, and a patterned fill is formed on the patterned thin film; the flat layer is polished to a preset thickness using a multi-zone polishing head; wherein the polishing time is no more than 3 minutes; and the polished flat layer is cleaned in a chemical mechanical planarization device.

[0008] Optionally, the step of polishing the flat layer to a preset thickness using a multi-zone polishing head includes:

[0009] The polishing head pressure is controlled to be no less than 5 psi, the rotation speed is controlled to be no less than 100 rpm, and the rotation speed difference between the polishing head and the polishing table is controlled to be no more than 6 rpm, so that the polishing rate reaches 8000 / min-13000 angstroms / min.

[0010] Optionally, the diameter of the abrasive particles in the polishing liquid used during polishing is 50 nm to 80 nm.

[0011] Optionally, the step of polishing the flat layer to a preset thickness using a multi-zone polishing head includes:

[0012] The flat layer is polished using a multi-area polishing head, and particles with a diameter greater than or equal to 1 μm in the polishing liquid are filtered during the polishing process until the layer is polished to a preset thickness.

[0013] Optionally, after polishing the flat layer to a preset thickness using a multi-zone polishing head, the method further includes:

[0014] The flat layer after polishing and before cleaning is subjected to water polishing for a preset time.

[0015] Optionally, the preset duration is 20-40 seconds.

[0016] Optionally, the polished flat layer is cleaned in a chemical mechanical planarization device, comprising:

[0017] The polished flat layer is scrubbed twice in a chemical mechanical planarization device; and the scrubbed flat layer is dried.

[0018] Optionally, the planar layer includes a first planar layer and a second planar layer; and forming the planar layer on the patterned film includes:

[0019] The first flat layer is deposited on the patterned thin film; the first flat layer is subjected to rapid thermal annealing; the second flat layer is deposited on the first flat layer subjected to rapid thermal annealing; and the second flat layer is subjected to rapid thermal annealing.

[0020] Optionally, the material of the first planar layer is borophosphosilicate glass or phosphosilicate glass.

[0021] Optionally, the material of the second planar layer is borophosphosilicate glass or phosphosilicate glass.

[0022] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following is a brief introduction to the drawings required for describing the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without inventive work. In the drawings:

[0024] Figure 1 A flow chart of a microsystem thin film planarization method provided by an embodiment of the present invention;

[0025] Figure 2-Figure 9 This is a schematic diagram of the structure of different manufacturing process stages of a condenser microphone provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0027] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0028] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or an intervening layer / element may be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0029] See also Figure 1 The present invention provides a microsystem thin film planarization method that can be used to planarize similar thin films in various microsystems, such as pressure sensors and condenser microphones. The microsystem thin film planarization method of the present invention is described below using the example of manufacturing a condenser microphone. During the condenser microphone manufacturing process, two PECVD (Plasma Enhanced Chemical Vapor Deposition) processes are required to deposit PSG (phosphosilicate glass). After the deposition, the step difference of the phosphosilicate glass reaches 1.2 μm, and the total film thickness reaches more than 6 μm. However, the final required thickness is 4 μm-4.5 μm, and the remaining thickness range needs to be controlled within ±0.2 μm, with the step difference in the pattern area less than ±0.1 μm. Conventional CMP methods generally use fume abrasive particles with a particle diameter of 0.2 μm-0.5 μm, and a removal rate of approximately 2000-5000 Å / minute. Due to the relatively thick film layer to be removed, this removal rate would require 10 minutes if polished in one pass. If grinding is continued for a long time, a large amount of heat will accumulate, causing defects in the wafer, and it will also be difficult to control the thickness of the sacrificial layer when using CMP polishing.

[0030] See also Figure 2-Figure 8 , shows a schematic diagram of the structure formed at different stages of a condenser microphone manufacturing method in this embodiment. The structure formed by the process flow of the micro-system thin film flattening method can be used to process the sacrificial layer (flattening layer 40) in the process flow of manufacturing a condenser microphone. This can avoid the above-mentioned problems and suppress the occurrence of new defects. The specific steps are as follows:

[0031] Provide a semiconductor substrate 10, which can be a silicon substrate, sapphire, silicon carbide, gallium nitride, etc., without limitation. Then, form an insulating layer 20 on the semiconductor substrate 10, such as Figure 2As shown; for example, taking a silicon substrate as an example, the silicon substrate can be oxidized to form a carbon dioxide film layer on the silicon substrate. The thickness of the insulating layer 20 is about 0.5um. Then, a first silicon nitride layer 31 is deposited on the insulating layer 20, and then a doped polysilicon layer 32 is deposited on the first silicon nitride layer 31 by low pressure chemical vapor deposition (LPCVD), and then a second silicon nitride layer 33 is deposited on the polysilicon layer 32. After the deposition is completed, the first silicon nitride layer 31, the polysilicon layer 32 and the second silicon nitride layer 33 are patterned and etched as required to form a patterned thin film 30, as shown Figure 3 There is no limitation on the shape and size of the grooves on the patterned film 30 .

[0032] The above process may also be replaced by other solutions in the prior art without limitation.

[0033] Next, a planarization layer 40 is formed on the patterned film 30; the material of the planarization layer 40 can be any one or more of the following: borophosphosilicate glass (BPSG) and phosphosilicate glass (PSG). It should be noted that the use of BPSG material can avoid the water absorption characteristics of PSG material after manufacturing, which leads to poor film quality and instability; BPSG material can overcome the water absorption characteristics of PSG. At the same time, because PSG material requires a temperature of no less than 1100°C to achieve reflow, while BPSG material can achieve reflow at 850°C, the thermal budget is smaller. Since the use of BPSG material can achieve better reflow and more stable film quality, the surface of the borosilicate glass layer can be made flatter and have a smaller step difference after rapid annealing, reducing the thickness and time of grinding and polishing.

[0034] It is understood that in some examples, the planar layer 40 may include a first planar layer 41 and a second planar layer 42; therefore, the following process may be used to form the planar layer 40. First, the first planar layer 41 is deposited on the patterned film 30; that is, during the deposition process, a plasma enhanced chemical vapor deposition (PECVD) process may be used to form a borophosphosilicate glass layer or a phosphosilicate glass layer with a thickness of 2 μm to 3.5 μm, such as Figure 4As shown. Next, the first flat layer 41 is subjected to rapid thermal processing (RTP); for example, when the material of the flat layer 40 is borophosphosilicate glass, the heating temperature can be controlled at 800°C to 850°C during the rapid thermal annealing, and the duration is 5-10s to ensure good reflow of the borophosphosilicate glass; after the rapid thermal annealing is completed, annealing is performed in a nitrogen environment, and the annealing time can be greater than or equal to 20s. By performing thermal annealing on the first flat layer, the flatness can be effectively improved, the surface step difference when depositing the second flat layer 42 can be reduced, and the polishing time can be shortened. Next, the second flat layer 42 is deposited on the first flat layer 41 that has completed the rapid thermal annealing; for example, a PECVD process is used to produce a 2um-3.5um borophosphosilicate glass layer or a phosphosilicate glass layer, so that the total thickness of the first flat layer 41 and the second flat layer 42 reaches 4um-7um, as shown Figure 6 Finally, the second flat layer 42 is subjected to a rapid thermal annealing process to further reduce the step difference on the surface of the second flat layer 42 and shorten the polishing time. The rapid thermal annealing process for the second flat layer 42 can be performed by referring to the treatment method for the first flat layer 41 and will not be repeated here.

[0035] Furthermore, CMP is used for polishing. A multi-zone polishing head 61 is used to polish the flat layer 40 to a predetermined thickness. During polishing, the polishing rate is controlled within a range of 6,000 to 13,000 angstroms per minute, with an optimal polishing rate of 8,000 to 13,000 angstroms per minute, ensuring that the polishing time is controlled within 3 minutes and that polishing is completed in one pass. This avoids excessive polishing time, which can lead to internal heat accumulation in the wafer and disrupt the dynamic chemical and mechanical balance, thereby forming a better surface morphology on the flat layer 40. Furthermore, the one-pass polishing process improves production efficiency, avoids polishing pad wear and excessive waste of polishing fluid, and reduces production costs.

[0036] In this embodiment, the pressure of the polishing head 61 can be controlled to be no less than 5psi, the rotation speed can be no less than 100rpm, and the rotation speed difference between the polishing head 61 and the polishing table 62 can be no more than 6rpm, so that the polishing rate reaches 8000 angstroms / minute-13000 angstroms / minute, ensuring that the total amount removed is approximately 2-3um, the removal rate is ≥0.8um / min, for example, it can be 0.9um / min, and the total time can be controlled within 3 minutes.

[0037] The polishing head 61 can adopt multi-zone pressure control (independent control zone ≥ 3) and controllable maintenance ring pressure technology, and the pressure difference between each zone is no more than 20%, ensuring that the polishing speed of each zone is consistent and uniform. Figure 6As shown; at the same time, the use of silica abrasive particles with small particle size and rounded surface can have a faster removal rate compared to fumed abrasive particles. Furthermore, the diameter of the abrasive particles in the polishing liquid can be selected to be 50nm-80nm, such as 60nm, 65nm, 70nm, etc. In some implementations, a CMP machine or auxiliary equipment (SDS) with a filtering device (filter diameter ≤ 5um) can be selected to filter particles with a diameter greater than or equal to 1um in the polishing liquid during the polishing process to prevent particles from agglomerating under high pressure and high speed, causing scratches on the wafer. The above control can reduce the risk of defects in the polishing process, and the intra-wafer non-uniformity is ≤5%.

[0038] It should be noted that during the polishing process, Nova online thickness control technology can be used. If the total amount of material removed is insufficient, the polishing time can be increased appropriately; this ensures that inter-wafer non-uniformity is controlled. However, existing optical endpoint detection (infrared or visible light) is not effective for ultra-thick film layers. Reaching the required thickness depends solely on time, which results in poor inter-wafer non-uniformity (WTWNU).

[0039] In some embodiments, the flat layer 40, after polishing and before cleaning, can be water-polished for a predetermined time to improve the surface finish of the flat layer 40. The predetermined time can be controlled to be between 20 and 40 seconds to avoid surface defects caused by prolonged water polishing. For example, the predetermined time can be 25 seconds, 30 seconds, 35 seconds, etc. Ultimately, the step difference of the flat layer 40 obtained through the above process can be controlled to no more than 0.1 micron.

[0040] Furthermore, the polished flat layer 40 is cleaned in a chemical mechanical planarization device to complete the planarization of the microsystem film, such as Figure 7 As shown. It is understood that in some examples, the polished flat layer 40 can be scrubbed twice in a chemical mechanical planarization device; the scrubbed flat layer 40 is dried, and the drying method can be high-speed spin drying or IPA drying, so that the surface cleanliness of the flat layer 40 meets the requirements.

[0041] Finally, the diaphragm layer 50 is formed, and the flat layer is released to form the cavity structure, upper electrode and lower electrode structures. The formation of the cavity structure, upper electrode and lower electrode structures can adopt existing mature processes, which are not limited in this embodiment. For example, LPCVD is used to form a doped polysilicon diaphragm layer 50 on the flat layer, and then wet etching is performed to form a smooth and stable side surface, such as Figure 8 Finally, upper and lower electrodes are formed (the polysilicon diaphragm layer 50 forms the upper electrode, and the polysilicon layer 32 forms the lower electrode) and the flat layer 40 is released to complete the manufacture of the condenser microphone, as shown. Figure 9 shown.

[0042] It should be noted that the flat layer 40 to be processed in this embodiment may also correspond to other thin film layers in other products, such as other sacrificial layers, diaphragm layers, insulating layers, etc., without limitation.

[0043] In this example, the KLA-F5X measurement tool was used, with 49-point rapid measurement data. The wafer's 5mm edge was excluded. After depositing PSG material (PECVD PSG 4%) on the wafer, the wafer position and corresponding thickness data were shown in the following table:

[0044] Table 1 Wafer thickness after deposition of PSG material (unit: nm)

[0045]

[0046] Then, the wafer after the PSG material is deposited and the rapid thermal annealing treatment is subjected to CMP grinding treatment, and the polishing rate parameter is controlled to reach 6000 angstroms / minute-13000 angstroms / minute, the total removal target thickness is 2.2um, and the total removal time is 160 seconds (within 3 minutes).

[0047] Table 2 Wafer thickness after polishing (unit: nm)

[0048]

[0049] At this time, the detection removal speed is shown in the following table:

[0050] Table 3 Wafer polishing thickness at each position (unit: angstrom)

[0051]

[0052] Tables 1-3 above show that using PSG as the planarization layer material, when polishing away a 2.2µm thick planarization layer, the removal time can be guaranteed to be 160s, with a removal rate of 6000-9000 Å / min. After removal, the surface flatness is excellent, and the step deviation is generally controlled within 4% (mostly within 3%). This allows for a single-shot polishing operation, avoiding excessive polishing time that can lead to internal heat accumulation on the wafer and disrupt the dynamic chemical and mechanical balance.

[0053] In summary, the microsystem thin film planarization method provided in an embodiment of the present invention forms a planar layer on a semiconductor substrate having a patterned thin film formed thereon, thereby patterning the patterned thin film. Subsequently, a multi-zone polishing head is used to polish the planar layer to a predetermined thickness, ensuring that the polishing time can be controlled within 3 minutes. This single-shot polishing process avoids excessive polishing time that can lead to internal heat accumulation on the wafer and disrupt the chemical and mechanical dynamic balance, thereby forming a superior surface morphology on the planar layer. Furthermore, this single-shot polishing process improves production efficiency, avoids polishing pad wear and excessive polishing fluid waste, and reduces production costs. Finally, the polished planar layer is cleaned in a chemical mechanical planarization device to obtain a planar layer with consistent thickness, good flatness, and good stability.

[0054] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0055] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0056] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A microsystem thin film planarization method, characterized in that: include: providing a semiconductor substrate having a patterned thin film formed thereon; forming a flat layer on the patterned film to form a patterned filling on the patterned film; Polishing the flat layer to a preset thickness using a multi-zone polishing head; wherein the polishing time is no more than 3 minutes; Cleaning the polished flat layer in a chemical mechanical planarization device; The flat layer includes a first flat layer and a second flat layer; and forming the flat layer on the patterned film includes: depositing the first planar layer on the patterned thin film; performing a rapid thermal annealing process on the first planar layer; Depositing the second planar layer on the first planar layer after the rapid thermal annealing process; performing a rapid thermal annealing process on the second planar layer; The step of polishing the flat layer to a preset thickness using a multi-area polishing head comprises: The polishing head pressure is controlled to be no less than 5 psi, the rotation speed is controlled to be no less than 100 rpm, and the rotation speed difference between the polishing head and the polishing table is controlled to be no more than 6 rpm, so that the polishing rate reaches 8000 / min-13000 angstroms / min.

2. The method according to claim 1, wherein The diameter of the abrasive particles in the polishing liquid used during polishing is 50nm-80nm.

3. The method according to claim 2, wherein The step of polishing the flat layer to a preset thickness using a multi-area polishing head comprises: The flat layer is polished using a multi-area polishing head, and particles with a diameter greater than or equal to 1 μm in the polishing liquid are filtered during the polishing process until the layer is polished to a preset thickness.

4. The method according to claim 1, wherein After polishing the flat layer to a preset thickness using a multi-area polishing head, the method further includes: The flat layer after polishing and before cleaning is subjected to water polishing for a preset time.

5. The method according to claim 4, wherein The preset duration is 20-40 seconds.

6. The method according to claim 1, wherein The step of cleaning the polished flat layer in a chemical mechanical planarization device comprises: The polished flat layer is scrubbed twice in a chemical mechanical planarization device; The flat layer after brushing is dried.

7. The method according to claim 1, wherein The material of the first planar layer is borophosphosilicate glass or phosphosilicate glass.

8. The method according to claim 1, wherein The material of the second planar layer is borophosphosilicate glass or phosphosilicate glass.

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