A method and system for one-to-many fragment mapping based on glDrawBuffer in a graphics processor

Abstract

The present application relates to a kind of glDrawBuffer-based one-to-many fragment mapping method and system in graphics processor.The method of the present application comprises the following steps:1) identifying the buffer of glDrawBuffer configuration;2) the write order of buffer is sorted, and buffer index is generated;3) according to the order determined, fragment is mapped into different buffer in turn, and fragment output process is realized using control state machine, received tile is sent multiple times, and different buffer index information is carried each time.The present application has the advantages of fast fragment processing speed, conducive to circuit timing implementation, clear circuit structure and improved multi-buffer drawing scene processing speed.

Description

Technical Field

[0001] This invention relates to the field of computer hardware technology, and in particular to a one-to-many fragment mapping method and system based on glDrawBuffer in a graphics processor. Background Technology

[0002] In computer graphics processing and computer graphics, fragments are the data that is ultimately written to the frame buffer for graphical display. During fragment processing, the fragment needs to undergo a series of operations with the data in the frame buffer. The data and results of these operations differ depending on the final frame buffer to which the fragment is written. The frame buffer to be written to is specified by the graphics parameter configuration command `glDrawBuffer`. A fragment can be configured to write to one or more buffers; therefore, a fragment needs to be split into multiple fragments for processing based on different frame buffer configurations. Summary of the Invention

[0003] To address the technical problems existing in the background art, the present invention provides a one-to-many fragment mapping method and system based on glDrawBuffer in a graphics processor, which has the advantages of fast fragment processing speed, convenient circuit timing implementation, clear circuit structure, and improved processing speed of multi-buffer drawing scenes.

[0004] The technical solution of this invention is as follows: This invention is a one-to-many fragment mapping method based on glDrawBuffer in a graphics processor, characterized in that the method includes the following steps:

[0005] 1) Identify the buffer configured by glDrawBuffer;

[0006] 2) Sort the write order of the buffer and generate buffer indices;

[0007] 3) Map the fragments to different buffers in the determined order. The fragment output process is implemented by a control state machine. The received tiles are sent in multiple times, each time carrying different buffer index information.

[0008] Further, the specific steps of step 1) are as follows: First, calculate the total number of glDrawBuffer configuration register gldrawbf values ​​that are 1. Then, decode the total to generate a 6-bit one-hot code: bit 0 indicates writing data once, bit 1 indicates writing data twice, bit 3 indicates writing data three times, bit 4 indicates writing data four times, bit 5 indicates writing data five times, bit 6 indicates writing data six times, and all bits being 0 indicates no writing. When the total is 0, it means no color buffer is written. At this time, it is necessary to determine whether depth testing or stencil testing is enabled. If either of them is enabled, it means that the depth buffer needs to be written. The number of times to send needs to be selected based on the most recent non-zero configuration parameter: if the buffer is configured to write to both the left and right buffers simultaneously, then both the left and right buffers need to be written twice; otherwise, only one time is written.

[0009] Furthermore, the buffer index generated in step 2) is:

[0010] The write buffer index variable index6: is RAU when the number of transmissions is 6, and is invalid in other cases;

[0011] The write buffer index variable index5: is LAU when the number of transmissions is 6; is LAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b01xxxx; and is RAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b1xxxxx.

[0012] The write buffer index variable index4 is RB when the gldrawbf parameter is 6'bxx1111; LAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b11xxxx; and RAU when the number of transmissions is 4 and the gldrawbf parameter is 6'b01xxxx.

[0013] The write buffer index variable `index3` is set to LB when the `gldrawbf` parameter is 6'bxxx111; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b001xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b011xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b101xxx; RB when the number of transmissions is 5 and the `gldrawbf` parameter is 6'b111xxx; LAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b01xxxx; LAU when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b11xxxx; and RAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b1xxxxx.

[0014] The write buffer index variable `index2` is RF when the `gldrawbf` parameter is 6'bxxxx11; LB when the `gldrawbf` parameter is 6'bxxx110; LB when the `gldrawbf` parameter is 6'bxxx101; RB when the number of transmissions is 2 and the `gldrawbf` parameter is 6'bxxx001xxx; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b101xxx; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b011xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b111xxx; LAU when the number of transmissions is 2 and the `gldrawbf` parameter is 6'b01xxxx; LAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b11xxxx; and RAU when the number of transmissions is 2 and the `gldrawbf` parameter is 6'b1xxxxx.

[0015] The write buffer index variable index1 is LF when the gldrawbf parameter is 6'bxxxxx1; RF when the gldrawbf parameter is 6'bxxxx10; LB when the gldrawbf parameter is 6'bxxx100; RB when the gldrawbf parameter is 6'bxx1000; LAU when the gldrawbf parameter is 6'bx10000; and RAU when the gldrawbf parameter is 6'b100000.

[0016] Furthermore, in step 3), the state machine includes seven states: IDLE, SEND1, SEND2, SEND3, SEND4, SEND5, and SEND6. The state transition process is as follows:

[0017] 1) IDLE state:

[0018] When the circuit is powered on and reset, the state machine is in this state; after the reset is canceled, if the input data is detected to be valid, data needs to be sent once, and the state machine jumps to the SEND1 state; data is sent, the first write address index is index1, and the output ready signal is equal to the input ready signal;

[0019] If the input data is valid, two data transmissions are required. The state machine then transitions to the SEND2 state. Data is transmitted, the second write address index is set to index2, and the ready signal '0' is output.

[0020] If the input data is valid, it needs to send data 3 times. The state machine then jumps to the SEND3 state; sends the data and the third write address index, index3, and outputs the ready signal '0'.

[0021] If the input data is valid, it needs to send data 4 times. The state machine then jumps to the SEND4 state; the data is sent, the 4th write address index is index4, and the ready signal '0' is output.

[0022] If the input data is valid, it needs to send data 5 times. The state machine then jumps to the SEND5 state; the data is sent, the 5th write address index is index5, and the ready signal '0' is output.

[0023] If the input data is valid, it needs to send data 6 times. The state machine then jumps to the SEND6 state; sends the data and the 6th write address index 6, and outputs the ready signal '0'.

[0024] Otherwise, it remains in the IDLE state and outputs the ready signal as '1';

[0025] 2) SEND1 status:

[0026] Data can be sent; if the input data is invalid, the state machine jumps to the IDLE state; data is sent, the first write address index is index1, and the ready signal is output as '1';

[0027] If the input data is valid, two data transmissions are required. The state machine then transitions to the SEND2 state. Data is transmitted, the second write address index is set to index2, and the ready signal '0' is output.

[0028] If the input data is valid, it needs to send data 3 times. The state machine then jumps to the SEND3 state; sends the data and the third write address index, index3, and outputs the ready signal '0'.

[0029] If the input data is valid, it needs to send data 4 times. The state machine then jumps to the SEND4 state; the data is sent, the 4th write address index is index4, and the ready signal '0' is output.

[0030] If the input data is valid, it needs to send data 5 times. The state machine then jumps to the SEND5 state; the data is sent, the 5th write address index is index5, and the ready signal '0' is output.

[0031] If the input data is valid, it needs to send data 6 times. The state machine then jumps to the SEND6 state; sends the data and the 6th write address index 6, and outputs the ready signal '0'.

[0032] 3) SEND2 status:

[0033] Data can be sent down. The state machine jumps to the SEND1 state, sends down the data and the first write address index1, and outputs the ready signal, which is equal to the input ready signal.

[0034] 4) SEND3 status:

[0035] Data can be sent down, the state machine jumps to the SEND2 state, and the data is sent down to the second write address index, index2.

[0036] 5) SEND4 status:

[0037] Data can be sent down, the state machine jumps to the SEND3 state, and the data is sent down to the third write address index, index3;

[0038] 6) SEND5 status:

[0039] Data can be sent down, the state machine jumps to the SEND4 state, and the data is sent down to the 4th write address index4;

[0040] 7) SEND6 status:

[0041] Data can be sent down. The state machine jumps to the SEND5 state to send the data and the 5th write address index, index5.

[0042] A system for implementing the above-mentioned one-to-many fragment mapping method based on glDrawBuffer in a graphics processor is characterized in that: the system includes a glDrawBuffer parameter parsing module, a buffer index generation module, and a fragment mapping module; the glDrawBuffer parameter parsing module and the buffer index generation module are respectively connected to the fragment mapping module.

[0043] Furthermore, the glDrawBuffer parameter parsing module parses the bufs value to determine the buffer to be written to and the number of times data is sent.

[0044] Furthermore, the glDrawBuffer parameter parsing module first calculates the total number of 1s in the glDrawBuffer configuration register gldrawbf, and then decodes the total to generate a 6-bit one-hot code: bit 0 indicates writing data once, bit 1 indicates writing data twice, bit 3 indicates writing data three times, bit 4 indicates writing data four times, bit 5 indicates writing data five times, bit 6 indicates writing data six times, and all bits being 0 indicates no writing. When the total is 0, it means no color buffer is written. At this time, it is necessary to determine whether depth testing or stencil testing is enabled. If either one is enabled, it means that the depth buffer needs to be written. The number of sends needs to be selected based on the most recent non-zero configuration parameter: if the buffer is configured to write to both the left and right buffers simultaneously, then both buffers need to be written twice; otherwise, only once.

[0045] Furthermore, the buffer index generation module generates six buffer indices based on the gldrawbf signal and the number of times it is sent.

[0046] Furthermore, the specific method by which the buffer index generation module generates the buffer index is as follows:

[0047] The write buffer index variable index6: is RAU when the number of transmissions is 6, and is invalid in other cases;

[0048] The write buffer index variable index5: is LAU when the number of transmissions is 6; is LAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b01xxxx; and is RAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b1xxxxx.

[0049] The write buffer index variable index4 is RB when the gldrawbf parameter is 6'bxx1111; LAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b11xxxx; and RAU when the number of transmissions is 4 and the gldrawbf parameter is 6'b01xxxx.

[0050] The write buffer index variable `index3` is set to LB when the `gldrawbf` parameter is 6'bxxx111; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b001xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b011xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b101xxx; RB when the number of transmissions is 5 and the `gldrawbf` parameter is 6'b111xxx; LAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b01xxxx; LAU when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b11xxxx; and RAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b1xxxxx.

[0051] The write buffer index variable `index2` is RF when the `gldrawbf` parameter is 6'bxxxx11; LB when the `gldrawbf` parameter is 6'bxxx110; LB when the `gldrawbf` parameter is 6'bxxx101; RB when the number of transmissions is 2 and the `gldrawbf` parameter is 6'bxxx001xxx; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b101xxx; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b011xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b111xxx; LAU when the number of transmissions is 2 and the `gldrawbf` parameter is 6'b01xxxx; LAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b11xxxx; and RAU when the number of transmissions is 2 and the `gldrawbf` parameter is 6'b1xxxxx.

[0052] The write buffer index variable index1 is LF when the gldrawbf parameter is 6'bxxxxx1; RF when the gldrawbf parameter is 6'bxxxx10; LB when the gldrawbf parameter is 6'bxxx100; RB when the gldrawbf parameter is 6'bxx1000; LAU when the gldrawbf parameter is 6'bx10000; and RAU when the gldrawbf parameter is 6'b100000.

[0053] Furthermore, the core of the fragment mapping module is a state machine, including seven states: IDLE, SEND1, SEND2, SEND3, SEND4, SEND5, and SEND6. The state transition process is as follows:

[0054] 1) IDLE state:

[0055] When the circuit is powered on and reset, the state machine is in this state; after the reset is canceled, if the input data is found to be valid, one data transmission is required, and the state machine jumps to the SEND1 state. Data is transmitted, the first write address index is index1, and the output ready signal is equal to the input ready signal.

[0056] If the input data is valid, two data transmissions are required. The state machine then transitions to the SEND2 state. Data is transmitted, the second write address index is set to index2, and the ready signal '0' is output.

[0057] If the input data is valid, it needs to send data 3 times. The state machine then jumps to the SEND3 state; sends the data and the third write address index, index3, and outputs the ready signal '0'.

[0058] If the input data is valid, it needs to send data 4 times. The state machine then jumps to the SEND4 state; the data is sent, the 4th write address index is index4, and the ready signal '0' is output.

[0059] If the input data is valid, it needs to send data 5 times. The state machine then jumps to the SEND5 state; the data is sent, the 5th write address index is index5, and the ready signal '0' is output.

[0060] If the input data is valid, it needs to send data 6 times. The state machine then jumps to the SEND6 state; sends the data and the 6th write address index 6, and outputs the ready signal '0'.

[0061] Otherwise, it remains in the IDLE state and outputs the ready signal as '1';

[0062] 2) SEND1 status:

[0063] Data can be sent; if the input data is invalid, the state machine jumps to the IDLE state; data is sent, the first write address index is index1, and the ready signal is output as '1';

[0064] If the input data is valid, two data transmissions are required. The state machine then transitions to the SEND2 state. Data is transmitted, the second write address index is set to index2, and the ready signal '0' is output.

[0065] If the input data is valid, it needs to send data 3 times. The state machine then jumps to the SEND3 state; sends the data and the third write address index, index3, and outputs the ready signal '0'.

[0066] If the input data is valid, it needs to send data 4 times. The state machine then jumps to the SEND4 state; the data is sent, the 4th write address index is index4, and the ready signal '0' is output.

[0067] If the input data is valid, it needs to send data 5 times. The state machine then jumps to the SEND5 state; the data is sent, the 5th write address index is index5, and the ready signal '0' is output.

[0068] If the input data is valid, it needs to send data 6 times. The state machine then jumps to the SEND6 state; sends the data and the 6th write address index 6, and outputs the ready signal '0'.

[0069] 3) SEND2 status:

[0070] Data can be sent down. The state machine jumps to the SEND1 state, sends down the data and the first write address index1, and outputs the ready signal, which is equal to the input ready signal.

[0071] 4) SEND3 status:

[0072] Data can be sent down, the state machine jumps to the SEND2 state, and the data is sent down to the second write address index, index2.

[0073] 5) SEND4 status:

[0074] Data can be sent down, the state machine jumps to the SEND3 state, and the data is sent down to the third write address index, index3;

[0075] 6) SEND5 status:

[0076] Data can be sent down, the state machine jumps to the SEND4 state, and the data is sent down to the 4th write address index4;

[0077] 7) SEND6 status:

[0078] Data can be sent down. The state machine jumps to the SEND5 state to send the data and the 5th write address index, index5.

[0079] This invention provides a one-to-many fragment mapping method and system based on glDrawBuffer in a graphics processor. It adopts a method of pre-processing configuration parameters and writing order, preparing data in advance before the fragment arrives, and sending data one at a time when the fragment arrives, resulting in fast fragment processing speed. The configuration parameters and real-time data are operated separately, which is beneficial for circuit timing implementation. The entire processing is precisely controlled by a state machine, with a clear circuit structure that is easy to implement. The graphics can be drawn only once and displayed in multiple buffers, improving the processing speed of multi-buffer drawing scenes. Attached Figure Description

[0080] Figure 1 This is a system block diagram of the present invention;

[0081] Figure 2 This is the method for generating the write buffer index in this invention;

[0082] Figure 3 This is the state transition of the present invention. Detailed Implementation

[0083] The technical solution of the present invention will be further described in detail below with reference to specific embodiments.

[0084] This invention provides a one-to-many fragment mapping method based on glDrawBuffer in a graphics processor, the method specifically including the following steps:

[0085] 1) Identify the buffer configured by glDrawBuffer;

[0086] First, calculate the total number of 1s in the glDrawBuffer configuration register gldrawbf. Then, decode the total to generate a 6-bit one-hot code: bit 0 indicates writing data once, bit 1 indicates writing data twice, bit 3 indicates writing data three times, bit 4 indicates writing data four times, bit 5 indicates writing data five times, bit 6 indicates writing data six times, and all bits being 0 indicates no writing. When the total is 0, it means no color buffer is written. In this case, it is necessary to determine whether depth testing or stencil testing is enabled. If either is enabled, it means the depth buffer needs to be written. The number of sends needs to be selected based on the most recent non-zero configuration parameter: if the buffer is configured to write to both left and right buffers simultaneously, then both buffers need to be written twice; otherwise, only once.

[0087] 2) Sort the write order of the buffer and generate buffer indices;

[0088] The resulting buffer index is:

[0089] The write buffer index variable index6: is RAU when the number of transmissions is 6, and is invalid in other cases;

[0090] The write buffer index variable index5: is LAU when the number of transmissions is 6; is LAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b01xxxx; and is RAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b1xxxxx.

[0091] The write buffer index variable index4 is RB when the gldrawbf parameter is 6'bxx1111; LAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b11xxxx; and RAU when the number of transmissions is 4 and the gldrawbf parameter is 6'b01xxxx.

[0092] The write buffer index variable `index3` is set to LB when the `gldrawbf` parameter is 6'bxxx111; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b001xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b011xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b101xxx; RB when the number of transmissions is 5 and the `gldrawbf` parameter is 6'b111xxx; LAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b01xxxx; LAU when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b11xxxx; and RAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b1xxxxx.

[0093] The write buffer index variable `index2` is RF when the `gldrawbf` parameter is 6'bxxxx11; LB when the `gldrawbf` parameter is 6'bxxx110; LB when the `gldrawbf` parameter is 6'bxxx101; RB when the number of transmissions is 2 and the `gldrawbf` parameter is 6'bxxx001xxx; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b101xxx; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b011xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b111xxx; LAU when the number of transmissions is 2 and the `gldrawbf` parameter is 6'b01xxxx; LAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b11xxxx; and RAU when the number of transmissions is 2 and the `gldrawbf` parameter is 6'b1xxxxx.

[0094] The write buffer index variable `index1` is LF when the `gldrawbf` parameter is 6'bxxxxx1; RF when the `gldrawbf` parameter is 6'bxxxx10; LB when the `gldrawbf` parameter is 6'bxxx100; RB when the `gldrawbf` parameter is 6'bxx1000; LAU when the `gldrawbf` parameter is 6'bx10000; and RAU when the `gldrawbf` parameter is 6'b100000.

[0095] 3) Map the fragments to different buffers in the determined order. The fragment output process is implemented by a control state machine. The received tiles are sent in multiple times, each time carrying different buffer index information.

[0096] The state machine consists of seven states: IDLE, SEND1, SEND2, SEND3, SEND4, SEND5, and SEND6. The state transition process is as follows:

[0097] 1) IDLE state:

[0098] When the circuit is powered on and reset, the state machine is in this state; after the reset is canceled, if the input data is detected to be valid, data needs to be sent once, and the state machine jumps to the SEND1 state; data is sent, the first write address index is index1, and the output ready signal is equal to the input ready signal;

[0099] If the input data is valid, two data transmissions are required. The state machine then transitions to the SEND2 state. Data is transmitted, the second write address index is set to index2, and the ready signal '0' is output.

[0100] If the input data is valid, it needs to send data 3 times. The state machine then jumps to the SEND3 state; sends the data and the third write address index, index3, and outputs the ready signal '0'.

[0101] If the input data is valid, it needs to send data 4 times. The state machine then jumps to the SEND4 state; the data is sent, the 4th write address index is index4, and the ready signal '0' is output.

[0102] If the input data is valid, it needs to send data 5 times. The state machine then jumps to the SEND5 state; the data is sent, the 5th write address index is index5, and the ready signal '0' is output.

[0103] If the input data is valid, it needs to send data 6 times. The state machine then jumps to the SEND6 state; sends the data and the 6th write address index 6, and outputs the ready signal '0'.

[0104] Otherwise, it remains in the IDLE state and outputs the ready signal as '1';

[0105] 2) SEND1 status:

[0106] Data can be sent; if the input data is invalid, the state machine jumps to the IDLE state; data is sent, the first write address index is index1, and the ready signal is output as '1';

[0107] If the input data is valid, two data transmissions are required. The state machine then transitions to the SEND2 state. Data is transmitted, the second write address index is set to index2, and the ready signal '0' is output.

[0108] If the input data is valid, it needs to send data 3 times. The state machine then jumps to the SEND3 state; sends the data and the third write address index, index3, and outputs the ready signal '0'.

[0109] If the input data is valid, it needs to send data 4 times. The state machine then jumps to the SEND4 state; the data is sent, the 4th write address index is index4, and the ready signal '0' is output.

[0110] If the input data is valid, it needs to send data 5 times. The state machine then jumps to the SEND5 state; the data is sent, the 5th write address index is index5, and the ready signal '0' is output.

[0111] If the input data is valid, it needs to send data 6 times. The state machine then jumps to the SEND6 state; sends the data and the 6th write address index 6, and outputs the ready signal '0'.

[0112] 3) SEND2 status:

[0113] Data can be sent down. The state machine jumps to the SEND1 state, sends down the data and the first write address index1, and outputs the ready signal, which is equal to the input ready signal.

[0114] 4) SEND3 status:

[0115] Data can be sent down, the state machine jumps to the SEND2 state, and the data is sent down to the second write address index, index2.

[0116] 5) SEND4 status:

[0117] Data can be sent down, the state machine jumps to the SEND3 state, and the data is sent down to the third write address index, index3;

[0118] 6) SEND5 status:

[0119] Data can be sent down, the state machine jumps to the SEND4 state, and the data is sent down to the 4th write address index4;

[0120] 7) SEND6 status:

[0121] Data can be sent down. The state machine jumps to the SEND5 state to send the data and the 5th write address index, index5.

[0122] See Figure 1 The structure of a specific embodiment of the one-to-many fragment mapping system based on glDrawBuffer in the graphics processor of the present invention includes three parts: a glDrawBuffer parameter parsing module, a buffer index generation module, and a fragment mapping module. The glDrawBuffer parameter parsing module and the buffer index generation module are respectively connected to the fragment mapping module to realize the mapping from one fragment to multiple fragments based on glDrawBuffer during the fragment processing stage.

[0123] The parameter value of the buffer configuration command glDrawBuffer(bufs) determines the number of fragment maps and the buffers to be written. Its value is an enumeration type with a 6-bit data format, containing seven parameter types: GL_NONE, GL_FRONT_LEFT (bit0), GL_FRONT_RIGHT (bit1), GL_BACK_LEFT (bit2), GL_BACK_RIGHT (bit3), GL_AUX0 (bit4), and GL_AUX1 (bit5). Each time, one or more of these parameters can be included, specifying one or more of the six color buffers (left front, left back, left auxiliary, right front, right back, and right auxiliary), or no buffer to write to.

[0124] The glDrawBuffer parameter parsing module parses the bufs value to determine the buffer to be written to and the number of times data is sent. First, it calculates the sum of the number of 1s in the glDrawBuffer configuration register gldrawbf. Then, it decodes the sum to generate a 6-bit one-hot code: bit 0 indicates writing data once, bit 1 indicates writing data twice, bit 3 indicates writing data three times, bit 4 indicates writing data four times, bit 5 indicates writing data five times, bit 6 indicates writing data six times, and all bits being 0 indicates no writing (the tile is discarded without outputting data). When the sum is 0, it means no color buffer is written. In this case, it needs to determine whether depth testing or stencil testing is enabled. If either is enabled, the depth buffer needs to be written, and the number of times to send data needs to be selected based on the most recent non-zero configuration parameter: if the buffer is configured to write to both left and right buffers simultaneously, then both buffers need to be written twice (only the depth buffer is written); otherwise, only one write is required.

[0125] The buffer index generation module generates six buffer indices based on the gldrawbf signal and the number of transmissions. The index generation method is as follows: Figure 2 As shown.

[0126] The fragment mapping module is based on a state machine, which includes seven states: 1. IDLE state; 2. SEND1 state; 3. SEND2 state; 4. SEND3 state; 5. SEND4 state; 6. SEND5 state; and 7. SEND6 state.

[0127] See Figure 2 The method for generating buffer indices in the buffer index generation module is described in detail below:

[0128] The write buffer index variable index6 is RAU when the number of transmissions is 6, and invalid in other cases.

[0129] The write buffer index variable index5: is LAU when the number of transmissions is 6; is LAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b01xxxx; and is RAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b1xxxxx.

[0130] The write buffer index variable index4 is RB when the gldrawbf parameter is 6'bxx1111; LAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b11xxxx; and RAU when the number of transmissions is 4 and the gldrawbf parameter is 6'b01xxxx.

[0131] The write buffer index variable `index3` is set to LB when the `gldrawbf` parameter is 6'bxxx111; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b001xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b011xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b101xxx; RB when the number of transmissions is 5 and the `gldrawbf` parameter is 6'b111xxx; LAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b01xxxx; LAU when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b11xxxx; and RAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b1xxxxx.

[0132] The write buffer index variable `index2` is RF when the `gldrawbf` parameter is 6'bxxxx11; LB when the `gldrawbf` parameter is 6'bxxxx110; LB when the `gldrawbf` parameter is 6'bxxxx101; RB when the number of transmissions is 2 and the `gldrawbf` parameter is 6'bxxxx001xxx; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b101xxx; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b011xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b111xxx; LAU when the number of transmissions is 2 and the `gldrawbf` parameter is 6'b01xxxx; LAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b11xxxx; and RAU when the number of transmissions is 2 and the `gldrawbf` parameter is 6'b1xxxxx.

[0133] The write buffer index variable index1 is LF when the gldrawbf parameter is 6'bxxxxx1; RF when the gldrawbf parameter is 6'bxxxx10; LB when the gldrawbf parameter is 6'bxxx100; RB when the gldrawbf parameter is 6'bxx1000; LAU when the gldrawbf parameter is 6'bx10000; and RAU when the gldrawbf parameter is 6'b100000.

[0134] See Figure 3 The fragment mapping module state transition is described in detail below:

[0135] 1. IDLE state:

[0136] When the circuit is powered on and reset, the state machine is in this state. After the reset is canceled, if the input data is detected to be valid, one data transmission is required, and the state machine jumps to the SEND1 state. Data is transmitted, the first write address index is index1, and the output ready signal is equal to the input ready signal;

[0137] If the input data is valid, two data transmissions are required. The state machine then transitions to the SEND2 state. Data is transmitted, the second write address index is set to index2, and the ready signal '0' is output.

[0138] If the input data is valid, it needs to send data 3 times. The state machine then jumps to the SEND3 state; sends the data and the third write address index, index3, and outputs the ready signal '0'.

[0139] If the input data is valid, it needs to send data 4 times. The state machine then jumps to the SEND4 state; the data is sent, the 4th write address index is index4, and the ready signal '0' is output.

[0140] If the input data is valid, it needs to send data 5 times. The state machine then jumps to the SEND5 state; the data is sent, the 5th write address index is index5, and the ready signal '0' is output.

[0141] If the input data is valid, it needs to send data 6 times. The state machine then jumps to the SEND6 state; sends the data and the 6th write address index 6, and outputs the ready signal '0'.

[0142] Otherwise, remain in the IDLE state. Output the ready signal as '1'.

[0143] 2. SEND1 status:

[0144] Data can be sent; if the input data is invalid, the state machine jumps to the IDLE state; data is sent, the first write address index is index1, and the ready signal is output as '1';

[0145] If the input data is valid, two data transmissions are required. The state machine then transitions to the SEND2 state. Data is transmitted, the second write address index is set to index2, and the ready signal '0' is output.

[0146] If the input data is valid, it needs to send data 3 times. The state machine then jumps to the SEND3 state; sends the data and the third write address index, index3, and outputs the ready signal '0'.

[0147] If the input data is valid, it needs to send data 4 times. The state machine then jumps to the SEND4 state; the data is sent, the 4th write address index is index4, and the ready signal '0' is output.

[0148] If the input data is valid, it needs to send data 5 times. The state machine then jumps to the SEND5 state; the data is sent, the 5th write address index is index5, and the ready signal '0' is output.

[0149] If the input data is valid, six data transmissions are required. The state machine then transitions to the SEND6 state. After transmitting the data and the sixth write address index (index6), the ready signal '0' is output.

[0150] 3. SEND2 status:

[0151] Data can be sent down. The state machine jumps to the SEND1 state, sends down the data and the first write address index, index1, and outputs the ready signal, which is equal to the input ready signal.

[0152] 4. SEND3 status:

[0153] Data can be sent down, the state machine jumps to the SEND2 state, and the data is sent down to the second write address index, index2.

[0154] 5. SEND4 status:

[0155] Data can be sent down, the state machine jumps to the SEND3 state, and the data is sent down to the third write address index, index3;

[0156] 6. SEND5 status:

[0157] Data can be sent down, the state machine jumps to the SEND4 state, and the data is sent down to the 4th write address index, index4.

[0158] 7. SEND6 status:

[0159] Data can be sent down. The state machine jumps to the SEND5 state to send the data and the 5th write address index, index5.

[0160] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A one-to-many fragment mapping method based on glDrawBuffer in a graphics processor, characterized in that: The method includes the following steps: 1) Identify the buffer configured by glDrawBuffer; First, calculate the total number of 1s in the glDrawBuffer configuration register gldrawbf. Then, decode the total to generate a 6-bit one-hot code: bit 0 indicates writing data once, bit 1 indicates writing data twice, bit 3 indicates writing data three times, bit 4 indicates writing data four times, bit 5 indicates writing data five times, bit 6 indicates writing data six times, and all bits being 0 indicates no writing. When the total is 0, it means no color buffer is written. In this case, it is necessary to determine whether depth testing or stencil testing is enabled. If either is enabled, it means the depth buffer needs to be written. The number of sends needs to be selected based on the most recent non-zero configuration parameter: if the buffer is configured to write to both left and right buffers simultaneously, then both buffers need to be written twice; otherwise, only once. 2) Sort the write order of the buffer and generate buffer indices; 3) Map the fragments to different buffers in the determined order. The fragment output process is implemented by a control state machine. The received tiles are sent in multiple times, each time carrying different buffer index information.

2. The one-to-many fragment mapping method based on glDrawBuffer in a graphics processor according to claim 1, characterized in that: The buffer index generated in step 2) is: The write buffer index variable index6: is RAU when the number of transmissions is 6, and is invalid in other cases; The write buffer index variable index5: is LAU when the number of transmissions is 6; is LAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b01xxxx; and is RAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b1xxxxx. The write buffer index variable index4 is RB when the gldrawbf parameter is 6'bxx1111; LAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b11xxxx; and RAU when the number of transmissions is 4 and the gldrawbf parameter is 6'b01xxxx. The write buffer index variable `index3` is set to LB when the `gldrawbf` parameter is 6'bxxx111; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b001xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b011xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b101xxx; RB when the number of transmissions is 5 and the `gldrawbf` parameter is 6'b111xxx; LAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b01xxxx; LAU when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b11xxxx; and RAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b1xxxxx. The write buffer index variable `index2` is RF when the `gldrawbf` parameter is 6'bxxxx11; LB when the `gldrawbf` parameter is 6'bxxx110; LB when the `gldrawbf` parameter is 6'bxxx101; RB when the number of transmissions is 2 and the `gldrawbf` parameter is 6'bxxx001xxx; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b101xxx; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b011xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b111xxx; LAU when the number of transmissions is 2 and the `gldrawbf` parameter is 6'b01xxxx; LAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b11xxxx; and RAU when the number of transmissions is 2 and the `gldrawbf` parameter is 6'b1xxxxx. The write buffer index variable index1 is LF when the gldrawbf parameter is 6'bxxxxx1; RF when the gldrawbf parameter is 6'bxxxx10; LB when the gldrawbf parameter is 6'bxxx100; and RB when the gldrawbf parameter is 6'bxx1000. When the gldrawbf parameter is 6'bx10000, it is LAU; when the gldrawbf parameter is 6'b100000, it is RAU.

3. The one-to-many fragment mapping method based on glDrawBuffer in a graphics processor according to claim 2, characterized in that: The state machine in step 3) includes seven states: IDLE, SEND1, SEND2, SEND3, SEND4, SEND5, and SEND6. The state transition process is as follows: 1) IDLE state: When the circuit is powered on and reset, the state machine is in this state; after the reset is canceled, if the input data is detected to be valid, data needs to be sent once, and the state machine jumps to the SEND1 state; data is sent, the first write address index is index1, and the output ready signal is equal to the input ready signal; If the input data is valid, two data transmissions are required. The state machine then transitions to the SEND2 state. Data is transmitted, the second write address index is set to index2, and the ready signal '0' is output. If the input data is valid, it needs to send data 3 times. The state machine then jumps to the SEND3 state; sends the data and the third write address index, index3, and outputs the ready signal '0'. If the input data is valid, it needs to send data 4 times. The state machine then jumps to the SEND4 state; the data is sent, the 4th write address index is index4, and the ready signal '0' is output. If the input data is valid, it needs to send data 5 times. The state machine then jumps to the SEND5 state; the data is sent, the 5th write address index is index5, and the ready signal '0' is output. If the input data is valid, it needs to send data 6 times. The state machine then jumps to the SEND6 state; sends the data and the 6th write address index 6, and outputs the ready signal '0'. Otherwise, it remains in the IDLE state and outputs the ready signal as '1'; 2) SEND1 status: Data can be sent; if the input data is invalid, the state machine jumps to the IDLE state; data is sent, the first write address index is index1, and the ready signal is output as '1'; If the input data is valid, two data transmissions are required. The state machine then transitions to the SEND2 state. Data is transmitted, the second write address index is set to index2, and the ready signal '0' is output. If the input data is valid, it needs to send data 3 times. The state machine then jumps to the SEND3 state; sends the data and the third write address index, index3, and outputs the ready signal '0'. If the input data is valid, it needs to send data 4 times. The state machine then jumps to the SEND4 state; the data is sent, the 4th write address index is index4, and the ready signal '0' is output. If the input data is valid, it needs to send data 5 times. The state machine then jumps to the SEND5 state; the data is sent, the 5th write address index is index5, and the ready signal '0' is output. If the input data is valid, it needs to send data 6 times. The state machine then jumps to the SEND6 state; sends the data and the 6th write address index 6, and outputs the ready signal '0'. 3) SEND2 state: Data can be sent down. The state machine jumps to the SEND1 state, sends down the data and the first write address index1, and outputs the ready signal, which is equal to the input ready signal. 4) SEND3 status: Data can be sent down, the state machine jumps to the SEND2 state, and the data is sent down to the second write address index, index2. 5) SEND4 status: Data can be sent down, the state machine jumps to the SEND3 state, and the data is sent down to the third write address index, index3; 6) SEND5 status: Data can be sent down, the state machine jumps to the SEND4 state, and the data is sent down to the 4th write address index4; 7) SEND6 status: Data can be sent down. The state machine jumps to the SEND5 state to send the data and the 5th write address index, index5.

4. A system for implementing the one-to-many fragment mapping method based on glDrawBuffer in a graphics processor as described in claim 1, characterized in that: The system includes a glDrawBuffer parameter parsing module, a buffer index generation module, and a fragment mapping module. The glDrawBuffer parameter parsing module and the buffer index generation module are respectively connected to the fragment mapping module. The glDrawBuffer parameter parsing module parses the bufs value to determine the buffer to be written and the number of times data is sent. The glDrawBuffer parameter parsing module first calculates the sum of the number of glDrawBuffer configuration register gldrawbf values ​​that are 1, and then decodes the sum to generate a 6-bit one-hot code: bit 0 indicates writing data once, bit 1 indicates writing data twice, bit 3 indicates writing data three times, bit 4 indicates writing data four times, bit 5 indicates writing data five times, bit 6 indicates writing data six times, and all bits being 0 indicates no writing. When the sum is 0, it means that no color buffer is written. At this time, it is necessary to determine whether depth testing or stencil testing is enabled. If either one is enabled, it means that the depth buffer needs to be written. The number of times to send data needs to be selected based on the most recent non-zero configuration parameter: if the buffer is configured to write to both left and right buffers simultaneously, then both left and right buffers need to be written twice; otherwise, only one write is required.

5. The one-to-many fragment mapping system based on glDrawBuffer in a graphics processor according to claim 4, characterized in that: The buffer index generation module generates 6 buffer indices based on the gldrawbf signal and the number of times it is sent.

6. The one-to-many fragment mapping system based on glDrawBuffer in a graphics processor according to claim 5, characterized in that: The specific method by which the buffer index generation module generates the buffer index is as follows: The write buffer index variable index6: is RAU when the number of transmissions is 6, and is invalid in other cases; The write buffer index variable index5: is LAU when the number of transmissions is 6; is LAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b01xxxx; and is RAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b1xxxxx. The write buffer index variable index4 is RB when the gldrawbf parameter is 6'bxx1111; LAU when the number of transmissions is 5 and the gldrawbf parameter is 6'b11xxxx; and RAU when the number of transmissions is 4 and the gldrawbf parameter is 6'b01xxxx. The write buffer index variable `index3` is set to LB when the `gldrawbf` parameter is 6'bxxx111; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b001xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b011xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b101xxx; RB when the number of transmissions is 5 and the `gldrawbf` parameter is 6'b111xxx; LAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b01xxxx; LAU when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b11xxxx; and RAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b1xxxxx. The write buffer index variable `index2` is RF when the `gldrawbf` parameter is 6'bxxxx11; LB when the `gldrawbf` parameter is 6'bxxx110; LB when the `gldrawbf` parameter is 6'bxxx101; RB when the number of transmissions is 2 and the `gldrawbf` parameter is 6'bxxx001xxx; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b101xxx; RB when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b011xxx; RB when the number of transmissions is 4 and the `gldrawbf` parameter is 6'b111xxx; LAU when the number of transmissions is 2 and the `gldrawbf` parameter is 6'b01xxxx; LAU when the number of transmissions is 3 and the `gldrawbf` parameter is 6'b11xxxx; and RAU when the number of transmissions is 2 and the `gldrawbf` parameter is 6'b1xxxxx. The write buffer index variable index1 is LF when the gldrawbf parameter is 6'bxxxxx1; RF when the gldrawbf parameter is 6'bxxxx10; LB when the gldrawbf parameter is 6'bxxx100; and RB when the gldrawbf parameter is 6'bxx1000. When the gldrawbf parameter is 6'bx10000, it is LAU; when the gldrawbf parameter is 6'b100000, it is RAU.

7. The one-to-many fragment mapping system based on glDrawBuffer in a graphics processor according to claim 6, characterized in that: The core of the fragment mapping module is a state machine, which includes seven states: IDLE, SEND1, SEND2, SEND3, SEND4, SEND5, and SEND6. The state transition process is as follows: 1) IDLE state: When the circuit is powered on and reset, the state machine is in this state; after the reset is canceled, if the input data is detected to be valid, data needs to be sent once, and the state machine jumps to the SEND1 state; data is sent, the first write address index is index1, and the output ready signal is equal to the input ready signal; If the input data is valid, two data transmissions are required. The state machine then transitions to the SEND2 state. Data is transmitted, the second write address index is set to index2, and the ready signal '0' is output. If the input data is valid, it needs to send data 3 times. The state machine then jumps to the SEND3 state; sends the data and the third write address index, index3, and outputs the ready signal '0'. If the input data is valid, it needs to send data 4 times. The state machine then jumps to the SEND4 state; the data is sent, the 4th write address index is index4, and the ready signal '0' is output. If the input data is valid, it needs to send data 5 times. The state machine then jumps to the SEND5 state; the data is sent, the 5th write address index is index5, and the ready signal '0' is output. If the input data is valid, it needs to send data 6 times. The state machine then jumps to the SEND6 state; sends the data and the 6th write address index 6, and outputs the ready signal '0'. Otherwise, it remains in the IDLE state and outputs the ready signal as '1'; 2) SEND1 status: Data can be sent; if the input data is invalid, the state machine jumps to the IDLE state; data is sent, the first write address index is index1, and the ready signal is output as '1'; If the input data is valid, two data transmissions are required. The state machine then transitions to the SEND2 state. Data is transmitted, the second write address index is set to index2, and the ready signal '0' is output. If the input data is valid, it needs to send data 3 times. The state machine then jumps to the SEND3 state; sends the data and the third write address index, index3, and outputs the ready signal '0'. If the input data is valid, it needs to send data 4 times. The state machine then jumps to the SEND4 state; the data is sent, the 4th write address index is index4, and the ready signal '0' is output. If the input data is valid, it needs to send data 5 times. The state machine then jumps to the SEND5 state; the data is sent, the 5th write address index is index5, and the ready signal '0' is output. If the input data is valid, it needs to send data 6 times. The state machine then jumps to the SEND6 state; sends the data and the 6th write address index 6, and outputs the ready signal '0'. 3) SEND2 state: Data can be sent down. The state machine jumps to the SEND1 state, sends down the data and the first write address index1, and outputs the ready signal, which is equal to the input ready signal. 4) SEND3 status: Data can be sent down, the state machine jumps to the SEND2 state, and the data is sent down to the second write address index, index2. 5) SEND4 status: Data can be sent down, the state machine jumps to the SEND3 state, and the data is sent down to the third write address index, index3; 6) SEND5 status: Data can be sent down, the state machine jumps to the SEND4 state, and the data is sent down to the 4th write address index4; 7) SEND6 status: Data can be sent down. The state machine jumps to the SEND5 state to send the data and the 5th write address index, index5.

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