Ultrasonic fingerprint device and electronic device

Abstract

The present application provides an ultrasonic fingerprint device and an electronic device, wherein the ultrasonic fingerprint device is arranged below a display screen of the electronic device to realize under-screen ultrasonic fingerprint recognition, wherein the ultrasonic fingerprint device comprises an ultrasonic fingerprint chip and a piezoelectric transducer arranged above the ultrasonic fingerprint chip; the piezoelectric transducer comprises a piezoelectric layer, an upper electrode located above the piezoelectric layer, and a lower electrode located below the piezoelectric layer; the ultrasonic fingerprint chip is a CMOS chip, the upper electrode is led out to the surface of the CMOS chip, and is connected to one end of a lead through a pad on the surface of the COMS chip, and the other end of the lead is connected to a circuit board below the ultrasonic fingerprint chip to realize electrical connection between the piezoelectric transducer and the circuit board.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of fingerprint recognition, and more specifically, to an ultrasonic fingerprint device and an electronic device. Background Art

[0002] With the progress of society, mobile phones have become one of the indispensable electronic devices in modern life. Currently, all mobile phones on the market have one or more identity authentication methods, including digital passwords, gesture graphics, facial recognition, fingerprint recognition, etc. Among them, fingerprint recognition has become a standard feature of most mobile phones due to its convenient application, fast recognition speed, stability and reliability. Fingerprint recognition has also developed different technical routes, including capacitive fingerprint recognition, optical fingerprint recognition and ultrasonic fingerprint recognition.

[0003] Ultrasonic fingerprint recognition can not only identify the surface morphology of fingerprints, but also identify the signal of the dermis layer of the finger, thus achieving natural 3D anti-counterfeiting. Compared with optical fingerprint recognition, ultrasonic fingerprint recognition has a higher tolerance for the cleanliness of the finger surface. Therefore, ultrasonic fingerprint recognition has gradually become a new generation of fingerprint recognition. Ultrasonic fingerprint devices usually include piezoelectric transducers and ultrasonic fingerprint chips. How to achieve the integration between piezoelectric transducers and ultrasonic fingerprint chips has become a problem that needs to be solved. Summary of the invention

[0004] The embodiments of the present application provide an ultrasonic fingerprint device and an electronic device, which can realize the integration between a piezoelectric transducer and an ultrasonic fingerprint chip.

[0005] In a first aspect, an ultrasonic fingerprint device is provided, which is arranged under a display screen of an electronic device to implement under-screen ultrasonic fingerprint recognition, wherein the ultrasonic fingerprint device includes an ultrasonic fingerprint chip and a piezoelectric transducer arranged above the ultrasonic fingerprint chip;

[0006] The piezoelectric transducer includes a piezoelectric layer, an upper electrode located above the piezoelectric layer, and a lower electrode located below the piezoelectric layer;

[0007] The ultrasonic fingerprint chip is a CMOS chip, and the upper electrode is led out from the upper surface of the piezoelectric layer to the surface of the CMOS chip, and is connected to one end of the lead through the pad on the surface of the CMOS chip, and the other end of the lead is connected to the circuit board under the ultrasonic fingerprint chip to realize the electrical connection between the piezoelectric transducer and the circuit board.

[0008] In the embodiment of the present application, the ultrasonic fingerprint device includes a CMOS chip and an ultrasonic transducer. The substrate of the CMOS chip is a silicon substrate, so wire bonding can be achieved. After the upper electrode is led out to the surface of the ultrasonic fingerprint chip, the upper electrode and the lead can be interconnected on the ultrasonic fingerprint chip through a bonding process, that is, the upper electrode is fixed and connected to one end of the lead by using the pad on the surface of the ultrasonic fingerprint chip, and the other end of the lead is connected to the circuit board under the ultrasonic fingerprint chip, thereby realizing the interconnection between the upper electrode and the circuit board. The process is easy to implement and has high reliability.

[0009] In one implementation, the ultrasonic fingerprint chip includes a substrate and multiple metal layers arranged in a first area of ​​the substrate, the substrate is a silicon substrate, the lower electrode is located above the second area of ​​the substrate, the top metal layer among the multiple metal layers includes N drive traces, N=1 or N is a positive integer greater than 1, the upper electrode is respectively connected to N pads through the N drive traces, and the N pads respectively connect the N drive traces to their respective corresponding leads.

[0010] On the one hand, the density of the silver paste material of the upper electrode is very low and cannot support the bonding process. In this embodiment, by setting a drive line on the ultrasonic fingerprint chip, the upper electrode can be led out to the surface of the ultrasonic fingerprint chip through the drive line. On the other hand, due to the use of a CMOS chip, the bonding process can be implemented on the chip surface to connect the drive line to the circuit board through the lead. In this way, the interconnection between the upper electrode and the circuit board is achieved.

[0011] In one implementation, a passivation layer is disposed above the top metal layer, a first window corresponding to the N driving lines is disposed on the passivation layer, and the upper electrode extends from the upper surface of the piezoelectric layer into the first window to connect the first connection areas of the N driving lines respectively located in the first window, thereby achieving electrical connection between the upper electrode and the N driving lines.

[0012] In one implementation, the first window includes N sub-windows corresponding to the N driving lines, and the first connection area of ​​each driving line is located in its corresponding sub-window.

[0013] In one implementation, the passivation layer is further provided with N second windows corresponding to the N driving lines, wherein each driving line is located in a second connection area within its corresponding second window and is connected to its corresponding lead through its corresponding pad.

[0014] In this embodiment, since the substrate of the CMOS chip is a silicon substrate, a bonding process can be implemented on the substrate. Therefore, by setting a second window, the bonding process can be used to achieve connection between the driving trace and the lead, and the driving trace is connected to the circuit board through the lead.

[0015] In one implementation, the piezoelectric layer extends above the multiple metal layers, the N driving wires extend into the piezoelectric layer, and the first connection region of the N driving wires is adjacent to the piezoelectric layer.

[0016] When the piezoelectric layer extends above multiple metal layers and the drive line extends into the piezoelectric layer, the first connection area of ​​the drive line can be close to the edge of the piezoelectric layer, that is, the distance between the piezoelectric layer and the first connection area is minimized, making the structure of the ultrasonic fingerprint device more compact.

[0017] In one implementation, the size of the first window is larger than the size of the first connection area of ​​the N driving lines, the upper electrode extends from the upper surface of the piezoelectric layer to the first part of the first window to cover the first connection area of ​​the N driving lines, and the second part of the first window is located below the piezoelectric layer.

[0018] When the size of the first window is larger than the size of the first connection area of ​​the N driving lines, the upper electrode extends to the first part of the first window to cover the first connection area of ​​the driving line located in the first part, and the second part of the first window extends into the piezoelectric layer and is located below the piezoelectric layer, thereby improving the connection reliability between the upper electrode and the driving line

[0019] In one implementation, a size of the first portion in the direction of the N driving lines is greater than or equal to 150 um; and / or a size of the second portion in the direction of the N driving lines is greater than or equal to 20 um.

[0020] In one implementation, the distance between other routing lines in the top metal layer adjacent to the N driving routing lines and the N driving routing lines is greater than or equal to 10 um.

[0021] Since the voltage of the driving signal of the upper electrode is usually high, significantly higher than the working voltage of the circuit in the ultrasonic fingerprint chip, it is not only easy to interfere with the circuit in the ultrasonic fingerprint chip, but also easy to cause electrical breakdown damage to the ultrasonic fingerprint chip. Therefore, other lines adjacent to the driving lines on the top metal layer should be kept at a distance from the driving lines to avoid the same-layer breakdown, ensure the safety of the ultrasonic fingerprint device, and prevent the driving lines from interfering with other lines on the top metal layer.

[0022] In one implementation, other wirings on the top metal layer adjacent to the N driving wirings are grounded, so that the top metal layer shields the N driving wirings, thereby preventing the N driving wirings from interfering with other wirings on the top metal layer.

[0023] In one implementation, a first metal layer among the multiple metal layers has holes drilled in areas corresponding to the N driving traces, and the first metal layer is an adjacent metal layer located below the top metal layer.

[0024] Since the first metal layer is an adjacent metal layer located below the top metal layer, by digging holes in the corresponding areas below the N driving lines, the electrical gap between the N driving lines and other lines of the first metal layer is increased, thereby increasing the compressive strength of the first metal layer and avoiding interlayer breakdown between the top metal layer and the first metal layer.

[0025] In one implementation, holes are dug in the area on the first metal layer corresponding to the N driving traces and in an area extending around the area by a length greater than or equal to 12 um.

[0026] By extending the hole area from the area corresponding to the N driving lines to the surroundings for a certain distance, the electrical clearance between the driving lines and other lines of the first metal layer is further increased, thereby avoiding interlayer breakdown between the top metal layer and the first metal layer to the greatest extent.

[0027] In one implementation, a region on a second metal layer among the plurality of metal layers corresponding to the N driving traces is grounded, and the second metal layer is an adjacent metal layer located below the first metal layer.

[0028] Since the second metal layer is an adjacent metal layer located below the first metal layer, by grounding its corresponding area below the driving wiring, the second metal layer has a shielding effect on the N driving wirings, thereby preventing other wirings on the second metal layer from interfering with the wirings on the third metal layer below it.

[0029] In one implementation, the area on the second metal layer corresponding to the N driving traces and an area extending around the area by more than or equal to 12 um are grounded.

[0030] By extending the grounding area on the second metal layer from the area corresponding to the N driving lines to the surrounding areas for a certain distance, the shielding effect of the second metal layer on the driving lines is further enhanced, and the interference of other lines of the second metal layer on the lines on the third metal layer below it is minimized.

[0031] In one implementation, a pad for grounding is disposed on the top metal layer, and the pad is disposed beside the second connection region of the N driving traces.

[0032] In order to prevent the high voltage of the driving line from causing electrical breakdown and interference to the metal layer in the ultrasonic fingerprint chip, a grounded pad is arranged next to the second connection area of ​​the driving line. There is a certain distance between the pad and the second connection area, which can prevent the driving signal from interfering with other surrounding signals.

[0033] In one implementation, the distance between the lower electrode and the passivation layer surrounding the lower electrode is greater than or equal to 100 um; and / or other traces in the top metal layer adjacent to the lower electrode are grounded.

[0034] There is a certain distance between the lower electrode and the passivation layer around the lower electrode, and / or other traces adjacent to the lower electrode on the top metal layer are grounded, which can play a shielding role and prevent external interference from affecting the pixels close to the edge of the array of the lower electrode, while reducing the edge effect of the edge pixels and improving the consistency between the edge effect and the center pixel.

[0035] In one implementation, the distance between the edge of the upper electrode and the edge of the piezoelectric layer is greater than or equal to 50 um, thereby preventing the upper electrode from overflowing to the surface of the ultrasonic fingerprint chip and avoiding the risk of breakdown.

[0036] In one implementation, N=1, and the area of ​​the first window at the portion close to the piezoelectric layer is larger than the area of ​​the portion far from the piezoelectric layer, thereby improving the connection reliability between the upper electrode and the driving wiring.

[0037] In one implementation, the first window has a trapezoidal shape, and a lower base of the trapezoid is closer to the piezoelectric layer than an upper base thereof.

[0038] In one implementation, the first window is L-shaped, and the L-shape consists of a first portion parallel to the direction of the driving line and a second portion perpendicular to the direction of the driving line, and the second portion is closer to the piezoelectric layer than the first portion.

[0039] In a second aspect, an electronic device is provided, comprising: a display screen; and the ultrasonic fingerprint device according to the first aspect or any implementation manner of the first aspect, wherein the ultrasonic fingerprint device is arranged below the display screen to implement under-screen ultrasonic fingerprint recognition. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is an integration method between the piezoelectric transducer and the ultrasonic fingerprint chip in the ultrasonic fingerprint device.

[0041] Figure 2 is a schematic block diagram of an ultrasonic fingerprint device according to an embodiment of the present application.

[0042] Figure 3 yes Figure 2 A schematic diagram of a possible structure of an ultrasonic fingerprint device is shown.

[0043] Figure 4 yes Figure 2 A schematic diagram of another possible structure of an ultrasonic fingerprint device is shown.

[0044] Figure 5 yes Figure 4 A schematic top view of a possible structure of an ultrasonic fingerprint device is shown.

[0045] Figure 6 yes Figure 4 A schematic top view of another possible structure of an ultrasonic fingerprint device is shown.

[0046] Figure 7 It is an equivalent circuit diagram between the driving wiring and the upper electrode when the oxide layer formed on the first connection region is not broken down.

[0047] Figure 8 It is an equivalent circuit diagram between the driving wiring and the upper electrode when the oxide layer formed on the first connection region is broken down.

[0048] Fig. 9 yes Figure 4 A schematic top view of a local area of ​​an ultrasonic fingerprint device is shown.

[0049] Fig.10 yes Figure 5 Cross-sectional view of region A along a direction perpendicular to the edge of the piezoelectric transducer.

[0050] Fig.11 It is a schematic diagram of the shape of the first window in one embodiment of the present application.

[0051] Fig.12 It is a schematic diagram of the shape of the first window in another embodiment of the present application.

[0052] Fig.13 yes Fig.12 A schematic diagram of some possible dimensions of the L-shape.

[0053] Fig.14 It is a schematic block diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0054] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0055] Figure 1 A conventional ultrasonic fingerprint device 1 is shown, which includes an ultrasonic fingerprint chip 101 and a piezoelectric transducer 102. The piezoelectric transducer 102 includes a piezoelectric layer 1021, an upper electrode 1022 located above the piezoelectric layer 1021, and a lower electrode 1023 located below the piezoelectric layer 1021. The piezoelectric layer 1021 is formed of a piezoelectric material such as PVDF or PVDF-TrFE. The piezoelectric transducer 102 is also called an ultrasonic transducer, which is disposed on the ultrasonic fingerprint chip 101. The passivation layer 1024 plays a protective role. The ultrasonic fingerprint chip 101 is a thin film transistor (TFT).

[0056] The material of the upper electrode 1022 is usually metal or metal mixture, such as silver paste (Ag). The density of silver paste is very low and does not support the bonding process (or wire bonding process). It needs to be led out through a lead and connected to the circuit board under the ultrasonic fingerprint chip 101 ( Figure 1 The upper electrode 1022 is connected to the circuit board through the lead wire (not shown), so as to realize the interconnection between the upper electrode 1022 and the circuit board. In this way, the driving signal output by the circuit board can be transmitted to the piezoelectric transducer 10 through the lead wire to stimulate the piezoelectric transducer 10 to generate an ultrasonic signal for fingerprint recognition. In addition, the signal of the upper electrode 120 can also be led out to the circuit board through the lead wire.

[0057] Figure 1 The ultrasonic fingerprint chip 101 shown is a TFT, and the wiring on the surface of the TFT has a low density due to its process characteristics and cannot meet the requirements of the bonding process. Therefore, the upper electrode 1022 cannot be connected to the circuit board through a lead on the surface of the ultrasonic fingerprint chip 101, and the upper electrode 1022 can only be led out through other processes. For example, Figure 1 As shown, a TVS through hole 103 is provided on the ultrasonic fingerprint chip 101, and the TVS through hole 103 is filled with a conductive material, so that the upper electrode 1022 can be led out to the circuit board through the TVS through hole 103; or, the upper electrode 1022 can be led out to the circuit board by pressing or other methods.

[0058] If a bonding process is to be performed on the surface of the TFT to achieve connection between the upper electrode 1022 and the lead using the bonding pad on the surface of the TFT, some special treatments need to be performed on the TFT, such as gold plating on the surface of the TFT, otherwise it will cause problems such as insufficient reliability, easy aging and detachment, etc. However, gold plating and other methods increase the process complexity and cost of the ultrasonic fingerprint device 1.

[0059] To this end, an embodiment of the present application proposes an ultrasonic fingerprint device, which can use a bonding process on the surface of an ultrasonic fingerprint chip to realize the lead-out of an upper electrode, so that there is a higher connection reliability between the upper electrode and the circuit board under the ultrasonic fingerprint chip.

[0060] Figure 2 FIG. 2 shows a schematic structural diagram of an ultrasonic fingerprint device according to an embodiment of the present application. Figure 2 As shown, the ultrasonic fingerprint device 2 includes a piezoelectric transducer 10 and an ultrasonic fingerprint chip 20 .

[0061] Figure 3 for Figure 2 A schematic diagram of a possible structure of the ultrasonic fingerprint device 2 is shown in FIG. Figure 3 As shown, the piezoelectric transducer 10 is disposed above the ultrasonic fingerprint chip 20 , and the piezoelectric transducer 10 includes a piezoelectric layer 110 , an upper electrode 120 located above the piezoelectric layer 110 , and a lower electrode 130 located below the piezoelectric layer 110 .

[0062] The ultrasonic fingerprint chip 20 can be, for example, a complementary metal oxide semiconductor (CMOS) chip. The upper electrode 120 is led out from the upper surface of the piezoelectric layer 110 to the surface of the CMOS chip 20, and is connected to one end of the lead 310 through the pad 241 on the surface of the CMOS chip 20. The other end of the lead 310 is connected to the circuit board 30 under the ultrasonic fingerprint chip to achieve electrical connection between the piezoelectric transducer 10 and the circuit board 30.

[0063] The ultrasonic fingerprint chip 20 is an application specific integrated circuit (ASIC) for ultrasonic fingerprint recognition, and the embodiment of the present application adopts a CMOS chip. The ultrasonic fingerprint chip 20 can output a driving signal and load it to the upper electrode 120 and the lower electrode 130 of the piezoelectric layer 110. Under the action of the driving signal, based on the piezoelectric effect, the piezoelectric layer 110 vibrates, thereby transmitting an ultrasonic signal to the finger above the display screen. The ultrasonic signal is transmitted to the surface of the finger, and is emitted or scattered at the fingerprint valley and fingerprint ridge to return an ultrasonic detection signal. The ultrasonic detection signal is transmitted to the piezoelectric layer 110. Based on the inverse piezoelectric effect, a potential difference is generated between the electrodes on both sides of the piezoelectric layer 110, and a corresponding electrical signal is obtained. By subsequently processing the electrical signal, the fingerprint information of the finger can be obtained.

[0064] The piezoelectric layer 110 can be formed of piezoelectric materials such as PVDF or PVDF-TrFE. Since the ultrasonic fingerprint device 2 of the embodiment of the present application adopts a CMOS chip 20, the substrate 210 of the CMOS chip 20 is a silicon substrate, and wire bonding can be achieved on the silicon substrate. After the upper electrode 120 is led out to the substrate 210, the upper electrode 120 and the lead 310 can be interconnected on the substrate 210 through a bonding process, that is, the upper electrode 120 is fixed and connected to one end of the lead 310 by using the pad 241 on the surface of the ultrasonic fingerprint chip 20, and the other end of the lead 310 is connected to the circuit board 30 under the ultrasonic fingerprint chip 20, thereby realizing the interconnection between the upper electrode 120 and the circuit board 30, which is easy to implement in terms of process and has high reliability.

[0065] but, Figure 3 The ultrasonic fingerprint device 2 shown has the following problems: first, the upper electrode 120 requires a lead, that is, it is necessary to realize an electrical connection between the upper electrode 120 and the circuit board 30 under the ultrasonic fingerprint chip 20 so as to apply the driving signal to the ultrasonic transducer 10; secondly, the driving signal of the upper electrode 120 usually requires a high voltage of tens of volts. If the driving signal of the upper electrode 120 is led to the surface of the ultrasonic fingerprint chip 20, since the driving voltage of the upper electrode 120 is significantly higher than the working voltage of the circuit in the ultrasonic fingerprint chip 20, the driving signal of the upper electrode 120 is likely to interfere with the circuit in the ultrasonic fingerprint chip 20, and it is also likely to cause electrical breakdown damage to the ultrasonic fingerprint chip 20.

[0066] To this end, in one implementation, a drive line 230 may be provided on the ultrasonic fingerprint chip 20, and the upper electrode 120 is connected to the pad 241 through the drive line 230. Hereinafter, the pad 241 is also referred to as a bonding pad 241. For example, see Figures 4 to 6 The ultrasonic fingerprint chip 20 includes a substrate 210 and a plurality of metal layers arranged in a first region 201 of the substrate 210. The substrate 210 is a silicon substrate. The lower electrode 130 is located above the second region 202 of the substrate 210. The top metal layer TM of the plurality of metal layers includes N driving traces, where N=1 or N is a positive integer greater than 1. The upper electrode 120 is connected to N pads 241 through N driving traces 230, respectively, and the N pads 241 respectively connect the N driving traces 230 to their respective corresponding leads 310.

[0067] On the one hand, the density of the silver paste material of the upper electrode 120 is very low and cannot support the bonding process. In this embodiment, by setting the driving trace 230 on the ultrasonic fingerprint chip, the upper electrode 120 can be led out to the surface of the ultrasonic fingerprint chip 20 through the driving trace 230. On the other hand, due to the use of the CMOS chip, the bonding process can be implemented on the chip surface to connect the driving trace 230 to the circuit board 30 through the lead 310. In this way, the interconnection between the upper electrode 120 and the circuit board 30 is achieved.

[0068] In one implementation, Figures 4 to 6 As shown, a passivation layer 220 is disposed above the top metal layer TM, and the passivation layer 220 plays a protective role. The passivation layer 220 is provided with first openings 221 corresponding to the N driving lines 230, and the portion of each driving line 230 located in the first opening 221 is the first connection area 231 of the driving line 230. The upper electrode 120 extends from the upper surface of the piezoelectric layer 110 into the first opening 221 to connect the first connection areas 231 of the N driving lines 230 located in the first opening 221.

[0069] In this embodiment, the top metal layer TM of the ultrasonic fingerprint chip 20 includes N driving lines 230 for connecting the upper electrode 120. A first window 221 is provided on the passivation layer 220 above the top metal layer TM. The upper electrode 120 extends from the upper surface and the edge of the piezoelectric layer 110 into the first window 221 and covers the first connection area 231 of each of the N driving lines 230 located in the first window 221, thereby realizing the electrical connection between the upper electrode 120 and the N driving lines 230.

[0070] Below, as an example, combined with Figures 4 to 13 The ultrasonic fingerprint device 2 of the embodiment of the present application is described in detail. The ultrasonic fingerprint device 2 in the embodiment of the present application can be arranged under the display screen of the electronic device to realize the ultrasonic fingerprint recognition under the screen.

[0071] like Figure 4 As shown, the ultrasonic fingerprint device 2 includes a piezoelectric transducer 10 and an ultrasonic fingerprint chip 20. The piezoelectric transducer 10 is arranged above the ultrasonic fingerprint chip 20. The piezoelectric transducer 10 includes a piezoelectric layer 110, an upper electrode 120 located above the piezoelectric layer 110, and a lower electrode 130 located below the piezoelectric layer 110. The ultrasonic fingerprint chip 20 includes a substrate 210 and a plurality of metal layers arranged in a first area 201 of the substrate 210. Figure 4In the figure, multiple metal layers including a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4 and a top metal layer TM are taken as an example, and the ultrasonic fingerprint chip 20 also includes a protective layer 220 located above the multiple metal layers, such as a passivation layer 220, and the passivation layer 220 is used for protection. The lower electrode 130 is located above the second area 202 of the substrate 210.

[0072] Among them, the top metal layer TM includes a driving line 230, that is, the driving line 230 is made on the top metal layer TM. In addition, the top metal layer TM may also include other lines. One end of the driving line 230 is close to the piezoelectric layer 110, and the other end is close to the edge of the ultrasonic fingerprint chip 20. A first window 221 is provided on the passivation layer 220, and the upper electrode 120 covers the upper surface of the piezoelectric layer 110 and is filled in the first window 221, so that the upper electrode 120 is in contact with the first connection area 231 of the driving line 230 located in the first window 221.

[0073] Taking the silver paste material used for the upper electrode 120 as an example, the upper electrode 120 is formed as a silver paste pad 121 on the first connection area 231 of the driving wiring 230, thereby realizing direct interconnection between the top metal layer TM and the upper electrode 120. Specifically, the silver paste before solidification has fluidity and can extend from the upper surface of the piezoelectric layer 110 along its edge to the first window 221, so as to be formed on the upper surface of the piezoelectric layer 110 and in the first window 221 at the same time, so that the upper electrode 120 contacts the portion of the driving wiring 230 located in the first window 221. The silver paste can cross the three-dimensional structure of the piezoelectric layer 110, and through the first window 221, a silver paste pad 121 can be formed on the first connection area 231 of the driving wiring 230.

[0074] It should be understood that the upper electrode 120 extends from the upper surface of the piezoelectric layer 110 into the first window 221, which means that the upper electrode 120 extends from the upper surface of the piezoelectric layer 110 into the first window 221 and covers part or all of the space in the first window 221. Generally, in order to prevent the silver paste of the upper electrode 120 from overflowing from the first window 221, the silver paste only needs to cover part of the space in the first window 221, as long as the silver paste can contact the drive wiring 230, without filling the entire first window 221.

[0075] In one implementation, the first window 221 includes N sub-windows corresponding to the N driving lines 230 , and the first connection region 231 of each driving line 230 is located in its corresponding sub-window.

[0076] That is to say, the first window 221 can be a whole window, and the first connection areas 231 of N driving lines 230 are all located in the first window 221. The upper electrode 120 extends from the upper surface of the piezoelectric layer 110 into the first window 221 and connects the first connection areas 231 of the N driving lines in the first window 221.

[0077] Alternatively, the first window 221 may include M sub-windows, where M is a positive integer less than or equal to N. For example, when M=N, the first window 221 includes N sub-windows corresponding to the N driving wires 230, and the upper electrode 120 extends from the upper surface of the piezoelectric layer 110 into the N sub-windows to respectively connect the first connection areas 231 of the N driving wires 230 located in the corresponding sub-windows.

[0078] It should be understood that the N driving lines are divided based on the number of independent signals, and a driving line that transmits an independent signal is called a driving line, and the N driving lines transmit N independent signals respectively. However, the number of metal wires used to transmit the corresponding independent signal in each driving line can be 1 or multiple metal wires connected in parallel.

[0079] In one implementation, N second windows 222 corresponding to the N driving lines 230 are also provided on the passivation layer 220, wherein each driving line 230 is located in the second connection area 232 within its corresponding second window 222 and is connected to its corresponding lead 310 through its corresponding pad 241.

[0080] In this embodiment, in the N second openings 222, the second connection regions 232 of the N driving traces 230 are respectively connected to the corresponding N leads 310 through the N pads 241. Since the substrate of the CMOS chip 20 is a silicon substrate, a bonding process can be implemented on the substrate 210. Therefore, by providing the second openings 222, the connection between the driving traces 230 and the leads 310 can be realized by using the bonding process, so that the driving traces 230 are connected to the circuit board 30 through the leads 310.

[0081] It should be noted that the N first connection regions 231 of the N driving wires are connected via the silver paste of the upper electrode 120 , and the N second connection regions 232 of the N driving wires need to be connected to the corresponding N leads via independent N bonding pads 241 .

[0082] In the embodiment of the present application, the number N of the above-mentioned drive lines 230 can be a positive integer. For example, N=1 means that only one drive line is made on the top metal layer TM; or N=2 means that two independent drive lines 230 are made on the top metal layer TM, respectively used to transmit two independent signals; or a larger number of independent drive lines 230 can be made on the top metal layer TM.

[0083] For example, N = 1, such as Figure 5 As shown, Figure 5 for Figure 4 A top view of a possible structure of the ultrasonic fingerprint device 2 is shown, in which the number of the driving trace 230 included in the top metal layer TM is 1, a first window 221 corresponding to the driving trace 230 is provided on the passivation layer 220, and the upper electrode 120 extends from the upper surface of the piezoelectric layer 110 into the first window 221 to connect the driving trace 230 to the first connection area 231 located in the first window 221.

[0084] For another example, N=2, such as Figure 6 As shown, Figure 6 for Figure 4 A top view of another possible structure of the ultrasonic fingerprint device 2 is shown, wherein the top metal layer TM includes two drive lines, namely, a drive line 230A and a drive line 230B. The passivation layer 220 is provided with a sub-window 221A corresponding to the drive line 230A, and a sub-window 221B corresponding to the drive line 230B. The upper electrode 120 extends from the upper surface of the piezoelectric layer 110 into the sub-window 221A and the sub-window 221B to respectively connect the portion of the drive line 230A located in the sub-window 221A and the portion of the drive line 230B located in the first window 221B.

[0085] The material of the driving line 230 is usually aluminum (Al) or other metals. Aluminum is highly chemically active and forms aluminum oxide (Al2O3) in the air. After a window is opened on the passivation layer 220, the aluminum of the first connection area 231 of the driving line 230 located in the first window 221 will be exposed to the air, and an aluminum oxide film will form on its surface. Aluminum oxide is non-conductive, and this aluminum oxide film will prevent the interconnection between the silver paste and the aluminum, resulting in poor contact between the upper electrode 120 and the driving line 230. In order to eliminate the influence of the oxide layer on the first connection area 231, an anti-oxidation protective layer can be plated on the surface of the first connection area 231, or a high voltage can be applied to the driving line 230 to use the high voltage to break through the oxide layer. However, for the former, the coating process will greatly increase the cost, and for the latter, since the equivalent circuit of the piezoelectric layer 110 is a capacitor, the capacitor is equivalent to an open circuit for DC voltage, and it is impossible to determine whether the oxide layer has been broken down by measuring resistance. It can only be measured by AC signal, which is not accurate enough and cannot be judged intuitively. In addition, the applied high voltage is applied to the two ends of the oxide layer through the equivalent capacitance of the piezoelectric layer 110, resulting in the voltage actually falling on the two ends of the oxide layer being much smaller than the externally applied voltage. This requires a higher voltage to break down the oxide layer, which is not conducive to mass production.

[0086] And for Figure 6 In the case where the number of driving lines 230 is 2, the efficiency of oxide layer breakdown can be significantly improved, and the DC resistance after breakdown can be accurately detected. Figure 7 and Figure 8 Provide specific instructions. Figure 7 is the equivalent circuit diagram when the oxide layer is not broken down. Figure 8 It is the equivalent circuit diagram after the oxide layer is broken down.

[0087] like Figure 7 As shown, bonding pad 241A connected to driving trace 230A and bonding pad 241B connected to driving trace 230B are respectively connected to external voltages, for example, bonding pad 241A is connected to 5 V, bonding pad 241B is connected to GND, or bonding pad 241A is connected to GND, bonding pad 241B is connected to 5 V. 5 V here is only an example, and other voltage values ​​may also be used.

[0088] Assuming that there is an oxide layer between the portion of the driving wiring 230A in the sub-window 221A and the silver paste pad 121A of the upper electrode 120, and there is an oxide layer 2313 between the portion of the driving wiring 230B in the sub-window 221B and the silver paste pad 121B of the upper electrode 120, the oxide layer 2313 can be equivalent to Figure 7The capacitors C1 and C2 shown in the figure, in this way, the 5V voltage will be directly applied to the two ends of the oxide layer 2313, thereby directly breaking down the oxide layer 2313, and will not be blocked by the capacitors C1 and C2 of the piezoelectric layer 110. The current of the external 5V voltage is detected. When the oxide layer 2313 is broken down, the current passing through the 5V voltage will increase significantly, so that it can be accurately determined whether the oxide layer 2313 is broken down. When it is determined that the oxide layer 2313 is broken down, as shown in FIG. Figure 8 As shown, the DC resistances R1 and R2 between the bonding pad 241A and the bonding pad 241B can be measured to directly determine the breakdown effect and the interconnect impedance, thereby accurately determining the connection status between the upper electrode 120 and the driving trace 230 after the breakdown.

[0089] The above-mentioned test process only needs to use DC voltage for testing throughout the whole process, and does not require AC voltage to measure capacitance. Moreover, the test voltage is relatively much lower, which can accurately measure and monitor the interconnection resistance, will not increase the size of the ultrasonic fingerprint chip 20, reduces costs, improves test efficiency, and is conducive to mass production.

[0090] It should be understood that after testing, when applied to actual products, the bonding pad 241A and the bonding pad 241B can continue to be disconnected or short-circuited. That is, the second connection area 232 of the driving trace 230A and the second connection area 232 of the driving trace 230B can be disconnected or connected to each other, wherein when connected, the driving trace 230A and the driving trace 230B are combined into one driving trace 230.

[0091] Figure 7 and Figure 8 Take the top metal layer TM with two drive traces, that is, N = 2, as an example. When N is other values, they need to be tested in pairs. For example, when N = 3, the first drive trace and the second drive trace can be tested first, one of which is grounded and the other is powered; then the second drive trace and the third drive trace can be tested, one of which is grounded and the other is powered.

[0092] For the sake of simplicity, the following describes the positional relationship and sizes of the driving trace 230 and various metal layers by taking N=1 as an example, that is, the top metal layer TM includes one driving trace.

[0093] In one implementation, Figures 4 to 6As shown, the piezoelectric layer 110 extends above the multiple metal layers, the N driving wires 230 extend into the piezoelectric layer 110, and the first connection areas 231 of the N driving wires 230 are adjacent to the piezoelectric layer 110. When the piezoelectric layer 110 extends above the multiple metal layers and the driving wires 230 extend into the piezoelectric layer 110, the first connection areas 231 of the driving wires 230 can be close to the edge of the piezoelectric layer 110, that is, the distance between the piezoelectric layer 110 and the first connection areas 231 is minimized, so that the structure of the ultrasonic fingerprint device 2 is more compact.

[0094] In one implementation, Figure 4 As shown, the size of the first window 221 is greater than or equal to the size of the first connection area 231 of the N driving lines, and the upper electrode 120 extends from the upper surface of the piezoelectric layer to the first part 221a of the first window 221 to cover the first connection area 231 of the N driving lines 230. The second part 221b of the first window 221 is located below the piezoelectric layer 110.

[0095] It can be seen that when the size of the first window 221 is larger than the size of the first connection area 231, the upper electrode 120 extends to the first part 221a of the first window 221 to cover the first connection area 231 of the driving line 230 located in the first part 221a, and the second part 221b of the first window 221 extends into the piezoelectric layer 110 and is located below the piezoelectric layer 110, thereby improving the connection reliability between the upper electrode 120 and the driving line 230.

[0096] In one implementation, the dimension S of the first portion 221a in the direction along the driving line 230, that is, in the X direction, is greater than or equal to 150 um, for example. Figure 4 In the figure, the size S of the first window 221 is 240 um as an example. The size g of the second portion 221 b along the driving line 230 is, for example, greater than or equal to 20 um.

[0097] Since the voltage of the driving signal of the upper electrode 120 is usually high, significantly higher than the working voltage of the circuit in the ultrasonic fingerprint chip 20, it is not only easy to interfere with the circuit in the ultrasonic fingerprint chip 20, but also easy to cause electrical breakdown damage to the ultrasonic fingerprint chip 20. Therefore, in one implementation, other wirings adjacent to the N driving wirings 230 on the top metal layer TM should maintain a distance from the N driving wirings 230. For example, the distance between other wirings adjacent to the driving wirings 230 on the top metal layer TM and the driving wirings 230 is greater than or equal to 10um, so as to avoid the same-layer breakdown, ensure the safety of the ultrasonic fingerprint device 2, and prevent the driving wiring 230 from interfering with other wirings on the top metal layer TM.

[0098] Fig. 9 for Figure 4 The schematic diagram of a top view of a local area of ​​the ultrasonic fingerprint device 2 is shown. Fig. 9 As an example, only one driving line is shown, and the distance f between the driving line 230 and other lines on the top metal layer TM is 10 um.

[0099] In the embodiment of the present application, since the driving trace 230 is electrically connected to the silver paste pad 121 , the distance between any metal layer and the driving trace 230 described herein refers to the distance between the metal layer and the edge of the silver paste pad 121 . Fig. 9 In the example, the silver paste pad 121 is rectangular and has a size of 240um×200um. The size of the first connection area 231 of the driving line 230 in the Y direction can be considered as the size corresponding to the silver paste pad 121. The size of the driving line 230 in the Y direction is Fig. 9 The 200 um dashed line in FIG. 2 shows the distance between each metal layer and the driving wiring 230 , which refers to the distance between the metal layer and the dashed line, that is, the distance between the metal layer and the edge of the silver paste pad 121 .

[0100] In one implementation, other wirings on the top metal layer TM adjacent to the N driving wirings 230 are grounded. Thus, the top metal layer TM shields the N driving wirings 230, thereby preventing the N driving wirings 230 from interfering with other wirings on the top metal layer TM. Fig. 9 As shown, Fig. 9 Only other traces on the top metal layer TM located on the right side of the driving trace 230 are shown, and other traces on the top metal layer TM adjacent to the driving trace 230 are grounded. Similarly, the top metal layer TM located on the upper side and left side of the driving trace 230 (not shown) is also grounded.

[0101] In one implementation, Figures 4 to 9 As shown, holes are dug in the areas corresponding to the N driving traces 230 on the first metal layer M1 among the multiple metal layers, and the first metal layer M1 is an adjacent metal layer located below the top metal layer TM.

[0102] Since the first metal layer M1 is an adjacent metal layer located below the top metal layer TM, by digging holes in the corresponding areas below the N driving lines 230, the electrical gap between the N driving lines 230 and other lines of the first metal layer M1 is increased, thereby increasing the compressive strength of the first metal layer M1 and avoiding interlayer breakdown between the top metal layer TM and the first metal layer M1.

[0103] In order to further increase the electrical clearance between the driving trace 230 and other traces of the first metal layer M1 and to avoid interlayer breakdown between the top metal layer TM and the first metal layer M1 to the greatest extent possible, in one implementation, as Figures 4 to 9 As shown, the area on the first metal layer M1 corresponding to the N driving lines 230 and the area extending around the area by a distance greater than or equal to a=12 um are dug. In other words, the dug area is extended from the area corresponding to the N driving lines 230 to the surrounding area by a certain distance a.

[0104] In one implementation, Figures 4 to 9 As shown, the region corresponding to the driving wiring 230 on the second metal layer M2 among the multiple metal layers is grounded, and the second metal layer M2 is an adjacent metal layer located below the first metal layer M1.

[0105] Since the second metal layer M2 is an adjacent metal layer located below the first metal layer M1, by grounding the corresponding area below the N driving wires 230, the second metal layer M2 shields the driving wires 230, thereby preventing other wires of the second metal layer M2 from interfering with the wires of the third metal layer M3 located below it. In this way, the wires of the third metal layer M3 and the fourth metal layer M4 can be freely selected.

[0106] In order to further enhance the shielding effect of the second metal layer M2 on the driving wiring 230 and minimize the interference of other wirings of the second metal layer M2 on the wirings of the third metal layer M3 located thereunder, in one implementation, the area on the second metal layer M2 corresponding to the N driving wirings 230 and the area extending around the area by more than or equal to 12 um are grounded. For example, Figures 4 to 9 As shown, the second metal layer M2 is located below the driving wiring 230 and extends to a grounded area around it by a distance a, so as to reduce interference of other wirings on the second metal layer M2 with the wirings on the third metal layer M3 below it.

[0107] Typically, the lower electrode 130 is an electrode array composed of a plurality of electrodes, each electrode in the electrode array corresponds to a pixel in the fingerprint image, and thus the electrode array below the piezoelectric layer 110 can be regarded as a pixel array.

[0108] In order to prevent the high voltage of the driving line 230 from causing electrical breakdown and interference to the metal layer in the ultrasonic fingerprint chip 20, in one implementation, as Figures 4 to 6As shown, a pad for grounding, namely, a GND pad 242, is provided on the top metal layer TM, and the GND pad 242 is located beside the second connection area 232 of the N driving lines 230. The GND pad 242 is provided beside the bonding pad 241 of the N driving lines 230, and there is a certain distance between the GND pad 242 and the bonding pad 241, so as to avoid the driving signal transmitted on the driving line 230 from interfering with other surrounding signals.

[0109] Fig.10 yes Figure 5 A cross-sectional view of region A in FIG. 1 along a direction perpendicular to the edge of the piezoelectric transducer 10. In one implementation, as Fig.10 As shown, the distance e between the lower electrode 130 and the passivation layer 220 around the lower electrode 130 is greater than or equal to 100 um. In another implementation, as Fig.10 As shown, other traces on the top metal layer TM adjacent to the bottom electrode 130 are grounded.

[0110] There is a certain distance between the lower electrode 130 and the passivation layer 220 around the lower electrode 130, and / or other traces on the top metal layer TM adjacent to the lower electrode 130 are grounded, which can play a shielding role and prevent external interference from affecting the pixels near the edge of the array of the lower electrode 130.

[0111] At the same time, if Fig.10 As shown, for the pixels on the left edge, since a distance e is reserved for opening windows in the passivation layer 220, there are also metal lines on the left side of the edge pixels, and the metal lines on the left are balanced with the electrodes on the right side, as if these edge pixels are also like central pixels, thereby reducing the edge effect of the edge pixels and improving the consistency between the edge pixels and the central pixels.

[0112] In one implementation, Fig.10 As shown, the distance c1 between the edge of the upper electrode 120 and the edge of the piezoelectric layer 110 is greater than or equal to 50 um, thereby preventing the upper electrode 120 from overflowing to the surface of the ultrasonic fingerprint chip 20 and avoiding the risk of breakdown.

[0113] In addition, if Fig.10 As shown, the edge of the passivation layer 220 exceeds the edge of the piezoelectric layer 110 by a distance c2, for example greater than or equal to 20 um; and / or the edge of the substrate 210 exceeds the edge of the passivation layer 220 by a distance c3, for example greater than or equal to 10 um.

[0114] In one implementation, N=1, and the area of ​​the first window 221 near the piezoelectric layer 110 is larger than the area of ​​the first window 221 away from the piezoelectric layer 110, thereby improving the connection reliability between the upper electrode 120 and the driving wiring.

[0115] For example, Figures 11 to 13 The shape and size of the first window 221 in some implementations of the present application are shown. Fig.11 As shown, the shape of the first window 221 is a trapezoid, wherein the lower base of the trapezoid is closer to the piezoelectric layer 110 than the upper base thereof; for another example, Fig.12 and Fig.13 As shown, the first window 221 is L-shaped, which is composed of a first part 2311 parallel to the direction of the driving line 230 and a second part 2312 perpendicular to the direction of the driving line 230. The second part 2312 is closer to the piezoelectric layer 110 than the first part 2311.

[0116] Fig.13 Shows Fig.12 Some possible sizes of the L-shaped first window 221 in the embodiment, the size of the L-shaped portion close to the piezoelectric layer 110 in the Y direction is larger than the size of the L-shaped portion away from the piezoelectric layer 110 in the Y direction, so as to improve the connection reliability between the upper electrode 120 and the first connection area 231 of the drive wiring 230 without occupying additional area. Wherein, L1, L2 and L3 respectively represent the edge of the piezoelectric layer 110, the edge of the insulating protective layer (over coating) on ​​the surface of the upper electrode 120, and the edge (die edge) of the ultrasonic fingerprint chip 20. The silver paste pad 121 fills a part of the area within the L-shaped first window 221 and covers the first connection area 231 of the drive wiring 230, wherein, Fig.13 As an example only, k1 is the size of the silver paste pad 121, k1=204um, the sizes of the L-shape are: k2=100um, k3=404um, k4=20um, k5=244.5um, k6=100um, k7=215um, k8=100um, k9 is determined according to k7, which can be 1000um here.

[0117] It should be understood that Figures 4 to 13 For various parameters not specifically described herein, the range may be considered to be ±50% of the values ​​shown.

[0118] like Fig.14 As shown, the present application also provides an electronic device 3, which includes a display screen 4 and the above-mentioned ultrasonic fingerprint device 2. The ultrasonic fingerprint chip 20 is bonded to the display screen 4 by an adhesive film 301, so that the ultrasonic fingerprint device 2 is located below the display screen 4, thereby realizing under-screen ultrasonic fingerprint recognition.

[0119] As an example but not limitation, the electronic device in the embodiment of the present application can be a portable or mobile computing device such as a terminal device, a mobile phone, a tablet computer, a laptop computer, a desktop computer, a gaming device, an in-vehicle electronic device or a wearable smart device, as well as other electronic devices such as an electronic database, a car, and an automated teller machine (ATM). The wearable smart device includes a device with full functions and large size that can realize full or partial functions without relying on a smart phone, such as a smart watch or smart glasses, and includes a device that only focuses on a certain type of application function and needs to be used in conjunction with other devices such as a smart phone, such as various types of smart bracelets and smart jewelry for vital sign monitoring.

[0120] It should be noted that, under the premise of no conflict, the various embodiments described in this application and / or the technical features in each embodiment can be arbitrarily combined with each other, and the technical solution obtained after the combination should also fall within the protection scope of this application.

[0121] The systems, devices and methods disclosed in the embodiments of the present application may be implemented in other ways. For example, some features of the method embodiments described above may be ignored or not performed. The device embodiments described above are merely schematic, and the division of units is merely a logical function division. There may be other division methods in actual implementation, and multiple units or components may be combined or integrated into another system. In addition, the coupling between the units or the coupling between the components may be direct coupling or indirect coupling, and the coupling may include electrical, mechanical or other forms of connection.

[0122] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described devices and equipment and the technical effects produced can refer to the corresponding processes and technical effects in the aforementioned method embodiments, and will not be repeated here.

[0123] It should be understood that the specific examples in the embodiments of the present application are only to help those skilled in the art to better understand the embodiments of the present application, rather than to limit the scope of the embodiments of the present application. Those skilled in the art can make various improvements and modifications based on the above embodiments, and these improvements or modifications all fall within the scope of protection of the present application.

[0124] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An ultrasonic fingerprint device, characterized in that: The ultrasonic fingerprint device is arranged under the display screen of the electronic device to realize the under-screen ultrasonic fingerprint recognition, and the ultrasonic fingerprint device includes an ultrasonic fingerprint chip and a piezoelectric transducer arranged above the ultrasonic fingerprint chip; The piezoelectric transducer comprises a piezoelectric layer, an upper electrode located above the piezoelectric layer, and a lower electrode located below the piezoelectric layer, wherein a distance between an edge of the upper electrode and an edge of the piezoelectric layer is greater than or equal to 50 um; The ultrasonic fingerprint chip is a complementary metal oxide semiconductor (CMOS) chip, the upper electrode is led out from the upper surface of the piezoelectric layer to the surface of the CMOS chip, and is connected to one end of the lead through a pad on the surface of the CMOS chip, and the other end of the lead is connected to a circuit board under the ultrasonic fingerprint chip to achieve electrical connection between the piezoelectric transducer and the circuit board, and the ultrasonic fingerprint chip is used to output a driving signal and load it to the upper electrode and the lower electrode of the piezoelectric layer, so that the piezoelectric layer vibrates and transmits an ultrasonic signal to the finger above the display screen; The ultrasonic fingerprint chip includes a substrate and multiple metal layers arranged in a first area of ​​the substrate, the substrate is a silicon substrate, the lower electrode is located above the second area of ​​the substrate, the top metal layer among the multiple metal layers includes N driving traces, N=1 or N is a positive integer greater than 1, the upper electrode is respectively connected to N pads through the N driving traces, the N pads respectively connect the N driving traces to their respective corresponding leads, and the other traces adjacent to the N driving traces in the top metal layer are greater than or equal to 10um from the N driving traces.

2. The ultrasonic fingerprint device according to claim 1, characterized in that: A passivation layer is arranged above the top metal layer, and a first window corresponding to the N driving lines is arranged on the passivation layer. The upper electrode extends from the upper surface of the piezoelectric layer into the first window to connect the first connection areas of each of the N driving lines located in the first window.

3. The ultrasonic fingerprint device according to claim 2, characterized in that: The first window includes N sub-windows corresponding to the N driving lines, and the first connection area of ​​each driving line is located in its corresponding sub-window.

4. The ultrasonic fingerprint device according to claim 2 or 3, characterized in that: The passivation layer is also provided with N second windows corresponding to the N driving lines, wherein each driving line is located in a second connection area within its corresponding second window and is connected to its corresponding lead through its corresponding pad.

5. The ultrasonic fingerprint device according to claim 2 or 3, characterized in that: The piezoelectric layer extends above the multiple metal layers, the N driving wires extend into the piezoelectric layer, and the first connection areas of the N driving wires are adjacent to the piezoelectric layer.

6. The ultrasonic fingerprint device according to claim 5, characterized in that: The size of the first window is larger than the size of the first connection area of ​​the N driving lines, the upper electrode extends from the upper surface of the piezoelectric layer to the first part of the first window to cover the first connection area of ​​the N driving lines, and the second part of the first window is located below the piezoelectric layer.

7. The ultrasonic fingerprint device according to claim 6, characterized in that: The size of the first portion in the direction of the N driving lines is greater than or equal to 150 um; and / or the size of the second portion in the direction of the N driving lines is greater than or equal to 20 um.

8. The ultrasonic fingerprint device according to any one of claims 1 to 3, characterized in that: Other traces on the top metal layer adjacent to the N driving traces are grounded.

9. The ultrasonic fingerprint device according to any one of claims 1 to 3, characterized in that: Holes are dug in areas corresponding to the N driving traces on a first metal layer among the multiple metal layers, and the first metal layer is an adjacent metal layer located below the top metal layer.

10. The ultrasonic fingerprint device according to claim 9, characterized in that: Holes are dug in the area on the first metal layer corresponding to the N driving wires and in the area extending around the area by more than or equal to 12 um.

11. The ultrasonic fingerprint device according to any one of claims 1 to 3, characterized in that: An area on a second metal layer among the multiple metal layers corresponding to the N driving traces is grounded, and the second metal layer is an adjacent metal layer located below the first metal layer.

12. The ultrasonic fingerprint device according to claim 11, characterized in that: The area on the second metal layer corresponding to the N driving wires and the area extending around the area by more than or equal to 12 um are grounded.

13. The ultrasonic fingerprint device according to claim 4, characterized in that: A pad for grounding is disposed on the top metal layer, and the pad is disposed beside the second connection region of the N driving traces.

14. The ultrasonic fingerprint device according to any one of claims 1 to 3, characterized in that: The distance between the lower electrode and the passivation layer surrounding the lower electrode is greater than or equal to 100 um; and / or other traces in the top metal layer adjacent to the lower electrode are grounded.

15. The ultrasonic fingerprint device according to claim 2 or 3, characterized in that: N=1, the area of ​​the first window at a portion close to the piezoelectric layer is larger than the area of ​​the portion far from the piezoelectric layer.

16. The ultrasonic fingerprint device according to claim 15, characterized in that: The shape of the first window is a trapezoid, and the lower base of the trapezoid is closer to the piezoelectric layer than the upper base thereof.

17. The ultrasonic fingerprint device according to claim 15, characterized in that: The first window has an L-shape, which is composed of a first portion parallel to the direction of the driving line and a second portion perpendicular to the direction of the driving line, and the second portion is closer to the piezoelectric layer than the first portion.

18. An electronic device, characterized in that: include: Display screen; as well as, According to any one of claims 1 to 17, the ultrasonic fingerprint device is arranged below the display screen to realize under-screen ultrasonic fingerprint recognition.

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