General grid-connected inverter direct digital correction design method, device and storage medium

Abstract

The present application discloses a direct digital correction design method, device and storage medium for a general-purpose grid-connected inverter. The direct digital correction design method for the general-purpose grid-connected inverter of the present application includes: calculating the open-loop cut-off frequency ω of the inverter control system to be corrected cg and the phase margin γ; setting the desired cut-off frequency ω cg‑exp and the desired phase margin γ exp , and determining the phase angle deficit φ ad ; arranging the poles p c and zeros z c of the lead compensator on the positive real axis within the unit circle of the z-plane, and z c > p c , and making p c and z c respectively point to the marked point with the polar coordinates of exp(jω cg‑exp T), and the included angle of the phasors is equal to the phase angle deficit φ ad ; calculating the correction factor K for the open-loop gain of the compensator according to the preset requirements gc ; selecting a preset recommended configuration scheme according to different control performance index requirements; and obtaining the difference equation. The present application is applicable to the field of power electronics control, and is particularly applicable to the power quality regulation and stability improvement of power electronic interface devices in smart grids.

Description

Technical Field

[0001] This application relates to the field of general-purpose grid-connected inverters, and in particular to a direct digital correction design method, device, and storage medium for general-purpose grid-connected inverters. Background Art

[0002] With the continuous development of computer control technology, control systems are increasingly abandoning traditional analog control and adopting more flexible and convenient digital control; however, digital control systems have problems such as zero-order hold discretization error, insufficient sampling accuracy, and inherent digital control delay, which will degrade the system stability index, so it is difficult to achieve the same effect as the original analog control. Therefore, it is necessary to correct the digital control system. In engineering practice, the phase margin is often used as the index to be corrected for digital control systems, but the existing correction methods have the following two deficiencies. On the one hand, s-domain correction requires Padé approximation of the 1.5-beat delay link, so it is difficult to accurately compensate the phase margin. On the other hand, w-domain lead (lag) design improves the phase margin by raising (lowering) the system cut-off frequency; however, lead correction causes the high-frequency shift of the system cut-off frequency, which in turn causes phase angle loss; lag correction uses the limited phase reserve of the system itself to achieve the compensation purpose. If the system itself has insufficient phase reserve, the desired compensation effect may not be achieved; obviously, the above lead (lag) correction designs all have certain limitations and are difficult to achieve the desired compensated phase margin.

[0003] Therefore, the above technical problems existing in the related technologies need to be solved urgently. Summary of the Invention

[0004] This application aims to solve one of the technical problems in the related technologies. To this end, the embodiments of this application provide a direct digital correction design method, device, and storage medium for general-purpose grid-connected inverters, which can accurately compensate the specified phase margin at relatively arbitrary cut-off frequencies.

[0005] According to one aspect of the embodiments of this application, a direct digital correction design method for a general-purpose grid-connected inverter is provided, and the method includes:

[0006] Calculating the open-loop cut-off frequency ω cg and phase margin γ of the inverter control system to be corrected;

[0007] Setting the desired cut-off frequency ω cg-exp and desired phase margin γ exp , and determining the phase angle deficit φ ad ;

[0008] Configuring the poles p c , zeros z c of the lead compensator on the positive real axis within the unit circle of the z-plane, and z c > p c, and make p c and z c respectively point to the marked points with polar coordinates exp(jω cg-exp T), and the included angle of the phasors is equal to the phase angle deficit φ ad ;

[0009] Calculate the corrector open-loop gain correction coefficient K according to the preset requirements gc ;

[0010] Select the preset recommended configuration scheme according to the requirements of different control performance indicators;

[0011] Obtain the difference equation.

[0012] In one embodiment, the open-loop cut-off frequency ω cg The calculation formula is:

[0013]

[0014] Wherein, G sys (z) is the open-loop transfer function of the inverter control system, and T is the sampling time.

[0015] In one embodiment, the phase angle deficit φ ad The calculation formula is:

[0016]

[0017] Wherein, γ exp is the desired phase margin, G sys is the open-loop transfer function of the inverter control system, and ω cg-exp is the set desired cut-off frequency.

[0018] In one embodiment, the determination method of the relative position of the pole p c and the zero point z c on the real axis includes:

[0019] Make p c and z c respectively point to the marked points with polar coordinates exp(jω cg-exp T), and the included angle of the phasors is equal to the phase angle deficit φ ad .

[0020] In one embodiment, the relative position relationship between z c and p c on the real axis is:

[0021] z c > p c

[0022] z c and pc The included angle relationship between two phasors pointing to the marked point with polar coordinates exp(jω cg-exp T) is as follows:

[0023] φ zc -φ pc = φ ad

[0024] z c The calculation formula for the relative position on the real axis is:

[0025]

[0026] p c The calculation formula for the relative position on the real axis is:

[0027]

[0028] where ω cg-exp is the set desired open-loop cut-off frequency, T is the sampling time, and φ pc is the argument of the pole p c pointing to the marked point in the z-plane, and φ zc is the argument of the pole z c pointing to the marked point in the z-plane.

[0029] In one embodiment, the corrector open-loop gain correction coefficient K gc is calculated as follows:

[0030]

[0031] In one embodiment, G C (z) is the corrector transfer function, and there is the following formula:

[0032]

[0033] In one embodiment, the preset recommended configuration scheme includes a first recommended configuration scheme and a second recommended configuration scheme;

[0034] The first recommended configuration scheme is: configure p c at the origin, i.e., p c = 0;

[0035] The second recommended configuration scheme is: configure p c as:

[0036]

[0037]

[0038] where p wis the pole of the w-domain lead compensator.

[0039] According to one aspect of the embodiments of the present application, there is provided a general-purpose grid-connected inverter direct digital correction design device, the device includes:

[0040] A first module, configured to calculate the open-loop cut-off frequency ω cg and phase margin γ of the inverter control system to be corrected;

[0041] A second module, configured to set the desired cut-off frequency ω cg-exp and desired phase margin γ exp , and determine the phase angle deficit φ ad ;

[0042] A third module, configured to arrange the pole p c , zero z c on the positive real axis within the unit circle of the z-plane, and z c > p c , and make p c and z c respectively point to the marked point with polar coordinates of exp(jω cg-exp T), and the included angle of the phasors is equal to the phase angle deficit φ ad ;

[0043] A fourth module, configured to calculate the corrector open-loop gain correction factor K gc according to preset requirements;

[0044] A fifth module, configured to select a preset recommended configuration scheme according to different control performance index requirements;

[0045] A sixth module, configured to obtain the difference equation.

[0046] According to one aspect of the embodiments of the present application, there is provided a general-purpose grid-connected inverter direct digital correction design device, the device includes:

[0047] At least one processor;

[0048] At least one memory, the memory is used to store at least one program;

[0049] When at least one of the programs is executed by at least one of the processors, the general-purpose grid-connected inverter direct digital correction design method described in the previous embodiments is implemented.

[0050] According to one aspect of the embodiments of the present application, there is provided a storage medium, the storage medium stores a program executable by a processor, and when the program executable by the processor is executed by the processor, the general-purpose grid-connected inverter direct digital correction design method described in the previous embodiments is implemented.

[0051] The beneficial effects of the general grid-connected inverter direct digital correction design method, device, and storage medium provided by the embodiments of the present application are as follows: 1) It can accurately compensate the phase margin of the control system under relatively arbitrarily specified open-loop cut-off frequency conditions; 2) The corrector design method is only carried out in the z-domain, without the complex domain transformation between the z-domain and the w-domain, and without approximately linearizing the calculation delay link and zero-order hold link containing e sT ; 3) The design process is simple and clear. In particular, it avoids the trial and error of corrector parameters, greatly reducing the design burden on engineers.

[0052] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0054] Figure 1 is a flowchart of the general grid-connected inverter direct digital correction design method provided by the embodiments of the present application;

[0055] Figure 2 is the structure and control block diagram of the general grid-connected inverter provided by the embodiments of the present application;

[0056] Figure 3 is the schematic diagram of the pole p c and zero point z c configuration provided by the embodiments of the present application;

[0057] Figure 4 is the schematic diagram of the general grid-connected inverter direct digital correction design device provided by the embodiments of the present application;

[0058] Figure 5 is the schematic diagram of another general grid-connected inverter direct digital correction design device provided by the embodiments of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0059] In order to enable those skilled in the art to better understand the solutions of the present application, the following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0060] The terms "first", "second", "third", "fourth", etc. in the description, claims and drawings of this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0061] Referring to "embodiment" herein means that a specific feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of this application. The phrase appears in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0062] With the continuous development of computer control technology, control systems are increasingly abandoning traditional analog control and adopting more flexible and convenient digital control; however, digital control systems have problems such as discretization error of the zero-order hold, insufficient sampling accuracy, and inherent delay of digital control, which will degrade the system stability index, so it is difficult to achieve the same effect as the original analog control. Therefore, it is necessary to correct the digital control system. In engineering practice, the phase margin is often used as the index to be corrected for digital control systems, but the existing correction methods have the following two deficiencies. On the one hand, s-domain correction requires Pade approximation of the 1.5-beat delay link, so it is difficult to accurately compensate the phase margin. On the other hand, w-domain lead (lag) design improves the phase margin by raising (lowering) the system cut-off frequency; however, lead correction causes high-frequency offset of the system cut-off frequency, which in turn causes phase angle loss; lag correction uses the limited phase reserve of the system itself to achieve the compensation purpose. If the system itself has insufficient phase reserve, the desired compensation effect may not be achieved; obviously, the above lead (lag) correction designs all have certain limitations and are difficult to achieve the desired compensated phase margin.

[0063] To solve the above problems, this application proposes a direct digital correction design method for a general-purpose grid-connected inverter, which can accurately compensate a specified phase margin at relatively arbitrary cut-off frequencies. The present invention is applicable to the field of power electronic control, and particularly applicable to the power quality regulation and stability improvement of power electronic interface devices in smart grids.

[0064] Figure 1 It is a flowchart of the direct digital correction design method for a general-purpose grid-connected inverter provided in an embodiment of this application. As Figure 1As shown in the figure, the general grid-connected inverter direct digital correction design method proposed in this application includes:

[0065] S101. Calculate the open-loop cut-off frequency ω cg and phase margin γ of the inverter control system to be corrected.

[0066] The open-loop cut-off frequency ω cg in step S101 is calculated by the formula:

[0067]

[0068] where G sys (z) is the open-loop transfer function of the inverter control system, and T is the sampling time.

[0069] S102. Set the desired cut-off frequency ω cg-exp and the desired phase margin γ exp , and determine the phase angle deficit φ ad .

[0070] Specifically, the phase angle deficit φ ad in step S102 is calculated by the formula:

[0071]

[0072] where γ exp is the desired phase margin, G sys is the open-loop transfer function of the inverter control system, and ω cg-exp is the set desired cut-off frequency.

[0073] S103. Configure the lead compensator poles p c , zeros z c inside the unit circle on the positive real axis of the z-plane, and z c > p c , and make p c and z c point to the marked point with polar coordinates exp(jω cg-exp T) respectively, and the included angle of the phasors is equal to the phase angle deficit

[0074] S104. Calculate the corrector open-loop gain correction factor K gc according to the preset requirements.

[0075] The corrector open-loop gain correction factor K gc in this embodiment is calculated by the formula:

[0076]

[0077] In this embodiment, G C(z) is the corrector transfer function, and has the following formula:

[0078]

[0079] S105. Select a preset recommended configuration scheme according to different control performance index requirements.

[0080] Specifically, the preset recommended configuration scheme in step S105 includes a first recommended configuration scheme and a second recommended configuration scheme; the first recommended configuration scheme is: configure p c at the origin, that is, p c = 0; the second recommended configuration scheme is: configure p c as:

[0081]

[0082]

[0083] where p w is the pole of the w-domain lead corrector.

[0084] S106. Obtain the difference equation.

[0085] Figure 2 This is the structure and control block diagram of the general grid-connected inverter provided by the embodiment of the present application. The subscript abc refers to the three phases a, b, and c. For the sake of simplicity of writing and the same control law for each phase, the subscript abc is omitted in the remaining text of the specification. In Figure 2 , the phase-locked loop samples the grid-side voltage u g , writes an algorithm to obtain the voltage phase, and these phases (ω n t, ω n t ± 2π / 3) are synthesized with the reference current amplitude I m to obtain the reference current i ref . The grid-connected inverter generally adopts a current control method, so the grid-connected current i g is sampled, and a closed-loop control method is designed; e is the grid-connected current tracking error, and its value is: e = i ref -i g , and e is sent as an input signal to the proportional quasi-resonant controller module G PQR (z) to obtain the controller output u c ; to avoid multiple intersections of the carrier wave and the modulation wave, the modulation signal is updated one beat later, that is, corresponding to the z –1 module; pulse width modulation adopts the symmetric regular sampling method to obtain a pulse sequence signal to control the on and off of the insulated gate bipolar transistor (IGBT). In addition: u dc represents the DC-side voltage of the inverter, u inv represents the inverter-side voltage, and L represents the output filter inductor.

[0086] Optionally, the pole p c and the zero z c The method for determining the relative positions on the real axis includes: making p c and z c respectively point to the marked point with polar coordinates exp(jω cg-exp T), and the included angle of the phasors is equal to the phase angle deficit φ ad . Figure 3 This is a schematic diagram of the configuration of the pole p c and the zero z c provided by the embodiment of the present application. As Figure 3 shown, the pole p c and the zero z c of the lead compensator are configured on the positive real axis within the unit circle in the z-plane, and it should be that z c > p c ; and from p c and z c to the vector pointing to the marked point [with polar coordinates exp(jω cg- exp T)] The included angle is exactly equal to φ ad . It should be noted that if the pole p c is configured on the negative real axis within the unit circle, there will be serious high-frequency oscillations in the controller output; if the pole is configured on a non-real axis within the unit circle, that is, the coefficient of z in the transfer function of the compensator contains an imaginary part, it is difficult to implement programmatically.

[0087] From Figure 3 , it is easy to know by using elementary trigonometric function relationships: the relative position constraint relationship between p c and z c , the relative position relationship between z c and p c on the real axis is:

[0088] z c > p c

[0089] z c and p c point to the marked point with polar coordinates exp(jω cg-exp T) The included angle relationship of the two phasors is:

[0090] φ zc -φ pc = φ ad

[0091] z c The calculation formula for the relative position of z on the real axis is:

[0092]

[0093] Correspondingly, p c The calculation formula for the relative position on the real axis is:

[0094]

[0095] where ω cg-exp is the set desired open-loop cut-off frequency, T is the sampling time, and φ pc is the argument of the pole p c pointing to the marked point in the z-plane, and φ zc is the argument of the pole z c pointing to the marked point in the z-plane.

[0096] In the above formula, φ zc and φ pc are respectively the vector angles of z c and p c pointing to the marked point of the desired open-loop cut-off frequency, and there is φ pc + φ ad = φ zc . If p c is configured first, then φ pc and φ zc can be determined. Subsequently, the position of z c is determined by the calculation formula of z c , and vice versa.

[0097] It should be noted that there are infinitely many configuration schemes for the zero and pole of the corrector determined by the calculation formulas of p c and z c . For example, with ω cg-exp = 5087.7 rad / s and γ exp = 60° as the performance requirements of the control system, then φ ad = 19.65° can be determined; then, combining the calculation formulas of p c and z c shows that: the allowable configuration range of the corrector zero z c is [0.4471, 1], and the corresponding allowable configuration range of the pole p c is [0, 0.8300]. Therefore, when the pole p c moves from 0 to 0.8300 along the positive real axis in the z-plane, there is a corresponding z c in the range of [0.4471, 1]. Those skilled in the art know that in the direct digital correction method, there are infinitely many configuration schemes for the zero and pole of the corrector, which will not be elaborated in this application.

[0098] This specification takes a 6.6 kW grid-connected inverter as an object and describes the design steps and principles of the described correction method. Note: In the case of this specification, the resonant frequency ω nA proportional quasi-resonant (PQR) controller with a frequency of 100π rad / s is used to accurately track the 50 Hz power frequency signal; however, it is not limited to this. Harmonic compensation can be achieved by changing the resonant frequency of the controller, and it can be widely applied to active power filters. The "general inverter structure" can refer to the L-type and LCL-type output filtering forms; current control can refer to: proportional quasi-resonant (PQR) control, proportional resonant (PR) control, proportional integral derivative (PID) control, and deadbeat control. This specification only takes the inverter with the L-type output filtering form and PQR control as an example to elaborate on the steps of the protected direct digital correction method, and should not be construed as a limitation of the present invention.

[0099] Table 1 Electrical and control parameters of the inverter example

[0100]

[0101] Through Figure 2 It is easy to obtain that the open-loop transfer function of the grid-connected inverter control system is:

[0102]

[0103]

[0104]

[0105] In the formula: G PQR (z) is the result of discretizing the proportional quasi-resonant controller G PQR (s).

[0106] It should be noted that: there are 7 typical methods in engineering that can be used for the discretization of G PQR (s) to G PQR (z); this specification only takes the bilinear transformation method as a design example to explain the present invention, and should not be construed as a limitation of the present invention. The 7 typical discretization methods in engineering refer to: pre-warped bilinear transformation method, bilinear transformation method, zero-pole matching method, impulse response invariance method, step response invariance method, backward difference method, and forward difference method.

[0107] After discretizing G PQR (s) using the bilinear transformation method, the coefficient expressions in G PQR (z) are respectively:

[0108] h3 = 1, h4 = 0, h5 = -1.

[0109] Substitute the electrical and control parameters of the inverter example in Table 1 into the calculation formula G sys (z); based on as the basis, the cut-off frequency ω of the system can be calculated respectivelycg and phase margin γ, specifically: ω cg = 4740.8 rad / s, γ = 42.87°.

[0110] To verify the feasibility of the technical solution of this application, this application verifies the first recommended configuration plan and the second recommended configuration plan. The verification process is as follows:

[0111] (1) Based on the unit step response of the inverter control system, verify the rationality of the first recommended configuration plan.

[0112] In the case of this specification, with ω cg-exp = 5087.7 rad / s, γ exp = 60° as the performance requirements of the control system, then it can be determined that Then: the zero point z of the corrector c The allowable configuration range is [0.4471, 1], corresponding to the pole p c The allowable configuration range is [0, 0.8300]. To compare the performance differences between the first recommended configuration plan (z c = 0.4471, p c = 0) and other non-recommended configuration plans, 8 zeros to be configured can be evenly inserted at intervals within the range of z c = [0.4471, 1]; then, the above 10 corrector zero-pole configuration orientations and open-loop gain correction coefficients are shown in Table 2.

[0113] Table 2 Corrector zero-pole configuration orientations and open-loop gain correction coefficients

[0114]

[0115] Furthermore, analyze the unit step response of the closed-loop transfer function under the above 10 configuration plans. The analysis shows that: when the corrector pole p c moves along the positive direction of the real axis, the peak time of the corresponding step response extends; specifically: the peak moments of the step responses of configurations 1, 2, and 3 are the 3rd beat, and the peak moments of the remaining configurations are all the 4th beat; when the corrector pole changes from configuration 1 to configuration 10 in sequence, the corresponding adjustment time continuously extends; specifically, the adjustment times from configuration 1 to configuration 10 are: 7.79 ms, 8.09 ms, 8.42 ms, 8.80 ms, 9.25 ms, 9.82 ms, 10.61 ms, 11.86 ms, 14.60 ms, ∞ ms.

[0116] Therefore, adopting configuration 1 (the first recommended configuration plan) can make the system have the shortest peak time and adjustment time, that is, adopting this plan can make the system have the best dynamic performance.

[0117] (2) Based on the steady-state accuracy of the system and the high-frequency attenuation characteristics, verify the rationality of the second recommended configuration scheme (z c = 0.46903, p c = 0.4609, K gc = 1.3156).

[0118] To avoid redundancy, only compare and analyze Configuration 1 (the first recommended configuration scheme), the second recommended configuration scheme, and Configuration 9; map these three configuration schemes to the w-domain and analyze the amplitude-frequency characteristics of the corrector and the corrected system respectively.

[0119] After calculation: The turning frequency ratios α (the ratio of the pole turning frequency to the zero turning frequency) corresponding to the first recommended configuration scheme, the second recommended configuration scheme, and Configuration 9 are: 2.61, 2.01, 4.11; the second recommended configuration scheme performs phase compensation at the geometric midpoint of the w-domain frequency characteristic of the corrector, and the corresponding turning frequency ratio α is the smallest, that is: making the vertical distance between the low-frequency segment and the high-frequency segment of the corrector the shortest (this distance is 20lgα); therefore, it is speculated that the second recommended configuration scheme results in a smaller steady-state accuracy loss and lower high-frequency noise.

[0120] In fact, in the low-frequency segment, the DC gains of the corrector are: 0.9162, 0.7559, 0.2898 (corresponding to the first recommended configuration scheme, the second recommended configuration scheme, and Configuration 9 respectively), that is, the amplitude-frequency characteristic curves of the low-frequency segment of the system are pulled down by 0.76 dB, 2.43 dB, and 10.75 dB respectively; and combined with the calculation of the steady-state error, it can be known that the rate error constants corresponding to the first recommended configuration scheme, the second recommended configuration scheme, and Configuration 9 are 4275.8, 3527.1, and 1352.1 respectively; furthermore, it can also be verified from the unit ramp response of the system that the second recommended configuration scheme has moderate tracking performance, that is, a moderate steady-state rate error.

[0121] In the high-frequency segment, the amplitude-frequency characteristic curves of the system are pulled up by 7.58 dB, 3.64 dB, and 1.52 dB respectively, that is, the second recommended configuration scheme generates less high-frequency noise. Obviously: The second recommended configuration scheme can make the corrected system have relatively moderate low-frequency and high-frequency characteristics.

[0122] (3) Verify the accuracy of the correction method

[0123] After calculation, using Configuration 1 - Configuration 10 and the second recommended configuration scheme, the open-loop control system all crosses the 0 dB line at the expected cut-off frequency of 5087.7 rad / s; and at this frequency, the phase angle of the open-loop system is -120°, that is, the phase margin is 60°, meeting the expected phase margin value. Therefore, this application can achieve: accurately compensating the specified phase margin at a relatively arbitrary cut-off frequency.

[0124] In addition, the present application also proposes a general-purpose grid-connected inverter direct digital correction design device, as Figure 4 The device includes:

[0125] A first module 401 for calculating the open-loop cut-off frequency ω cg and phase margin γ of the inverter control system to be corrected;

[0126] A second module 402 for setting the desired cut-off frequency ω cg-exp and desired phase margin γ exp , determining the phase angle deficit φ ad ;

[0127] A third module 403 for configuring the poles p c and zeros z c of the lead compensator on the positive real axis within the unit circle of the z-plane, and z c > p c , and making p c and z c respectively point to the marked point with polar coordinates exp(jω cg-exp T), and the included angle of the phasors is equal to the phase angle deficit φ ad ;

[0128] A fourth module 404 for calculating the correction factor K gc of the open-loop gain of the compensator according to preset requirements;

[0129] A fifth module 405 for selecting a preset recommended configuration scheme according to different control performance index requirements;

[0130] A sixth module 406 for obtaining the difference equation.

[0131] In addition, the present application also proposes a general-purpose grid-connected inverter direct digital correction design device, as Figure 5 The device includes:

[0132] At least one processor 501;

[0133] At least one memory 502, and the memory 502 is used to store at least one program;

[0134] When at least one of the programs is executed by at least one of the processors 501, the general-purpose grid-connected inverter direct digital correction design method described in the previous embodiment is implemented.

[0135] In addition, the present application also proposes a storage medium, and the storage medium stores a program executable by a processor. When the program executable by the processor is executed by the processor, the general-purpose grid-connected inverter direct digital correction design method described in the previous embodiment is implemented.

[0136] Similarly, the content in the above method embodiments is applicable to this storage medium embodiment. The functions specifically implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those in the above method embodiments.

[0137] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order mentioned in the operation diagrams. For example, depending on the functions / operations involved, two consecutive blocks shown may actually be executed substantially simultaneously or the blocks can sometimes be executed in the reverse order. Additionally, the embodiments presented and described in the flowcharts of this application are provided by way of example for the purpose of providing a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logical flows presented herein. Alternative embodiments are contemplated where the order of various operations is changed and where sub-operations described as part of a larger operation are executed independently.

[0138] Furthermore, although this application is described in the context of functional modules, it should be understood that, unless otherwise stated to the contrary, one or more of the functions and / or features may be integrated in a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It can also be understood that a detailed discussion of the actual implementation of each module is not necessary for understanding this application. Rather, given the attributes, functions, and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the modules will be understood within the ordinary skill of an engineer. Thus, those skilled in the art can implement this application as set forth in the claims without undue experimentation. It can also be understood that the specific concepts disclosed are illustrative only and are not intended to limit the scope of this application, which is determined by the full scope of the appended claims and their equivalents.

[0139] If a function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in various embodiments of this application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs.

[0140] The logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a definite sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in combination with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in combination with an instruction execution system, apparatus, or device.

[0141] More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection part with one or more wirings (electronic device), a portable computer disk cartridge (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, a computer-readable medium can even be paper or other suitable media on which a program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, then editing, interpreting, or processing it in other suitable ways as necessary, and then storing it in a computer memory.

[0142] It should be understood that each part of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0143] In the foregoing description of this specification, descriptions with reference to the terms "one embodiment / Example", "another embodiment / Example", or "certain embodiments / Examples", etc., mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0144] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application. The scope of the present application is defined by the claims and their equivalents.

[0145] The above, the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent substitutions on some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present application.

Claims

1. A direct digital correction design method for a general-purpose grid-connected inverter, characterized in that, The method includes: Calculate the open-loop cut-off frequency ω and phase margin γ of the inverter control system to be calibrated; cg ​ Set the desired cut-off frequency ω cg-exp and the desired phase margin γ exp , and determine the phase angle deficit φ ad ; Place the pole p of the lead compensator c , zero z c on the positive real axis within the unit circle in the z-plane, and z c and p c have a relative position relationship on the real axis such that z c > p c , and make p c and z c point to the marked point with polar coordinates exp(jω cg-exp T) respectively, and the included angle of the phasors is equal to the phase angle deficit φ ad ; where, the included angle relationship of the two phasors of z c and p c pointing to the marked point with polar coordinates exp(jω cg-exp T) is as follows: φ zc -φ pc =φ ad z c The calculation formula for the relative position on the real axis is as follows: p c The calculation formula for the relative position on the real axis is as follows: where T is the sampling time, φ pc is the argument of the pole p c in the z-plane pointing to the marked point, and φ zc is the argument of the pole z c in the z-plane pointing to the marked point; Calculate the corrector open-loop gain correction factor K according to the preset requirements gc ; The corrector open-loop gain correction factor K gc The calculation formula is as follows: Among them, G sys is the open-loop transfer function of the inverter control system; Selecting a preset recommended configuration solution according to different control performance index requirements; Obtaining a difference equation.

2. The direct digital correction design method of the general grid-connected inverter according to claim 1, characterized in that The open-loop cut-off frequency ω cg has the following calculation formula:

3. The direct digital correction design method of the general grid-connected inverter according to claim 1, characterized in that, The phase angle deficit φ ad has the following calculation formula: where γ exp is the desired phase margin.

4. The direct digital correction design method of the general grid-connected inverter according to claim 1, characterized in that G C (z) is the transfer function of the corrector, and has the following formula:

5. The direct digital correction design method of the universal grid-connected inverter according to claim 1, characterized in that The preset recommended configuration solution includes a first recommended configuration solution and a second recommended configuration solution; The first recommended configuration plan is as follows: Place p c at the origin, that is, p c = 0; The second recommended configuration scheme is: Set p c to be: where p w is the pole of the w-domain lead compensator.

6. Universal grid-connected inverter direct digital correction design device, characterized in that, The device includes: The first module is used to calculate the open-loop cut-off frequency ω of the inverter control system to be corrected cg and the phase margin γ; The second module is used to set the desired cut-off frequency ω cg-exp and the desired phase margin γ exp , and determine the phase angle deficit φ ad ; The third module is used to place the pole p of the lead compensator c , zero z c on the positive real axis within the unit circle of the z-plane, and z c and p c have a relative position relationship on the real axis such that z c > p c , and make p c and z c respectively point to the marked point with polar coordinates exp(jω cg-exp T), and the included angle of the phasors is equal to the phase angle deficit φ ad ; where the included angle relationship of the two phasors of z c and p c pointing to the marked point with polar coordinates exp(jω cg-exp T) is: φ zc -φ pc =φ ad z c The calculation formula for the relative position on the real axis is as follows: p c The calculation formula for the relative position on the real axis is as follows: Among them, T is the sampling time, φ pc is the argument of the pole p c in the z-plane pointing to the marked point, φ zc is the argument of the pole z c in the z-plane pointing to the marked point; The fourth module is used to calculate the corrector open-loop gain correction factor K according to preset requirements gc ; The corrector open-loop gain correction factor K gc has the following calculation formula: Among them, G sys is the open-loop transfer function of the inverter control system; A fifth module, configured to select a preset recommended configuration solution according to different control performance index requirements; A sixth module, configured to obtain a difference equation.

7. General grid-connected inverter direct digital correction design device, characterized in that, The device includes: At least one processor; At least one memory, where the memory is used to store at least one program; When at least one of the at least one program is executed by at least one of the at least one processor, the direct digital correction design method for a general-purpose grid-connected inverter as described in any one of claims 1-5 is implemented.

8. Storage medium, characterized in that, The storage medium stores a program executable by a processor, and when the program executable by the processor is executed by the processor, the direct digital correction design method for a general-purpose grid-connected inverter as described in any one of claims 1-5 is implemented.

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