Comparator and decision feedback equalization circuit

Abstract

The application provides a comparator and a decision feedback equalization circuit. The comparator comprises: a first-stage main circuit connected with a power supply end and a ground end, provided with a first pair of tubes and a second pair of tubes of different types, used for receiving a first input signal and a first reference signal, and further used for generating a first differential signal according to the first input signal and the first reference signal in a sampling stage; a first-stage auxiliary circuit connected with the power supply end or the ground end, provided with a third pair of tubes and a fourth pair of tubes of different types, used for receiving a second input signal and a second reference signal, and further used for generating a second differential signal according to the second input signal and the second reference signal; and a second-stage circuit used for amplifying and latching a voltage signal at an output end of the first-stage main circuit and a voltage signal at an output end of the first-stage auxiliary circuit in a regeneration stage, so as to output a comparison result. The comparator provided by the application can eliminate inter-symbol interference, expand the range of the reference signal, and has a lower working voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to integrated circuits, in particular to a comparator and a decision feedback equalization circuit. BACKGROUND

[0002] Nowadays, people's demand for mobile devices such as mobile phones, tablets and various wearable accessories has greatly increased, which greatly enriches our daily life and work.

[0003] However, due to the limited battery life, higher requirements are put forward for the power consumption of each component in the mobile device. Dynamic random access memory (DRAM) is an essential component in mobile devices, so DRAM also needs to achieve lower operating voltage and lower energy consumption. Among them, the comparator is an important device for realizing the data read and write of DRAM, and the existing comparator cannot meet the current use demand. SUMMARY

[0004] The present application provides a comparator and a decision feedback equalization circuit, aiming to eliminate the inter-symbol interference of the comparator, reduce the operating voltage of the comparator, and expand the range of the reference signal of the comparator.

[0005] In a first aspect, the present application provides a comparator, comprising:

[0006] A first-stage main circuit connected to a power supply end and a ground end, provided with a first pair of tubes and a second pair of tubes, the first pair of tubes and the second pair of tubes being different in type, the first pair of tubes and the second pair of tubes being used to receive a first input signal and a first reference signal, and further being used to generate a first differential signal according to the first input signal and the first reference signal in a sampling stage;

[0007] A first-stage auxiliary circuit connected to the power supply end or the ground end, provided with a third pair of tubes and a fourth pair of tubes, the third pair of tubes and the fourth pair of tubes being different in type, the third pair of tubes and the fourth pair of tubes being used to receive a second input signal and a second reference signal, and further being used to generate a second differential signal according to the second input signal and the second reference signal in the sampling stage;

[0008] A second-stage circuit connected to the first-stage main circuit and the first-stage auxiliary circuit, used to amplify and latch process a voltage signal at an output end of the first-stage main circuit and a voltage signal at an output end of the first-stage auxiliary circuit in a regeneration stage, to output a comparison result.

[0009] In a second aspect, the present application provides a decision feedback equalization circuit, comprising four comparators involved in the first aspect and the optional solutions, sequentially marked as a first comparator, a second comparator, a third comparator and a fourth comparator.

[0010] a first input terminal for receiving the first input signal, a second input terminal for receiving the first reference signal, a third input terminal connected to the first output terminal of the fourth comparator, and a fourth input terminal connected to the second output terminal of the fourth comparator;

[0011] a first input terminal for receiving the first input signal, a second input terminal for receiving the first reference signal, a third input terminal connected to the first output terminal of the fourth comparator, and a fourth input terminal connected to the second output terminal of the fourth comparator;

[0012] a first input terminal for receiving the first input signal, a second input terminal for receiving the first reference signal, a third input terminal connected to the first output terminal of the fourth comparator, and a fourth input terminal connected to the second output terminal of the fourth comparator;

[0013] a first input terminal for receiving the first input signal, a second input terminal for receiving the first reference signal, a third input terminal connected to the first output terminal of the fourth comparator, and a fourth input terminal connected to the second output terminal of the fourth comparator.

[0014] The application provides a comparator decision feedback equalization circuit. The comparator comprises a first-stage main circuit, a first-stage auxiliary circuit and a second-stage circuit. The first-stage main circuit is provided with a first pair of transistors and a second pair of transistors, and is used for generating a first differential signal according to a first input signal and a first reference signal in a sampling stage. Since the first pair of transistors and the second pair of transistors are different in type, that is, the pulling ability of the first pair of transistors and the second pair of transistors to voltage is opposite, when the first input signal and the first reference signal make the pulling ability of the first pair of transistors and the second pair of transistors to voltage unbalanced, even if the difference between the first input signal and the first reference signal is very small, the two pairs of transistors can accurately sense, thereby improving the sensing accuracy of the comparator. Since the first-stage circuit contains two pairs of transistors different in type, when the value range of the first reference signal is relatively wide, for example, can vary from 0.3V to 0.9V, the generation of differential signals in the two pairs of transistors can be realized, thereby expanding the working range of the comparator. The main circuit is used for generating a first differential signal according to a first input signal and a first reference signal in a sampling stage. The auxiliary circuit is used for generating a second differential signal according to a second input signal and a second reference signal in a sampling stage. The second-stage circuit is used for amplifying and latching the first differential signal and the second differential signal in a regeneration stage, so as to output a comparison result. When inter-symbol interference occurs and the first-stage main circuit cannot accurately sense and output a differential signal, the second differential signal output by the first-stage auxiliary circuit can adjust the first differential signal, thereby eliminating the inter-symbol interference and improving the accuracy of the comparator. Through the two-stage circuit setting, that is, the first-stage circuit generates a differential signal, and the second-stage circuit generates a comparison result according to the differential signal, the number of transistors in the same circuit path can be reduced, thereby reducing the working voltage of the comparator. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0016] Figure 1 A specific circuit diagram of a comparator provided in this application;

[0017] Figure 2 The timing diagram of the comparator provided in this application;

[0018] Figure 3 A structural block diagram of a comparator provided in this application;

[0019] Figure 4 For based on Figure 3 A specific circuit diagram of the provided comparator;

[0020] Figure 5 For based on Figure 3 Another specific circuit diagram of the provided comparator;

[0021] Figure 6 A block diagram of a decision feedback equalization circuit provided in this application;

[0022] Figure 7 A schematic diagram illustrating the effect of the decision feedback equalization circuit provided in this application;

[0023] Figure 8 The timing diagram of the decision feedback equalization circuit provided in this application.

[0024] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0026] like Figure 1As shown, the comparator comprises an input circuit 101, an output circuit 102 and a reset circuit 103. The output of the input circuit 101 is connected to the input of the output circuit 102. The reset circuit 103 is also connected to the output circuit 102.

[0027] The input circuit 101 comprises a transistor N1, a transistor N2 and a transistor N3. The transistor N1 and the transistor N2 constitute a differential transistor pair. The gate of the transistor N1 and the gate of the transistor N2 constitute a first input IN and a second input IN of the input circuit. The drain of the transistor N1 and the drain of the transistor N2 constitute two outputs of the input circuit.

[0028] The output circuit 102 comprises a transistor P1, a transistor P2, a transistor N4 and a transistor N5. The four transistors constitute a cross-coupled transistor pair. The drain of the transistor P1 and the drain of the transistor N4 constitute a first output ON of the output circuit 102. The drain of the transistor P2 and the drain of the transistor N5 constitute a second output OP of the output circuit 102. The reset circuit 103 comprises a transistor P3 and a transistor P4.

[0029] The working process of the comparator is divided into four stages, namely, a reset stage, a sampling stage, a regeneration stage and a decision stage. The working process of the comparator shown will be described below in combination with the following figures: Figure 2 Figure 1

[0030] In the reset stage, that is, from t0 to t1, the clock signal is low, the transistor N3 is open, the input circuit and the output circuit stop working, the transistor P3 and the transistor P4 are closed, and the reset circuit works to pull the voltage of the drain of the transistor N4 and the drain of the transistor N5 to high level.

[0031] In the sampling stage, that is, from t1 to t2, the clock signal is high, the transistor P3 and the transistor P4 are open, and the reset circuit stops working. The transistor N3 is closed, the input circuit collects the input signal through the first input IN, and collects the reference signal through the second input IN. The input signal pulls down the voltage of the drain of the transistor N1, and the reference signal pulls down the voltage of the drain of the transistor N2. The drain of the transistor N1 pulls down the voltage of the drain of the transistor N4, and the drain of the transistor N2 pulls down the voltage of the drain of the transistor N5. Since the input signal is higher than the reference signal, the input signal pulls down the voltage of the drain of the transistor N1 at a faster rate, thereby making the voltage of the drain of the transistor N4 lower than the voltage of the drain of the transistor N5.

[0032] ​​During the regeneration phase, from time t2 to t3, the drain voltages of transistor N4 and N5 reach the flip voltage, transistors P2 and N4 are turned on, while transistors P1 and N5 are gradually turned off. Transistor P2 pulls up the drain voltage of transistor N5, and transistor N4 pulls down the drain voltage of transistor N4.

[0033] During the decision-making phase, from time t3 to t4, transistors P2 and N4 are turned on, while transistors P1 and N5 are turned off. The drain voltage of transistor N5 continues to be pulled up, and the drain voltage of transistor N4 continues to be pulled down. After pulling the drain of transistor N5 to a low level and the drain voltage of transistor N4 to a high level, the drain voltages of transistors N4 and N5 are maintained.

[0034] When the next working cycle arrives, the clock signal goes low, and the drain voltages of transistors N4 and N5 are reset to high by transistors P1 and P2.

[0035] like Figure 3 As shown, one embodiment of this application provides a comparator, which includes a first main stage circuit 201, a first auxiliary stage circuit 202, and a second stage circuit 203. Both the first stage circuit 201 and the first auxiliary stage circuit 202 have output terminals, and the second stage circuit 203 has an input terminal. The output terminals of the first stage circuit 201 and the first auxiliary stage circuit 202 are connected to each other, and then connected to the input terminal of the second stage circuit 203.

[0036] The first-stage main circuit 201 is connected to the power supply terminal and the ground terminal, causing the transistors in the first-stage main circuit 201 to form a current path. The first-stage auxiliary circuit 202 is connected to the power supply terminal and the ground terminal, causing the transistors in the first-stage auxiliary circuit 202 to form a current path. The second-stage circuit 203 is connected to either the power supply terminal or the ground terminal, causing the transistors in the second-stage circuit 203 to form another current path. Compared to a comparator structure containing only one stage of circuitry, this configuration reduces the number of transistors in each current path, thereby lowering the comparator's operating voltage.

[0037] In one embodiment, the first-stage circuit 201 and the second-stage circuit 202 have the same number of transistors in their respective current paths, so that the first-stage circuit 201 and the second-stage circuit 202 operate at the same voltage, reducing the number of power supply terminals required by the comparator and simplifying the comparator circuit.

[0038] The first-stage main circuit 201 is provided with a first pair of transistors and a second pair of transistors, which are used to receive a first input signal and a first reference signal. That is, a first transistor in the first pair of transistors is used to receive the first input signal, and a second transistor in the first pair of transistors is used to receive the first reference signal. A first transistor in the second pair of transistors is used to receive the first input signal, and a second transistor in the second pair of transistors is used to receive the first reference signal. The first pair of transistors and the second pair of transistors are also used to generate a first differential signal according to the first input signal and the first reference signal in a sampling stage.

[0039] Since the first pair of transistors and the second pair of transistors have different transistor types, the pulling directions of the voltage are different. The first input signal and the first reference signal are used to control the pulling capabilities of the first pair of transistors and the second pair of transistors on the voltage. If the first input signal and the first reference signal make the pulling capabilities of the first pair of transistors and the second pair of transistors on the voltage unbalanced, a first differential signal can be generated on the first pair of transistors and the second pair of transistors even if the difference between the first input signal and the first reference signal is very small, thereby improving the accuracy of the comparator.

[0040] For example, the first pair of transistors includes a first input transistor P1 and a second input transistor P2, the second pair of transistors includes a third input transistor N1 and a fourth input transistor N2, and the first reference signal makes the pulling capability of the second input transistor P2 upward and the pulling capability of the fourth input transistor N2 downward balanced. When the first input signal is slightly greater than the first reference signal, the first input signal makes the pulling capability of the first input transistor P1 upward and the pulling capability of the third input transistor N1 downward unbalanced, and then a first differential signal is generated on the first pair of transistors and the second pair of transistors.

[0041] It should be further noted that since the first pair of transistors and the second pair of transistors of different types are used to receive the first input signal and the first reference signal, the value of the first reference signal can be changed from 0.3V to 0.9V, and a first differential signal can be generated on the first pair of transistors and the second pair of transistors, thereby expanding the selection range of the reference voltage of the comparator.

[0042] The first-stage auxiliary circuit is provided with a third pair of transistors and a fourth pair of transistors, which are different in type, and are used to receive a second input signal and a second reference signal, and are also used to generate a second differential signal according to the second input signal and the second reference signal. The circuit structure of the first-stage auxiliary circuit is similar to that of the first-stage main circuit, and the first-stage auxiliary circuit will not be described here. For details, reference can be made to the description of the first-stage main circuit.

[0043] The first-stage main circuit 201 and the first-stage auxiliary circuit 202 are each provided with two output ends, which are marked as a first output end and a second output end. The second-stage circuit 203 is provided with two input ends, which are marked as a first input end and a second input end. The first output end of the first-stage main circuit 201 and the first output end of the first-stage auxiliary circuit 202 are connected and then connected to the first input end of the second-stage circuit 203, and the second output end of the first-stage main circuit 201 and the second output end of the first-stage auxiliary circuit 202 are connected and then connected to the second input end of the second-stage circuit 203. The first-stage main circuit is configured to generate a first differential signal according to a first input signal and a first reference signal in a sampling stage, and the first-stage auxiliary circuit is configured to generate a second differential signal according to a second input signal and a second reference signal in the sampling stage. The second-stage circuit is configured to amplify and latch the first differential signal and the second differential signal in a regeneration stage to output a comparison result.

[0044] The comparator includes a first-stage main circuit and a first-stage auxiliary circuit, the first-stage main circuit generates a first differential signal, and the first-stage auxiliary circuit generates a second differential signal. When code interference occurs and the first-stage main circuit cannot accurately sense and output the differential signal, the second differential signal output by the first-stage auxiliary circuit can adjust the first differential signal, so that the second-stage circuit generates a comparison result according to the adjusted first differential signal, thereby eliminating code interference and improving the accuracy of the comparator.

[0045] As shown in Figure 4 An embodiment of the present application provides a specific circuit of a comparator, and the comparator includes a first-stage main circuit 201, a first-stage auxiliary circuit 202, and a second-stage circuit 203.

[0046] The first-stage circuit includes a first input transistor P1, a second input transistor P2, a third input transistor N1, a fourth input transistor N2, and a fifth input transistor N3. The first input transistor P1 and the second input transistor P2 form a first pair of transistors. The third input transistor N1 and the fourth input transistor N2 form a second pair of transistors.

[0047] The control end of the first input transistor P1 is configured to receive a first input signal In1, the first end of the first input transistor P1 is connected to a power supply end, and the second end of the first input transistor P1 serves as a first output end of the first-stage main circuit.

[0048] The control end of the second input transistor P2 is configured to receive a first reference signal Vr1, the first end of the second input transistor P2 is connected to the power supply end, and the second end of the second input transistor P2 serves as a second output end of the first-stage main circuit.

[0049] The control terminal of the third input transistor N1 is used for receiving the first input signal In1, and the first terminal of the third input transistor N1 is connected with the second terminal of the first input transistor P1 to form the first output terminal of the first main circuit. The control terminal of the third input transistor N1 is connected with the control terminal of the first input transistor P1 to form the first input terminal of the comparator.

[0050] The control terminal of the fourth input transistor N2 is used for receiving the second reference signal Vr1, and the first terminal of the fourth input transistor N2 is connected with the second terminal of the second input transistor P2 to form the second output terminal of the first main circuit. The control terminal of the fourth input transistor N2 is connected with the control terminal of the second input transistor P2 to form the second input terminal of the comparator.

[0051] The control terminal of the fifth input transistor N3 is used for receiving the clock signal, the first terminal of the fifth input transistor N3 is connected with the second terminal of the third input transistor N1 and the second terminal of the fourth input transistor N2, and the second terminal of the fifth input transistor N3 is connected with the ground terminal.

[0052] The fifth input transistor N3 is used for controlling the working state of the first main circuit. In the reset stage, the fifth input transistor N3 is disconnected, and the first main circuit stops working. In the sampling stage, the regeneration stage and the decision stage, the first main circuit works. In the sampling stage, the first input transistor P1, the second input transistor P2, the third input transistor N1 and the fourth input transistor N2 generate the first differential signal under the control of the first input signal and the first reference signal.

[0053] The first auxiliary circuit 102 comprises at least one equalization module 1020 in parallel, each equalization module 1020 is provided with a first output terminal and a second output terminal, the first output terminals of each equalization module 1020 are connected with each other to form the first output terminal of the first auxiliary circuit 102, and the second output terminals of each equalization module 1020 are connected with each other to form the second output terminal of the first auxiliary circuit 102.

[0054] Each equalization module 1020 comprises a sixth input transistor P3, a seventh input transistor P4, an eighth input transistor N4, a ninth input transistor N5 and a tenth input transistor N6. Each input transistor is provided with a control terminal, a first terminal and a second terminal.

[0055] The control terminals of the sixth input transistors P3 of the equalization modules are connected, the control terminals of the eighth input transistors N4 of the equalization modules are connected, and the control terminals of the sixth input transistors P3 and the control terminals of the eighth input transistors N4 of the equalization modules are connected with each other to form the third input terminal of the comparator.

[0056] The control end of the seventh input transistor P4 of each equalization module is connected, the control end of the ninth input transistor N5 of each equalization module is connected, and the control end of the seventh input transistor P4 and the control end of the ninth input transistor N5 of each equalization module are connected to each other to form a fourth input end of a comparator.

[0057] The second end of the sixth input transistor P3 and the first end of the eighth input transistor N4 are connected to serve as a first output end of the equalization module 1020, and the control end of the sixth input transistor P3 and the control end of the eighth input transistor N4 are used to receive a second input signal In2.

[0058] The second end of the seventh input transistor P4 and the first end of the ninth input transistor N5 are connected to serve as a second output end of the equalization module 1020, and the control end of the seventh input transistor P4 and the control end of the ninth input transistor N5 are used to receive a second reference signal Vr2.

[0059] The first end of the tenth input transistor N6 is connected to the second end of the eighth input transistor N4 and the second end of the ninth input transistor N5, and the second end of the tenth input transistor N6 is connected to a ground end.

[0060] The tenth input transistor N6 is used to control the working state of the first-stage auxiliary circuit. In the reset stage, the tenth input transistor N6 is turned off, and the first-stage auxiliary circuit stops working, and in the sampling stage, the regeneration stage and the decision stage, the first-stage auxiliary circuit works. In the sampling stage, the sixth input transistor P3, the seventh input transistor P4, the eighth input transistor N4 and the ninth input transistor N5 generate a second differential signal under the control of the second input signal and the second reference signal.

[0061] The output circuit 105 includes a first output transistor N7, a second output transistor N8, a third output transistor P5 and a fourth output transistor P6. The first end of the first output transistor N7 is connected to the second end of the third output transistor P5, and the first end of the second output transistor N8 is connected to the second end of the fourth output transistor P6. The control end of the first output transistor N7 is connected to the control end of the third output transistor P5, and the second end of the fourth output transistor P6 is connected. The control end of the second output transistor N8 is connected to the control end of the fourth output transistor P6, and the second end of the third output transistor P5 is connected.

[0062] The second end of the first output transistor N7 is the first input end of the output circuit 105, and the second end of the second output transistor N8 is the second input end of the output circuit 105. The second end of the third output transistor P5 serves as a first output end PB of a comparator, and the second end of the fourth output transistor P6 serves as a second output end P of the comparator.

[0063] After the first differential signal and the second differential signal are generated by the first primary circuit and the first auxiliary circuit respectively, the voltage of the first end of the first output transistor N7 and the first end of the second output transistor N8 is pulled down. The transistor is turned on when the voltage is pulled down to the flip voltage. That is, the first output transistor N7 and the fourth output transistor P6 are turned on, or the second output transistor N8 and the third output transistor P5 are turned on, so as to pull the voltage of the two output ends of the comparator in different directions, so as to amplify and latch the voltage signal of the output end of the first primary circuit and the first auxiliary circuit, and output the comparison result.

[0064] In an embodiment, the comparator further comprises a reset circuit for resetting the voltage of the two output ends of the comparator. The reset circuit comprises a first reset transistor P7 and a second reset transistor P8. The first end of the first reset transistor P7 is connected to the power supply end, and the second end of the first reset transistor P7 is connected to the second end of the third output transistor P5, so as to pull the second end of the third output transistor P5 to high level after being turned on in the reset stage.

[0065] The first end of the second reset transistor P8 is connected to the power supply end, and the second end of the second reset transistor P8 is connected to the second end of the fourth output transistor P6, so as to pull the second end of the fourth output transistor P6 to high level after being turned on in the reset stage.

[0066] In an embodiment, the first input transistor P1, the second input transistor P2, the sixth input transistor P3 and the seventh input transistor P4 are of the same type, and the third input transistor N1, the fourth input transistor N2, the fifth input transistor N3, the eighth input transistor N4, the ninth input transistor N5 and the tenth input transistor N6 are of the same type.

[0067] If the first input transistor P1, the second input transistor P2, the sixth input transistor P3 and the seventh input transistor P4 are P-type transistors, the source of the P-type transistor is the first end, and the gate of the P-type transistor is the control end. If the third input transistor N1, the fourth input transistor N2, the fifth input transistor N3, the eighth input transistor N4, the ninth input transistor N5 and the tenth input transistor N6 are N-type transistors, the drain of the N-type transistor is the first end, and the gate of the N-type transistor is the control end.

[0068] In an embodiment, the first input transistor P1 and the second input transistor P2 are of the same size, the sixth input transistor P3 and the seventh input transistor P4 are of the same size, and the size of the sixth input transistor P3 is less than half of the size of the first input transistor P1.

[0069] The third input transistor N1 and the fourth input transistor N2 have the same size, the eighth input transistor N4 and the ninth input transistor N5 have the same size, and the size of the eighth input transistor N4 is less than half of the size of the third input transistor N1.

[0070] By the above arrangement, the influence of the first-stage auxiliary circuit pair on the first differential signal can be avoided, for example, the first input signal and the first reference signal make the first end voltage of the first input transistor N1 greater than the first end voltage of the second input transistor N2, and the intervention of the second differential signal makes the first differential signal reverse, that is, the first end voltage of the first input transistor N1 is less than the first end voltage of the second input transistor N2.

[0071] In an embodiment, the first output transistor N7 and the second output transistor N8 have the same type of transistor, and the third output transistor P5 and the fourth output transistor P6 have the same type of transistor.

[0072] If the first output transistor N7 and the second output transistor N8 are both N-type transistors, the drain of the N-type transistor is the first end, and the gate of the N-type transistor is the control end. If the third output transistor P5 and the fourth output transistor P6 are both P-type transistors, the source of the P-type transistor is the first end, and the gate of the P-type transistor is the control end.

[0073] The first-stage main circuit is connected to the ground end through the fifth input transistor N3 and connected to the power supply end through the first input transistor P1 or the second input transistor P2. Each current path in the first-stage main circuit includes three transistors, for example, the current path formed by the third input transistor N1, the fifth input transistor N3, and the first input transistor P1.

[0074] The second-stage circuit is connected to the power supply end through the third output transistor P5 or the fourth output transistor P6. Each current path in the second-stage circuit includes four transistors, for example, the current path formed by the third output transistor P5, the first output transistor N7, the third input transistor N1, and the fifth input transistor N3.

[0075] By the above arrangement, the structure of the first-stage circuit and the second-stage circuit is adopted, and compared with a comparator adopting a one-stage structure, the working voltage of the comparator is lower, and the application range is wider.

[0076] The following Table 1 illustrates that the comparator can realize rail-to-rail detection, that is, the variation range of the first reference voltage is relatively large. Taking the power supply end voltage VDD as 1.2V as an example, the range of the first reference signal can vary from 0.3V to 0.9V.

[0077] Table 1 Working principle of the sampling stage of the comparator

[0078]

[0079] In the third case, the first input transistor P1, the second input transistor P2 and the third input transistor N1 are all turned on, the pull-up ability of the first input transistor P1 is less than the second input transistor P2, and the third input transistor N1 also pulls down the voltage of the first input transistor P1, so VP1<VP2.

[0080] In the sixth case, the first input transistor P1, the second input transistor P2, the third input transistor N1 and the fourth input transistor N2 are all turned on, the pull-up ability of the first input transistor P1 is greater than the second input transistor P2, and the ability of the third input transistor N1 to pull down the voltage of the first input transistor P1 is less than the ability of the fourth input transistor N2 to pull down the voltage of the second input transistor P2, so VP1>VP2.

[0081] The analysis of other cases can refer to the analysis of the third and sixth cases, which will not be described here.

[0082] That is, when the first reference voltage changes from 0.3V to 0.9V, the first differential signal can be generated on the first input transistor P1 and the second input transistor P2, and the comparison result can be generated by the second stage circuit according to the first differential signal and the second differential signal, so as to realize rail-to-rail detection.

[0083] The principle of eliminating inter-symbol interference of the comparator will be described below in combination with Table 2, wherein the values of the second input signal and the second reference signal at t1 are determined according to the size of the first input signal and the first reference signal at t0. If the first input signal at t0 is greater than the first reference signal at t0, the value of the second input signal at t1 is less than the second reference signal, and vice versa.

[0084] Table 2: Inter-symbol interference case

[0085]

[0086] As can be seen from Table 2, in the first case, the inter-symbol interference makes the voltage of the first input transistor N1 equal to the voltage of the second input transistor N2, but the voltage of the fourth input transistor N4 is less than the voltage of the fifth input transistor N5, so that the voltage of the first output terminal O1 of the first stage main circuit is less than the voltage of the second output terminal O2, which is the same as the result of the absence of the inter-symbol interference, and the inter-symbol interference is eliminated. It should be noted that, since the size of each transistor in the auxiliary circuit is less than one half of the size of each transistor in the main circuit, even in the second case, VN1 < VN2, VN4 > VN5, where VN1, VN2, VN4 and VN5 represent the drain voltages of the first input transistor N1, the second input transistor N2, the third input transistor N3 and the fourth input transistor N4 respectively, but the pulling ability of the voltage of the fourth input transistor N4 and the fifth input transistor N5 is less than the pulling ability of the voltage of the first input transistor N1 and the second input transistor N2, so that the voltage VO1 of the first output terminal of the first stage main circuit is still less than the voltage VO2 of the second output terminal of the first stage main circuit, which is the same as the result of the absence of the inter-symbol interference, and the inter-symbol interference is eliminated.

[0087] As shown in Figure 5 An embodiment of the present application provides a specific circuit of a comparator, which comprises a first main stage circuit 201, a first stage auxiliary circuit 202 and a second stage circuit 203.

[0088] The first stage circuit comprises a first input transistor N1, a second input transistor N2, a third input transistor P1, a fourth input transistor P2 and a fifth input transistor P3. The first input transistor N1 and the second input transistor N2 constitute a first pair of transistors. The third input transistor P1 and the fourth input transistor P2 constitute a second pair of transistors.

[0089] The control terminal of the first input transistor N1 is used for receiving a first input signal In1, the first terminal of the first input transistor N1 is connected to a ground terminal, and the second terminal of the first input transistor N1 serves as a first output terminal of the first stage main circuit.

[0090] The control terminal of the second input transistor N2 is used for receiving a first reference signal Vr1, the first terminal of the second input transistor N2 is connected to the ground terminal, and the second terminal of the second input transistor N2 serves as a second output terminal of the first stage main circuit.

[0091] The control terminal of the third input transistor P1 is used for receiving the first input signal In1, the first terminal of the third input transistor P1 is connected to the second terminal of the first input transistor N1 to form the first output terminal of the first stage main circuit, and the control terminal of the third input transistor P1 is connected to the control terminal of the first input transistor N1 to form a first input terminal of the comparator.

[0092] The control terminal of the fourth input transistor P2 is used for receiving a second reference signal Vr1, the first terminal of the fourth input transistor P2 is connected with the second terminal of the second input transistor N2 to form a second output terminal of the first main circuit, and the control terminal of the fourth input transistor P2 is connected with the control terminal of the second input transistor N2 to form a second input terminal of the comparator.

[0093] The control terminal of the fifth input transistor P3 is used for receiving a clock signal, the first terminal of the fifth input transistor P3 is connected with the second terminal of the third input transistor P1 and the second terminal of the fourth input transistor P2, and the second terminal of the fifth input transistor P3 is connected with a power terminal.

[0094] The fifth input transistor P3 is used for controlling the working state of the first main circuit. In a reset stage, the fifth input transistor P3 is disconnected, and the first main circuit stops working, and in a sampling stage, a regeneration stage and a decision stage, the first main circuit works. In the sampling stage, the first input transistor N1, the second input transistor N2, the third input transistor P1 and the fourth input transistor P2 generate a first differential signal under the control of the first input signal and the first reference signal.

[0095] The first auxiliary circuit 102 comprises at least one equalization module 1020 in parallel, each equalization module 1020 is provided with a first output terminal and a second output terminal, the first output terminals of each equalization module 1020 are connected with each other to form a first output terminal of the first auxiliary circuit 102, and the second output terminals of each equalization module 1020 are connected with each other to form a second output terminal of the first auxiliary circuit 102.

[0096] Each equalization module 1020 comprises a sixth input transistor N3, a seventh input transistor N4, an eighth input transistor P4, a ninth input transistor P5 and a tenth input transistor P6. Each input transistor is provided with a control terminal, a first terminal and a second terminal.

[0097] The control terminals of the sixth input transistors N3 of the equalization modules are connected, the control terminals of the eighth input transistors P4 of the equalization modules are connected, and the control terminals of the sixth input transistors N3 and the control terminals of the eighth input transistors P4 of the equalization modules are connected with each other to form a third input terminal of the comparator.

[0098] The control terminals of the seventh input transistors N4 of the equalization modules are connected, the control terminals of the ninth input transistors P5 of the equalization modules are connected, and the control terminals of the seventh input transistors N4 and the control terminals of the ninth input transistors P5 of the equalization modules are connected with each other to form a fourth input terminal of the comparator.

[0099] The second end of the sixth input transistor N3 and the first end of the eighth input transistor P4 are connected as a first output end of the equalization module 1020, and the control end of the sixth input transistor N3 and the control end of the eighth input transistor P4 are used to receive the second input signal In2.

[0100] The second end of the seventh input transistor N4 and the first end of the ninth input transistor P5 are connected as a second output end of the equalization module 1020, and the control end of the seventh input transistor N4 and the control end of the ninth input transistor P5 are used to receive the second reference signal Vr2.

[0101] The first end of the tenth input transistor P6 is connected to the second end of the eighth input transistor P4 and the second end of the ninth input transistor P5, and the second end of the tenth input transistor P6 is connected to the power supply end.

[0102] The tenth input transistor P6 is used to control the working state of the first-stage auxiliary circuit. In the reset stage, the tenth input transistor P6 is turned off, and the first-stage auxiliary circuit stops working, and in the sampling stage, the regeneration stage and the decision stage, the first-stage auxiliary circuit works. In the sampling stage, the sixth input transistor N3, the seventh input transistor N4, the eighth input transistor P4 and the ninth input transistor P5 generate a second differential signal under the control of the second input signal and the second reference signal.

[0103] The output circuit 105 includes a first output transistor P7, a second output transistor P8, a third output transistor N5 and a fourth output transistor N6. The first end of the first output transistor P7 is connected to the second end of the third output transistor N5, and the first end of the second output transistor P8 is connected to the second end of the fourth output transistor N6. The control end of the first output transistor P7 is connected to the control end of the third output transistor N5 and is connected to the second end of the fourth output transistor N6. The control end of the second output transistor P8 is connected to the control end of the fourth output transistor N6 and is connected to the second end of the third output transistor N5.

[0104] The second end of the first output transistor P7 is the first input end of the output circuit 105, and the second end of the second output transistor P8 is the second input end of the output circuit 105. The second end of the third output transistor N5 is the first output end PB of the comparator, and the second end of the fourth output transistor N6 is the second output end P of the comparator.

[0105] After the first differential signal and the second differential signal are generated by the first primary circuit and the first auxiliary circuit respectively, the voltage of the first end of the first output transistor P7 and the first end of the second output transistor P8 is pulled down. The transistor is turned on when the voltage is pulled down to the flip voltage. That is, the first output transistor P7 and the fourth output transistor N6 are turned on, or the second output transistor P8 and the third output transistor N5 are turned on, so as to pull the voltage of the two output ends of the comparator in different directions, so as to amplify and latch the voltage signal of the output end of the first primary circuit and the first auxiliary circuit, and output the comparison result.

[0106] In an embodiment, the comparator further comprises a reset circuit for resetting the voltage of the two output ends of the comparator. The reset circuit comprises a first reset transistor N7 and a second reset transistor N8. The first end of the first reset transistor N7 is connected to the ground end, and the second end of the first reset transistor N7 is connected to the second end of the third output transistor N5, so as to pull the second end of the third output transistor N5 to high level after being turned on in the reset stage.

[0107] The first end of the second reset transistor N8 is connected to the ground end, and the second end of the second reset transistor N8 is connected to the second end of the fourth output transistor N6, so as to pull the second end of the fourth output transistor N6 to high level after being turned on in the reset stage.

[0108] In an embodiment, the first input transistor N1, the second input transistor N2, the sixth input transistor N3 and the seventh input transistor N4 are of the same type, and the third input transistor P1, the fourth input transistor P2, the fifth input transistor P3, the eighth input transistor P4, the ninth input transistor P5 and the tenth input transistor P6 are of the same type.

[0109] If the first input transistor N1, the second input transistor N2, the sixth input transistor N3 and the seventh input transistor N4 are N-type transistors, the source of the N-type transistor is the first end, and the gate of the N-type transistor is the control end. If the third input transistor P1, the fourth input transistor P2, the fifth input transistor P3, the eighth input transistor P4, the ninth input transistor P5 and the tenth input transistor P6 are P-type transistors, the drain of the P-type transistor is the first end, and the gate of the P-type transistor is the control end.

[0110] In an embodiment, the first input transistor N1 and the second input transistor N2 are of the same size, the sixth input transistor N3 and the seventh input transistor N4 are of the same size, and the size of the sixth input transistor N3 is less than one half of the size of the first input transistor N1.

[0111] The third input transistor P1 and the fourth input transistor P2 have the same size, and the eighth input transistor P4 and the ninth input transistor P5 have the same size; the size of the eighth input transistor P4 is less than half of the size of the third input transistor P1.

[0112] Through the above setting, the influence of the first-stage auxiliary circuit pair on the first differential signal can be avoided, for example, the first input signal and the first reference signal make the first end voltage of the first input transistor P1 greater than the first end voltage of the second input transistor P2, and the intervention of the second differential signal makes the first differential signal reverse, that is, the first end voltage of the first input transistor P1 is less than the first end voltage of the second input transistor P2.

[0113] In an embodiment, the first output transistor P7 and the second output transistor P8 have the same type of transistor, and the third output transistor N5 and the fourth output transistor N6 have the same type of transistor.

[0114] If the first output transistor P7 and the second output transistor P8 are both P-type transistors, the drain of the P-type transistor is the first end, and the gate of the P-type transistor is the control end; if the third output transistor N5 and the fourth output transistor N6 are both N-type transistors, the source of the N-type transistor is the first end, and the gate of the N-type transistor is the control end.

[0115] The first-stage main circuit is connected to the power supply end through the fifth input transistor P3 and connected to the ground end through the first input transistor N1 or the second input transistor N2. Each current path in the first-stage main circuit includes three transistors, for example, the current path formed by the third input transistor P1, the fifth input transistor P3, and the first input transistor N1.

[0116] The second-stage circuit is connected to the ground end through the third output transistor N5 or the fourth output transistor N5. Each current path in the second-stage circuit includes four transistors, for example, the current path formed by the third output transistor N5, the first output transistor P7, the third input transistor P1, and the fifth input transistor P3.

[0117] Through the above setting, the structure of the first-stage circuit and the second-stage circuit is adopted, compared with a comparator adopting a one-stage structure, the working voltage of the comparator is lower, and the application range is wider.

[0118] The principle of realizing rail-to-rail detection of the comparator is the same as that in Table 1, which will not be described here.

[0119] The principle of realizing the elimination of inter-symbol interference of the comparator will be described below in combination with Table 3, wherein the setting mode of the second reference signal and the second input signal is the same as that in Table 2, which will not be described here.

[0120] Table 3: Case of Inter-symbol Interference

[0121]

[0122] As can be seen from Table 3, in the first case, the inter-symbol interference makes the voltage of the first input transistor P1 equal to the voltage of the second input transistor P2, but the voltage of the fourth input transistor P4 is less than the voltage of the fifth input transistor P5, so that the voltage of the first output terminal O1 of the first stage circuit is less than the voltage of the second output terminal O2, which is the same as the result of the absence of inter-symbol interference, and the inter-symbol interference is eliminated. It should be noted that, since the size of each transistor in the auxiliary circuit is less than one half of the size of each transistor in the main circuit, even in the second case, VP1 < VP2, VP4 > VP5, where VP1, VP2, VP4 and VP5 represent the drain voltages of the first input transistor P1, the second input transistor P2, the third input transistor P3 and the fourth input transistor P4 respectively, but the pulling ability of the voltage of the fourth input transistor P4 and the fifth input transistor P5 is less than the pulling ability of the voltage of the first input transistor P1 and the second input transistor P2, so that the voltage VO1 of the first output terminal of the first stage circuit is still less than the voltage VO2 of the second output terminal of the first stage circuit, which is the same as the result of the absence of inter-symbol interference, and the inter-symbol interference is eliminated.

[0123] As shown in FIG. 1, an embodiment of the present application provides a decision feedback equalization circuit, which comprises four comparators described in the above embodiments, and are sequentially marked as a first comparator 100, a second comparator 200, a third comparator 300 and a fourth comparator 400. Figure 6 The third input terminal In2 of the first comparator 100 is connected with the first output terminal P270B of the fourth comparator 400, and the fourth input terminal Vr2 of the first comparator 100 is connected with the second output terminal P270 of the fourth comparator 400. The third input terminal In2 of the second comparator 200 is connected with the first output terminal P0B of the first comparator 100, and the fourth input terminal Vr2 of the second comparator 200 is connected with the second output terminal P0 of the first comparator 100. The third input terminal In2 of the third comparator 300 is connected with the first output terminal P90B of the second comparator 200, and the fourth input terminal Vr2 of the third comparator 300 is connected with the second output terminal P90 of the second comparator 200. The third input terminal In2 of the fourth comparator 400 is connected with the first output terminal P270B of the third comparator 300, and the fourth input terminal Vr2 of the fourth comparator 400 is connected with the second output terminal P270 of the third comparator 300.

[0124]

[0125] ​The first input end In1 of the first to fourth comparators 100-400 receives a first input signal, and the second input end Vref1 of the first to fourth comparators 100-400 receives a first reference signal.

[0126] Suppose that the fourth register 400 outputs a digital "1" when the first input signal is greater than the first reference signal at the last time, and the signal of the third input end In2 of the first register 100 is less than the signal of the fourth input end Vr2 at the current time, and suppose that the first input signal is also greater than the first reference signal at the current time, and the intersymbol interference still makes the first input signal greater than the first reference signal, the first register 100 still outputs a digital "1".

[0127] Suppose that the fourth register 400 outputs a digital "1" when the first input signal is greater than the first reference signal at the last time, and the signal of the third input end In2 of the first register 100 is less than the signal of the fourth input end Vr2 at the current time, and suppose that the first input signal is less than the first reference signal at the current time, and the intersymbol interference makes the first input signal equal to or slightly greater than the first reference signal, and since the signal of the third input end In2 is less than the signal of the fourth input end Vr2, the first register 100 still outputs a digital "0".

[0128] Suppose that the fourth register 400 outputs a digital "0" when the first input signal is less than the first reference signal at the last time, and the signal of the third input end In2 of the first register 100 is greater than the signal of the fourth input end Vr2 at the current time, and suppose that the first input signal is also less than the first reference signal at the current time, and the intersymbol interference still makes the first input signal less than the first reference signal, the first register 100 still outputs a digital "0".

[0129] Suppose that the fourth register 400 outputs a digital "0" when the first input signal is less than the first reference signal at the last time, and the signal of the third input end In2 of the first register 100 is greater than the signal of the fourth input end Vr2 at the current time, and suppose that the first input signal is greater than the first reference signal at the current time, and the intersymbol interference makes the first input signal equal to or slightly less than the first reference signal, and since the signal of the third input end is greater than the signal of the fourth input end, the first register 100 still outputs a digital "1".

[0130] The working principles of the second to fourth registers 200-400 are the same as that of the first register 100, and thus will not be described herein.

[0131] Figure 6 The decision feedback equalization circuit shown is a first-order circuit, and a multi-order circuit is usually used to achieve better elimination of intersymbol interference. Figure 7Fig. 4 is a schematic diagram of the effect of the fourth-order decision feedback equalization circuit, and tap1 to tap4 represent the first-order decision feedback equalization circuit to the fourth-order decision feedback equalization circuit in sequence. As shown in Fig. 4, the actual waveform of the first input signal under the influence of the intersymbol interference is shown as curve 1, and the falling edge is relatively flat when the first input signal switches from a high level to a low level, that is, there is a false recognition of the first input signal as a high level. The fourth-order decision feedback equalization circuit can effectively eliminate the intersymbol interference, so that the equivalent waveform of the first input signal input into the decision feedback equalization circuit is shown as curve 2, and the falling edge becomes steep. Figure 7

[0132] In an embodiment, the phase of the first clock signal of the first comparator 100 is 90° earlier than the phase of the second clock signal of the second comparator 200, the phase of the first clock signal of the first comparator 100 is 180° earlier than the phase of the third clock signal of the third comparator 300, and the phase of the first clock signal of the first comparator 100 is 270° earlier than the phase of the fourth clock signal of the fourth comparator 400.

[0133] In an embodiment, the voltage flip time of the output end of the first comparator 100 to the voltage flip time T of the output end of the fourth comparator 400 FB is less than the time interval 1U1 between the first clock signal and the second clock signal, as shown in Fig. 5. Taking the fourth comparator as an example, when the flip time of the output voltage of the fourth comparator 400 is less than 1U1, 1UI represents the time interval between the first clock signal and the second clock signal, which can ensure that the fourth comparator 400 has stably output the comparison result when the clock signal of the first comparator 100 arrives, and the fourth comparator 400 maintains the comparison result, so that the first comparator 100 can eliminate the intersymbol interference according to the comparison result of the fourth comparator 400. Figure 8

[0134] In an embodiment, the decision feedback equalization circuit further includes four registers, which are marked as a first register 500, a second register 600, a third register 700, and a fourth register 800 in sequence. The input end of the first register 500 is connected with the two output ends of the first comparator 100, the input end of the second register 600 is connected with the two output ends of the second comparator 200, the input end of the third register 700 is connected with the two output ends of the third comparator 300, and the input end of the fourth register 800 is connected with the two output ends of the fourth comparator 400. The four registers are respectively used to store the comparison results of the outputs of the four corresponding comparators, D0 is the output result of the first register 500, D90 is the output result of the second register 600, D180 is the output result of the third register 700, and D270 is the output result of the fourth register 800.

[0135] ​​In the technical scheme, two output terminals of the fourth register are connected with two input terminals of the first register, two output terminals of the first register are connected with two input terminals of the second register, and the like, so as to form a decision feedback equalization circuit, and the other two input terminals of the four registers receive the first input signal and the first reference signal, and under the control of the output terminal signals of the four registers, the inter-symbol interference caused by continuously inputting the first input signal in the registers can be effectively eliminated.

[0136] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0137] It is to be understood that the application is not limited to the precise construction described above and shown in the attached drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application is limited only by the claims that follow.

Claims

1. A decision feedback equalization circuit, comprising: The comparator comprises four comparators, which are sequentially marked as a first comparator, a second comparator, a third comparator and a fourth comparator; Each of the comparators is provided with four input ends and two output ends, and comprises: The first-stage main circuit is provided with two input ends and two output ends, the two input ends are used as the first input end and the second input end of the comparator, and are connected with a power supply end and a grounding end; the first-stage main circuit is provided with a first pair of tubes and a second pair of tubes, the first pair of tubes and the second pair of tubes are different in type, and are used for receiving a first input signal and a first reference signal through the two input ends, and are also used for generating a first differential signal according to the first input signal and the first reference signal in a sampling stage; The first-stage auxiliary circuit is provided with two input ends and two output ends, the two input ends are used as the third input end and the fourth input end of the comparator, and the output ends are connected with the output ends of the first-stage main circuit; the first-stage auxiliary circuit is connected with a power supply end or a grounding end, and is provided with a third pair of tubes and a fourth pair of tubes, the third pair of tubes and the fourth pair of tubes are different in type, and are used for receiving a second input signal and a second reference signal through the two input ends, and are also used for generating a second differential signal according to the second input signal and the second reference signal in the sampling stage; The second-stage circuit is provided with two input ends and two output ends, the two output ends are used as the output ends of the comparator, and the two input ends are connected with the two output ends of the first-stage main circuit; the second-stage circuit is used for amplifying and latching the voltage signals of the output ends of the first-stage main circuit and the output ends of the first-stage auxiliary circuit in a regeneration stage, so as to output a comparison result; The first input end of the first comparator is used for receiving a first input signal, the second input end is used for receiving a first reference signal, the third input end is directly connected with the first output end of the fourth comparator and is used for receiving a second input signal, and the fourth input end is directly connected with the second output end of the fourth comparator and is used for receiving a second reference signal; The first input end of the second comparator is used for receiving a first input signal, the second input end is used for receiving a first reference signal, the third input end is directly connected with the first output end of the first comparator and is used for receiving a second input signal, and the fourth input end is directly connected with the second output end of the first comparator and is used for receiving a second reference signal; The first input end of the third comparator is used for receiving a first input signal, the second input end is used for receiving a first reference signal, the third input end is directly connected with the first output end of the second comparator and is used for receiving a second input signal, and the fourth input end is directly connected with the second output end of the second comparator and is used for receiving a second reference signal; The first input end of the fourth comparator is used for receiving a first input signal, the second input end is used for receiving a first reference signal, the third input end is directly connected with the first output end of the third comparator and is used for receiving a second input signal, and the fourth input end is directly connected with the second output end of the third comparator and is used for receiving a second reference signal.

2. The decision feedback equalization circuit of claim 1, wherein, The first-stage main circuit, the first-stage auxiliary circuit and the second-stage circuit have the same number of transistors in respective current paths.

3. The decision feedback equalization circuit of claim 1, wherein, The first-stage main circuit comprises: a first input transistor having a control terminal for receiving the first input signal and a second terminal as a first output terminal of the first-stage main circuit; a second input transistor having a control terminal for receiving the first reference signal and a second terminal as a second output terminal of the first-stage main circuit; a third input transistor having a control terminal for receiving the first input signal and a first terminal connected to the second terminal of the first input transistor; a fourth input transistor having a control terminal for receiving the first reference signal and a first terminal connected to the second terminal of the second input transistor; a fifth input transistor having a control terminal for receiving a clock signal, a first terminal connected to the second terminals of the third and fourth input transistors, and a second terminal connected to a ground terminal or a power supply terminal.

4. The decision feedback equalization circuit of claim 3, wherein, The first-stage auxiliary circuit comprises at least one regulating module, each regulating module comprising: a sixth input transistor having a control terminal for receiving the second input signal and a second terminal as a first output terminal of the first-stage auxiliary circuit; a seventh input transistor having a control terminal for receiving the second reference signal and a second terminal as a second output terminal of the first-stage auxiliary circuit; an eighth input transistor having a control terminal for receiving the second input signal and a first terminal connected to the second terminal of the sixth input transistor; a ninth input transistor having a control terminal for receiving the second reference signal and a first terminal connected to the second terminal of the seventh input transistor; a tenth input transistor having a control terminal for receiving a clock signal, a first terminal connected to the second terminals of the eighth and ninth input transistors, and a second terminal connected to a ground terminal or a power supply terminal.

5. The decision feedback equalization circuit of claim 4, wherein: the first input transistor, the second input transistor, the sixth input transistor and the seventh input transistor are of the same type; the third input transistor, the fourth input transistor, the fifth input transistor, the eighth input transistor, the ninth input transistor and the tenth input transistor are of the same type.

6. The decision feedback equalization circuit of claim 5, wherein: the first input transistor and the second input transistor are of the same size, the sixth input transistor and the seventh input transistor are of the same size, and the sixth input transistor is smaller than one-half of the size of the first input transistor; the third input transistor and the fourth input transistor are of the same size, the eighth input transistor and the ninth input transistor are of the same size; and the eighth input transistor is smaller than one-half of the size of the third input transistor.

7. The decision feedback equalization circuit of claim 5, wherein: When the first input transistor, the second input transistor, the sixth input transistor, and the seventh input transistor are P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal. When the third input transistor, the fourth input transistor, the fifth input transistor, the eighth input transistor, the ninth input transistor, and the tenth input transistor are N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

8. The decision feedback equalization circuit of claim 5, wherein: When the first input transistor, the second input transistor, the sixth input transistor, and the seventh input transistor are N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal. When the third input transistor, the fourth input transistor, the fifth input transistor, the eighth input transistor, the ninth input transistor, and the tenth input transistor are P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

9. The decision feedback equalization circuit of claim 1, wherein, The second stage circuit comprises: a first output transistor, the second terminal of which is the first input terminal of the second stage circuit; a second output transistor, the second terminal of which is the second input terminal of the second stage circuit; a third output transistor, the control terminal of which is connected to the control terminal of the first output transistor, and the second terminal of which is connected to the second terminal of the fourth output transistor, the second terminal of the third output transistor serving as the first output terminal of the second stage circuit; a fourth output transistor, the control terminal of which is connected to the control terminal of the second output transistor, and the second terminal of which is connected to the second terminal of the third output transistor, the second terminal of the fourth output transistor serving as the second output terminal of the second stage circuit.

10. The decision feedback equalization circuit of claim 9, wherein: If the first output transistor and the second output transistor are both N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal. If the third output transistor and the fourth output transistor are both P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

11. The decision feedback equalization circuit of claim 9, wherein: If the first output transistor and the second output transistor are both P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal. If the third output transistor and the fourth output transistor are both N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

12. The decision feedback equalization circuit of claim 1, wherein: the phase of the first clock signal of the first comparator is 90° earlier than the phase of the second clock signal of the second comparator; the phase of the first clock signal of the first comparator is 180° earlier than the phase of the third clock signal of the third comparator; the phase of the first clock signal of the first comparator is 270° earlier than the phase of the fourth clock signal of the fourth comparator.

13. The decision feedback equalization circuit of claim 12, wherein: a voltage transition time of the output of the first comparator and a voltage transition time of the output of the fourth comparator are each less than a time interval between the first clock signal and the second clock signal.

14. The decision feedback equalization circuit of any one of claims 1 to 13, wherein, further comprising: four registers, labeled in order as a first register, a second register, a third register, and a fourth register; an input of the first register is connected to the two outputs of the first comparator; an input of the second register is connected to the two outputs of the second comparator; an input of the third register is connected to the two outputs of the third comparator; an input of the fourth register is connected to the two outputs of the fourth comparator.

Images