Comparator and decision feedback equalization circuit

Abstract

The application provides a comparator and a decision feedback equalization circuit. The comparator comprises: a first-stage circuit, which comprises a main circuit, an auxiliary circuit and a common circuit, the main circuit and the auxiliary circuit are connected to a power supply end or a ground end, the common circuit is connected to the ground end or the power supply end, the main circuit is used for generating a first differential signal according to a first input signal and a first reference signal in a sampling stage, the auxiliary circuit is used for generating a second differential signal according to a second input signal and a second reference signal in the sampling stage, and a second-stage circuit, which is connected to the power supply end and the ground end and connected to an output end of the first-stage circuit, is used for amplifying and latching the first differential signal and the second differential signal in a regeneration stage to output a comparison result. The comparator provided by the application can eliminate inter-symbol interference, and the working voltage is also low.

Description

Technical Field

[0001] This application relates to integrated circuits, and more particularly to a comparator and a decision feedback equalization circuit. Background Technology

[0002] Today, people's demand for mobile devices such as smartphones, tablets, and various wearable accessories has increased significantly, greatly enriching our daily lives and work.

[0003] However, due to limited battery life, higher demands are placed on the power consumption of various components in mobile devices. Dynamic Random Access Memory (DRAM) is an essential component in mobile devices, therefore, DRAM also urgently needs to achieve lower operating voltage and lower power consumption. Among them, the comparator is a crucial device for realizing DRAM data read and write, and existing comparators can no longer meet current usage requirements. Summary of the Invention

[0004] This application provides a comparator and a decision feedback equalization circuit, which aims to eliminate inter-symbol interference of the comparator and reduce the operating voltage of the comparator.

[0005] In a first aspect, this application provides a comparator, comprising:

[0006] The first-level circuit includes a main circuit, an auxiliary circuit, and a common circuit. The main circuit and the auxiliary circuit are both connected to the power supply terminal or the ground terminal, and the common circuit is connected to the ground terminal or the power supply terminal. The main circuit is used to generate a first differential signal based on the first input signal and the first reference signal during the sampling stage. The auxiliary circuit is used to generate a second differential signal based on the second input signal and the second reference signal during the sampling stage.

[0007] The second-stage circuit, which connects the power supply terminal and the ground terminal, is connected to the output terminal of the first-stage circuit. It is used to amplify and latch the first differential signal and the second differential signal during the regeneration stage to output the comparison result.

[0008] In a second aspect, a decision feedback equalization circuit is characterized in that it includes four comparators as described in any one of claims 11, which are sequentially labeled as a first comparator, a second comparator, a third comparator, and a fourth comparator.

[0009] The first comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the fourth comparator, and a fourth input terminal connected to the second output terminal of the fourth comparator.

[0010] The second comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the first comparator, and a fourth input terminal connected to the second output terminal of the first comparator.

[0011] The third comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the second comparator, and a fourth input terminal connected to the second output terminal of the second comparator.

[0012] The fourth comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the third comparator, and a fourth input terminal connected to the second output terminal of the third comparator.

[0013] This application provides a comparator and a decision feedback equalization circuit. The comparator includes a first-stage circuit and a second-stage circuit. The first-stage circuit includes a main circuit, an auxiliary circuit, and a common circuit. The main circuit generates a first differential signal based on a first input signal and a first reference signal during the sampling stage. The auxiliary circuit generates a second differential signal based on a second input signal and a second reference signal during the sampling stage. The second-stage circuit amplifies and latches the first and second differential signals during the regeneration stage to output a comparison result. When inter-symbol interference (ISI) prevents the main circuit from accurately sensing and outputting the differential signal, the second differential signal output by the auxiliary circuit can adjust the first differential signal, thereby eliminating ISI and improving the comparator's accuracy. By using a two-stage circuit setup—that is, the first-stage circuit generates the differential signal, and the second-stage circuit generates the comparison result based on the differential signal—the number of transistors in the same circuit path can be reduced, thereby reducing the comparator's operating voltage. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0015] Figure 1 A specific circuit diagram of a comparator provided in this application;

[0016] Figure 2 The timing diagram of the comparator provided in this application;

[0017] Figure 3 A structural block diagram of a comparator provided in this application;

[0018] Figure 4 For based on Figure 3 A specific circuit diagram of the provided comparator;

[0019] Figure 5 For based on Figure 3 Another specific circuit diagram of the provided comparator;

[0020] Figure 6 A block diagram of a decision feedback equalization circuit provided in this application;

[0021] Figure 7 A schematic diagram illustrating the effect of the decision feedback equalization circuit provided in this application;

[0022] Figure 8 The timing diagram of the decision feedback equalization circuit provided in this application.

[0023] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0024] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0025] like Figure 1 As shown, the comparator includes an input circuit 101, an output circuit 102, and a reset circuit 103. The output terminal of the input circuit 101 is connected to the input terminal of the output circuit 102. The reset circuit 103 is also connected to the output circuit 102.

[0026] The input circuit 101 includes transistors N1, N2, and N3. Transistors N1 and N2 form a differential transistor pair. The gates of transistors N1 and N2 form the first input terminal IP and the second input terminal IN of the input circuit. The drains of transistors N1 and N2 form the two output terminals of the input circuit.

[0027] The output circuit 102 includes transistors P1, P2, N4, and N5, which form a cross-coupled transistor pair. The drains of transistors P1 and N4 form the first output terminal ON of the output circuit 102, and the drains of transistors P2 and N5 form the second output terminal OP of the output circuit 102. The reset circuit 103 includes transistors P3 and P4.

[0028] The comparator's operation consists of four stages: reset, sampling, regeneration, and decision. The following section will discuss these stages in conjunction with... Figure 2 describe Figure 1 The working process of the comparator shown is as follows:

[0029] During the reset phase, from time t0 to time t1, the clock signal is low, transistor N3 is open, the input and output circuits stop working, transistors P3 and P4 are closed, the reset circuit works, and pulls the drain voltage of transistor N4 and the drain voltage of transistor N5 to high level.

[0030] During the sampling phase, from time t1 to t2, the clock signal is high, transistors P3 and P4 are open, and the reset circuit stops working. Transistor N3 is closed, and the input circuit acquires the input signal through the first input terminal IP and the reference signal through the second input terminal IN. The input signal pulls down the drain voltage of transistor N1, and the reference signal pulls down the drain voltage of transistor N2. The drain of transistor N1 pulls down the drain voltage of transistor N4, and the drain of transistor N2 pulls down the drain voltage of transistor N5. Because the input signal is higher than the reference signal, the rate at which the input signal pulls down the drain voltage of transistor N1 is faster, resulting in the drain voltage of transistor N4 being lower than that of transistor N5.

[0031] During the regeneration phase, from time t2 to t3, the drain voltages of transistor N4 and N5 reach the flip voltage, transistors P2 and N4 are turned on, while transistors P1 and N5 are gradually turned off. Transistor P2 pulls up the drain voltage of transistor N5, and transistor N4 pulls down the drain voltage of transistor N4.

[0032] During the decision-making phase, from time t3 to t4, transistors P2 and N4 are turned on, while transistors P1 and N5 are turned off. The drain voltage of transistor N5 continues to be pulled up, and the drain voltage of transistor N4 continues to be pulled down. After pulling the drain of transistor N5 to a low level and the drain voltage of transistor N4 to a high level, the drain voltages of transistors N4 and N5 are maintained.

[0033] When the next working cycle arrives, the clock signal goes low, and the drain voltages of transistors N4 and N5 are reset to high by transistors P1 and P2.

[0034] like Figure 3 As shown, this application discloses a comparator, which includes a first-stage circuit 201 and a second-stage circuit 202. The first-stage circuit 201 includes a main circuit 2011, an auxiliary circuit 2012, and a common circuit 2013.

[0035] The main circuit 2011, auxiliary circuit 2012, and common circuit 2013 each have two output terminals, labeled as the first output terminal and the second output terminal. The first output terminals of the main circuit 2011, auxiliary circuit 2012, and common circuit 2013 are interconnected to form the first output terminal of the first-stage circuit 201. The second output terminals of the main circuit 2011, auxiliary circuit 2012, and common circuit 2013 are interconnected to form the second output terminal of the second-stage circuit 202.

[0036] When the main circuit 2011 and auxiliary circuit 2012 are connected to the power supply, the common circuit 2013 is connected to the ground. When the main circuit 2011 and auxiliary circuit 2012 are connected to the ground, the common circuit 2013 is connected to the power supply. This arrangement creates a single current path for the transistors in the first-stage circuit 201. The second-stage circuit 203 connects to both the power supply and ground, creating another current path for the transistors in the second-stage circuit 203. Compared to a comparator structure containing only one stage of circuitry, this arrangement reduces the number of transistors in each current path, thereby lowering the comparator's operating voltage.

[0037] The second-stage circuit 202 has two input terminals, labeled as the first input terminal and the second input terminal. The first input terminal of the second-stage circuit 202 is connected to the first output terminal O1 of the first-stage circuit, and the second input terminal of the second-stage circuit 202 is connected to the second output terminal O2 of the first-stage circuit. The main circuit generates a first differential signal based on the first input signal and the first reference signal during the sampling phase, and the auxiliary circuit generates a second differential signal based on the second input signal and the second reference signal during the sampling phase. The second-stage circuit amplifies and latches the first and second differential signals during the regeneration phase to output the comparison result.

[0038] The first-stage circuit includes a main circuit and an auxiliary circuit. The main circuit and the auxiliary circuit generate a first differential signal and a second differential signal, respectively. When inter-symbol interference occurs, preventing the main circuit from accurately sensing and outputting the differential signal, the second differential signal output by the auxiliary circuit can adjust the first differential signal. This allows the second-stage circuit to generate a comparison result based on the adjusted first differential signal, thereby eliminating inter-symbol interference and improving the accuracy of the comparator.

[0039] In one embodiment, the first-stage circuit 201 and the second-stage circuit 202 have the same number of transistors in their respective current paths, so that the first-stage circuit 201 and the second-stage circuit 202 operate at the same voltage, reducing the number of power supply terminals required by the comparator and simplifying the comparator circuit.

[0040] In the above technical solution, by setting up a main circuit and an auxiliary circuit in the first-stage circuit, when the main circuit is unable to accurately output the first differential signal due to inter-symbol interference, the auxiliary circuit adjusts the first differential signal so that the second-stage circuit can accurately generate the comparison result based on the adjusted first differential signal, thereby improving the accuracy of the comparator. Furthermore, using a two-stage structure can reduce the operating voltage of the comparator.

[0041] like Figure 4 As shown, an embodiment of this application provides a specific circuit structure for a comparator, wherein there is a first-stage circuit 201 and a second-stage circuit 202. The first-stage circuit 201 includes a main circuit 2011, an auxiliary circuit 2012, and a common circuit 2013.

[0042] The main circuit includes a first input transistor N1, a second input transistor N2, and a third input transistor N3. The control terminal of the first input transistor N1 serves as the first input terminal of the comparator, used to receive the first input signal In1. The first terminal of the first input transistor N1 serves as the first output terminal of the main circuit. The control terminal of the second input transistor N2 serves as the second input terminal of the comparator, used to receive the first reference signal Vr1. The first terminal of the second input transistor N2 serves as the second output terminal of the main circuit. The control terminal of the third input transistor N3 receives a clock signal. The first terminal of the third input transistor N3 is connected to the second terminal of the first input transistor N1, the second terminal of the second input transistor N2, and the second terminal of the third input transistor N3 is connected to ground.

[0043] The third input transistor N3 is used to control the operating state of the main circuit. During the reset phase, the third input transistor N3 is turned off, and the first-stage circuit stops working. During the sampling phase, regeneration phase, and decision phase, the main circuit operates. During the sampling phase, the first input transistor N1 and the second input transistor N2 generate the first differential signal under the control of the first input signal and the first reference signal.

[0044] The auxiliary circuit 2012 includes at least one parallel equalization module 2014. Each equalization module 2014 has a first output terminal and a second output terminal. The first output terminals of each equalization module 2014 are connected to each other to form the first output terminal of the auxiliary circuit 2012. The second output terminals of each equalization module 2014 are connected to each other to form the second output terminal of the auxiliary circuit 2012.

[0045] Each equalizer module includes a fourth input transistor N4, a fifth input transistor N5, and a sixth input transistor N6. The control terminals of the fourth input transistors N4 of each equalizer module are connected to form the third input terminal of the comparator. The control terminals of the fifth input transistors N5 of each equalizer module are connected to form the fourth input terminal of the comparator.

[0046] The control terminal of the fourth input transistor N4 receives the second input signal In2, and the first terminal of the fourth input transistor N4 serves as the first output terminal of the equalization module. The control terminal of the fifth input transistor N5 receives the second reference signal Vr2, and the first terminal of the fifth input transistor N5 serves as the second output terminal of the equalization module. The control terminal of the sixth input transistor N6 receives the clock signal, and the first terminal of the sixth input transistor N6 is connected to the second terminals of the fourth input transistor N4 and the fifth input transistor N5. The second terminal of the sixth input transistor N6 is used to connect to the ground terminal.

[0047] The sixth input transistor N6 is used to control the operating state of the equalization module. During the reset phase, the sixth input transistor N6 is turned off, and the equalization module stops working. The equalization module operates during the sampling, regeneration, and decision phases. During the sampling phase, the fourth input transistor N4 and the fifth input transistor N5 generate a second differential numerator signal under the control of the second input signal and the second reference signal. The second differential numerator signals output by each equalization module are superimposed to form the second differential signal.

[0048] The common circuit 2013 includes a seventh input transistor P1 and an eighth input transistor P2. The control terminal of the seventh input transistor P1 is used to receive a clock signal, the first terminal of the seventh input transistor P1 is connected to the power supply terminal, and the second terminal of the seventh input transistor P1 is connected to the first terminal of the first input transistor N1 and the first terminal of the fourth input transistor N4.

[0049] The control terminal of the eighth input transistor P2 is used to receive the clock signal. The first terminal of the eighth input transistor P2 is connected to the power supply terminal. The second terminal of the eighth input transistor P2 is connected to the first terminal of the second input transistor N2 and the first terminal of the fifth input transistor N5.

[0050] The seventh input transistor P1 and the eighth input transistor P2 are turned on during the reset phase to reset the voltages at the two output terminals of the first stage circuit to a high level.

[0051] The second-stage circuit includes a first output transistor N7, a second output transistor N8, a third output transistor N9, a fourth output transistor N10, a fifth output transistor P3, a sixth output transistor P4, and a seventh output transistor P5.

[0052] The control terminal of the first output transistor N7 is the first input terminal of the second-stage circuit and is connected to the first terminal of the first input transistor N1 in the first-stage circuit. The first terminal of the first output transistor N7 is the first output terminal of the second-stage circuit. The second terminal of the first output transistor N7 is connected to the ground terminal.

[0053] The control terminal of the second output transistor N8 is the second input terminal of the second-stage circuit, and is connected to the first terminal of the second input transistor N2 in the first-stage circuit. The first terminal of the second output transistor N8 is the second output terminal of the second-stage circuit. The second terminal of the second output transistor N8 is connected to the ground terminal.

[0054] The first terminal of the third output transistor N9 is connected to the first terminal of the first output transistor N7, and the second terminal of the third output transistor N9 is connected to the second terminal of the first output transistor N7.

[0055] The first terminal of the fourth output transistor N10 is connected to the first terminal of the second output transistor N8, and the second terminal of the fourth output transistor N10 is connected to the second terminal of the second output transistor N8.

[0056] The second terminal of the fifth output transistor P3 is connected to the first terminal of the third output transistor N9. The control terminal of the fifth output transistor P3 is connected to the control terminal of the third output transistor N9 and then connected to the first terminal of the fourth output transistor N10.

[0057] The second terminal of the sixth output transistor P4 is connected to the first terminal of the fourth output transistor N10. The control terminal of the sixth output transistor P4 is connected to the control terminal of the fourth output transistor N10 and then connected to the first terminal of the third output transistor N9.

[0058] The control terminal of the seventh output transistor P5 is used to receive the clock signal. The first terminal of the seventh output transistor P5 is connected to the power supply terminal. The second terminal of the seventh output transistor P5 is connected to the first terminal of the fifth output transistor P3 and the first terminal of the sixth output transistor P4.

[0059] The seventh output transistor P5 is used to control the operating state of the second-stage circuit. During the reset phase, the seventh output transistor P5 is turned off, and the second-stage circuit stops working. During the sampling phase, regeneration phase, and decision phase, the seventh output transistor P5 is active.

[0060] During the regeneration and decision-making phases, the first output transistor N7 and the second output transistor N8 are used to amplify the differential signal of the first-stage circuit. The third output transistor N9, the fourth output transistor N10, the fifth output transistor P3, and the sixth output transistor P4 form a latch, which is used to amplify and latch the signal at the first terminal of the first output transistor N7 and the second output transistor N8 to output the comparison result.

[0061] The main circuit is connected to the ground terminal through the third input transistor N3, and to the power supply terminal through the seventh input transistor P1 and the eighth input transistor P2. Each current path in the main circuit contains three transistors, for example, the current path formed by the first input transistor N1, the third input transistor N3, and the seventh input transistor P1.

[0062] The second-stage circuit connects to ground via any one of the first output transistors N7 to the fourth output transistor N10, and to the power supply via the seventh output transistor P5. Each current path in the second-stage circuit contains three transistors; for example, the current path formed by the first output transistor N7, the fifth input transistor P3, and the seventh input transistor P5.

[0063] With the above setup, using a first-stage circuit and a second-stage circuit structure, the comparator operates at a lower voltage and has a wider range of applications compared to a comparator using a single-stage structure.

[0064] In one embodiment, the first input transistor N1 to the sixth input transistor N6 are of the same type, and the seventh input transistor P1 and the eighth input transistor P2 are of the same type.

[0065] If the first input transistor N1 to the sixth input transistor N6 are all N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal. If the seventh input transistor P1 and the eighth input transistor P2 are P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0066] In one embodiment, the first input transistor N1 and the second input transistor N2 are the same size, the fourth input transistor N4 and the fifth input transistor N5 are the same size, and the size of the fourth input transistor N4 is less than half the size of the first input transistor N1.

[0067] With the above settings, the influence of the auxiliary circuit can be avoided from being too great, which would cause the first differential signal to be reversed. For example, the first input signal and the first reference signal make the first terminal voltage of the first input transistor N1 greater than the first terminal voltage of the second input transistor N2. Due to the intervention of the second differential signal, the first differential signal is reversed, which means that the first terminal voltage of the first input transistor N1 is less than the first terminal voltage of the second input transistor N2.

[0068] In one embodiment, the first output transistor N7 to the fourth output transistor N10 are of the same type, and the fifth output transistor P3 to the seventh output transistor P5 are of the same type.

[0069] If the first output transistor N7 to the fourth output transistor N10 are all N-type transistors, with the drain of the N-type transistor being the first terminal and the gate of the N-type transistor being the control terminal. If the fifth output transistor P3 to the seventh output transistor P5 are all P-type transistors, with the source of the P-type transistor being the first terminal and the gate of the P-type transistor being the control terminal.

[0070] The principle of the comparator in eliminating inter-symbol interference is described below with reference to Table 1. The values ​​of the second input signal and the second reference signal at time t1 are determined based on the magnitudes of the first input signal and the first reference signal at time t0. If the first input signal at time t0 is greater than the first reference signal at time t0, the second input signal at time t1 is less than the value of the second reference signal, and vice versa.

[0071] Table 1. Inter-symbol interference situation

[0072]

[0073] As shown in Table 1, in the first case, inter-symbol interference makes the voltage of the first input transistor N1 equal to the voltage of the second input transistor N2, but the voltage of the fourth input transistor N4 is less than the voltage of the fifth input transistor N5, which makes the voltage of the first output terminal O1 of the first stage circuit less than the voltage of the second output terminal O2. This is the same result as when there is no inter-symbol interference, and the inter-symbol interference is eliminated. It should be noted here that, since the size of each transistor in the auxiliary circuit is less than half the size of each transistor in the main circuit, even in the second case, VN1 < VN2, VN4 > VN5, where VN1, VN2, VN4, and VN5 represent the drain voltages of the first input transistor N1, the second input transistor N2, the third input transistor N3, and the fourth input transistor N4, respectively, the voltage pull capability of the fourth input transistor N4 and the fifth input transistor N5 is less than that of the first input transistor N1 and the second input transistor N2. This results in the voltage VO1 at the first output terminal of the first stage circuit still being less than the voltage VO2 at the second output terminal of the first stage circuit. This is the same result as the absence of inter-symbol interference, and the inter-symbol interference is eliminated.

[0074] like Figure 5 As shown, an embodiment of this application provides a specific circuit structure for a comparator, wherein there is a first-stage circuit 201 and a second-stage circuit 202. The first-stage circuit 201 includes a main circuit 2011, an auxiliary circuit 2012, and a common circuit 2013.

[0075] The main circuit includes a first input transistor P1, a second input transistor P2, and a third input transistor P3.

[0076] The control terminal of the first input transistor P1 serves as the first input terminal of the comparator, used to receive the first input signal In1. The first terminal of the first input transistor P1 serves as the first output terminal of the main circuit. The control terminal of the second input transistor P2 serves as the second input terminal of the comparator, used to receive the first reference signal Vr1. The first terminal of the second input transistor P2 serves as the second output terminal of the main circuit. The control terminal of the third input transistor P3 receives the clock signal. The first terminal of the third input transistor P3 is connected to the second terminal of the first input transistor P1, the first terminal of the third input transistor P3 is connected to the second terminal of the second input transistor P2, and the second terminal of the third input transistor P3 is connected to the power supply terminal.

[0077] The third input transistor P3 is used to control the operating state of the main circuit. During the reset phase, the third input transistor P3 is turned off, and the first-stage circuit stops working. During the sampling phase, regeneration phase, and decision phase, the main circuit operates. During the sampling phase, the first input transistor P1 and the second input transistor P2 generate the first differential signal under the control of the first input signal and the first reference signal.

[0078] The auxiliary circuit 2012 includes at least one parallel equalization module 2014. Each equalization module 2014 has a first output terminal and a second output terminal. The first output terminals of each equalization module 2014 are connected to each other to form the first output terminal of the auxiliary circuit 2012. The second output terminals of each equalization module 2014 are connected to each other to form the second output terminal of the auxiliary circuit 2012.

[0079] Each equalizer module includes a fourth input transistor P4, a fifth input transistor P5, and a sixth input transistor P6. The control terminals of the fourth input transistors P4 of each equalizer module are connected to form the third input terminal of the comparator. The control terminals of the fifth input transistors P5 of each equalizer module are connected to form the fourth input terminal of the comparator.

[0080] The control terminal of the fourth input transistor P4 receives the second input signal In2, and the first terminal of the fourth input transistor P4 serves as the first output terminal of the equalization module. The control terminal of the fifth input transistor P5 receives the second reference signal Vr2, and the first terminal of the fifth input transistor P5 serves as the second output terminal of the equalization module. The control terminal of the sixth input transistor P6 receives the clock signal, and the first terminal of the sixth input transistor P6 is connected to the second terminals of the fourth input transistor P4 and the fifth input transistor P5. The second terminal of the sixth input transistor P6 is connected to the power supply terminal.

[0081] The sixth input transistor P6 controls the operating state of the equalization module. During the reset phase, the sixth input transistor P6 is turned off, and the equalization module stops working. The equalization module operates during the sampling, regeneration, and decision phases. During the sampling phase, the fourth input transistor P4 and the fifth input transistor P5 generate the second differential numerator signal under the control of the second input signal and the second reference signal. The second differential numerator signals output by each equalization module are superimposed to form the second differential signal.

[0082] The common circuit 2013 includes a seventh input transistor N1 and an eighth input transistor N2. The control terminal of the seventh input transistor N1 is used to receive a clock signal. The first terminal of the seventh input transistor N1 is connected to the ground terminal, and the second terminal of the seventh input transistor N1 is connected to the first terminal of the first input transistor P1 and the first terminal of the fourth input transistor P4.

[0083] The control terminal of the eighth input transistor N2 is used to receive the clock signal. The first terminal of the eighth input transistor N2 is connected to the ground terminal. The second terminal of the eighth input transistor N2 is connected to the first terminal of the second input transistor P2 and the first terminal of the fifth input transistor P5.

[0084] The seventh input transistor N1 and the eighth input transistor N2 are turned on during the reset phase to reset the voltages at the two output terminals of the first-stage circuit to a high level.

[0085] The second-stage circuit includes a first output transistor P7, a second output transistor P8, a third output transistor P9, a fourth output transistor P10, a fifth output transistor N3, a sixth output transistor N4, and a seventh output transistor N5.

[0086] The control terminal of the first output transistor P7 is the first input terminal of the second-stage circuit, and is connected to the first terminal of the first input transistor P1 in the first-stage circuit. The first terminal of the first output transistor P7 is the first output terminal of the second-stage circuit. The second terminal of the first output transistor P7 is connected to the power supply terminal.

[0087] The control terminal of the second output transistor P8 is the second input terminal of the second-stage circuit, and is connected to the first terminal of the second input transistor P2 in the first-stage circuit. The first terminal of the second output transistor P8 is the first output terminal of the second-stage circuit. The second terminal of the second output transistor P8 is connected to the power supply terminal.

[0088] The first terminal of the third output transistor P9 is connected to the first terminal of the first output transistor P7, and the second terminal of the third output transistor P9 is connected to the second terminal of the first output transistor P7.

[0089] The first terminal of the fourth output transistor P10 is connected to the first terminal of the second output transistor P8, and the second terminal of the fourth output transistor P10 is connected to the second terminal of the second output transistor P8.

[0090] The second terminal of the fifth output transistor N3 is connected to the first terminal of the third output transistor P9. The control terminal of the fifth output transistor N3 is connected to the control terminal of the third output transistor P9 and then connected to the first terminal of the fourth output transistor P10.

[0091] The second terminal of the sixth output transistor N4 is connected to the first terminal of the fourth output transistor P10. The control terminal of the sixth output transistor N4 is connected to the control terminal of the fourth output transistor P10 and then connected to the first terminal of the third output transistor P9.

[0092] The control terminal of the seventh output transistor N5 is used to receive the clock signal. The first terminal of the seventh output transistor N5 is connected to the ground terminal. The second terminal of the seventh output transistor N5 is connected to the first terminal of the fifth output transistor N3 and the first terminal of the sixth output transistor N4.

[0093] The seventh output transistor N5 is used to control the operating state of the second-stage circuit. During the reset phase, the seventh output transistor N5 is turned off, and the second-stage circuit stops working. During the sampling phase, regeneration phase, and decision phase, the seventh output transistor N5 is active.

[0094] During the regeneration and decision-making phases, the first output transistor P7 and the second output transistor P8 are used to amplify the differential signal of the first-stage circuit. The third output transistor P9, the fourth output transistor P10, the fifth output transistor N3, and the sixth output transistor N4 form a latch, which is used to amplify and latch the signal at the first terminal of the first output transistor P7 and the second output transistor P8 to output the comparison result.

[0095] The main circuit is connected to the power supply terminal through the third input transistor P3, and to the ground terminal through the seventh input transistor N1 and the eighth input transistor N2. Each current path in the main circuit contains three transistors, for example, the current path formed by the first input transistor P1, the third input transistor P3, and the seventh input transistor N1.

[0096] The second-stage circuit connects to the power supply terminal via any one of the first output transistors P7 to the fourth output transistor P10, and connects to the ground terminal via the seventh output transistor N5. Each current path in the second-stage circuit contains three transistors; for example, the current path formed by the first output transistor P7, the fifth input transistor N3, and the seventh input transistor N5.

[0097] With the above setup, using a first-stage circuit and a second-stage circuit structure, the comparator operates at a lower voltage and has a wider range of applications compared to a comparator using a single-stage structure.

[0098] In one embodiment, the first input transistor P1 to the sixth input transistor P6 are of the same type, and the seventh input transistor N1 and the eighth input transistor N2 are of the same type.

[0099] If the first input transistor P1 to the sixth input transistor P6 are all P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal. If the seventh input transistor N1 and the eighth input transistor N2 are N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0100] In one embodiment, the first input transistor P1 and the second input transistor P2 are the same size, the fourth input transistor P4 and the fifth input transistor P5 are the same size, and the size of the fourth input transistor P4 is less than half the size of the first input transistor P1.

[0101] With the above settings, the influence of the auxiliary circuit can be avoided from being too great, which would cause the first differential signal to be reversed. For example, the first input signal and the first reference signal make the first terminal voltage of the first input transistor P1 greater than the first terminal voltage of the second input transistor P2. Due to the intervention of the second differential signal, the first differential signal is reversed, which means that the first terminal voltage of the first input transistor P1 is less than the first terminal voltage of the second input transistor P2.

[0102] In one embodiment, the first output transistor P7 to the fourth output transistor P10 are of the same type, and the fifth output transistor N3 to the seventh output transistor N5 are of the same type.

[0103] If the first output transistor P7 to the fourth output transistor P10 are all P-type transistors, with the drain of the P-type transistor being the first terminal and the gate of the P-type transistor being the control terminal. If the fifth output transistor N3 to the seventh output transistor N5 are all N-type transistors, with the source of the N-type transistor being the first terminal and the gate of the N-type transistor being the control terminal.

[0104] The principle of this comparator in eliminating inter-symbol interference is described below with reference to Table 2. The setting method of the second reference signal and the second input signal is the same as that in Table 1, and will not be repeated here.

[0105] Table 2 shows the inter-symbol interference situation.

[0106]

[0107] As shown in Table 2, in the first case, inter-symbol interference (ISI) causes the voltages of the first input transistor P1 and the second input transistor P2 to be equal, but the voltage of the fourth input transistor P4 is less than the voltage of the fifth input transistor P5. This results in the voltage at the first output terminal O1 of the first stage circuit being less than the voltage at the second output terminal O2. This is the same result as without ISI, and the ISI is eliminated. It should be noted that, since the size of each transistor in the auxiliary circuit is less than half the size of each transistor in the main circuit, even in the second case, where VP1 < VP2 and VP4 > VP5 (where VP1, VP2, VP4, and VP5 represent the drain voltages of the first input transistor P1, the second input transistor P2, the third input transistor P3, and the fourth input transistor P4, respectively), the voltage pull capability of the fourth input transistor P4 and the fifth input transistor P5 is less than that of the first input transistor P1 and the second input transistor P2. This results in the voltage VO1 at the first output terminal of the first stage circuit still being less than the voltage VO2 at the second output terminal of the first stage circuit. This is the same result as without ISI, and the ISI is eliminated.

[0108] like Figure 6 As shown, an embodiment of this application provides a decision feedback equalization circuit, including the four comparators described in the above embodiment, which are sequentially labeled as first comparator 100, second comparator 200, third comparator 300 and fourth comparator 400.

[0109] Specifically, the third input terminal In2 of the first comparator 100 is connected to the first output terminal P270B of the fourth comparator 400, and the fourth input terminal Vr2 of the first comparator 100 is connected to the second output terminal P270 of the fourth comparator 400. The third input terminal In2 of the second comparator 200 is connected to the first output terminal P0B of the first comparator 100, and the fourth input terminal Vr2 of the second comparator 200 is connected to the second output terminal P0 of the first comparator 100. The third input terminal In2 of the third comparator 300 is connected to the first output terminal P90B of the second comparator 200, and the fourth input terminal Vr2 of the third comparator 300 is connected to the second output terminal P90 of the second comparator 200. The third input terminal In2 of the fourth comparator 400 is connected to the first output terminal P270B of the third comparator 300, and the fourth input terminal Vr2 of the fourth comparator 400 is connected to the second output terminal P270 of the third comparator 300.

[0110] The first input terminal In1 of the first comparator 100 to the fourth comparator 400 all receive the first input signal, and the second input terminal Vref1 of the first comparator 100 to the fourth comparator 400 all receive the first reference signal.

[0111] Assuming that at the previous moment, when the first input signal was greater than the first reference signal, the fourth register 400 output the number "1", at the current moment, the third input terminal In2 of the first register 100 receives a low level, and the fourth input terminal Vr2 of the first register 100 receives a high level. That is, the signal at the third input terminal In2 is less than the signal at the fourth input terminal Vr2. Assuming that the first input signal is also greater than the first reference signal at the current moment, inter-symbol interference will still make the first input signal greater than the first reference signal, and the first register 100 will still output the number "1".

[0112] Assuming that at the previous moment, when the first input signal was greater than the first reference signal, the fourth register 400 output the number "1". At the current moment, the signal at the third input terminal In2 of the first register is less than the signal at the fourth input terminal Vr2. Assuming that the first input signal is less than the first reference signal at the current moment, if inter-symbol interference makes the first input signal equal to or slightly greater than the first reference signal, since the signal at the third input terminal In2 is less than the signal at the fourth input terminal Vr2, the first register 100 will still output the number "0".

[0113] Assuming that at the previous moment, when the first input signal was less than the first reference signal, the fourth register 400 output the number "0". At the current moment, the signal at the third input terminal In2 of the first register 100 is greater than the signal at the fourth input terminal Vr2. Assuming that the first input signal is also less than the first reference signal at the current moment, inter-symbol interference will still cause the first input signal to be less than the first reference signal, and the first register 100 will still output the number "0".

[0114] Assuming that at the previous moment, when the first input signal was less than the first reference signal, the fourth register 400 output the number "0". At the current moment, the signal In2 at the third input terminal of the first register 100 is greater than the signal at the fourth input terminal Vr2. Assuming that the first input signal is greater than the first reference signal at the current moment, if inter-symbol interference makes the first input signal equal to or slightly less than the first reference signal, the first register 100 will still output the number "1" because the signal at the third input terminal is greater than the signal at the fourth input terminal.

[0115] The working principle of the second register 200 to the fourth register 400 is the same as that of the first register 100, and will not be repeated here.

[0116] Figure 6 The decision feedback equalization circuit shown is a first-order circuit. To achieve better elimination of inter-symbol interference, multi-order circuits are usually used. Figure 7 This is a schematic diagram of the effect of a fourth-order decision feedback equalizer circuit. Tap1 to tap4 represent the first-order to fourth-order decision feedback equalizer circuits, respectively. Figure 7As shown in Figure 1, the actual waveform of the first input signal under inter-symbol interference (ISI) is relatively flat when the first input signal switches from high to low level, indicating a possibility of misidentification of the first input signal as high. The fourth-order decision feedback equalization circuit effectively eliminates ISI, resulting in the equivalent waveform of the first input signal input to the equalization circuit, as shown in Figure 2, with a steeper falling edge.

[0117] In one embodiment, the phase of the first clock signal of the first comparator 100 is 90° earlier than the phase of the second clock signal of the second comparator 200, the phase of the first clock signal of the first comparator 100 is 180° earlier than the phase of the third clock signal of the third comparator 300, and the phase of the first clock signal of the first comparator 100 is 270° earlier than the phase of the fourth clock signal of the fourth comparator 400.

[0118] In one embodiment, the voltage flip time from the output of the first comparator 100 to the voltage flip time T at the output of the fourth comparator 400 is... FB Both are less than the time interval 1U1 between the first clock signal and the second clock signal, such as Figure 8 As shown, taking the fourth comparator as an example, when the switching time of the output voltage of the fourth comparator 400 is less than 1U1, 1UI represents the time interval between the first clock signal and the second clock signal. This ensures that when the clock signal of the first comparator 100 arrives, the fourth comparator 400 has already stably output the comparison result, and the fourth comparator 400 maintains the comparison result, so that the first comparator 100 can eliminate inter-symbol interference based on the comparison result of the fourth comparator 400.

[0119] In one embodiment, the decision feedback equalization circuit further includes four registers, labeled sequentially as first register 500, second register 600, third register 700, and fourth register 800. The input of first register 500 is connected to the two outputs of first comparator 100, the input of second register 600 is connected to the two outputs of second comparator 200, the input of third register 700 is connected to the two outputs of third comparator 300, and the input of fourth register 800 is connected to the two outputs of fourth comparator 400. The four registers are used to store the comparison results of the four corresponding comparators: D0 is the result output by first register 500, D90 is the result output by second register 600, D180 is the result output by third register 700, and D270 is the result output by fourth register 800.

[0120] In the above technical solution, the two output terminals of the fourth register are connected to the two input terminals of the first register, and the two output terminals of the first register are connected to the two input terminals of the second register, and so on, to form a decision feedback equalization circuit. The other two input terminals of the four registers receive the first input signal and the first reference signal. Under the control of the output terminal signals of the four registers, the inter-symbol interference caused by the continuous input of the first input signal in the register can be effectively eliminated.

[0121] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0122] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A decision feedback equalization circuit, comprising: The four comparators are sequentially marked as a first comparator, a second comparator, a third comparator and a fourth comparator; Each of the comparators comprises: A first stage circuit comprising a main circuit, an auxiliary circuit and a common circuit, the main circuit and the auxiliary circuit are connected to a power supply end or a ground end, the common circuit is connected to the ground end or the power supply end, the main circuit is used for generating a first differential signal according to a first input signal and a first reference signal in a sampling stage, and the auxiliary circuit is used for generating a second differential signal according to a second input signal and a second reference signal in the sampling stage; A second stage circuit connected to the power supply end and the ground end, and connected to an output end of the first stage circuit, used for amplifying and latching the first differential signal and the second differential signal in a regeneration stage to output a comparison result; The first comparator has a first input end for receiving the first input signal, a second input end for receiving the first reference signal, a third input end directly connected to a first output end of the fourth comparator for receiving the second input signal, and a fourth input end directly connected to a second output end of the fourth comparator for receiving the second reference signal; The second comparator has a first input end for receiving the first input signal, a second input end for receiving the first reference signal, a third input end directly connected to a first output end of the first comparator for receiving the second input signal, and a fourth input end directly connected to a second output end of the first comparator for receiving the second reference signal; The third comparator has a first input end for receiving the first input signal, a second input end for receiving the first reference signal, a third input end directly connected to a first output end of the second comparator for receiving the second input signal, and a fourth input end directly connected to a second output end of the second comparator for receiving the second reference signal; The fourth comparator has a first input end for receiving the first input signal, a second input end for receiving the first reference signal, a third input end directly connected to a first output end of the third comparator for receiving the second input signal, and a fourth input end directly connected to a second output end of the third comparator for receiving the second reference signal.

2. The decision feedback equalization circuit of claim 1, wherein, The first stage circuit and the second stage circuit have the same number of transistors in respective current paths.

3. The decision feedback equalization circuit of claim 2, wherein, The main circuit comprises: A first input transistor having a control end for receiving the first input signal and a first end as a first output end of the main circuit; A second input transistor having a control end for receiving the first reference signal and a first end as a second output end of the main circuit; A third input transistor having a control end for receiving a clock signal, a first end connected to a second end of the first input transistor and a second end of the second input transistor, and a second end connected to a ground end or a power supply end.

4. The decision feedback equalization circuit of claim 3, wherein, The auxiliary circuit comprises at least one equalization module in parallel; each equalization module comprises: A fourth input transistor having a control end for receiving the second input signal and a first end as a first output end of the equalization module; a fifth input transistor, a control terminal of which is arranged to receive the second reference signal, a first terminal of which is arranged as a second output terminal of the equalization module; a sixth input transistor, a control terminal of which is arranged to receive a clock signal, a first terminal of which is connected to a second terminal of the fourth input transistor and a second terminal of the fifth input transistor, and a second terminal of which is arranged to be connected to a ground terminal or a power supply terminal.

5. The decision feedback equalization circuit of claim 4, wherein, The common circuit comprises: a seventh input transistor, a control terminal of which is arranged to receive the clock signal, a first terminal of which is connected to the power supply terminal or the ground terminal, and a second terminal of which is connected to the first terminal of the first input transistor and the first terminal of the fourth input transistor; an eighth input transistor, a control terminal of which is arranged to receive the clock signal, a first terminal of which is connected to the power supply terminal or the ground terminal, and a second terminal of which is connected to the first terminal of the second input transistor and the first terminal of the fifth input transistor.

6. The decision feedback equalization circuit of claim 5, wherein, The first input transistor to the sixth input transistor are of the same type, and the seventh input transistor and the eighth input transistor are of the same type.

7. The decision feedback equalization circuit according to claim 6, wherein: the first input transistor and the second input transistor are of the same size; the fourth input transistor and the fifth input transistor are of the same size; the fourth input transistor is smaller than one half of the size of the first input transistor.

8. The decision feedback equalization circuit according to claim 7, wherein: if the first input transistor to the sixth input transistor are all N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal; if the seventh input transistor and the eighth input transistor are both P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal; or if the first input transistor to the sixth input transistor are all P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal; if the seventh input transistor and the eighth input transistor are both N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal. The second-stage circuit comprises:

9. The decision feedback equalization circuit of claim 1, wherein, a first output transistor, a control terminal of which is arranged as a first input terminal of the second-stage circuit, a first terminal of which is arranged as a first output terminal of the second-stage circuit, and a second terminal of which is connected to the ground terminal or the power supply terminal; a second output transistor, a control terminal of which is arranged as a second input terminal of the second-stage circuit, a first terminal of which is arranged as a second output terminal of the second-stage circuit, and a second terminal of which is connected to the ground terminal or the power supply terminal; a third output transistor, a first terminal of which is connected to the first terminal of the first output transistor, and a second terminal of which is connected to the second terminal of the first output transistor; a fourth output transistor, a first terminal of which is connected to the first terminal of the second output transistor, and a second terminal of which is connected to the second terminal of the second output transistor; a fifth output transistor, a second terminal of which is connected to the first terminal of the third output transistor, a control terminal of which is connected to the control terminal of the third output transistor, and a control terminal of which is further connected to the first terminal of the fourth output transistor; ​ a sixth output transistor, a second end of which is connected to a first end of the fourth output transistor, a control end of which is connected to a control end of the fourth output transistor, and the control end of which is also connected to a first end of the third output transistor; a seventh output transistor, a control end of which is configured to receive a clock signal, a first end of which is connected to a power supply end or a ground end, and a second end of which is connected to a first end of the fifth output transistor and a first end of the sixth output transistor.

10. The decision feedback equalization circuit of claim 9, wherein: the first output transistor to the fourth output transistor are all N-type transistors, a drain of the N-type transistor being the first end, and a gate of the N-type transistor being the control end; the fifth output transistor to the seventh output transistor are all P-type transistors, a source of the P-type transistor being the first end, and a gate of the P-type transistor being the control end.

11. The decision feedback equalization circuit of claim 9, wherein: the first output transistor to the fourth output transistor are all P-type transistors, a drain of the P-type transistor being the first end, and a gate of the P-type transistor being the control end; the fifth output transistor to the seventh output transistor are all N-type transistors, a source of the N-type transistor being the first end, and a gate of the N-type transistor being the control end.

12. The decision feedback equalization circuit of claim 1, wherein: a phase of the first clock signal of the first comparator is 90° earlier than a phase of the second clock signal of the second comparator; a phase of the first clock signal of the first comparator is 180° earlier than a phase of the third clock signal of the third comparator; a phase of the first clock signal of the first comparator is 270° earlier than a phase of the fourth clock signal of the fourth comparator.

13. The decision feedback equalization circuit of claim 12, wherein: a voltage flipping time of the output end of the first comparator to a voltage flipping time of the output end of the fourth comparator are all less than a time interval between the first clock signal and the second clock signal.

14. The decision feedback equalization circuit of any one of claims 1 to 13, wherein, further comprising: four registers, sequentially labeled as a first register, a second register, a third register, and a fourth register; an input end of the first register is connected to two output ends of the first comparator; an input end of the second register is connected to two output ends of the second comparator; an input end of the third register is connected to two output ends of the third comparator; an input end of the fourth register is connected to two output ends of the fourth comparator.

Images