Perovskite crystalline silicon stacked solar cell crystalline silicon bottom cell manufacturing method and cell

Abstract

The present invention discloses a method for manufacturing a crystalline silicon bottom cell of a perovskite crystalline silicon stacked solar cell and a cell, and relates to the field of solar energy technology. The method comprises: preparing a silicon wafer substrate; preparing a first passivation layer on the upper surface of the silicon wafer substrate; preparing a second passivation layer on the lower surface of the silicon wafer substrate; preparing a carrier selective transport layer on the lower surface of the second passivation layer; preparing an anti-reflection layer on the lower surface of the carrier selective transport layer; and preparing a metal bottom electrode layer on the lower surface of the anti-reflection layer. The method for manufacturing a crystalline silicon bottom cell of a perovskite crystalline silicon stacked solar cell and a cell of the present invention reduce the input of indium materials in the crystalline silicon bottom cell, thereby meeting the application requirements of the perovskite crystalline silicon stacked solar cell.

Description

Technical Field

[0001] The present invention relates to the field of solar energy technology, and in particular to a method for manufacturing a crystalline silicon bottom cell of a perovskite crystalline silicon stacked solar cell and a cell. Background Art

[0002] Solar cells are one of the most important technologies driving the renewable energy revolution. Today, research on solar cells has made significant progress in conversion efficiency. However, it is still necessary to improve the efficiency of photovoltaic modules. Higher efficiency photovoltaic modules can make the system more compact, thereby reducing the cost of the system.

[0003] Generally speaking, it is necessary to reduce absorption losses while maintaining or increasing the voltage of photovoltaic cells. In addition, single-junction solar cells have an efficiency ceiling (Shockley-Queisser limit), and the efficiency of single-junction cells cannot exceed this limit. In view of this, one of the strategies to improve the efficiency of photovoltaic cells is to use stacked cells.

[0004] Tandem cells include multiple (≥2) subcells composed of materials with different absorption characteristics, allowing more efficient use of light energy in different bands from the solar spectrum. In particular, tandem cells combine an upper solar cell with a high-efficiency wide bandgap with a lower solar cell with a low bandgap to improve overall efficiency. The tandem allows high-energy photons to be absorbed in the upper subcell (top cell), which can generate a high voltage to reduce the heat loss of high-energy photons; and allows the lower subcell (bottom cell) to absorb low-energy photons (which have been transmitted through the upper subcell), which helps to collect energy from photons in different bands.

[0005] Due to their bandgap characteristics, crystalline silicon solar cells are often used as low-level subcells in stacks. Silicon heterojunction lower subcells dominate stack research. In order to develop stack structures suitable for commercial-scale production, it is best to optimize the performance and cost of the lower subcell (i.e., crystalline silicon bottom cell), as well as its compatibility with subsequent process steps to form the stack structure. For example, there are restrictions on the consumption of indium. The distribution of indium in the earth's crust is relatively small and dispersed. It is listed as a rare metal, which will affect the use of perovskite crystalline silicon stacked solar cells. The crystalline silicon bottom cell in the perovskite crystalline silicon stacked solar cell involves the use of indium materials, so it is very necessary to adopt different crystalline silicon bottom cell solutions. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the prior art. The present invention provides a method for manufacturing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell and a cell, which reduces the input of indium material in the crystalline silicon bottom cell, thereby meeting the application requirements of the perovskite crystalline silicon tandem solar cell.

[0007] In order to solve the above problems, the present invention proposes a method for manufacturing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell, the method comprising:

[0008] Prepare a silicon wafer substrate, wherein the thickness of the silicon wafer substrate is between 100 μm and 500 μm, the silicon wafer substrate is made of N-type silicon or P-type silicon, and the resistivity of the silicon wafer substrate is between 0.1 ohm·cm and 20 ohm·cm;

[0009] A first passivation layer is prepared on the upper surface of the silicon wafer substrate, wherein the first passivation layer comprises a first doped polysilicon layer and a first tunneling silicon oxide layer, wherein the thickness of the first doped polysilicon layer is between 0-135 nm, and the thickness of the first tunneling silicon oxide layer is between 0-15 nm;

[0010] Preparing a second passivation layer on the lower surface of the silicon wafer substrate, wherein the thickness of the second passivation layer is between 0-135 nm;

[0011] A carrier selective transport layer is formed on the lower surface of the second passivation layer, wherein the thickness of the carrier selective transport layer is between 0 and 200 nm;

[0012] An anti-reflection layer is prepared on the lower surface of the carrier selective transport layer, wherein the thickness of the anti-reflection layer is between 0-300 nm;

[0013] A metal bottom electrode layer is prepared on the lower surface of the anti-reflection layer, and the thickness of the metal bottom electrode layer is 1-2000 μm.

[0014] The upper surface of the silicon wafer substrate is prepared with a velvet structure or a polished surface structure, and the lower surface of the silicon wafer substrate is prepared with a velvet structure or a polished surface structure;

[0015] When preparing the velvet structure, it is prepared through an alkali velveting process, and the surface roughness of the velvet structure is Ra<2; when preparing the polished surface structure, it is prepared through an acid polishing, or alkali polishing, or mechanical polishing process, and the surface roughness of the polished surface structure is Ra<0.2.

[0016] The step of preparing a first passivation layer on the upper surface of the silicon wafer substrate comprises:

[0017] When preparing the first passivation layer based on the N-type doped polysilicon layer, the thickness of the N-type doped polysilicon layer in the first passivation layer is controlled to be 0-120nm, and the doping concentration is 8*10 18 cm -3 Up to 1.5*10 21 cm -3 , the square resistance is 20-150Ω / □; or when the first passivation layer is prepared based on the P-type doped polysilicon layer, the thickness of the P-type doped polysilicon layer in the first passivation layer is controlled to be 0-120nm, and the doping concentration is 8*1018 cm -3 Up to 3*10 21 cm -3 , square resistance is 20-150Ω / □;

[0018] When preparing the first tunneling silicon oxide layer, the thickness of the first tunneling silicon oxide layer is controlled to be within a range of 0-15 nm.

[0019] The step of preparing a second passivation layer on the lower surface of the silicon wafer substrate comprises:

[0020] When the first passivation layer is prepared based on an N-type doped polysilicon layer, the second passivation layer is prepared based on a P-type doped polysilicon layer or a P-type diffusion doped layer, and the square resistance of the N-type doped polysilicon layer or the N-type diffusion doped layer is 20-150Ω / □; or when the first passivation layer is prepared based on a P-type doped polysilicon layer, the second passivation layer is prepared based on an N-type doped polysilicon layer or an N-type diffusion doped layer, and the square resistance of the N-type doped polysilicon layer or the N-type diffusion doped layer is 20-150Ω / □.

[0021] The step of preparing a second passivation layer on the lower surface of the silicon wafer substrate comprises:

[0022] When preparing the second passivation layer based on the N-type doped polysilicon layer, the thickness of the N-type doped polysilicon layer in the second passivation layer is controlled to be 0-120nm, and the doping concentration is 8*10 18 cm -3 Up to 1.5*10 21 cm -3 , the square resistance is 20-150Ω / □; or when the second passivation layer is prepared based on the P-type doped polysilicon layer, the thickness of the P-type doped polysilicon layer in the second passivation layer is controlled to be 0-120nm, and the doping concentration is 8*10 18 cm -3 Up to 3*10 21 cm -3 , square resistance is 20-150Ω / □;

[0023] When preparing the second tunneling silicon oxide layer, the thickness of the second tunneling silicon oxide layer is controlled to be within a range of 0-15 nm.

[0024] The step of preparing the carrier selective transport layer on the lower surface of the second passivation layer comprises: preparing the carrier selective transport layer by ALD or PVD;

[0025] The carrier selective transport layer includes an electron selective transport layer or a hole selective transport layer. The preparation material of the electron selective transport layer includes one or more of ZnO, TaOx, TiOx, SnOx, TiNx, ZrO2, TiSnOx, SnZnOx and their derivatives; the preparation material of the hole selective transport layer includes one or more of MoOx, WOx, VOx, Cu2O, CuI and their derivatives.

[0026] Correspondingly, the present invention further provides a crystalline silicon bottom cell, which is applied to a perovskite crystalline silicon stacked solar cell, and the crystalline silicon bottom cell comprises:

[0027] A silicon wafer substrate, wherein the thickness of the silicon wafer substrate is between 100 μm and 500 μm, the silicon wafer substrate is made of N-type silicon or P-type silicon, and the resistivity of the silicon wafer substrate is between 0.1 ohm·cm and 20 ohm·cm;

[0028] A first passivation layer, the first passivation layer is located on the upper surface of the silicon wafer substrate, the first passivation layer includes a doped polysilicon layer and a first tunneling silicon oxide layer, the thickness of the first passivation layer is between 0-135 nm, and the thickness of the first tunneling silicon oxide layer is between 0-15 nm;

[0029] A second passivation layer, wherein the second passivation layer is located on the lower surface of the silicon wafer substrate, and the thickness of the second passivation layer is between 0-135 nm;

[0030] A carrier selective transport layer, the carrier selective transport layer is located on the lower surface of the carrier selective transport layer of the second passivation layer, and the thickness of the carrier selective transport layer is between 0-200nm;

[0031] An anti-reflection layer, the anti-reflection layer is located on the lower surface of the carrier selective transport layer, and the thickness of the anti-reflection layer is between 0-300nm;

[0032] A metal bottom electrode layer is located on the lower surface of the anti-reflection layer, and the thickness of the metal bottom electrode layer is 1-2000 μm.

[0033] When the first passivation layer is prepared based on the N-type doped polysilicon layer, the thickness of the N-type doped polysilicon layer in the first passivation layer is 0-120 nm, and the doping concentration is 8*10 18 cm -3 Up to 1.5*10 21 cm -3 ; or when the first passivation layer is prepared based on the P-type doped polysilicon layer, the thickness of the P-type doped polysilicon layer in the first passivation layer is 0-120nm, and the doping concentration is 8*10 18 cm-3 Up to 3*10 21 cm -3 ;

[0034] The thickness of the first tunneling silicon oxide layer of the first passivation layer is 0-15 nm.

[0035] When the first passivation layer includes an N-type doped polysilicon layer, the second passivation layer includes a P-type doped polysilicon layer or a P-type diffused doped layer; the thickness of the N-type doped polysilicon layer in the second passivation layer is 0-120nm, and the doping concentration is 8*10 18 cm -3 Up to 1.5*10 21 cm -3 ;

[0036] Alternatively, when the first passivation layer includes a P-type doped polysilicon layer, the second passivation layer is prepared based on an N-type doped polysilicon layer or an N-type diffused doped layer; the thickness of the P-type doped polysilicon layer in the second passivation layer is 0-120 nm, and the doping concentration is 8*10 18 cm -3 Up to 3*10 21 cm -3 ;

[0037] The thickness of the second tunneling silicon oxide layer is 0-15 nm.

[0038] The metal bottom electrode layer is a full coverage structure or a gate line structure.

[0039] The crystalline silicon bottom cell and its manufacturing method in the embodiment of the present invention can reduce the use of indium materials, so that the crystalline silicon bottom cell can be used as a part of the perovskite crystalline silicon stacked solar cell, thereby promoting the use of the perovskite crystalline silicon stacked solar cell, and greatly improving the commercial efficiency. By adding an anti-reflection layer, the absorption capacity of the silicon crystalline bottom cell is enhanced. The crystalline silicon bottom cells of this structure are all made of conventional materials, which can reduce the use of precious metal indium materials, reduce the cost of crystalline silicon bottom cells, popularize the application of crystalline silicon bottom cells in perovskite crystalline silicon stacked solar cells, and make the subsequent process steps of forming the stacked structure more compatible. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1is a first structural schematic diagram of a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell in an embodiment of the present invention;

[0042] Figure 2 2 is a schematic diagram of the second structure of a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell in an embodiment of the present invention;

[0043] Figure 3 is a third structural schematic diagram of a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell in an embodiment of the present invention;

[0044] Figure 4 4 is a schematic diagram of the structure of the crystalline silicon bottom cell of the perovskite crystalline silicon tandem solar cell in an embodiment of the present invention;

[0045] Figure 5 is a fifth structural schematic diagram of a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell in an embodiment of the present invention;

[0046] Figure 6 is a sixth structural schematic diagram of a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell in an embodiment of the present invention;

[0047] Figure 7 It is a flow chart of a method for manufacturing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell in an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] Specifically, Figure 1 The first structural schematic diagram of the crystalline silicon bottom cell of the perovskite crystalline silicon tandem solar cell in the embodiment of the present invention is shown. Figure 2 The second structural schematic diagram of the crystalline silicon bottom cell of the perovskite crystalline silicon stacked solar cell in the embodiment of the present invention is shown, and the crystalline silicon bottom cell includes: a silicon wafer substrate, a first passivation layer, a second passivation layer, a carrier selective transport layer, an anti-reflection layer, and a metal bottom electrode layer, wherein:

[0050] The silicon wafer substrate is made of N-type silicon or P-type silicon, the upper surface and the lower surface of the silicon wafer substrate are velvet structures or polished surface structures, the upper surface of the silicon wafer substrate is provided with a first passivation layer having a passivation effect, and the lower surface is provided with a second passivation layer having a passivation effect;

[0051] A carrier selective transport layer is arranged on the lower surface of the second passivation layer, an anti-reflection layer is arranged on the lower surface of the carrier selective transport layer, and a metal bottom electrode layer is arranged on the lower surface of the anti-reflection layer.

[0052] The metal bottom electrode layer can be a full coverage structure or a gate line structure, such as Figure 1 The metal bottom electrode layer shown in the figure is a fully covered structure. Figure 2 Shown is the metal electrode layer of the gate line structure.

[0053] The first passivation layer here includes a doped polysilicon layer and a first tunneling silicon oxide layer, and the second passivation layer includes a doped polysilicon layer and a second tunneling silicon oxide layer, or the second passivation layer includes a diffusion doping layer. Here, the polarity of the first passivation layer is opposite to that of the second passivation layer, that is, when the first passivation layer includes an N-type doped polysilicon layer, the second passivation layer includes a P-type doped polysilicon layer or a P-type diffusion doping layer, and the square resistance of the P-type doped polysilicon layer or the P-type diffusion doping layer is 20-150Ω / □; or when the first passivation layer includes a P-type doped polysilicon layer, the second passivation layer includes an N-type doped polysilicon layer or an N-type diffusion doping layer, and the square resistance of the N-type doped polysilicon layer or the N-type diffusion doping layer is 20-150Ω / □. Here, the doped polysilicon layer can be prepared by PECVD or LPCVD process, and the diffusion doping layer can be prepared by a tubular diffusion furnace.

[0054] Figure 3 A third structural schematic diagram of the crystalline silicon bottom cell of the perovskite crystalline silicon stacked solar cell in an embodiment of the present invention is shown, wherein the first passivation layer here includes an N-type doped polysilicon layer and a first tunneling silicon oxide layer, and the second passivation layer here includes a P-type doped polysilicon layer and a second tunneling silicon oxide layer, wherein: the first tunneling silicon oxide layer is located between the N-type doped polysilicon layer and the silicon wafer substrate, and the second tunneling silicon oxide layer is located between the P-type doped polysilicon layer and the silicon wafer substrate.

[0055] Figure 4 A fourth structural schematic diagram of a perovskite crystalline silicon stacked solar cell and a crystalline silicon bottom cell in an embodiment of the present invention is shown, wherein the first passivation layer includes a P-type doped polysilicon layer and a first tunneling silicon oxide layer, and the second passivation layer includes an N-type doped polysilicon layer and a second tunneling silicon oxide layer, wherein: the first tunneling silicon oxide layer is located between the P-type doped polysilicon layer and the silicon wafer substrate, and the second tunneling silicon oxide layer is located between the N-type doped polysilicon layer and the silicon wafer substrate.

[0056] Figure 5 A fifth structural schematic diagram of the crystalline silicon bottom cell of the perovskite crystalline silicon stacked solar cell in an embodiment of the present invention is shown, wherein the first passivation layer here includes an N-type doped polysilicon layer and a first tunneling silicon oxide layer, and the second passivation layer here includes a P-type diffused doped layer, wherein: the first tunneling silicon oxide layer is located between the N-type doped polysilicon layer and the silicon wafer substrate.

[0057] Figure 6 A fifth structural schematic diagram of the crystalline silicon bottom cell of the perovskite crystalline silicon stacked solar cell in an embodiment of the present invention is shown, wherein the first passivation layer here includes a P-type doped polysilicon layer and a first tunneling silicon oxide layer, and the second passivation layer here includes an N-type diffused doped layer, wherein: the first tunneling silicon oxide layer is located between the P-type doped polysilicon layer and the silicon wafer substrate.

[0058] It should be noted that the carrier selective transport layer includes Al 2 O 3 Material, anti-reflection layer is SiN x (Silicon Nitride) or SiN x O y (silicon oxynitride) and other materials.

[0059] The first passivation layer is a POLO structure (poly-SionOxide) formed by combining doped polysilicon and tunneling silicon oxide, and the second passivation layer can be a POLO structure formed by combining doped polysilicon and tunneling silicon oxide, or a diffusion doping layer formed by diffusion.

[0060] There are several ways to prepare doped polysilicon layers:

[0061] 1. Use LPCVD to prepare undoped polysilicon layer + ion implantation doping;

[0062] 2. Use LPCVD to prepare undoped polysilicon layer + thermal diffusion doping;

[0063] 3. In-situ doping LPCVD to prepare doped polysilicon layer;

[0064] 4. Preparation of doped polysilicon layer by PECVD;

[0065] 5. Prepare doped polysilicon layer by PEALD.

[0066] The diffuse doping layer can be prepared by: thermal diffusion or ion implantation.

[0067] It should be noted that the thickness of the silicon wafer substrate is 100 μm-500 μm, and the resistivity is between 0.1 ohm·cm and 20 ohm·cm. The upper surface of the silicon wafer is a velvet structure or a polished surface structure, and the lower surface is a velvet structure or a polished surface structure.

[0068] It should be noted that the velvet structure can be prepared by an alkali velveting process, and the surface roughness of the velvet structure is Ra<2. The chemicals used in the alkali velveting process are one or more of NaOH, KOH, and a surfactant, and the process time is 0-60 minutes.

[0069] It should be noted that the polished surface structure, ie the plane structure, can be prepared by acid polishing, alkali polishing, or mechanical polishing, and its surface roughness Ra<0.2.

[0070] It should be noted that the material of the carrier selective transport layer is one or more of SiOx, Al2O3, AlN, InSb, SiC, TiOx, and TiN, and the passivation layer can be a single layer or a stack of dielectric layers, such as SiOx / AlOx, with a thickness of 0-200nm. The carrier selective transport layer here can be prepared by ALD or PECVD.

[0071] It should be noted that the material used to make the anti-reflection layer is Al 2 O 3 、SiN x 、SiN x O y MgF 2 , LiF, the anti-reflection layer can be a single layer or a stack of dielectric layers, such as SiO x or SiN x , thickness is 0-300nm.

[0072] The anti-reflection layer extends between the portions of the upper electrode. The anti-reflection layer can reduce the reflection on the surface of the silicon substrate. The AR coating in the anti-reflection layer is formed using two or more sub-layers, one of which is a barrier layer, and the barrier layer can have anti-reflection properties. That is, the AR coating can include a stack including a dielectric layer and a barrier layer. In a specific implementation process, the TiO x (barrier layer) and SiO x The stack can provide AR functionality. In a specific implementation, the stack can also be used to form an anti-reflection layer, that is, the AR coating can optimize the thickness of the coating and / or barrier layer to enhance the absorption of the silicon solar cell. Other sublayers forming the AR coating can be deposited on top of the barrier layer. Between the independent elements of the electrode, the barrier layer will be deposited between the electrode and the inner layer of the cell, and other sublayers will extend between the electrode portion above the barrier layer. The anti-reflection layer can include SiN x (Silicon Nitride) or SiN x O y (Silicon Oxynitride).

[0073] It should be noted that the thickness of the P-type doped polysilicon layer is 0-120nm, and the doping concentration is 8*10 18 cm -3 Up to 3*10 21 cm -3 .

[0074] It should be noted that the P-type doped polysilicon layer can be prepared by PECVD in-situ doping, LPCVD in-situ doping or thermal diffusion process.

[0075] The thermal diffusion process here is to dope a P-type polysilicon layer with a P-type dopant to produce a P-type doped layer; and to configure a precursor back-to-back with another precursor to prepare a P-type doped polysilicon layer.

[0076] The thermal diffusion process involves the use of high temperatures to increase the diffusion rate to accelerate the required reactions of the P-type doped polysilicon layer, thereby forming the required P-type doped polysilicon layer in a shorter time. The thermal diffusion process not only accelerates the required reactions, but also accelerates the undesirable reactions. During the preparation process, part of the precursor is contaminated by dopants, and the silicon-based charge transport layer obtains its transport properties by adding specific dopants (P-type) to silicon. Here, the P-type doped polysilicon layer is prepared based on boron diffusion. The boron diffusion process requires higher temperatures for diffusion, and the borosilicate glass formed can cause the layer to lose its specific charge transport properties. Here, the borosilicate glass-like BSG layer can be removed by wet chemical methods, using NaOH or KOH solution to etch for 10-100 minutes. Placing the precursor back-to-back with another precursor in a diffusion furnace can also largely avoid the formation of such BSG layers.

[0077] It should be noted that the thickness of the N-type doped polysilicon layer is 0-120nm, and the doping concentration is 8*10 18 cm -3 Up to 1.5*10 21 cm -3 .

[0078] The N-type doped polysilicon layer here can be prepared by PECVD in-situ doping, LPCVD in-situ doping or thermal diffusion process.

[0079] The thermal diffusion process here is to dope an N-type polysilicon layer with an N-type dopant to generate an N-type doped layer; and to configure a precursor and another precursor back to back to prepare an N-type doped polysilicon layer.

[0080] The thermal diffusion process involves the use of high temperatures to increase the diffusion rate to speed up the desired reaction, thereby forming the desired N-type doped polysilicon layer in a shorter time. The thermal diffusion process not only accelerates the desired reaction, but also accelerates the undesirable reactions. During the preparation process, part of the precursor is contaminated with dopants. The silicon-based charge transport layer obtains its transport properties by adding specific dopants (N-type) to silicon. Here, the N-type doped polysilicon layer is prepared based on boron diffusion. The boron diffusion process requires higher temperatures for diffusion, and the borosilicate glass formed can cause the layer to lose its specific charge transport properties. Here, the borosilicate glass-like BSG layer can be removed by wet chemical methods, using NaOH or KOH solution to etch for 10-100 minutes. Placing the precursor back-to-back with another precursor in the diffusion furnace can also largely avoid the formation of such BSG layers.

[0081] Here, the thickness of the first tunneling silicon oxide layer and the second tunneling silicon oxide layer is 0-15 nm. Here, the silicon oxide layer can be prepared by thermal oxidation, wet chemical method, wet oxygen method, or by applying ultraviolet radiation in an ozone environment.

[0082] The material of the metal bottom electrode layer is one or more of aluminum, silver, titanium, palladium, nickel, chromium, tin or copper. The thickness of the metal bottom electrode layer is 1-2000μm. The metal bottom electrode layer can be prepared by one or more processes of PVD, screen printing and electroplating.

[0083] The method for manufacturing a crystalline silicon bottom cell of a perovskite crystalline silicon stacked solar cell involved in an embodiment of the present invention comprises: preparing a first passivation layer on the upper surface of a silicon wafer substrate, and preparing a second passivation layer on the lower surface of the silicon wafer substrate, the surface of the silicon wafer substrate has a velvet structure or a polished surface structure, the thickness of the silicon wafer substrate is controlled between 100 μm and 500 μm, and the resistivity of the silicon wafer substrate is between 0.1 ohm·cm and 20 ohm·cm; preparing a carrier selective transport layer on the lower surface of the second passivation layer, the thickness of the carrier selective transport layer is controlled between 0 nm and 300 nm; preparing an anti-reflection layer on the lower surface of the carrier selective transport layer, the thickness of the anti-reflection layer is controlled between 0 and 300 nm; and preparing a metal bottom electrode layer on the lower surface of the anti-reflection layer.

[0084] Specifically, Figure 7 The flowchart of the method for manufacturing the crystalline silicon bottom cell of the perovskite crystalline silicon tandem solar cell in the embodiment of the present invention is shown, which comprises the following steps:

[0085] S701, preparing a silicon wafer substrate;

[0086] The silicon wafer substrate is made of N-type silicon or P-type silicon, and a velvet surface structure or a polished surface structure is prepared on the upper surface and the lower surface of the silicon wafer substrate.

[0087] Here it is necessary to control the thickness of the silicon wafer substrate between 100μm-500μm, for example, the thickness can be: 100μm, 150μm, 200μm, 300μm, 400μm, 500μm, etc., and control the resistivity of the silicon wafer substrate between 0.1ohm·cm and 20ohm·cm, for example, the resistivity can be: 0.1ohm·cm, 0.2ohm·cm, 0.5ohm·cm, 1ohm·cm, 2ohm·cm, 5ohm·cm, 10ohm·cm, 15ohm·cm, 20ohm·cm, etc.

[0088] The velvet structure can be prepared by an alkali velveting process, and the surface roughness of the velvet structure is Ra<2. The chemicals used in the alkali velveting process are one or more of NaOH, KOH, and a surfactant, and the process time is 0-60 minutes.

[0089] When preparing the polished surface structure, that is, the plane structure, it can be prepared by acid polishing, alkali polishing, or mechanical polishing process, and the surface roughness of the polished surface structure, that is, the plane structure, Ra<0.2.

[0090] S702, preparing a first passivation layer on the upper surface of the silicon wafer substrate;

[0091] The first passivation layer includes a doped polysilicon layer and a first tunneling silicon oxide layer, and the doped polysilicon layer and the first tunneling silicon oxide layer need to be prepared here. The first tunneling silicon oxide layer can be prepared on the upper surface of the silicon wafer substrate first, and then the doped polysilicon layer of the first passivation layer can be prepared on the upper surface of the first tunneling silicon oxide layer; or after the first passivation layer is prepared based on the first passivation layer doped polysilicon layer and the first tunneling silicon oxide layer, the first passivation layer is prepared on the upper surface of the silicon wafer substrate. The thickness of the first passivation layer is any value between 0-135nm.

[0092] When preparing the first passivation layer based on the N-type doped polysilicon layer, the thickness of the N-type doped polysilicon layer is controlled to be 0-120nm, and the doping concentration is 8*10 18 cm -3 Up to 1.5*10 21 cm -3 , the square resistance is 20-150Ω / □. The N-type doped polysilicon layer here can be prepared by PECVD in-situ doping, LPCVD in-situ doping or thermal diffusion process. The thermal diffusion process here is to dope the N-type polysilicon layer with an N-type dopant to produce an N-type doped layer; and to configure the precursor back-to-back with another precursor to prepare an N-type doped polysilicon layer.

[0093] When preparing the first passivation layer based on the P-type doped polysilicon layer, the thickness of the P-type doped polysilicon layer is controlled to be 0-120nm, and the doping concentration is 8*1018 cm -3 Up to 3*10 21 cm -3 , square resistance is 20-150Ω / □, and the P-type doped polysilicon layer can be prepared by PECVD in-situ doping, LPCVD in-situ doping or thermal diffusion process. The thermal diffusion process here is to dope the P-type polysilicon layer with a P-type dopant to produce a P-type doped layer; and to configure a precursor back-to-back with another precursor to prepare a P-type doped polysilicon layer.

[0094] Here, the thickness of the first tunneling silicon oxide layer needs to be controlled within a range of 0-15 nm, and the thickness of the first tunneling silicon oxide layer can be 0.2 nm, 0.5 nm, 1 nm, 3 nm, 5 nm, 8 nm, 10 nm, 11 nm, 15 nm, etc. The first tunneling silicon oxide layer can be prepared by thermal oxidation, wet chemical method, wet oxygen method, or by applying ultraviolet radiation in an ozone environment.

[0095] S703, preparing a second passivation layer on the lower surface of the silicon wafer substrate;

[0096] The second passivation layer here may include a doped polysilicon layer and a second tunneling silicon oxide layer, and it is necessary to prepare a doped polysilicon layer and a first tunneling silicon oxide layer. The second tunneling silicon oxide layer may be prepared on the lower surface of the silicon wafer substrate first, and then the doped polysilicon layer of the second passivation layer may be prepared on the lower surface of the second tunneling silicon oxide layer; or after preparing the second passivation layer based on the second passivation layer doped polysilicon layer and the second tunneling silicon oxide layer, the second passivation layer may be prepared on the upper surface of the silicon wafer substrate. The doped polysilicon layer here may be a P-type doped polysilicon layer or an N-type doped polysilicon layer.

[0097] The second passivation layer here includes a diffusion doping layer, and the diffusion doping layer here can be a P-type diffusion doping layer or an N-type diffusion doping layer.

[0098] When the first passivation layer is prepared based on an N-type doped polysilicon layer, the second passivation layer is prepared based on a P-type doped polysilicon layer or a P-type diffusion doped layer, and the square resistance of the P-type doped polysilicon layer or the P-type diffusion doped layer is 20-150Ω / □; when the first passivation layer is prepared based on a P-type doped polysilicon layer, the second passivation layer is prepared based on an N-type doped polysilicon layer or an N-type diffusion doped layer, and the square resistance of the N-type doped polysilicon layer or the N-type diffusion doped layer is 20-150Ω / □. Here, it is necessary to control the polarity of the first passivation layer to be opposite to that of the second passivation layer.

[0099] When preparing the second passivation layer based on the N-type doped polysilicon layer, the thickness of the N-type doped polysilicon layer is controlled to be 0-120nm, and the doping concentration is 8*10 18 cm -3 Up to 1.5*1021 cm -3 The N-type doped polysilicon layer here can be prepared by PECVD in-situ doping, LPCVD in-situ doping or thermal diffusion process. The thermal diffusion process here is to dope the N-type polysilicon layer with N-type dopants to produce an N-type doped layer; and to configure a precursor back to back with another precursor to prepare an N-type doped polysilicon layer.

[0100] When preparing the second passivation layer based on the P-type doped polysilicon layer, the thickness of the P-type doped polysilicon layer is controlled to be 0-120nm, and the doping concentration is 8*10 18 cm -3 Up to 3*10 21 cm -3 The P-type doped polysilicon layer can be prepared by PECVD in-situ doping, LPCVD in-situ doping or thermal diffusion process. The thermal diffusion process here is to dope the P-type polysilicon layer with a P-type dopant to produce a P-type doped layer; and to configure a precursor back-to-back with another precursor to prepare a P-type doped polysilicon layer.

[0101] Here, the thickness of the second tunneling silicon oxide layer needs to be controlled within a range of 0-15 nm, and the thickness of the second tunneling silicon oxide layer can be 0.2 nm, 0.5 nm, 1 nm, 3 nm, 5 nm, 8 nm, 10 nm, 11 nm, 15 nm, etc. The second tunneling silicon oxide layer can be prepared by thermal oxidation, wet chemical method, wet oxygen method, or by applying ultraviolet radiation in an ozone environment.

[0102] Here, an N-type diffusion doping layer or a P-type diffusion doping layer can be prepared by thermal diffusion.

[0103] S704, preparing a carrier selective transport layer on the lower surface of the second passivation layer;

[0104] The material of the carrier selective transport layer is one or more of SiOx, Al2O3, AlN, InSb, SiC, TiOx, and TiN. The passivation layer can be a single layer or a stack of dielectric layers, such as SiOx / AlOx, with a thickness of 0-200nm.

[0105] The charge carrier selective transport layer here can be prepared by ALD or PECVD, that is, the charge carrier selective transport layer is prepared by ALD or PECVD.

[0106] S705, preparing an anti-reflection layer on the lower surface of the carrier selective transport layer;

[0107] The anti-reflection layer is made of Al 2 O 3 、SiN x 、SiN x Oy MgF 2 , LiF, the anti-reflection layer can be a single layer or a stack of dielectric layers, such as SiO x or SiN x , thickness is 0-300nm.

[0108] The anti-reflection layer extends between the portions of the upper electrode. The anti-reflection layer can reduce the reflection on the surface of the silicon substrate. The AR coating in the anti-reflection layer is formed using two or more sub-layers, one of which is a barrier layer, and the barrier layer can have anti-reflection properties. That is, the AR coating can include a stack including a dielectric layer and a barrier layer. In a specific implementation process, the TiO x (barrier layer) and SiO x The stack can provide AR functionality. In a specific implementation, the stack can also be used to form an anti-reflection layer, that is, the AR coating can optimize the thickness of the coating and / or barrier layer to enhance the absorption of the silicon solar cell. Other sublayers forming the AR coating can be deposited on top of the barrier layer. Between the independent elements of the electrode, the barrier layer will be deposited between the electrode and the inner layer of the cell, and other sublayers will extend between the electrode portion above the barrier layer. The anti-reflection layer can include SiN x (Silicon Nitride) or SiN x O y (Silicon Oxynitride).

[0109] S706, preparing a metal bottom electrode layer on the lower surface of the anti-reflection layer.

[0110] The material of the metal bottom electrode layer is one or more of aluminum, silver, titanium, palladium, nickel, chromium, tin or copper. The thickness of the metal bottom electrode layer is 1-2000μm. The metal bottom electrode layer can be prepared by one or more processes of PVD, screen printing and electroplating.

[0111] The crystalline silicon bottom cell and its manufacturing method in the embodiment of the present invention can reduce the use of indium materials, so that the crystalline silicon bottom cell can be used as a part of the perovskite crystalline silicon stacked solar cell, thereby promoting the use of the perovskite crystalline silicon stacked solar cell, and greatly improving the commercial efficiency. By adding an anti-reflection layer, the absorption capacity of the silicon crystalline bottom cell is enhanced. The crystalline silicon bottom cells of this structure are all made of conventional materials, which can reduce the use of precious metal indium materials, reduce the cost of crystalline silicon bottom cells, popularize the application of crystalline silicon bottom cells in perovskite crystalline silicon stacked solar cells, and make the subsequent process steps of forming the stacked structure more compatible.

[0112] The embodiments of the present invention are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for manufacturing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell, characterized in that: The method comprises: Prepare a silicon wafer substrate, wherein the thickness of the silicon wafer substrate is between 100 μm and 500 μm, the silicon wafer substrate is made of N-type silicon or P-type silicon, and the resistivity of the silicon wafer substrate is between 0.1 ohm•cm and 20 ohm•cm; A first passivation layer is prepared on the upper surface of the silicon wafer substrate, wherein the first passivation layer comprises a first doped polysilicon layer and a first tunneling silicon oxide layer stacked in sequence from bottom to top, wherein the thickness of the first doped polysilicon layer is between 0-135 nm, and the thickness of the first tunneling silicon oxide layer is between 0-15 nm; A second passivation layer is prepared on the lower surface of the silicon wafer substrate, wherein the thickness of the second passivation layer is between 0 and 135 nm; the second passivation layer comprises a doped polysilicon layer and a second tunneling silicon oxide layer stacked in sequence from bottom to top; A carrier selective transport layer is prepared on the lower surface of the second passivation layer, wherein the thickness of the carrier selective transport layer is between 0 and 200 nm; the material of the carrier selective transport layer is one or more of SiOx, Al2O3, AlN, InSb, SiC, TiOx, and TiN; An anti-reflection layer is prepared on the lower surface of the carrier selective transport layer, wherein the thickness of the anti-reflection layer is between 0-300 nm; Preparing a metal bottom electrode layer on the lower surface of the anti-reflection layer, wherein the thickness of the metal bottom electrode layer is 1-2000 μm; Wherein, the step of preparing a first passivation layer on the upper surface of the silicon wafer substrate comprises: When the first passivation layer is prepared based on the N-type doped polysilicon layer, the thickness of the N-type doped polysilicon layer in the first passivation layer is controlled to be 0-120 nm, and the doping concentration is 8*10 18 cm −3 Up to 1.5*10 21 cm −3 , the square resistance is 20-150 Ω / □; or when the first passivation layer is prepared based on the P-type doped polysilicon layer, the thickness of the P-type doped polysilicon layer in the first passivation layer is controlled to be 0-120 nm, and the doping concentration is 8*10 18 cm −3 Up to 3*10 21 cm −3 , square resistance is 20-150 Ω / □; When preparing the first tunneling silicon oxide layer, controlling the thickness of the first tunneling silicon oxide layer to be within a range of 0-15 nm; Wherein, the preparation of the second passivation layer on the lower surface of the silicon wafer substrate comprises: When the first passivation layer is prepared based on an N-type doped polysilicon layer, the second passivation layer is prepared based on a P-type doped polysilicon layer or a P-type diffusion doped layer, and the square resistance of the P-type doped polysilicon layer or the P-type diffusion doped layer is 20-150 Ω / □; or when the first passivation layer is prepared based on a P-type doped polysilicon layer, the second passivation layer is prepared based on an N-type doped polysilicon layer or an N-type diffusion doped layer, and the square resistance of the N-type doped polysilicon layer or the N-type diffusion doped layer is 20-150 Ω / □; Wherein, the preparation of the second passivation layer on the lower surface of the silicon wafer substrate comprises: When preparing the second passivation layer based on the N-type doped polysilicon layer, the thickness of the N-type doped polysilicon layer in the second passivation layer is controlled to be 0-120 nm, and the doping concentration is 8*10 18 cm −3 Up to 1.5*10 21 cm −3 , the square resistance is 20-150 Ω / □; or when the second passivation layer is prepared based on the P-type doped polysilicon layer, the thickness of the P-type doped polysilicon layer in the second passivation layer is controlled to be 0-120nm, and the doping concentration is 8*10 18 cm −3 Up to 3*10 21 cm −3 , square resistance is 20-150 Ω / □; When preparing the second tunneling silicon oxide layer, the thickness of the second tunneling silicon oxide layer is controlled to be within a range of 0-15 nm.

2. The method for manufacturing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell according to claim 1, characterized in that: The upper surface of the silicon wafer substrate is prepared with a velvet structure or a polished surface structure, and the lower surface of the silicon wafer substrate is prepared with a velvet structure or a polished surface structure; When preparing the velvet structure, it is prepared through an alkali velveting process, and the surface roughness of the velvet structure is Ra<2; when preparing the polished surface structure, it is prepared through an acid polishing, or alkali polishing, or mechanical polishing process, and the surface roughness of the polished surface structure is Ra<0.

2.

3. The method for manufacturing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell according to claim 1, characterized in that: The step of preparing the carrier selective transport layer on the lower surface of the second passivation layer comprises: preparing the carrier selective transport layer by ALD or PVD; The carrier selective transport layer includes an electron selective transport layer or a hole selective transport layer.

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