A read-write control system and a read-write control method for image data

Abstract

The present invention discloses a read-write control system and a read-write control method for image data. The read-write control system comprises a write control module, a read control module, a first FIFO module, a second FIFO module and a third FIFO module; the read control module is used for reading the U component of the reference column of the pixel data of the same row from the second FIFO module and reading the V component of the reference column of the pixel data of the same row from the third FIFO module whenever the Y components of the preset front and rear columns of the pixel data of the same row are read continuously from the first FIFO module; the read control module is also used for repeatedly reading the U component of the reference column of the pixel data of the matching row from the second FIFO module twice and repeatedly reading the V component of the reference column of the pixel data of the matching row from the third FIFO module during the process of the write control module continuously writing the Y components of the preset upper and lower rows of pixel data into the first FIFO module.

Description

Technical Field

[0001] The present invention belongs to the technical field of image pixel data processing, and in particular relates to a read-write control system and a read-write control method for image data. Background Art

[0002] YUV is an image format, which is divided into three components. The Y component represents brightness (Luminance or Luma), which is the grayscale value; while the U component and the V component represent chrominance (Chrominance or Chroma), which is used to describe the color and saturation of the image and is used to specify the color of the pixel.

[0003] In the process of converting data into YUV image format, the prior art needs to design at least 48 FIFO memories and additional data cache space in order to merge and transmit the Y component, U component and V component, which constitutes a large on-chip area. In addition, the U component and V component at the same row and column position need to be copied and cached repeatedly, which occupies more bandwidth resources and increases the burden on the system bus. Summary of the invention

[0004] In order to overcome the above technical defects, the present invention discloses a read-write control system and a read-write control method for image data, which is suitable for processing image data (i.e., pixel data) in YUV420 format while saving bandwidth and area resources. The specific technical solution is as follows:

[0005] A read-write control system for image data, the read-write control system is used to read and write pixel data in YUV format; the read-write control system comprises a write control module, a read control module, a first FIFO module, a second FIFO module and a third FIFO module; the write control module is used to sequentially write the Y component of each column of each row of pixel data from a frame of image pre-stored externally into the first FIFO module, sequentially write the U component of the reference column of the pixel data of the matching row into the second FIFO module, and sequentially write the V component of the reference column of the pixel data of the matching row into the third FIFO module, so that the write control module writes the Y component of the preset upper and lower rows of pixel data to the first FIFO module each time, then writes the U component of the reference column of the pixel data of one row into the second FIFO module, and writes the V component of the reference column of the pixel data of one row into the third FIFO module; the read control module is used to write the Y component of the reference column of the pixel data of one row into the second FIFO module each time the write control module continuously writes the Y component of the preset upper and lower rows of pixel data to the first FIFO module The block writes the Y components of each column of a row of pixel data into the first FIFO module, and then reads the Y components from the first FIFO module in sequence; the read control module is used to read the U component of the reference column of the pixel data in the same row from the second FIFO module and read the V component of the reference column of the pixel data in the same row from the third FIFO module whenever the Y components of the preset two columns of pixel data in the same row are read continuously from the first FIFO module, so as to form pixel data that conforms to a specific YUV format; the read control module is also used to repeatedly read the U component of the reference column of the pixel data in the same matching row from the second FIFO module twice, and repeatedly read the V component of the reference column of the pixel data in the same matching row from the third FIFO module twice, when the write control module continuously writes the Y components of the preset two rows of pixel data in the first FIFO module.

[0006] Further, the read control module is used to read the U component of a reference column of the pixel data of the matching row from the second FIFO module and read the V component of a reference column of the pixel data of the matching row from the third FIFO module in each round of reading the Y components of the preset front and rear columns of the pixel data of the current row from the first FIFO module, so that in the pixel data of the same row of the same frame image, the read control module reads one U component from the second FIFO module and one V component from the third FIFO module every time it reads two Y components from the first FIFO module; then the current column Y component, the U component of the reference column, and the V component of the reference column among the Y components of the preset front and rear columns of the pixel data of the current row are combined into one pixel data conforming to a specific YUV format, and the latter column Y component, the U component of the same reference column, and the V component of the same reference column among the Y components of the preset front and rear columns of the pixel data of the current row are combined into another pixel data conforming to a specific YUV format; wherein the matching row is the current row.

[0007] Further, among the pixel data of the current row, the Y components of the preset front and rear two columns of the pixel data of the current row read from the first FIFO module in different rounds are Y components with different column orderings among the pixel data of the same row; in two adjacent rounds of reading, the Y component of the rear column of the pixel data of the same row read from the first FIFO module in the current round and the Y component of the current column of the pixel data of the same row read from the first FIFO module in the next round are Y components with adjacent column orderings; the absolute value of the difference between the U component of the reference column of the pixel data of the same row read from the second FIFO module in the current round and the U component of the reference column of the pixel data of the same row read from the second FIFO module in the next round in the same frame of image is 2; the absolute value of the difference between the V component of the reference column of the pixel data of the same row read from the third FIFO module in the current round and the V component of the reference column of the pixel data of the same row read from the third FIFO module in the next round in the same frame of image is 2.

[0008] Further, the read control module is used to, in each round of reading the Y components of each column of the preset upper and lower rows of pixel data, trigger the write control module to control the Y components of the corresponding column of the next row of pixel data to be written into the first FIFO module whenever the Y components of a column of the pixel data of the current row are read, and do not trigger the U components of the pixel data of the next row to be written into the second FIFO module, and do not trigger the V components of the pixel data of the next row to be written into the third FIFO module; the read control module is also used to, after reading the Y components of all columns of the pixel data of the current row, repeatedly read the U components of the reference columns of the pixel data of the matching row from the second FIFO module to realize polling the same batch of U components pre-cached from the starting address of the second FIFO module, and repeatedly read the V components of the reference columns of the pixel data of the matching row from the third FIFO module to realize polling the same batch of V components pre-cached from the starting address of the third FIFO module; wherein the current row is the matching row.

[0009] Furthermore, among the Y components of each column of the preset upper and lower rows of pixel data, the Y components of the preset upper and lower rows of pixel data read from the first FIFO module in different rounds are Y components with different row orderings among the pixel data of the same frame image; in two adjacent rounds of reading, the Y component of the pixel data of the next row read from the first FIFO module in the current round and the Y component of the pixel data of the current row read from the first FIFO module in the next round are Y components with adjacent row orderings; the absolute value of the difference between the U component of the reference column of the pixel data of the same row read from the second FIFO module in the current round and the U component of the reference column of the pixel data of the same row read from the second FIFO module in the next round in the same frame image is 2; the absolute value of the difference between the V component of the reference column of the pixel data of the same row read from the third FIFO module in the current round and the V component of the reference column of the pixel data of the same row read from the third FIFO module in the next round in the same frame image is 2.

[0010] Furthermore, the read control module is used to trigger the first FIFO module to cache the Y components of each column of a new row of pixel data to update the Y components of each column of a row of pixel data originally stored therein, trigger the second FIFO module to cache the U components of the reference columns of a new row of pixel data to update the U components of the reference columns of a row of pixel data originally stored therein, and trigger the third FIFO module to cache the V components of the reference columns of a new row of pixel data to update the V components of the reference columns of a row of pixel data originally stored therein, whenever the Y components of each column of the preset upper and lower rows of pixel data are read, the U components of the reference columns of the current row of pixel data are read from the second FIFO module, and the V components of the reference columns of the current row of pixel data are read from the third FIFO module.

[0011] Further, if the read control module starts from row 0 and sequentially reads the Y components of each column of each row of pixel data from the first FIFO module, the pixel data of the matching row is set to the pixel data of the even rows of the same frame image, and the reference column of the pixel data of the matching row is set to the odd column or the even column of the pixel data of the even rows of the same frame image; if the read control module starts from row 1 and sequentially reads the Y components of each column of each row of pixel data from the first FIFO module, the pixel data of the matching row is set to the pixel data of the odd rows of the same frame image in the second FIFO module and the third FIFO module, and the reference column of the pixel data of the matching row is set to the odd column or the even column of the pixel data of the even rows of the same frame image in the second FIFO module and the third FIFO module. The reference column of the pixel data of the matching row in the first FIFO block and the third FIFO module is set to the odd column or even column of the pixel data of the odd row of the same frame image; wherein the depth size of the first FIFO module is equal to the number of all Y components in a row of pixel data, the depth size of the second FIFO module is equal to the number of U components of all reference columns in a row of pixel data, and the depth size of the third FIFO module is equal to the number of V components of all reference columns in a row of pixel data; wherein half of the depth size of the first FIFO module is equal to the depth size of the second FIFO module, and the depth size of the second FIFO module is equal to the depth size of the third FIFO module.

[0012] Further, if the reference column of the pixel data of the matching row is set to the odd column of the pixel data of the even row of the same frame image, the read control module synchronously reads the Y component of the odd column of the pixel data of the same even row from the first FIFO module, reads the U component of the odd column of the pixel data of the same even row from the second FIFO module, and reads the V component of the odd column of the pixel data of the same even row from the third FIFO module, so that in the preset front and rear two columns of the pixel data of the same even row, the pixel data of the odd column is read out first relative to the pixel data of the even column. is read; if the reference column of the pixel data of the matching row is set to the even column of the pixel data of the even row of the same frame image, the read control module synchronously reads the Y component of the even column of the pixel data of the same even row from the first FIFO module, reads the U component of the even column of the pixel data of the same even row from the second FIFO module, and reads the V component of the even column of the pixel data of the same even row from the third FIFO module, so that among the preset front and rear two columns of the pixel data of the same even row, the pixel data of the even column is read first relative to the pixel data of the odd column. Reading; if the reference column of the pixel data of the matching row is set to the odd column of the pixel data of the odd row of the same frame image, the read control module synchronously reads the Y component of the odd column of the pixel data of the same odd row from the first FIFO module, reads the U component of the odd column of the pixel data of the same odd row from the second FIFO module, and reads the V component of the odd column of the pixel data of the same odd row from the third FIFO module, so that among the preset front and rear two columns of the pixel data of the same odd row, the pixel data of the odd column is read first relative to the pixel data of the even column Take; if the reference column of the pixel data of the matching row is set to the even column of the pixel data of the odd row of the same frame image, the read control module synchronously reads out the Y component of the even column of the pixel data of the same odd row from the first FIFO module, reads out the U component of the even column of the pixel data of the same odd row from the second FIFO module, and reads out the V component of the even column of the pixel data of the same odd row from the third FIFO module, so that among the preset front and rear two columns of the pixel data of the same odd row, the pixel data of the even column is read first relative to the pixel data of the odd column.

[0013] Furthermore, the write control module is used to control the U component of the reference column of the pixel data of the next row to be written into the second FIFO module in order to retain the U component of the same column of the pixel data of the current row previously cached, and not control the V component of the reference column of the pixel data of the next row to be written into the third FIFO module in order to retain the V component of the same column of the pixel data of the current row previously cached, during each round of writing the Y component of each column of the preset upper and lower rows of pixel data into the first FIFO module; wherein the current row is the matching row.

[0014] Further, among the Y components of each column of the preset upper and lower rows of pixel data, the Y components of the preset upper and lower rows of pixel data written into the first FIFO module in different rounds are Y components with different row orderings among the pixel data of the same frame image; in two adjacent rounds of writing, the Y component of the pixel data of the next row written into the first FIFO module in the current round and the Y component of the pixel data of the current row written into the first FIFO module in the next round are Y components with adjacent row orderings; the absolute value of the difference between the U component of the reference column of the pixel data of the same row written into the second FIFO module in the current round and the U component of the reference column of the pixel data of the same row written into the second FIFO module in the next round in the same frame image is 2; when The absolute value of the difference between the V component of the reference column of the same row of pixel data written to the third FIFO module in the previous round and the V component of the reference column of the same row of pixel data written to the third FIFO module in the next round in the same frame image is 2; wherein, in each round of writing, the first FIFO module first caches the Y components of all columns of the pixel data of the current row, and then refreshes the Y components of all columns of the previously cached row of pixel data to cache the Y components of all columns of the next row of pixel data; in each round of writing, the second FIFO module caches at most the U components of all reference columns of a row of pixel data; in each round of writing, the third FIFO module caches at most the V components of all reference columns of a row of pixel data.

[0015] Furthermore, the write control module is used to write the Y components of each column of a new row of pixel data to the first FIFO module to update the Y components of each column of a row of pixel data originally stored therein, write the U component of the reference column of a new row of pixel data to the second FIFO module to update the U component of the reference column of a row of pixel data originally stored therein, and write the V component of the reference column of a new row of pixel data to the third FIFO module to update the V component of the reference column of a row of pixel data originally stored therein, whenever the Y components of each column of the preset upper and lower rows of pixel data are written to the first FIFO module, the U component of the reference column of the current row of pixel data is written to the second FIFO module, and the V component of the reference column of the current row of pixel data is written to the third FIFO module.

[0016] Furthermore, the write control module is used to, in each round of writing the Y components of the preset front and rear two columns of the pixel data of the current row to the first FIFO module, only write the U component of the reference column of the pixel data of the current row to the second FIFO module once and trigger the read control module to perform a read operation, and only write the V component of the reference column of the pixel data of the current row to the third FIFO module once and trigger the read control module to perform a read operation; wherein the current row is the matching row.

[0017] Further, among the pixel data of the current row, the Y components of the preset front and rear two columns of the pixel data of the current row written to the first FIFO module in different rounds are Y components with different column orderings among the pixel data of the same row; in the process of two adjacent rounds of writing to the first FIFO module, the Y component of the rear column of the pixel data of the same row written to the first FIFO module in the current round and the Y component of the current column of the pixel data of the same row written to the first FIFO module in the next round are Y components with adjacent column orderings; the absolute value of the difference between the U component of the reference column of the pixel data of the same row written to the second FIFO module in the current round and the U component of the reference column of the pixel data of the same row written to the second FIFO module in the next round in the same frame of image is 2; the absolute value of the difference between the V component of the reference column of the pixel data of the same row written to the third FIFO module in the current round and the V component of the reference column of the pixel data of the same row written to the third FIFO module in the next round in the same frame of image is 2.

[0018] Furthermore, a pre-stored frame of image is composed of a group of pixel data blocks or multiple groups of pixel data blocks; each group of pixel data blocks is composed of pixel data corresponding to a pixel array; in a pixel array, each row and column of pixels has a Y component; pixels of the same color are composed of four adjacent pixels up, down, left and right, pixels of the same color share the same U component, and pixels of the same color share the same V component.

[0019] Furthermore, a frame of image is stored in the memory of the read-write control system peripheral device in the form of: for every 4 Y components stored, one U component and one V component are mapped accordingly.

[0020] A read-write control method for image data, the read-write control method is used for reading and writing pixel data in YUV format; the read-write control method comprises: from a frame of image pre-stored externally, sequentially writing the Y component of each column of each row of pixel data into a first FIFO module, sequentially writing the U component of the reference column of the pixel data of the matching row into a second FIFO module, and sequentially writing the V component of the reference column of the pixel data of the matching row into a third FIFO module; whenever the Y component of the preset front and rear columns of the pixel data of the same row is continuously read from the first FIFO module, the U component of the reference column of the pixel data of the same row is read from the second FIFO module, and the V component of the reference column of the pixel data of the same row is read from the third FIFO module, so as to form pixel data conforming to a specific YUV format; in the process of continuously writing the Y component of the preset upper and lower rows of pixel data into the first FIFO module, repeatedly reading the U component of the reference column of the pixel data of the same matching row from the second FIFO module twice, and repeatedly reading the V component of the reference column of the pixel data of the same matching row from the third FIFO module twice, so as to form pixel data conforming to a specific YUV format.

[0021] Further, the read-write control method includes: in each round of reading the Y components of the preset front and rear two columns of the pixel data of the current row from the first FIFO module, reading the U component of a reference column of the pixel data of the matching row from the second FIFO module, and reading the V component of a reference column of the pixel data of the matching row from the third FIFO module, so that in the pixel data of the same row of the same frame image, for every two Y components read from the first FIFO module, a U component is read from the second FIFO module, and a V component is read from the third FIFO module; then the current column Y component, the U component of the reference column, and the V component of the reference column among the Y components of the preset front and rear two columns of the pixel data of the current row are combined into a pixel data conforming to a specific YUV format, and the latter column Y component, the U component of the same reference column, and the V component of the same reference column among the Y components of the preset front and rear two columns of the pixel data of the current row are combined into another pixel data conforming to a specific YUV format; wherein, the matching row is the current row.

[0022] Further, among the pixel data of the current row, the Y components of the preset front and rear two columns of the pixel data of the current row read from the first FIFO module in different rounds are Y components with different column orderings among the pixel data of the same row; in two adjacent rounds of reading, the Y component of the rear column of the pixel data of the same row read from the first FIFO module in the current round and the Y component of the current column of the pixel data of the same row read from the first FIFO module in the next round are Y components with adjacent column orderings; the absolute value of the difference between the U component of the reference column of the pixel data of the same row read from the second FIFO module in the current round and the U component of the reference column of the pixel data of the same row read from the second FIFO module in the next round in the same frame of image is 2; the absolute value of the difference between the V component of the reference column of the pixel data of the same row read from the third FIFO module in the current round and the V component of the reference column of the pixel data of the same row read from the third FIFO module in the next round in the same frame of image is 2.

[0023] Further, in each round of reading the Y components of each column of the preset upper and lower rows of pixel data, whenever the Y components of a column of the pixel data of the current row are read, the Y components of the corresponding columns of the pixel data of the next row are controlled to be written into the first FIFO module, and the U components of the pixel data of the next row are not controlled to be written into the second FIFO module, and the V components of the pixel data of the next row are not controlled to be written into the third FIFO module; after reading the Y components of all columns of the pixel data of the current row, the U components of the reference columns of the pixel data of the matching row are repeatedly read from the second FIFO module to realize polling the same batch of U components pre-cached from the starting address of the second FIFO module, and the V components of the reference columns of the pixel data of the matching row are repeatedly read from the third FIFO module to realize polling the same batch of V components pre-cached from the starting address of the third FIFO module; wherein, the current row is the matching row.

[0024] Furthermore, among the Y components of each column of the preset upper and lower rows of pixel data, the Y components of the preset upper and lower rows of pixel data read from the first FIFO module in different rounds are Y components with different row orderings among the pixel data of the same frame image; in two adjacent rounds of reading, the Y component of the pixel data of the next row read from the first FIFO module in the current round and the Y component of the pixel data of the current row read from the first FIFO module in the next round are Y components with adjacent row orderings; the absolute value of the difference between the U component of the reference column of the pixel data of the same row read from the second FIFO module in the current round and the U component of the reference column of the pixel data of the same row read from the second FIFO module in the next round in the same frame image is 2; the absolute value of the difference between the V component of the reference column of the pixel data of the same row read from the third FIFO module in the current round and the V component of the reference column of the pixel data of the same row read from the third FIFO module in the next round in the same frame image is 2.

[0025] Furthermore, whenever the Y components of each column of the preset upper and lower rows of pixel data are read, the U components of the reference columns of the current row of pixel data are read from the second FIFO module, and the V components of the reference columns of the current row of pixel data are read from the third FIFO module, the first FIFO module is triggered to cache the Y components of each column of a new row of pixel data to update the Y components of each column of a row of pixel data originally stored, the second FIFO module is triggered to cache the U components of the reference columns of a new row of pixel data to update the U components of the reference columns of a row of pixel data originally stored, and the third FIFO module is triggered to cache the V components of the reference columns of a new row of pixel data to update the V components of the reference columns of a row of pixel data originally stored.

[0026] The technical effect of the present invention is that: the present invention designs three FIFO modules, namely a first FIFO module for storing Y components, a second FIFO module for storing U components, and a third FIFO module for storing U components. In order to obtain pixel data that conforms to the YUV format, it is configured under the condition of reading pixel data of the same row: whenever the Y components of the preset front and rear two columns of the pixel data of the same row are continuously read from the first FIFO module, the U component of the reference column of the pixel data of the matching row is read from the second FIFO module once, and the V component of the reference column of the pixel data of the matching row is read from the third FIFO module once, so that in the pixel data of the same row, the first FIFO module reads pixel data column by column, the second FIFO module reads pixel data every other column (such as odd columns), and the third FIFO module reads pixel data every other column (such as odd columns). Specifically, the pixel data of the odd columns are all read from the three FIFO modules, and the pixel data of the even columns are only read from the first FIFO module. Under the condition of reading pixel data across rows, it is configured that: the write control module writes the Y component of two rows of pixel data to the first FIFO module every time it continuously writes the U component of the reference column of one row of pixel data to the second FIFO module, and writes the V component of the reference column of one row of pixel data to the third FIFO module, so that the first FIFO module is updated with pixel data row by row, the second FIFO module is updated with pixel data alternately (for example, odd rows), and the third FIFO module is updated with pixel data alternately (for example, odd rows); the read control module is configured to repeatedly read the U component of the reference column of the pixel data of the same matching row from the second FIFO module twice every time it continuously reads the Y component of the pixel data of the corresponding row from the first FIFO module, and repeatedly reads the V component of the reference column of the pixel data of the same matching row from the third FIFO module twice.

[0027] In summary, the first FIFO module transmits the Y component row by row and column by column, the second FIFO module updates the U component across rows and columns and transmits the U component in the same row and columns, and the third FIFO module updates the V component across rows and columns and transmits the V component in the same row and columns. Compared with the reading and writing method of pixel data in the YUV format provided by the prior art, it is possible to manage the area occupied by the FIFO module and the bandwidth resources required for reading and writing under the premise of converting and processing images with the same resolution, including: reducing the capacity of a single FIFO, saving cache bandwidth when processing the U component and the V component in alternate rows or columns; and there is no need to set up cache space outside the first FIFO module, the second FIFO module and the third FIFO module to store the pixel data read from the peripheral memory and the pixel data read from the FIFO module. By repeatedly caching the pixel data of a specific row and a specific column in a corresponding FIFO in batches or caching the pixel data of a specific row and a specific column in three FIFOs at the same time, the process of converting a larger resolution image and saving it in the YUV format is accelerated, and the transmission time in the additional cache space is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of a read-write control system for pixel data based on YUV format provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention. In the description of this application, the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating a relative arrangement order or implying relative importance.

[0030] In order to read and write Y component, U component and V component respectively to form corresponding pixel data in YUV format under the premise of low transmission bandwidth and small on-chip area (the area occupied by bus buffer resources in the chip and storage resources in the chip), so that in the same row of pixel data, every two identical Y components correspond to one U component and the two identical Y components correspond to one V component, and in two adjacent rows of pixel data, every four identical Y components correspond to the same U component and the four identical Y components correspond to the same V component, so as to meet the image pixel compression format; the present invention discloses a read-write control system for image data, the read-write control system is used to read and write pixel data in YUV format; refer to Figure 1It can be seen that the read-write control system includes a write control module, a read control module, a first FIFO module, a second FIFO module and a third FIFO module, that is, in this embodiment, the three pixel components of each row of the image are respectively stored in a corresponding FIFO module (FIFO queue), and a first FIFO module for storing the Y component, a second FIFO module for storing the U component, and a third FIFO module for storing the U component are designed respectively. The write control module is used to write the Y components of each column of each row of pixel data from a frame of image pre-stored externally into the first FIFO module in sequence, write the U components of the reference columns of the pixel data of the matching row in sequence into the second FIFO module, and write the V components of the reference columns of the pixel data of the matching row in sequence into the third FIFO module, so that the write control module writes the Y components of the preset upper and lower rows of pixel data to the first FIFO module each time, writes the U components of the reference columns of one row of pixel data to the second FIFO module, and writes the V components of the reference columns of one row of pixel data to the third FIFO module, wherein the Y components of the upper and lower rows of pixel data that are not repeated are written into the first FIFO module; for the same frame of image, the write control module updates the pixel data (specifically the Y components) pre-cached in the first FIFO module row by row. , the write control module updates the pixel data (specifically the U component) in the second FIFO module in alternating rows, and the write control module updates the pixel data (specifically the V component) cached in the third FIFO module in alternating rows. If counting starts from 1, the U component in the second FIFO module is refreshed only when the write control module obtains the pixel data of odd rows from a pre-stored frame image, and the V component in the third FIFO module is refreshed only when the write control module obtains the pixel data of odd rows from a pre-stored frame image. The matching rows are the odd rows of the same frame image, and the corresponding reference columns are the odd columns of the same frame image. In this embodiment, the write control module first reads back a row of pixel data from the memory of the peripheral device, and then stores the Y component, the U component and the V component in three different FIFO modules respectively, so that the read control module can read them out.

[0031] It should be noted that the write control module and the read control module can be separated into independent control devices, or integrated into one control device; the write control module and the read control module are both electrically connected to the first FIFO module, the second FIFO module and the third FIFO module. Preferably, the first FIFO module, the second FIFO module and the third FIFO module are allowed to share the same read control module and a write control module; the first FIFO module, the second FIFO module and the third FIFO module are also allowed to each have a read control module and a write control module.

[0032] A read control module is used for reading the Y components from the first FIFO module in sequence whenever the write control module writes the Y components of each column of a row of pixel data into the first FIFO module, so that the first FIFO module caches the Y components of the same frame image row by row; a read control module is used for reading the U component of the reference column of the pixel data of the matching row from the second FIFO module once each time the Y components of the preset front and rear columns of the pixel data of the same row are read continuously from the first FIFO module (which can be counted as reading twice), which can be counted as reading the U component of the reference column of the pixel data of the same row once and can be retained for conversion to a specific YUV format; and reading the V component of the reference column of the pixel data of the matching row from the third FIFO module once, which can be counted as reading the U component of the reference column of the pixel data of the same row once and can be retained for conversion to a specific YUV format; thereby realizing that in the pixel data of the same row of the same frame image, the read control module The module reads pixel data column by column through the first FIFO module, that is, the first FIFO module caches the Y component of a row of pixel data column by column and transmits it out under the control of the read control module, so that the first FIFO module reads pixel data column by column; correspondingly, in the pixel data of the same row of the same frame image, the read control module reads pixel data column by column through the second FIFO module, that is, the second FIFO module caches the U component of a row of pixel data column by column and transmits it out under the control of the read control module. Relative to the first FIFO module, in the same read data cycle, the second FIFO module reads the U component by alternate columns (for example, odd columns), and the third FIFO module reads the V component by alternate columns (for example, odd columns), so that every time two Y components are read continuously from the first FIFO module, one U component is read from the second FIFO module, and one V component is read from the second FIFO module, thereby forming pixel data in corresponding YUV format. The read control module is also used to repeatedly read the U component of the reference column of the pixel data of the same matching row from the second FIFO module twice, and repeatedly read the V component of the reference column of the pixel data of the same matching row from the third FIFO module twice, during the process of the write control module continuously writing the Y component of the pixel data of the upper and lower rows preset into the first FIFO module, so as to form pixel data conforming to a specific YUV format. Specifically, the read control module is used to continuously read the Y component of the pixel data of the upper and lower rows preset from the first FIFO module during the process of the write control module continuously writing the Y component of the pixel data of the upper and lower rows preset into the first FIFO module, which can be counted as reading two rows, and is synchronously performed with the write operation of the write control module to implement a pipeline structure, and repeatedly read the U component of the reference column of the pixel data of the same matching row from the second FIFO module twice, and repeatedly read the V component of the reference column of the pixel data of the same matching row from the third FIFO module twice.For the same frame image or each line of pixel data thereof, the write control module updates the Y component pre-cached in the first FIFO module line by line, and the read control module reads the Y component line by line through the first FIFO module; the write control module updates the U component in the second FIFO module line by line, and the read control module reads the U component line by line through the second FIFO module; the write control module updates the V component in the third FIFO module line by line, and the read control module reads the V component line by line through the third FIFO module.

[0033] For the reading of pixel data of the same row, the read control module is used to read the U component of a reference column of the pixel data of the matching row from the second FIFO module and read the V component of a reference column of the pixel data of the matching row from the third FIFO module in each round of reading the Y components of the preset two columns before and after the pixel data of the current row from the first FIFO module, wherein the matching row is the current row; when the Y component of the current column is read out from the first FIFO module, on the one hand, the currently read U component and the V component are matched with the Y component of the current column to form pixel data in a specific YUV format, and on the other hand, the currently read U component and the V component are temporarily cached; when the next column of Y components is read out from the first FIFO module, it is not necessary to read the U component from the second FIFO module or the V component from the third FIFO module, but directly use the previously cached U component and the V component to match the next column of Y components to form new pixel data in a specific YUV format; thereby, in the pixel data of the same row of the same frame image, the read control module reads two Y components from the first FIFO module and reads two V components from the second FIFO module. The IFO module reads a U component, and reads a V component from the third FIFO module. Here, the reading process of the Y components of the preset front and rear two columns of the pixel data of the current row is recorded as a round of reading process, specifically a round of reading operation of two adjacent columns (numbers) of pixel components in the same row. In each round of reading, two Y components in the pixel data of the same row are read from the first FIFO module, wherein the two Y components share the same U component read from the second FIFO module, and the two Y components share the same V component read from the third FIFO module; therefore, the current row of pixel data can be recorded as a U component read from the first FIFO module, and the V component read from the third FIFO module can be recorded as a V component read from the third FIFO module. The current column Y component among the preset front and rear two columns of the pixel data of the previous row, the U component of a reference column, and the V component of a reference column constitute pixel data that conforms to a specific YUV format, which can be used as a pixel point in the YUV420 format converted first; then the latter column Y component among the preset front and rear two columns of the pixel data of the current row, the U component of the same reference column, and the V component of the same reference column constitute another pixel data that conforms to a specific YUV format, which can be used as a pixel point in the YUV420 format converted later.

[0034] For reading pixel data of different rows or two rows above and below, the read control module is used to, in each round of reading the Y components of each column of the preset two rows of pixel data above and below, trigger the write control module to control the Y component of the corresponding column of the next row of pixel data to be written into the first FIFO module whenever the Y component of one column of the pixel data of the current row is read, and not trigger the write control module to write the U component of the pixel data of the next row into the second FIFO module, but the write control module has already written the U component of the pixel data of the current row into the second FIFO module, so that the U component of the pixel data of the current row cached in the second FIFO module is not refreshed by the U component of the pixel data of the next row; and not trigger the write control module to write the V component of the pixel data of the next row into the third FIFO module, but the write control module has already written the U component of the pixel data of the current row into the third FIFO module. The V component of the pixel data is written into the third FIFO module, so that the V component of the pixel data of the current row cached in the third FIFO module is not refreshed by the V component of the pixel data of the next row; wherein the pixel data of the current row and the pixel data of the next row are recorded as preset upper and lower rows of pixel data, and reading the pixel data of the current row (including the Y component of each column of the pixel data of the current row) and the pixel data of the next row (including the Y component of each column of the pixel data of the next row) is recorded as a round of reading process, specifically a round of reading operation of the Y component of each column of two adjacent rows, so that the read control module reads the Y component of two rows of pixel data from the first FIFO module twice in a row, then reads the U component of the reference column of the pixel data of the same row from the second FIFO module twice, and reads the V component of the reference column of the pixel data of the same row from the third FIFO module twice.On the basis that the current row is a matching row, the read control module is used to, in each round of reading the Y components of each column of the preset upper and lower rows of pixel data, after reading the Y components of all columns of the pixel data of the current row, repeatedly read the U components of the reference column of the pixel data of the matching row from the second FIFO module once to realize polling from the same starting address of the second FIFO module (i.e., re-reading from the first address unit) the same batch of U components pre-cached therein, the same batch of U components can be understood as the U components of the reference column of the pixel data of the current row, corresponding to the U components of the reference column of the pixel data of the matching row, and the implementation method of polling from the same starting address in the second FIFO module The method is to restore the initial address value of the read pointer to facilitate re-traversal of the U component cached in the second FIFO module; and repeatedly read the V component of the reference column of the pixel data of the matching row from the third FIFO module once to realize polling from the same starting address of the third FIFO module (i.e., re-reading from the first address unit) the same batch of V components pre-cached. The same batch of V components can be understood as the V component of the reference column of the pixel data of the current row, corresponding to the V component of the reference column of the pixel data of the matching row. The implementation method of polling from the same starting address in the third FIFO module is to restore the initial address value of the read pointer to facilitate re-traversal of the V component cached in the third FIFO module.

[0035] Preferably, if counting starts from 1, in the process of continuously reading the Y component of two adjacent rows of pixel data from the first FIFO module (implemented under the premise that the write control module is updated row by row), the U component of the pixel data belonging to the same odd row of the same frame image is repeatedly read from the second FIFO module twice, and the V component of the pixel data belonging to the same odd row of the same frame image is repeatedly read from the third FIFO module twice. Therefore, the U component of the odd row read from the second FIFO module for the first time, the V component of the odd row read from the third FIFO module in the same batch (in the same reading cycle, also recorded as the first time), and the Y component of the odd row read from the first FIFO module in the same batch (in the same reading cycle, also recorded as the first time) can constitute the pixel data in the YUV420 format; and the U component of the odd row read from the second FIFO module for the second time, the V component of the odd row read from the third FIFO module in the same batch (in the same reading cycle, also recorded as the second time) can constitute the pixel data in the YUV420 format. The V component of the odd rows and the Y component of the even rows read from the first FIFO module in the same batch (within the same reading cycle, also recorded as the second time) can also form pixel data in YUV420 format, wherein the U component of each column of the odd rows read from the second FIFO module for the second time is equal to the U component of the same column of the odd rows read from the second FIFO module for the first time, and the V component of each column of the odd rows read from the third FIFO module for the second time is equal to the V component of the same column of the odd rows read from the third FIFO module for the first time.

[0036] On the basis of the above embodiment, the read control module is further used to read the U component of the reference column of the pixel data of the matching row from the second FIFO module and read the V component of the reference column of the pixel data of the matching row from the third FIFO module when reading the Y component of a column of a row of pixel data from the first FIFO module, and then combine the currently read Y component, U component and V component into image pixels that conform to the YUV format, specifically for each row of pixel data in the same frame of image; thereby, the bandwidth for reading data is saved compared to the reading state in which the U component and the V component in the pixel data in the YUV format correspond one-to-one with the Y component, and reading bandwidth resources are saved for each row of pixel data in the same frame of image.

[0037] In summary, the present invention designs three FIFO modules, namely, a first FIFO module for storing Y components, a second FIFO module for storing U components, and a third FIFO module for storing U components. In order to obtain pixel data conforming to the YUV format, it is configured under the condition of reading pixel data of the same row: whenever the Y components of the preset two columns before and after the pixel data of the same row are continuously read from the first FIFO module, the U component of the reference column of the pixel data of the matching row is read from the second FIFO module once, and the V component of the reference column of the pixel data of the matching row is read from the third FIFO module once, so that in the pixel data of the same row, the first FIFO module is read column by column, and the second FIFO module is read column by column. Pixel data is read in alternate columns (such as odd columns), and the third FIFO module reads pixel data in alternate columns (such as odd columns). Specifically, the pixel data of odd columns are read from the three FIFO modules, and the Y components of even columns are only read from the first FIFO module. U components with the same values ​​are not cached repeatedly in the second FIFO module, and V components with the same values ​​are not cached repeatedly in the third FIFO module, because in this embodiment, the U component of the odd column among the preset front and rear two columns of the pixel data in the same row is equal to the U component of the even column among the preset front and rear two columns of the pixel data in the same row, and the V component of the odd column among the preset front and rear two columns of the pixel data in the same row is equal to the V component of the even column among the preset front and rear two columns of the pixel data in the same row. Under the condition of reading pixel data across rows, the configuration is as follows: when the write control module continuously writes the Y component of two rows of pixel data to the first FIFO module, only the U component of the reference column of the pixel data of one row is written to the second FIFO module, and only the V component of the reference column of the pixel data of one row is written to the third FIFO module, so that the first FIFO module is updated with pixel data row by row, the second FIFO module is updated with pixel data alternately (for example, odd rows), and the third FIFO module is updated with pixel data alternately (for example, odd rows); the configuration is as follows: when the read control module reads the Y component of the corresponding row of pixel data from the first FIFO module twice in a row, the U component of the reference column of the pixel data of the same matching row is repeatedly read from the second FIFO module twice, and the V component of the reference column of the pixel data of the same matching row is repeatedly read from the third FIFO module twice. Further, based on the pixel array of the same frame image, it can be understood that the first FIFO module transmits the Y component row by row and column by column, the second FIFO module updates the U component across rows and columns and transmits the U component in the same row and columns, and the third FIFO module updates the V component across rows and columns and transmits the V component in the same row and columns.Compared with the reading and writing method of pixel data in YUV format provided by the prior art, the present invention can manage the area occupied by the FIFO module and the bandwidth resources required for reading and writing under the premise of converting and processing images with the same resolution, including: reducing the capacity of a single FIFO (it is not necessary to fill all three pixel components into the same FIFO module), saving cache bandwidth when processing the U component and the V component in the same frame image in alternate rows or columns; and there is no need to set cache space outside the first FIFO module, the second FIFO module and the third FIFO module to store the pixel data read from the peripheral memory and the pixel data read from the FIFO module. By repeatedly caching the pixel data of specific rows and specific columns in batches in a corresponding FIFO or caching the pixel data of specific rows and specific columns in three FIFOs at the same time, the process of converting a larger resolution image and saving it in YUV format is accelerated, and the transmission time in the additional cache space is reduced.

[0038] Preferably, a pre-stored frame of image is composed of a group of pixel data blocks, or multiple groups of pixel data blocks, wherein each group of pixel data blocks is composed of pixel data corresponding to a pixel array, and preferably, a pixel array is composed of 4 rows and 8 columns of pixels, so as to convert pixel data in YUV420 format; it should be noted that pixels of the same color are composed of four adjacent pixels in the upper, lower, left and right directions, which are equivalent to four pixels in a four-square grid area, and pixels of the same color share the same U component, and pixels of the same color share the same V component, so that in two rows of pixels in the pixel array, there are two columns of pixels sharing the same U component, and the two columns of pixels share the same V component; therefore, the storage form of a frame of image in the memory of the read-write control system peripheral is as follows: for every 4 Y components stored, a corresponding U component and a corresponding V component are mapped, and a U component is not matched by repeatedly storing multiple identical U components and multiple identical V components to be read to form pixel data in a specific YUV format.

[0039] Preferably, in a pixel array, each pixel has a Y component; in the same pixel array, if the number of U components and the number of V components do not correspond one-to-one to the number of Y components, then in order to facilitate reading and converting the image in YUV format, the U component and the V component can be copied and expanded to four times the original, so that the U component and the V component correspond one-to-one to the Y component, then in the same pixel array, each pixel has a Y component, a U component and a V component. If the pixel data is read in the order of the row number and the column number of each pixel, including each Y component, each U component and each V component, a large bandwidth will be occupied. Therefore, the way to store the pixel array or the frame of the image in this embodiment is to first continuously store all the Y components, and then continuously store all the Y components. Continue to store all the uncopied U components, and then continuously store all the uncopied V components. At this time, the number of U components and the number of V components are both smaller than the number of Y components, but the storage address mapping of the four Y components adjacent to each other in the upper, lower, left, and right directions can correspond to the storage address of a U component, and the storage address of the U component and the corresponding storage address of each Y component are assigned index information that is in the same row and column, and the storage address of the V component and the storage address of each Y component are assigned index information that is in the same row and column, so as to facilitate the reading operation of the write control module, specifically, to facilitate writing a Y component into the first FIFO module, while writing the U component assigned index information in the same row and column into the second FIFO module, and also writing the V component assigned index information in the same row and column into the third FIFO module.

[0040] In the above embodiment, a frame of image to be read and written is composed of 4 rows and 8 columns of pixels, forming an image with a resolution of 8 times 4, with a total of 32 pixels. Its storage format in the memory of the external device is as follows: the Y components of four rows and eight columns are input into the memory in sequence, forming a storage format of {Y1, Y2, Y3, ..., Y31, Y32}, wherein the number after Y represents the index number in a pixel array, and if the row number starts counting from 0, the index number of the Y component of the mth column of the nth row is equal to m+8*n, where n is an integer greater than or equal to 0 but less than 4, m is a positive integer less than or equal to 8, and * represents multiplication. Then the two rows and four columns of U components are serially input into the memory to form a storage format of {U1, U3, U5, ..., U21, U23}, where the number after U represents the index number in a pixel array. If the row number starts counting from 0, the index number of the U component in the qth column of the pth row is equal to p+16*q, q is an even number less than 4 and q is greater than or equal to 0, p is an odd number less than or equal to 8 and p is greater than 0, and * represents multiplication. Then the two rows and four columns of V components are serially input into the memory to form a storage format of {V1, V3, V5, ..., V21, V23}, where the number after V represents the index number in a pixel array. If the row number starts counting from 0, the index number of the V component in the qth column of the pth row is equal to p+16*q, q is an even number less than 4 and q is greater than or equal to 0, p is an odd number less than 8 and p is greater than 0, and * represents multiplication.

[0041] It should be noted that, under the control of the write control module, the Y component of a frame of image is written into the first FIFO module in a serial transmission manner, and the address index number of the Y component in the first FIFO module is configured according to the writing order, forming the order in which the Y component is read by the corresponding read pointer in the first FIFO module; the U component of a frame of image is written into the second FIFO module in a serial transmission manner, and the address index number of the U component in the second FIFO module is configured according to the writing order, forming the order in which the U component is read by the read pointer in the second FIFO module; the V component of a frame of image is written into the third FIFO module in a serial transmission manner, and the address index number of the V component in the third FIFO module is configured according to the writing order, forming the order in which the V component is read by the read pointer in the third FIFO module; so that the read control module reads the Y component from the first FIFO module, the U component from the second FIFO module, and the V component from the third FIFO module in sequence according to the corresponding address index number to form pixel data in YUV format.

[0042] Among them, the depth size of the first FIFO module is equal to the number of all Y components in a row of pixel data, the depth size of the second FIFO module is equal to the number of U components of all reference columns in a row of pixel data, and the depth size of the third FIFO module is equal to the number of V components of all reference columns in a row of pixel data; half of the depth size of the first FIFO module is equal to the depth size of the second FIFO module, and the depth size of the second FIFO module is equal to the depth size of the third FIFO module. If a frame of image to be processed is composed of 4 rows and 8 columns of pixels, then a row of pixel data has 8 Y components, so the depth of the first FIFO module is set to 8, and the depth of the second FIFO module and the depth of the third FIFO module are both set to 4.

[0043] It should be noted that the FIFO module is the abbreviation of First In First Out in English. It is a first-in-first-out dual-port buffer, that is, the first data entering it is the first to be removed, one of which is the input port of the memory and the other is the output port of the memory. The difference between the FIFO module and the ordinary memory is that there is no external read and write address line, so it is very simple to use. Data can only be written and read sequentially. Its data address is completed by the pre-configured read pointer and write pointer traversal. Unlike ordinary memory, it can be determined by the address line to read or write a certain specified address. Based on the cognitive level of those skilled in the art, it can be known that the FIFO (First In First Out) module is a first-in-first-out cache device, which can pre-write the obtained data into the FIFO module, and then take out all of them in the original order and provide them to the device that needs the data. An important indicator of the FIFO module is the maximum number of data that the FIFO module can store, which is called depth. For a FIFO module with a smaller depth, its storage unit uses a FIFO register, hereinafter referred to as FIFO, such as: receiving FIFO and sending FIFO. For a FIFO module with a larger depth, its storage unit uses SRAM (Static Random Access Memory). Generally, the working principle of the FIFO module is as follows: data is read / written sequentially from / to the storage module under the control of read / write pulses with independent read / write address pointers. The read / write pointers start from the first address unit, read / write sequentially to the last address unit, and then return to the first address unit.

[0044] As an embodiment, among the pixel data of the current row, the Y components of the preset front and rear two columns of the pixel data of the current row read from the first FIFO module in different rounds are Y components with different column orderings among the pixel data of the current row, and each round reads the Y components of the adjacent two columns of the same row of the same frame image from the first FIFO module; the column number corresponding to each Y component read in the current round is different from the column number corresponding to each Y component read in the next round, and the column number corresponding to each Y component read in the same round is also different. During two adjacent rounds of reading, the Y component of the rear column of the pixel data of the same row read from the first FIFO module in the current round and the Y component of the current column of the pixel data of the same row read from the first FIFO module in the next round are Y components with adjacent column orderings, and are two Y components whose absolute value of the difference in column number among the pixel data of the same row is 1. On the other hand, the absolute value of the difference in column numbers between the U component of the reference column of the same row of pixel data read from the second FIFO module in the current round and the U component of the reference column of the same row of pixel data read from the second FIFO module in the next round in the same frame image is 2; the absolute value of the difference in column numbers between the V component of the reference column of the same row of pixel data read from the third FIFO module in the current round and the V component of the reference column of the same row of pixel data read from the third FIFO module in the next round in the same frame image is 2. Preferably, for the same row of pixel data, the column number of the Y component read in the current round is smaller than the column number of the Y component read in the next round, the column number of the U component read in the current round is smaller than the column number of the U component read in the next round, and the column number of the V component read in the current round is smaller than the column number of the V component read in the next round. Thereby, in the pixel data of the same row, the first FIFO module reads the pixel data column by column, the second FIFO module reads the pixel data in alternate columns (for example, odd columns), and the third FIFO module reads the pixel data in alternate columns (for example, odd columns). Specifically, the pixel data of odd columns are all read from the three FIFO modules, and the pixel data of even columns are only read from the first FIFO module.

[0045] As an embodiment, in order to form pixel data of an image in YUV format from the first FIFO module, the second FIFO module and the third FIFO module, the present embodiment makes the following reading implementation for an image composed of 4 rows and 8 columns of pixels in a frame: for the front and rear columns of the first row of pixel data cached, the reading control module reads the Y1 component (the Y component of the odd column) from the first FIFO module, reads the U1 component (the U component of the odd column) from the second FIFO module and temporarily stores it, and reads the V1 component (the V component of the odd column) from the third FIFO module and temporarily stores it. Stored to form the first pixel point Y1U1V1 that conforms to the YUV420 format; since in the pixel data of the same row of the same frame image, the read control module reads two Y components from the first FIFO module, reads one U component from the second FIFO module, and reads one V component from the third FIFO module; therefore, the read control module of this embodiment reads two Y components from the first FIFO module, reads an odd-numbered column of U components from the second FIFO module, and reads an odd-numbered column of V components from the third FIFO module, that is, the read control module reads two Y components from the first FIFO module, reads one U component from the second FIFO module, and reads one V component from the third FIFO module. The O module and the third FIFO module both read the pixel components of odd columns, while the read control module only reads the Y component of even columns from the first FIFO module; therefore, when reading the other two columns of the first row of pixel data cached, it is recorded as the second round of reading two columns of data, and the read control module reads the Y2 component (the Y component of the even column) from the first FIFO module, and then continues to use the temporarily stored U1 component and V1 component to form the second pixel point Y2U1V1 that conforms to the YUV420 format; when reading two columns of data in the third round, the Y3 component (the Y component of the odd column) is read from the first FIFO module, and the U3 component is read from the second FIFO module. The U component of the odd column is read and temporarily stored, and the V3 component (the V component of the odd column) is read from the third FIFO module and temporarily stored to form the third pixel point Y3U3V3 that conforms to the YUV420 format; when the two columns of data are read in the fourth round, the Y4 component (the Y component of the even column) is read from the first FIFO module, and then the temporarily stored U3 component and V3 component are used to form the fourth pixel point Y4U3V3 that conforms to the YUV420 format; and so on, the 8 Y components in the first row of pixel data are traversed according to the aforementioned reading method to form the fifth, sixth, seventh, and eighth pixel points that conform to the YUV420 format.

[0046] On the basis of the above embodiment, the read control module is used for, in each round of reading the Y component of each column of the preset upper and lower rows of pixel data, whenever the Y component of a column of the pixel data of the current row is read, triggering the write control module to control the Y component of the corresponding column of the pixel data of the next row to be written into the first FIFO module, because the first FIFO module has been filled after the pixel data of the current row is written, and then whenever the read control module reads the Y component of a column of the pixel data of the current row from the first FIFO module, the read address pointer will move to the next address unit, and the address read last time can be written by the Y component of the corresponding column of the pixel data of the next row and the Y component at the address is updated, so as to realize the pipeline mechanism; at this time, the read control module may also read the U component and the V component of the reference column of the pixel data of the current row, and before reading, the U component of the reference column of the pixel data of the matching row has filled the second FIFO module, and the V component of the reference column of the pixel data of the matching row has filled the third FIFO module, wherein the matching row is the current row; even if the U component in the second FIFO module is guided by the read pointer, Read one, but do not trigger the write control module to write the U component of the pixel data of the next row into the second FIFO module to prevent the data cached in the second FIFO module from being updated, and do not trigger the V component of the pixel data of the next row to be written into the third FIFO module to prevent the data cached in the third FIFO module from being updated; therefore, the read control module is used to keep the U component cached in the second FIFO module from being updated after reading the Y components of all columns of the pixel data of the current row, repeatedly read the U component of the reference column of the pixel data of the matching row from the second FIFO module to realize polling the same batch of U components pre-cached from the starting address of the second FIFO module, the same batch of U components are the U components of the reference column of the pixel data of the matching row of the second FIFO module that are pre-filled, and the way to repeatedly read the U component of the reference column of the pixel data of the matching row from the second FIFO module is to clear the read pointer of the second FIFO module to point back to the starting address of the second FIFO module, and then the read pointer of the second FIFO module starts to offset to realize repeated reading of the U component of the reference column of the pixel data of the matching row.Furthermore, the V component cached in the third FIFO module is kept not updated, and the V component of the reference column of the pixel data of the matching row is repeatedly read from the third FIFO module to realize polling the same batch of V components pre-cached therein starting from the starting address of the third FIFO module, wherein the same batch of V components is the V component of the reference column of the pixel data of the matching row pre-filled in the third FIFO module, and the manner of repeatedly reading the V component of the reference column of the pixel data of the matching row from the third FIFO module is to clear the read pointer of the third FIFO module to point back to the starting address of the third FIFO module, and then the read pointer of the third FIFO module starts to offset to realize repeated reading of the V component of the reference column of the pixel data of the matching row. Therefore, in the process of the read control module reading the Y component of the pixel data of the current row from the first FIFO module twice in a row, the U component of the reference column of the pixel data of the same matching row (current row) is repeatedly read from the second FIFO module twice, and the V component of the reference column of the pixel data of the same matching row (current row) is repeatedly read from the third FIFO module twice.

[0047] Specifically, for an image composed of 4 rows and 8 columns of pixels in a frame, after reading a row of pixel data, that is, reading out the 8 Y components in the first row of pixel data and sequentially forming the first to eighth pixels that conform to the YUV420 format, the write control module needs to write the Y components of each column of the second row of pixel data into the first FIFO module, and update the Y components of each column of the first row of pixel data. However, it is necessary to control the U components of the odd columns of the first row of pixel data cached in the second FIFO module to remain unchanged, and it is also necessary to control the V components of the odd columns of the first row of pixel data cached in the third FIFO module to remain unchanged. It should be noted that the corresponding read pointer points to the fourth unit address of the second FIFO module, and the corresponding read pointer points to the fourth unit address of the third FIFO module. As long as new data is not written to the corresponding FIFO module subsequently, the FIFO module will still maintain the original number. Therefore, the read pointer of the FIFO module is cleared to 0 at this time, so that it continues to point to the first unit address, so that the second FIFO module and the third FIFO module can repeat the reading again. The Y component of the second line of pixel data written into the first FIFO module is marked as Y9 to Y16 in sequence. In order to form the ninth to sixteenth pixel points that conform to the YUV420 format, the reading method is similar to the reading method of each pixel component of the first line of pixel data, and the U component read from the second FIFO module and the V component read from the third FIFO module do not change compared with when processing the first line of pixel data.

[0048] In the above embodiment, among the Y components of each column of the preset upper and lower rows of pixel data, the Y components of the preset upper and lower rows of pixel data read from the first FIFO module in different rounds are Y components with different row orderings among the pixel data of the same frame image, wherein the pixel data of the current row and the pixel data of the next row are recorded as the preset upper and lower rows of pixel data, if reading the pixel data of the current row (including the Y components of each column of the pixel data of the current row) and the pixel data of the next row (including the Y components of each column of the pixel data of the next row) is recorded as a round of reading process, then each round reads the Y components of each column of two adjacent rows of the same frame image from the first FIFO module; further, in the two adjacent rounds of reading process, the Y component of the pixel data of the next row read from the first FIFO module in the current round and the Y component of the pixel data of the current row read from the first FIFO module in the next round are Y components with adjacent row orderings, which can be understood as two Y components whose absolute value of the difference in row sequence number in the same column of pixel data is 1. At the same time, the absolute value of the difference between the U component of the reference column of the same row of pixel data read from the second FIFO module in the current round and the U component of the reference column of the same row of pixel data read from the second FIFO module in the next round in the same frame image is 2; the absolute value of the difference between the V component of the reference column of the same row of pixel data read from the third FIFO module in the current round and the V component of the reference column of the same row of pixel data read from the third FIFO module in the next round in the same frame image is 2.

[0049] Preferably, for the preset upper and lower rows of pixel data, the row number of the Y component read in the current round is smaller than the row number of the Y component read in the next round, the row number of the U component read in the current round is smaller than the row number of the U component read in the next round, and the row number of the V component read in the current round is smaller than the row number of the V component read in the next round.

[0050] On the basis of the above embodiment, the read control module is used to trigger the first FIFO module to cache the Y components of each column of a new row of pixel data to update the Y components of each column of a row of pixel data originally stored, trigger the second FIFO module to cache the U components of the reference columns of a new row of pixel data to update the U components of the reference columns of a row of pixel data originally stored, and trigger the third FIFO module to cache the V components of the reference columns of a new row of pixel data to update the V components of the reference columns of a row of pixel data originally stored, whenever the Y components of each column of the preset upper and lower rows of pixel data are read, the U components of the reference columns of the current row (the matching row) are read from the second FIFO module, and the V components of the reference columns of the current row (the matching row) are read from the third FIFO module, so that the first FIFO module, the second FIFO module and the third FIFO module are updated simultaneously after the Y components, U components and V components of the preset upper and lower rows of pixel data are read. Specifically, for an image consisting of 4 rows and 8 columns of pixels in a frame, after reading two rows of pixel data, that is, reading out the 8 Y components in the first row of pixel data and the 8 Y components in the second row of pixel data and sequentially forming the first to sixteenth pixels that conform to the YUV420 format, the write control module needs to write the Y components of each column of the third row of pixel data into the first FIFO module, update the Y components of each column of the second row of pixel data, and also needs to update the U components of the odd columns of the third row of pixel data with the U components of the second row of pixel data cached in the second FIFO module, and also needs to update the V components of the odd columns of the third row of pixel data with the V components of the second row of pixel data cached in the second FIFO module. Among them, the Y components of the third row of pixel data written into the first FIFO module are marked as Y17 to Y24 in sequence; the U components of the odd columns of the third row of pixel data written into the second FIFO module are marked as U17 to Y23 in sequence; the V components of the odd columns of the third row of pixel data written into the third FIFO module are marked as V17 to V23 in sequence; in order to form the seventeenth to twenty-fourth pixel points that conform to the YUV420 format, the reading method is similar to the reading method of each pixel component of the first row of pixel data, which will not be repeated here.

[0051] On this basis, when the write control module needs to write the Y components of each column of the fourth row of pixel data into the first FIFO module to update the Y components of each column of the third row of pixel data, in order to form the twenty-fifth to thirty-second pixel points that conform to the YUV420 format, it is necessary to read the second FIFO module and the third FIFO module in the same way as the second row of pixel data, which will not be repeated here.

[0052] It should be noted that, if the read control module starts from row 0 and reads the Y component of each column of each row of pixel data from the first FIFO module in sequence, the pixel data of the matching row is set to the pixel data of the even rows of the same frame image, and the reference column of the pixel data of the matching row is set to the odd column or the even column of the pixel data of the even rows of the same frame image, generally the even column is selected to comply with the counting rule of the row number; by the same token, it can be deduced that if the read control module starts from row 1 and reads the Y component of each column of each row of pixel data from the first FIFO module in sequence, the image of the matching row is set to the odd column or the even column of the pixel data of the even rows of the same frame image in sequence. The pixel data is set to the pixel data of the odd rows of the same frame image, and the reference column of the pixel data of the matching row is set to the odd column or even column of the pixel data of the odd rows of the same frame image in the second FIFO module and the third FIFO module, and the odd column is generally selected to comply with the counting rule of the row number; and the cache address of the U component in the second FIFO module is configured according to the writing order, and the cache address of the written U component is generally configured in sequence according to the first-in-first-out queue storage form; and the cache address of the V component in the third FIFO module is configured according to the writing order, and the cache address of the written V component is generally configured in sequence according to the first-in-first-out queue storage form. Thereby reducing the capacity of a single FIFO, saving cache bandwidth when processing U and V components in alternate rows or columns.

[0053] Regardless of counting from row 0 or row 1, the configuration is as follows: the depth size of the first FIFO module is equal to the number of all Y components in a row of pixel data, the depth size of the second FIFO module is equal to the number of U components of all reference columns in a row of pixel data, and the depth size of the third FIFO module is equal to the number of V components of all reference columns in a row of pixel data; wherein, half of the depth size of the first FIFO module is equal to the depth size of the second FIFO module, and the depth size of the second FIFO module is equal to the depth size of the third FIFO module.

[0054] In the above embodiment, if the reference column of the pixel data of the matching row is set to the odd column of the pixel data of the even row of the same frame image, the read control module synchronously reads the Y component of the odd column of the pixel data of the same even row from the first FIFO module, reads the U component of the odd column of the pixel data of the same even row from the second FIFO module, and reads the V component of the odd column of the pixel data of the same even row from the third FIFO module, so that in the preset front and rear two columns of the pixel data of the same even row, the pixel data of the odd column is read by the read-write control module first relative to the pixel data of the even column, especially the Y component of the pixel data of the same row, at this time, only the U component and the V component of the odd column are read out to form the pixel data of the specific YUV format. In the specific reading process, only the relevant row and column numbers are replaced, and the reading rules in the row and column direction do not change, which will not be repeated here.

[0055] If the reference column of the pixel data of the matching row is set to the even column of the pixel data of the even row of the same frame image, the read control module synchronously reads the Y component of the even column of the pixel data of the same even row from the first FIFO module, reads the U component of the even column of the pixel data of the same even row from the second FIFO module, and reads the V component of the even column of the pixel data of the same even row from the third FIFO module, so that in the preset front and rear two columns of the pixel data of the same even row, the pixel data of the even column is read first relative to the pixel data of the odd column, especially the Y component of the pixel data of the same row, at this time, only the U component and the V component of the even column are read out to form the pixel data of the specific YUV format. In the specific reading process, only the relevant row and column numbers are replaced, and the reading rules in the row and column direction do not change, which will not be repeated here.

[0056] If the reference column of the pixel data of the matching row is set to the odd column of the pixel data of the odd row of the same frame image, the read control module synchronously reads the Y component of the odd column of the pixel data of the same odd row from the first FIFO module, reads the U component of the odd column of the pixel data of the same odd row from the second FIFO module, and reads the V component of the odd column of the pixel data of the same odd row from the third FIFO module, so that in the preset front and rear two columns of the pixel data of the same odd row, the pixel data of the odd column is read first relative to the pixel data of the even column, especially the Y component of the pixel data of the same row. At this time, only the U component and the V component of the odd column are read out to form the pixel data in a specific YUV format. In the specific reading process, only the relevant row and column numbers are replaced, and the reading rules in the row and column directions do not change, which will not be repeated here.

[0057] If the reference column of the pixel data of the matching row is set to the even column of the pixel data of the odd row of the same frame image, the read control module synchronously reads out the Y component of the even column of the pixel data of the same odd row from the first FIFO module, reads out the U component of the even column of the pixel data of the same odd row from the second FIFO module, and reads out the V component of the even column of the pixel data of the same odd row from the third FIFO module, so that in the preset front and rear two columns of the pixel data of the same odd row, the pixel data of the even column is read first relative to the pixel data of the odd column, especially the Y component of the pixel data of the same row, at this time, only the U component and the V component of the even column are read out to form the pixel data of the specific YUV format. In the specific reading process, only the relevant row and column numbers are replaced, and the reading rules in the row and column direction do not change, which will not be repeated here.

[0058] As another embodiment, the write control module is used for not controlling the U component of the reference column of the next row of pixel data to be written into the second FIFO module to retain the U component of the same column of the pixel data of the current row previously cached, and not controlling the V component of the reference column of the next row of pixel data to be written into the third FIFO module to retain the V component of the same column of the pixel data of the current row previously cached, during each round of writing the Y component of each column of the preset upper and lower rows of pixel data to the first FIFO module. The pixel data of the current row and the pixel data of the next row are recorded as the preset upper and lower rows of pixel data, and the current row is the matching row; if the pixel data written into the current row (including the Y component of each column of the pixel data of the current row) and the pixel data of the next row (including the Y component of each column of the pixel data of the next row) are recorded as a round of writing process, then in this round of writing process, only the U component of the reference column of the pixel data of the current row is written into the second FIFO module, and only the V component of the reference column of the pixel data of the current row is written into the third FIFO module, so that: the read control module reads the pixel data of the current row after reading the pixel data of the current row. After the Y components of all columns of pixel data are read from the second FIFO module, the U component cached by the second FIFO module is kept not updated, and the U component of the reference column of the pixel data of the matching row is repeatedly read from the second FIFO module to realize polling the same batch of U components pre-cached from the starting address of the second FIFO module; and the read control module keeps the V component cached by the third FIFO module not updated, and repeatedly reads the V component of the reference column of the pixel data of the matching row from the third FIFO module to realize polling the same batch of V components pre-cached from the starting address of the third FIFO module. Therefore, every time the write control module continuously writes the Y component of two rows of pixel data to the first FIFO module, the U component of the reference column of the pixel data of a matching row is written to the second FIFO module, and the V component of the reference column of the pixel data of the same matching row is written to the third FIFO module.

[0059] Specifically, among the Y components of each column of the preset upper and lower rows of pixel data, the Y components of the preset upper and lower rows of pixel data written into the first FIFO module in different rounds are Y components with different row orderings among the pixel data of the same frame image, that is, the row sequence numbers of the Y components written into the first FIFO module in each round are different, specifically, the Y components of each column of two adjacent rows of the same frame image written into the first FIFO module in each round; during two adjacent rounds of writing, the Y component of the pixel data of the next row written into the first FIFO module in the current round and the Y component of the pixel data of the current row written into the first FIFO module in the next round are Y components with adjacent row orderings (corresponding to the Y component whose absolute value of the difference of the row sequence numbers in the pixel data of the same column is 1), wherein, in each round of writing, the first FIFO module first caches the Y components of all columns of the pixel data of the current row, corresponding to the write phase of writing the pixel data of the current row; and then refreshes the Y components of all columns of a previously cached row of pixel data (corresponding to the pixel data of the current row) to cache the Y components of all columns of the pixel data of the next row, corresponding to the write phase of writing the pixel data of the next row. In the corresponding writing stage, under the control of the write control module, the second FIFO module caches at most the U components of all reference columns of a row of pixel data in each round of writing, but no refresh operation occurs; correspondingly, the third FIFO module caches at most the V components of all reference columns of a row of pixel data in each round of writing, but no refresh operation occurs. The absolute value of the difference between the U component of the reference column of the same row of pixel data written to the second FIFO module in the current round and the U component of the reference column of the same row of pixel data written to the second FIFO module in the next round in the same frame of image is 2; the absolute value of the difference between the V component of the reference column of the same row of pixel data written to the third FIFO module in the current round and the V component of the reference column of the same row of pixel data written to the third FIFO module in the next round in the same frame of image is 2; further, for the preset upper and lower rows of pixel data, the row number of the Y component written in the current round is less than the row number of the Y component written in the next round, the row number of the U component written in the current round is less than the row number of the U component written in the next round, and the row number of the V component written in the current round is less than the row number of the V component written in the next round. The first FIFO module is updated with pixel data row by row, the second FIFO module is updated with pixel data alternately (such as odd rows), and the third FIFO module is updated with pixel data alternately (such as odd rows).

[0060] On the basis of the above embodiment, the write control module is used to write the Y components of each column of a new row of pixel data to the first FIFO module to update the Y components of each column of a row of pixel data originally stored therein, write the U component of the reference column of a new row of pixel data to the second FIFO module to update the U component of the reference column of a row of pixel data originally stored therein, and write the V component of the reference column of a new row of pixel data to the third FIFO module to update the V component of the reference column of a row of pixel data originally stored therein, whenever the Y components of each column of the preset upper and lower rows of pixel data are written to the first FIFO module, the U component of the reference column of the current row of pixel data is written to the second FIFO module, and the V component of the reference column of the current row of pixel data is written to the third FIFO module. Thereby, the first FIFO module is controlled to cache the Y components of each column of a new row of pixel data to update the Y components of each column of a row of pixel data originally stored therein, the second FIFO module is controlled to cache the U components of the reference columns of a new row of pixel data to update the U components of the reference columns of a row of pixel data originally stored therein, and the third FIFO module is controlled to cache the V components of the reference columns of a new row of pixel data to update the V components of the reference columns of a row of pixel data originally stored therein, thereby realizing that the first FIFO module, the second FIFO module and the third FIFO module are updated simultaneously only after the Y components, U components and V components of the preset upper and lower rows of pixel data are read out.

[0061] As an embodiment, the write control module is used to, in each round of writing the Y components of the preset front and rear two columns of the pixel data of the current row to the first FIFO module, only write the U component of the reference column of the pixel data of the current row to the second FIFO module once and trigger the read control module to perform a read operation, and only write the V component of the reference column of the pixel data of the current row to the third FIFO module once and trigger the read control module to perform a read operation, wherein the current row is the matching row, and this embodiment records the Y component of the current column of the pixel data of the same row and the Y component of the next column of the pixel data of the same row as one round of writing process; then for the write operation of the pixel data of the same row, the write control module is used to, in each round of writing the Y components of the preset front and rear two columns of the pixel data of the current row to the first FIFO module, write the U component of a reference column of the pixel data of the same row to the second FIFO module, and write the V component of a reference column of the pixel data of the same row to the third FIFO module, and determine that the first FIFO module is written with pixel data column by column, the second FIFO module is written with pixel data every other column, and the third FIFO module is written with pixel data every other column.

[0062] Among them, the Y components of the two columns written in the same row share the same U component written to the second FIFO module, and the Y components of the two columns written in the same row share the same V component written to the third FIFO module; therefore, the Y component of the current column among the Y components of the preset front and rear two columns of the pixel data of the current row, the U component of a reference column, and the V component of a reference column can be combined into a pixel data that conforms to a specific YUV format, which can be used as a YUV420 format pixel point that is subsequently read and converted; then the Y component of the latter column among the Y components of the preset front and rear two columns of the pixel data of the current row, the U component of the same reference column, and the V component of the same reference column can be combined into another pixel data that conforms to a specific YUV format, which can be used as another YUV420 format pixel point that is subsequently converted.

[0063] Specifically, among the pixel data of the current row, the Y components of the preset front and rear two columns of the pixel data of the current row written to the first FIFO module in different rounds are Y components with different column orders among the pixel data of the same row; each round writes the Y components of two adjacent columns of the same row of the same frame image into the first FIFO module; the column number corresponding to each Y component written in the current round is different from the column number corresponding to each Y component written in the next round, and the column numbers corresponding to the two Y components written in the same round are also different. During two adjacent rounds of writing to the first FIFO module, the Y component of the next column of the pixel data of the same row written to the first FIFO module in the current round and the Y component of the current column of the pixel data of the same row written to the first FIFO module in the next round are Y components with adjacent column sorting, and are two Y components whose absolute value of the difference in column numbers among the pixel data of the same row is 1; the column number of the U component of the reference column of the pixel data of the same row written to the second FIFO module in the current round and the column number of the U component of the reference column of the pixel data of the same row written to the second FIFO module in the next round differ by 2; the column number of the V component of the reference column of the pixel data of the same row written to the third FIFO module in the current round and the column number of the V component of the reference column of the pixel data of the same row written to the third FIFO module in the next round differ by 2. Preferably, for the pixel data of the same row, the column number of the Y component written in the current round is smaller than the column number of the Y component written in the next round, the column number of the U component written in the current round is smaller than the column number of the U component written in the next round, and the column number of the V component written in the current round is smaller than the column number of the V component written in the next round. Thus, in the pixel data of the same row, the first FIFO module is written with pixel data column by column, the second FIFO module is written with pixel data in alternate columns (such as odd columns), and the third FIFO module is written with pixel data in alternate columns (such as odd columns). Specifically, the pixel data of odd columns can be written into the three FIFO modules, and the pixel data of even columns is only allowed to be written into the first FIFO module.

[0064] As an embodiment, for an image consisting of 4 rows and 8 columns of pixels in a frame, the following writing implementation method is performed:

[0065] In the process of writing the first two columns of data of the first row in the first round, the write control module writes the Y1 component (the Y component of the odd column) to the first FIFO module, writes the U1 component (the U component of the odd column) to the second FIFO module, and writes the V1 component (the V component of the odd column) to the third FIFO module; because in the pixel data of the same row of the same frame image, the write control module writes one U component to the second FIFO module and one V component to the third FIFO module for every two Y components written to the first FIFO module; therefore, the write control module of this embodiment writes one U component of the odd column to the second FIFO module and one V component of the odd column to the third FIFO module for every two Y components written to the first FIFO module. Therefore, the write control module writes the Y2 component (the Y component of the even column) to the first FIFO module, but does not write the U2 component to the second FIFO module, nor does it write the U2 component to the third FIFO module. FIFO module writes V2 component; when writing two new columns of data in the third round (the columns are sorted later, that is, the column numbers are larger), the Y3 component (the Y component of the odd column) is written to the first FIFO module, the U3 component (the U component of the odd column) is written to the second FIFO module, and the V3 component (the V component of the odd column) is written to the third FIFO module; when writing two new columns of data in the fourth round, the Y4 component (the Y component of the even column) is written to the first FIFO module, but the U4 component is not written to the second FIFO module, nor is the V4 component written to the third FIFO module; and so on, after traversing the 8 Y components, 4 U components and 4 V components in the first row of pixel data in the aforementioned writing method, the storage format of the first FIFO module is {Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8}, the storage format of the second FIFO module is {U1, U3, U5, U7}, and the storage format of the third FIFO module is {V1, V3, V5, V7}.

[0066] After writing the pixel data of the first row, the write control module needs to write the Y components of each column of the second row of pixel data into the first FIFO module to update the Y components of each column of the first row of pixel data. However, it is necessary to control the U components of the odd-numbered columns of the first row of pixel data cached in the second FIFO module to remain unchanged, and it is also necessary to control the V components of the odd-numbered columns of the first row of pixel data cached in the third FIFO module to remain unchanged. Then, when the storage format of the first FIFO module is {Y9, Y10, Y11, Y12, Y13, Y14, Y15, Y16}, the storage format of the second FIFO module is still {U1, U3, U5, U7}, and the storage format of the third FIFO module is still {V1, V3, V5, V7}.

[0067] After writing the second row of pixel data, the write control module needs to write the Y components of each column of the third row of pixel data into the first FIFO module, update the Y components of each column of the second row of pixel data, and also needs to update the U components of the odd columns of the third row of pixel data with the U components of the second row of pixel data cached in the second FIFO module, and also needs to update the V components of the odd columns of the third row of pixel data with the V components of the second row of pixel data cached in the second FIFO module. Among them, the Y components of the third row of pixel data written into the first FIFO module are marked as Y17 to Y24 in sequence; the U components of the odd columns of the third row of pixel data written into the second FIFO module are marked as U17 to Y23 in sequence; the V components of the odd columns of the third row of pixel data written into the third FIFO module are marked as V17 to V23 in sequence.

[0068] After writing the third row of pixel data, the write control module needs to write the Y components of each column of the fourth row of pixel data into the first FIFO module to update the Y components of each column of the third row of pixel data. In order to form the twenty-fifth to thirty-second pixel points that conform to the YUV420 format, it is necessary to write into the second FIFO module and the third FIFO module in the same way as the second row of pixel data, which will not be repeated here.

[0069] In the above-mentioned embodiment of the write control module, if the write control module starts from the 0th row and writes the Y components of each column of each row of pixel data of the same frame image to the first FIFO module in sequence, the pixel data of the matching row is set to the pixel data of the even row of the same frame image, and the reference column of the pixel data of the matching row is set to the odd column or its even column of the pixel data of the even row of the same frame image, generally selected to be the even column to comply with the counting rule of the row number; and the cache address of the U component in the second FIFO module is configured according to the writing order, generally the cache address of the written U component is configured in sequence in a first-in-first-out queue storage form; and the cache address of the V component in the third FIFO module is configured according to the writing order, generally the cache address of the written V component is configured in sequence in a first-in-first-out queue storage form.

[0070] If the write control module starts from the first row and writes the Y components of each column of each row of pixel data of the same frame image to the first FIFO module in sequence, the pixel data of the matching row is set to the pixel data of the odd row of the same frame image, and the reference column of the pixel data of the matching row is set to the odd column or even column of the pixel data of the odd row of the same frame image; the odd column is generally selected to comply with the counting rule of the row number; and the cache address of the U component in the second FIFO module is configured in the writing order, generally the cache address of the written U component is configured in sequence in the first-in-first-out queue storage form; and the cache address of the V component in the third FIFO module is configured in the writing order, generally the cache address of the written V component is configured in sequence in the first-in-first-out queue storage form. Thereby reducing the capacity of a single FIFO, saving cache bandwidth when processing U and V components in alternate rows or columns.

[0071] In the aforementioned embodiment, if the reference column of the pixel data of the matching row is set to the odd column of the pixel data of the even row of the same frame image, the read control module writes the Y component of the odd column of the pixel data of the same even row to the first FIFO module, synchronously writes the U component of the odd column of the pixel data of the same even row to the second FIFO module, and synchronously writes the V component of the odd column of the pixel data of the same even row to the third FIFO module, so that among the preset front and rear two columns of the pixel data of the same even row, the pixel data of the odd column is written into the corresponding FIFO module before the pixel data of the even column, so that among the pixel data of the same row, only the odd column of the U component and the V component are read out to form pixel data in a specific YUV format.

[0072] If the reference column of the pixel data of the matching row is set to the even column of the pixel data of the even row of the same frame image, the read control module writes the Y component of the even column of the pixel data of the same even row to the first FIFO module, synchronously writes the U component of the even column of the pixel data of the same even row to the second FIFO module, and synchronously writes the V component of the even column of the pixel data of the same even row to the third FIFO module, so that among the preset front and rear two columns of the pixel data of the same even row, the pixel data of the even column is written into the corresponding FIFO module first relative to the pixel data of the odd column; so that among the pixel data of the same row, only the U component and the V component of the even column are read out to form pixel data in a specific YUV format.

[0073] If the reference column of the pixel data of the matching row is set to the odd column of the pixel data of the odd row of the same frame image, the read control module writes the Y component of the odd column of the pixel data of the same odd row to the first FIFO module, synchronously writes the U component of the odd column of the pixel data of the same odd row to the second FIFO module, and synchronously writes the V component of the odd column of the pixel data of the same odd row to the third FIFO module, so that among the preset front and rear two columns of the pixel data of the same odd row, the pixel data of the odd column is written into the corresponding FIFO module first relative to the pixel data of the even column; so that among the pixel data of the same row, only the odd columns of the U component and the V component are read out to form pixel data in a specific YUV format.

[0074] If the reference column of the pixel data of the matching row is set to the even column of the pixel data of the odd row of the same frame image, the read control module writes the Y component of the even column of the pixel data of the same odd row to the first FIFO module, synchronously writes the U component of the even column of the pixel data of the same odd row to the second FIFO module, and synchronously writes the V component of the even column of the pixel data of the same odd row to the third FIFO module, so that among the preset front and rear two columns of the pixel data of the same odd row, the pixel data of the even column is written into the corresponding FIFO module first relative to the pixel data of the odd column; so that among the pixel data of the same row, only the even columns of the U component and the V component are read out to form pixel data in a specific YUV format.

[0075] In order to read and write the Y component, the U component and the V component respectively to form corresponding pixel data in YUV format under the premise of low transmission bandwidth and small on-chip area (the area occupied by the bus cache resources in the chip and the storage resources in the chip), so that in the same row of pixel data, every two identical Y components correspond to one U component and the two identical Y components correspond to one V component, and in two adjacent rows of pixel data, every four identical Y components correspond to the same U component and the four identical Y components correspond to the same V component, so as to meet the image pixel compression format; the present invention also discloses a read and write control method for image data, which is used to read and write pixel data in YUV format.

[0076] In this embodiment, the three pixel components of each row of the image are respectively stored in a corresponding FIFO module (FIFO queue), and a first FIFO module for storing the Y component, a second FIFO module for storing the U component, and a third FIFO module for storing the U component are designed respectively.

[0077] The read-write control method comprises: step A, from a frame of image pre-stored externally, sequentially writing the Y component of each column of each row of pixel data into the first FIFO module, sequentially writing the U component of the reference column of the pixel data of the matching row into the second FIFO module, sequentially writing the V component of the reference column of the pixel data of the matching row into the third FIFO module, so that each time the Y component of the preset upper and lower rows of pixel data is continuously written into the first FIFO module, the U component of the reference column of a row of pixel data is written into the second FIFO module, and the V component of the reference column of a row of pixel data is written into the third FIFO module, wherein the Y component of the upper and lower rows of pixel data that are not repeated is written into the first FIFO module; for the same frame of image, updating the first FIFO module row by row The pixel data (specifically the Y component) pre-cached in the first FIFO module is updated in an alternate row, the pixel data (specifically the U component) in the second FIFO module is updated in an alternate row, and the pixel data (specifically the V component) cached in the third FIFO module is updated in an alternate row. If counting starts from 1, the U component in the second FIFO module is refreshed only when the pixel data of the odd rows is obtained from a pre-stored frame of image, and the V component in the third FIFO module is refreshed only when the pixel data of the odd rows is obtained from a pre-stored frame of image, then the matching rows are the odd rows of the same frame of image, and the corresponding reference columns are the odd columns of the same frame of image; in this embodiment, a row of pixel data is first read back from the memory of the peripheral device, and then the Y component, U component and V component are respectively stored in three different FIFO modules.

[0078] The read-write control method further includes: step B, whenever the Y components of each column of a row of pixel data are written into the first FIFO module, the Y components are read from the first FIFO module in sequence, so that the first FIFO module caches the Y components of the same frame image row by row; in particular, after the Y components of each column of a row of pixel data are written into the first FIFO module, each time the Y components of the preset two columns before and after the pixel data of the same row are read from the first FIFO module continuously (which can be counted as reading twice), the U component of the reference column of the pixel data of the matching row is read from the second FIFO module once, which can be counted as reading the U component of the reference column of the pixel data of the same row once and can be retained for conversion into a specific YUV format; and the V component of the reference column of the pixel data of the matching row is read from the third FIFO module once, which can be counted as reading the U component of the reference column of the pixel data of the same row once and can be retained for conversion into a specific YUV format. Formula; thereby, in the pixel data of the same row of the same frame image, the pixel data is read column by column through the first FIFO module, that is, the first FIFO module caches and transmits the Y component of a row of pixel data column by column, so that the first FIFO module reads the pixel data column by column; correspondingly, in the pixel data of the same row of the same frame image, the pixel data is read by the second FIFO module in alternate columns, that is, the second FIFO module caches and transmits the U component of a row of pixel data in alternate columns, and relative to the first FIFO module, in the same data reading cycle, the second FIFO module reads the U component in alternate columns (for example, odd columns), and the third FIFO module reads the V component in alternate columns (for example, odd columns), so that every time two Y components are read continuously from the first FIFO module, one U component is read from the second FIFO module, and one V component is read from the second FIFO module, thereby forming pixel data in corresponding YUV format.

[0079] The read-write control method further includes: step C, in the process of continuously writing the Y component of the preset upper and lower two rows of pixel data into the first FIFO module, repeatedly reading the U component of the reference column of the pixel data of the same matching row from the second FIFO module twice, and repeatedly reading the V component of the reference column of the pixel data of the same matching row from the third FIFO module twice, so as to form pixel data conforming to a specific YUV format. Specifically, in the process of continuously writing the Y component of the preset upper and lower two rows of pixel data into the first FIFO module, continuously reading the Y component of the preset upper and lower two rows of pixel data from the first FIFO module can be counted as reading two rows, and is synchronously performed with the write operation to implement a pipeline structure, and repeatedly reading the U component of the reference column of the pixel data of the same matching row from the second FIFO module twice, and repeatedly reading the V component of the reference column of the pixel data of the same matching row from the third FIFO module twice. For the same frame image or each line of pixel data thereof, if the Y component pre-cached in the first FIFO module is updated line by line, the Y component is read line by line through the first FIFO module; if the U component in the second FIFO module is updated interlaced, the U component is read interlaced through the second FIFO module; if the V component in the third FIFO module is updated interlaced, the V component is read interlaced through the third FIFO module.

[0080] For the reading of the pixel data of the same row, in each round of reading the Y components of the preset two columns before and after the pixel data of the current row from the first FIFO module, the U component of a reference column of the pixel data of the matching row is read from the second FIFO module, and the V component of a reference column of the pixel data of the matching row is read from the third FIFO module, wherein the matching row is the current row; when the Y component of the current column is read out from the first FIFO module, on the one hand, the U component and the V component currently read out are matched with the Y component of the current column to form the pixel data of the specific YUV format, and on the other hand, the U component and the V component currently read out are temporarily cached; when the next column of Y components is read out from the first FIFO module, it is not necessary to read the U component from the second FIFO module, nor to read the V component from the third FIFO module, but the previously cached U component and the V component are directly used to match the next column of Y components to form the new specific YUV format of pixel data; thereby, in the pixel data of the same row of the same frame image, for every two Y components read out from the first FIFO module, one is read out from the second FIFO module. U components are read from the third FIFO module, and a V component is read from the third FIFO module, where the reading process of the Y components of the preset front and rear two columns of the pixel data of the current row is recorded as a round of reading process, specifically a round of reading operation of two adjacent columns (pieces) of pixel components in the same row, and in each round of reading, two Y components in the pixel data of the same row are read from the first FIFO module, wherein the two Y components share the same U component read from the second FIFO module, and the two Y components share the same V component read from the third FIFO module; therefore, the Y component of the current column among the Y components of the preset front and rear two columns of the pixel data of the current row, the U component of a reference column, and the V component of a reference column can be composed of a pixel data conforming to a specific YUV format, which can be used as a pixel point in the YUV420 format converted first; then the Y component of the latter column among the Y components of the preset front and rear two columns of the pixel data of the current row, the U component of the same reference column, and the V component of the same reference column can be composed of another pixel data conforming to a specific YUV format, which can be used as a pixel point in the YUV420 format converted later.

[0081] For reading pixel data of different rows or two rows above and below, in each round of reading the Y component of each column of the preset two rows above and below, whenever the Y component of one column of the pixel data of the current row is read, the Y component of the corresponding column of the pixel data of the next row is controlled to be written into the first FIFO module, and the U component of the pixel data of the next row is not triggered to be written into the second FIFO module, but the U component of the pixel data of the current row has been written into the second FIFO module, so that the U component of the pixel data of the current row cached in the second FIFO module is not refreshed by the U component of the pixel data of the next row; and the V component of the pixel data of the next row is not triggered to be written into the third FIFO module, but the V component of the pixel data of the current row has been written into the third ... The V component of the pixel data of the current row cached in the third FIFO module is not refreshed by the V component of the pixel data of the next row; wherein the pixel data of the current row and the pixel data of the next row are recorded as preset upper and lower rows of pixel data, and reading the pixel data of the current row (including the Y component of each column of the pixel data of the current row) and the pixel data of the next row (including the Y component of each column of the pixel data of the next row) is recorded as a round of reading process, specifically a round of reading operation of the Y component of each column of two adjacent rows, so that for every two consecutive times the Y component of two rows of pixel data is read from the first FIFO module, the U component of the reference column of the pixel data of the same row is read twice from the second FIFO module, and the V component of the reference column of the pixel data of the same row is read twice from the third FIFO module. On the basis that the current row is a matching row, in each round of reading the Y components of each column of the preset upper and lower rows of pixel data, after reading the Y components of all columns of the pixel data of the current row, repeatedly read the U components of the reference column of the pixel data of the matching row from the second FIFO module once to realize polling from the same starting address of the second FIFO module (i.e., re-reading from the first address unit) of the same batch of U components pre-cached therein, the same batch of U components can be understood as the U components of the reference column of the pixel data of the current row, corresponding to the U components of the reference column of the pixel data of the matching row, and the implementation method of polling from the same starting address in the second FIFO module is to let it The read pointer restores the initial address value to facilitate re-traversal of the U component cached in the second FIFO module; and repeatedly reads the V component of the reference column of the pixel data of the matching row from the third FIFO module once to realize polling from the same starting address of the third FIFO module (i.e., re-reading from the first address unit) the same batch of V components pre-cached therein, the same batch of V components can be understood as the V component of the reference column of the pixel data of the current row, corresponding to the V component of the reference column of the pixel data of the matching row, and the implementation method of polling from the same starting address in the third FIFO module is to restore the initial address value of the read pointer to facilitate re-traversal of the V component cached in the third FIFO module.

[0082] Accordingly, the various component modules of the read-write control system disclosed in the aforementioned embodiment completely correspond to the various read-write modes of the read-write control method flow, and the various component modules of the read-write control system disclosed in the aforementioned embodiment should be understood as the hardware logic circuit modules that must be established to implement the various read-write modes of the read-write control method flow. The technical solution of the read-write control system defined by such a group of hardware logic circuit modules can be understood as a physical device that mainly implements the solution through hardware, and can also be understood as a program module framework that mainly implements the technical problems existing in the aforementioned background technology through the computer program corresponding to the read-write control method. In particular, the read control module and the write control module disclosed in the aforementioned embodiment can be integrated into a control module as the execution subject of the read-write control method.

[0083] Preferably, if counting starts from 1, in the process of continuously reading the Y component of two adjacent rows of pixel data from the first FIFO module (implemented under the premise of updating row by row), the U component of the pixel data belonging to the same odd row of the same frame image is repeatedly read from the second FIFO module twice, and the V component of the pixel data belonging to the same odd row of the same frame image is repeatedly read from the third FIFO module twice. Therefore, the U component of the odd row read from the second FIFO module for the first time, the V component of the odd row read from the third FIFO module in the same batch (in the same reading cycle, also recorded as the first time), and the Y component of the odd row read from the first FIFO module in the same batch (in the same reading cycle, also recorded as the first time) can constitute the pixel data in the YUV420 format; and the U component of the odd row read from the second FIFO module for the second time, the V component of the odd row read from the third FIFO module in the same batch (in the same reading cycle, also recorded as the second time) can constitute the pixel data in the YUV420 format. The V component of the odd rows and the Y component of the even rows read from the first FIFO module in the same batch (within the same reading cycle, also recorded as the second time) can also form pixel data in YUV420 format, wherein the U component of each column of the odd rows read from the second FIFO module for the second time is equal to the U component of the same column of the odd rows read from the second FIFO module for the first time, and the V component of each column of the odd rows read from the third FIFO module for the second time is equal to the V component of the same column of the odd rows read from the third FIFO module for the first time.

[0084] On the basis of the above embodiment, when the Y component of a column of a row of pixel data is read from the first FIFO module, the U component of the reference column of the pixel data of the matching row is read from the second FIFO module, and the V component of the reference column of the pixel data of the matching row is read from the third FIFO module, and then the currently read Y component, U component and V component are combined into image pixels conforming to the YUV format, specifically for each row of pixel data in the same frame image; thereby, the bandwidth for reading data is saved compared to the reading state in which the U component and the V component in the pixel data in the YUV format correspond one-to-one with the Y component, and the reading bandwidth resources are saved for each row of pixel data in the same frame image.

[0085] In summary, the present invention designs three FIFO modules, namely, a first FIFO module for storing Y components, a second FIFO module for storing U components, and a third FIFO module for storing U components. In order to obtain pixel data conforming to the YUV format, it is configured under the condition of reading pixel data of the same row: whenever the Y components of the preset two columns before and after the pixel data of the same row are continuously read from the first FIFO module, the U component of the reference column of the pixel data of the matching row is read from the second FIFO module once, and the V component of the reference column of the pixel data of the matching row is read from the third FIFO module once, so that in the pixel data of the same row, the first FIFO module is read column by column, and the second FIFO module is read column by column. Pixel data is read in alternate columns (such as odd columns), and the third FIFO module reads pixel data in alternate columns (such as odd columns). Specifically, the pixel data of odd columns are read from the three FIFO modules, and the Y components of even columns are only read from the first FIFO module. U components with the same values ​​are not cached repeatedly in the second FIFO module, and V components with the same values ​​are not cached repeatedly in the third FIFO module, because in this embodiment, the U component of the odd column among the preset front and rear two columns of the pixel data in the same row is equal to the U component of the even column among the preset front and rear two columns of the pixel data in the same row, and the V component of the odd column among the preset front and rear two columns of the pixel data in the same row is equal to the V component of the even column among the preset front and rear two columns of the pixel data in the same row. Under the condition of reading pixel data across rows, it is configured that: every time the Y component of two rows of pixel data is continuously written to the first FIFO module, only the U component of the reference column of the pixel data of one row is written to the second FIFO module, and only the V component of the reference column of the pixel data of one row is written to the third FIFO module, so that the first FIFO module is updated with pixel data row by row, the second FIFO module is updated with pixel data alternately (for example, odd rows), and the third FIFO module is updated with pixel data alternately (for example, odd rows); then, in the process of reading the Y component of the corresponding row of pixel data from the first FIFO module twice in a row, the U component of the reference column of the pixel data of the same matching row is repeatedly read from the second FIFO module twice, and the V component of the reference column of the pixel data of the same matching row is repeatedly read from the third FIFO module twice. Further, based on the pixel array of the same frame image, it can be understood that the first FIFO module transmits the Y component row by row and column by column, the second FIFO module updates the U component across rows and columns and transmits the U component in the same row and columns, and the third FIFO module updates the V component across rows and columns and transmits the V component in the same row and columns.Compared with the reading and writing method of pixel data in YUV format provided by the prior art, the present invention can manage the area occupied by the FIFO module and the bandwidth resources required for reading and writing under the premise of converting and processing images with the same resolution, including: reducing the capacity of a single FIFO (it is not necessary to fill all three pixel components into the same FIFO module), saving cache bandwidth when processing the U component and the V component in the same frame image in alternate rows or columns; and there is no need to set cache space outside the first FIFO module, the second FIFO module and the third FIFO module to store the pixel data read from the peripheral memory and the pixel data read from the FIFO module. By repeatedly caching the pixel data of specific rows and specific columns in batches in a corresponding FIFO or caching the pixel data of specific rows and specific columns in three FIFOs at the same time, the process of converting a larger resolution image and saving it in YUV format is accelerated, and the transmission time in the additional cache space is reduced.

[0086] Preferably, a pre-stored frame of image is composed of a group of pixel data blocks, or multiple groups of pixel data blocks, wherein each group of pixel data blocks is composed of pixel data corresponding to a pixel array, and preferably, a pixel array is composed of 4 rows and 8 columns of pixels, so as to convert pixel data in YUV420 format; it should be noted that pixels of the same color are composed of four adjacent pixels in the upper, lower, left and right directions, which are equivalent to four pixels in a four-square grid area, and pixels of the same color share the same U component, and pixels of the same color share the same V component, so that in two rows of pixels in the pixel array, there are two columns of pixels sharing the same U component, and the two columns of pixels share the same V component; therefore, the storage form of a frame of image in the memory is as follows: for every 4 Y components stored, a corresponding U component and a corresponding V component are mapped, and a U component is not matched by repeatedly storing multiple identical U components and multiple identical V components to be read to form pixel data in a specific YUV format.

[0087] Preferably, in a pixel array, each pixel has a Y component; in the same pixel array, if the number of U components and the number of V components do not correspond one-to-one to the number of Y components, then in order to facilitate reading and converting the image in YUV format, the U component and the V component can be copied and expanded to four times the original, then the U component and the V component correspond one-to-one to the Y component, then in the same pixel array, each pixel has a Y component, a U component and a V component, if the pixel data is read in the order of the row number and the column number of each pixel, including each Y component, each U component and each V component, it will occupy a large bandwidth, therefore, the method of storing the pixel array or the frame of image in this embodiment is to first continuously store the Some Y components, and then continuously store all the uncopied U components, and then continuously store all the uncopied V components. At this time, the number of U components and the number of V components are less than the number of Y components, but the storage address mapping of the four Y components adjacent to each other up, down, left, and right can correspond to the storage address of a U component, and the storage address of the U component and the corresponding storage address of each Y component are assigned index information that is in the same row and column, and the storage address of the V component and the storage address of each Y component are assigned index information that is in the same row and column. Specifically, it is convenient to write a Y component into the first FIFO module, write the U component assigned the index information of the same row and column into the second FIFO module, and write the V component assigned the index information of the same row and column into the third FIFO module.

[0088] In the above embodiment, a frame of image to be read and written is composed of 4 rows and 8 columns of pixels, forming an image with a resolution of 8 times 4, with a total of 32 pixels. Its storage format in the memory of the external device is as follows: the Y components of four rows and eight columns are input into the memory in sequence, forming a storage format of {Y1, Y2, Y3, ..., Y31, Y32}, wherein the number after Y represents the index number in a pixel array, and if the row number starts counting from 0, the index number of the Y component of the mth column of the nth row is equal to m+8*n, where n is an integer greater than or equal to 0 but less than 4, m is a positive integer less than or equal to 8, and * represents multiplication. Then the two rows and four columns of U components are serially input into the memory to form a storage format of {U1, U3, U5, ..., U21, U23}, where the number after U represents the index number in a pixel array. If the row number starts counting from 0, the index number of the U component in the qth column of the pth row is equal to p+16*q, q is an even number less than 4 and q is greater than or equal to 0, p is an odd number less than or equal to 8 and p is greater than 0, and * represents multiplication. Then the two rows and four columns of V components are serially input into the memory to form a storage format of {V1, V3, V5, ..., V21, V23}, where the number after V represents the index number in a pixel array. If the row number starts counting from 0, the index number of the V component in the qth column of the pth row is equal to p+16*q, q is an even number less than 4 and q is greater than or equal to 0, p is an odd number less than 8 and p is greater than 0, and * represents multiplication.

[0089] It should be noted that the Y component of a frame of image is written into the first FIFO module in a serial transmission manner, and the address index number of the Y component in the first FIFO module is configured according to the writing order, forming the order in which the Y component is read by the corresponding read pointer in the first FIFO module; the U component of a frame of image is written into the second FIFO module in a serial transmission manner, and the address index number of the U component in the second FIFO module is configured according to the writing order, forming the order in which the U component is read by the read pointer in the second FIFO module; the V component of a frame of image is written into the third FIFO module in a serial transmission manner, and the address index number of the V component in the third FIFO module is configured according to the writing order, forming the order in which the V component is read by the read pointer in the third FIFO module; according to the corresponding address index number, the Y component is read from the first FIFO module, the U component is read from the second FIFO module, and the V component is read from the third FIFO module in turn to form pixel data in YUV format.

[0090] Among them, the depth size of the first FIFO module is equal to the number of all Y components in a row of pixel data, the depth size of the second FIFO module is equal to the number of U components of all reference columns in a row of pixel data, and the depth size of the third FIFO module is equal to the number of V components of all reference columns in a row of pixel data; half of the depth size of the first FIFO module is equal to the depth size of the second FIFO module, and the depth size of the second FIFO module is equal to the depth size of the third FIFO module. If a frame of image to be processed is composed of 4 rows and 8 columns of pixels, then a row of pixel data has 8 Y components, so the depth of the first FIFO module is set to 8, and the depth of the second FIFO module and the depth of the third FIFO module are both set to 4.

[0091] It should be noted that the FIFO module is the abbreviation of First In First Out in English. It is a first-in-first-out dual-port buffer, that is, the first data entering it is the first to be removed, one of which is the input port of the memory and the other is the output port of the memory. The difference between the FIFO module and the ordinary memory is that there is no external read and write address line, so it is very simple to use. Data can only be written and read sequentially. Its data address is completed by the pre-configured read pointer and write pointer traversal. Unlike ordinary memory, it can be determined by the address line to read or write a certain specified address. Based on the cognitive level of those skilled in the art, it can be known that the FIFO (First In First Out) module is a first-in-first-out cache device, which can pre-write the obtained data into the FIFO module, and then take out all of them in the original order and provide them to the device that needs the data. An important indicator of the FIFO module is the maximum number of data that the FIFO module can store, which is called depth. For a FIFO module with a smaller depth, its storage unit uses a FIFO register, hereinafter referred to as FIFO, such as: receiving FIFO and sending FIFO. For a FIFO module with a larger depth, its storage unit uses SRAM (Static Random Access Memory). Generally, the working principle of the FIFO module is as follows: data is read / written sequentially from / to the storage module under the control of read / write pulses with independent read / write address pointers. The read / write pointers start from the first address unit, read / write sequentially to the last address unit, and then return to the first address unit.

[0092] As an embodiment, among the pixel data of the current row, the Y components of the preset front and rear two columns of the pixel data of the current row read from the first FIFO module in different rounds are Y components with different column orderings among the pixel data of the current row, and each round reads the Y components of the adjacent two columns of the same row of the same frame image from the first FIFO module; the column number corresponding to each Y component read in the current round is different from the column number corresponding to each Y component read in the next round, and the column number corresponding to each Y component read in the same round is also different. During two adjacent rounds of reading, the Y component of the rear column of the pixel data of the same row read from the first FIFO module in the current round and the Y component of the current column of the pixel data of the same row read from the first FIFO module in the next round are Y components with adjacent column orderings, and are two Y components whose absolute value of the difference in column number among the pixel data of the same row is 1. On the other hand, the absolute value of the difference in column numbers between the U component of the reference column of the same row of pixel data read from the second FIFO module in the current round and the U component of the reference column of the same row of pixel data read from the second FIFO module in the next round in the same frame image is 2; the absolute value of the difference in column numbers between the V component of the reference column of the same row of pixel data read from the third FIFO module in the current round and the V component of the reference column of the same row of pixel data read from the third FIFO module in the next round in the same frame image is 2. Preferably, for the same row of pixel data, the column number of the Y component read in the current round is smaller than the column number of the Y component read in the next round, the column number of the U component read in the current round is smaller than the column number of the U component read in the next round, and the column number of the V component read in the current round is smaller than the column number of the V component read in the next round. Thereby, in the pixel data of the same row, the first FIFO module reads the pixel data column by column, the second FIFO module reads the pixel data in alternate columns (for example, odd columns), and the third FIFO module reads the pixel data in alternate columns (for example, odd columns). Specifically, the pixel data of odd columns are all read from the three FIFO modules, and the pixel data of even columns are only read from the first FIFO module.

[0093] As an embodiment, in order to form pixel data of an image in YUV format from the first FIFO module, the second FIFO module and the third FIFO module, this embodiment makes the following reading implementation method for an image composed of 4 rows and 8 columns of pixels in a frame: for the first and second columns of the first row of pixel data cached, it is recorded as the first round of reading two columns of data, the Y1 component (the Y component of the odd column) is read from the first FIFO module, the U1 component (the U component of the odd column) is read from the second FIFO module and temporarily stored, and the V1 component (the V component of the odd column) is read from the third FIFO module. ) and temporarily store them to form the first pixel point Y1U1V1 that conforms to the YUV420 format; since in the pixel data of the same row of the same frame image, for every two Y components read from the first FIFO module, a U component is read from the second FIFO module, and a V component is read from the third FIFO module; therefore, in this embodiment, for every two Y components read from the first FIFO module, a U component of an odd column is read from the second FIFO module, and a V component of an odd column is read from the third FIFO module, that is, the first FIFO module, the second FIFO module and the third FIFO module are read. If the first FIFO module reads the pixel components of odd columns, only the Y component of even columns is read from the first FIFO module; therefore, when reading the other two columns of the first row of cached pixel data, it is recorded as the second round of reading two columns of data, reading the Y2 component (the Y component of the even column) from the first FIFO module, and then continuing to use the temporarily stored U1 component and V1 component to form the second pixel point Y2U1V1 that conforms to the YUV420 format; when reading two columns of data in the third round, read the Y3 component (the Y component of the odd column) from the first FIFO module, and read the U3 component (the U component of the odd column) from the second FIFO module. And temporarily store it, read the V3 component (the V component of the odd column) from the third FIFO module and temporarily store it to form the third pixel point Y3U3V3 that conforms to the YUV420 format; when reading two columns of data in the fourth round, read the Y4 component (the Y component of the even column) from the first FIFO module, and then continue to use the temporarily stored U3 component and V3 component to form the fourth pixel point Y4U3V3 that conforms to the YUV420 format; and so on, traverse the 8 Y components in the first row of pixel data according to the aforementioned reading method to form the fifth, sixth, seventh, and eighth pixel points that conform to the YUV420 format.

[0094] On the basis of the above embodiment, in each round of reading the Y component of each column of the preset upper and lower rows of pixel data, each time the Y component of a column of the pixel data of the current row is read, the Y component of the corresponding column of the pixel data of the next row is triggered to be written into the first FIFO module. The reason is that after the pixel data of the current row is written, the first FIFO module has been filled, and then each time the Y component of a column of the pixel data of the current row is read from the first FIFO module, the read address pointer will move to the next address unit, and the address read last time can be written by the Y component of the corresponding column of the pixel data of the next row and the Y component at the address is updated, so as to realize the pipeline mechanism; at this time, it is also possible to read the U component and V component of the reference column of the pixel data of the current row, and before reading, the U component of the reference column of the pixel data of the matching row has filled the second FIFO module, and the V component of the reference column of the pixel data of the matching row has filled the third FIFO module, wherein the matching row is the current row; even if one U component in the second FIFO module is read under the guidance of the read pointer, but The U component of the pixel data of the next row is not triggered to be written into the second FIFO module to prevent the data cached in the second FIFO module from being updated, and the V component of the pixel data of the next row is not triggered to be written into the third FIFO module to prevent the data cached in the third FIFO module from being updated; therefore, after reading the Y components of all columns of the pixel data of the current row, the U component cached in the second FIFO module is kept not updated, and the U component of the reference column of the pixel data of the matching row is repeatedly read from the second FIFO module to realize polling the same batch of U components pre-cached from the starting address of the second FIFO module, the same batch of U components are the U components of the reference column of the pixel data of the matching row of the second FIFO module that are pre-filled, and the way to repeatedly read the U component of the reference column of the pixel data of the matching row from the second FIFO module is to clear the read pointer of the second FIFO module to point back to the starting address of the second FIFO module, and then the read pointer of the second FIFO module starts to offset to realize repeated reading of the U component of the reference column of the pixel data of the matching row.Furthermore, the V component cached in the third FIFO module is kept not updated, and the V component of the reference column of the pixel data of the matching row is repeatedly read from the third FIFO module to realize polling the same batch of V components pre-cached therein starting from the starting address of the third FIFO module, wherein the same batch of V components is the V component of the reference column of the pixel data of the matching row pre-filled in the third FIFO module, and the manner of repeatedly reading the V component of the reference column of the pixel data of the matching row from the third FIFO module is to clear the read pointer of the third FIFO module to point back to the starting address of the third FIFO module, and then the read pointer of the third FIFO module starts to offset to realize repeated reading of the V component of the reference column of the pixel data of the matching row. Therefore, in the process of reading the Y component of the pixel data of the current row from the first FIFO module twice in a row, the U component of the reference column of the pixel data of the same matching row (current row) is repeatedly read from the second FIFO module twice, and the V component of the reference column of the pixel data of the same matching row (current row) is repeatedly read from the third FIFO module twice.

[0095] Specifically, for an image composed of 4 rows and 8 columns of pixels in a frame, after reading a row of pixel data, that is, reading out the 8 Y components in the first row of pixel data and sequentially forming the first to eighth pixels that conform to the YUV420 format, it is necessary to write the Y components of each column of the second row of pixel data into the first FIFO module, and update the Y components of each column of the first row of pixel data. However, it is necessary to control the U components of the odd columns of the first row of pixel data cached in the second FIFO module to remain unchanged, and it is also necessary to control the V components of the odd columns of the first row of pixel data cached in the third FIFO module to remain unchanged. It should be noted that the corresponding read pointer points to the fourth unit address of the second FIFO module, and the corresponding read pointer points to the fourth unit address of the third FIFO module. As long as new data is not written to the corresponding FIFO module subsequently, the FIFO module will still maintain the original number. Therefore, the read pointer of the FIFO module is cleared to 0 at this time, so that it continues to point to the first unit address, so that the second FIFO module and the third FIFO module can repeat the reading again. The Y component of the second line of pixel data written into the first FIFO module is marked as Y9 to Y16 in sequence. In order to form the ninth to sixteenth pixel points that conform to the YUV420 format, the reading method is similar to the reading method of each pixel component of the first line of pixel data, and the U component read from the second FIFO module and the V component read from the third FIFO module do not change compared with when processing the first line of pixel data.

[0096] In the above embodiment, among the Y components of each column of the preset upper and lower rows of pixel data, the Y components of the preset upper and lower rows of pixel data read from the first FIFO module in different rounds are Y components with different row orderings among the pixel data of the same frame image, wherein the pixel data of the current row and the pixel data of the next row are recorded as the preset upper and lower rows of pixel data, if reading the pixel data of the current row (including the Y components of each column of the pixel data of the current row) and the pixel data of the next row (including the Y components of each column of the pixel data of the next row) is recorded as a round of reading process, then each round reads the Y components of each column of two adjacent rows of the same frame image from the first FIFO module; further, in the two adjacent rounds of reading process, the Y component of the pixel data of the next row read from the first FIFO module in the current round and the Y component of the pixel data of the current row read from the first FIFO module in the next round are Y components with adjacent row orderings, which can be understood as two Y components whose absolute value of the difference in row sequence number in the same column of pixel data is 1. At the same time, the absolute value of the difference in row number between the U component of the reference column of the same row of pixel data read from the second FIFO module in the current round and the U component of the reference column of the same row of pixel data read from the second FIFO module in the next round in the same frame image is 2; the absolute value of the difference in row number between the V component of the reference column of the same row of pixel data read from the third FIFO module in the current round and the V component of the reference column of the same row of pixel data read from the third FIFO module in the next round in the same frame image is 2.

[0097] Preferably, for the preset upper and lower rows of pixel data, the row number of the Y component read in the current round is smaller than the row number of the Y component read in the next round, the row number of the U component read in the current round is smaller than the row number of the U component read in the next round, and the row number of the V component read in the current round is smaller than the row number of the V component read in the next round.

[0098] On the basis of the above embodiment, whenever the Y component of each column of the preset upper and lower rows of pixel data is read, the U component of the reference column of the pixel data of the current row (the matching row) is read from the second FIFO module, and the V component of the reference column of the pixel data of the current row (the matching row) is read from the third FIFO module, the first FIFO module is triggered to cache the Y component of each column of a new row of pixel data to update the Y component of each column of a row of pixel data originally stored, the second FIFO module is triggered to cache the U component of the reference column of a new row of pixel data to update the U component of the reference column of a row of pixel data originally stored, and the third FIFO module is triggered to cache the V component of the reference column of a new row of pixel data to update the V component of the reference column of a row of pixel data originally stored, so that the first FIFO module, the second FIFO module and the third FIFO module are updated simultaneously after the Y component, U component and V component of the preset upper and lower rows of pixel data are read. Specifically, for an image consisting of 4 rows and 8 columns of pixels in a frame, after reading two rows of pixel data, that is, reading out the 8 Y components in the first row of pixel data and the 8 Y components in the second row of pixel data and sequentially forming the first to sixteenth pixels that conform to the YUV420 format, it is necessary to write the Y components of each column of the third row of pixel data into the first FIFO module, update the Y components of each column of the second row of pixel data, and also update the U components of the odd columns of the third row of pixel data with the U components of the second row of pixel data cached in the second FIFO module, and also update the V components of the odd columns of the third row of pixel data with the V components of the second row of pixel data cached in the second FIFO module. Among them, the Y component of the third row of pixel data written into the first FIFO module is marked as Y17 to Y24 in sequence; the U component of the odd-numbered columns of the third row of pixel data written into the second FIFO module is marked as U17 to Y23 in sequence; the V component of the odd-numbered columns of the third row of pixel data written into the third FIFO module is marked as V17 to V23 in sequence; in order to form the seventeenth to twenty-fourth pixel points that conform to the YUV420 format, the reading method is similar to the reading method of each pixel component of the first row of pixel data, which will not be repeated here. For the introduction of the write operation of the relevant FIFO module in this embodiment, please refer to the above-mentioned read-write control system embodiment, which will not be repeated here.

[0099] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0100] Professionals may further appreciate that the modules and algorithm flows of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0101] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, software modules executed by a processor, or a combination of the two. The software modules may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0102] The above is a detailed introduction to the pixel data read-write control system and the read-write control method provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A read-write control system for image data, characterized in that: The read-write control system is used to read and write pixel data; the read-write control system includes a write control module, a read control module, a first FIFO module, a second FIFO module and a third FIFO module; A write control module, used to sequentially write the Y component of each column of each row of pixel data from a frame of image pre-stored externally into the first FIFO module, sequentially write the U component of the reference column of the pixel data of the matching row into the second FIFO module, and sequentially write the V component of the reference column of the pixel data of the matching row into the third FIFO module; A read control module, configured to read the Y components from the first FIFO module in sequence whenever the write control module writes the Y components of each column of a row of pixel data into the first FIFO module; The read control module is used to read the U component of the reference column of the pixel data in the same row from the second FIFO module and read the V component of the reference column of the pixel data in the same row from the third FIFO module whenever the Y components of the preset two preceding and following columns of the pixel data in the same row are read continuously from the first FIFO module, so as to form the pixel data in a specific YUV format; the read control module is also used to repeatedly read the U component of the reference column of the pixel data in the same matching row from the second FIFO module twice and repeatedly read the V component of the reference column of the pixel data in the same matching row from the third FIFO module twice in the process of the write control module continuously writing the Y components of the preset two preceding and following rows of pixel data into the first FIFO module, so as to form the pixel data in a specific YUV format; A read control module, configured to, in each round of reading the Y components of each column of the preset upper and lower rows of pixel data, trigger the write control module to control the Y component of the corresponding column of the next row of pixel data to be written into the first FIFO module, and not trigger the U component of the next row of pixel data to be written into the second FIFO module, and not trigger the V component of the next row of pixel data to be written into the third FIFO module, whenever the Y component of one column of the pixel data of the current row is read; The read control module is also used to repeatedly read the U component of the reference column of the pixel data of the matching row from the second FIFO module after reading the Y component of all columns of the pixel data of the current row to poll the same batch of U components pre-cached from the starting address of the second FIFO module, and repeatedly read the V component of the reference column of the pixel data of the matching row from the third FIFO module to poll the same batch of V components pre-cached from the starting address of the third FIFO module; wherein the current row is the matching row.

2. The read-write control system according to claim 1, characterized in that: The read control module is used to read the U component of a reference column of the pixel data of the matching row from the second FIFO module and read the V component of a reference column of the pixel data of the matching row from the third FIFO module in each round of reading the Y components of the preset front and rear columns of the pixel data of the current row from the first FIFO module, so as to realize that in the pixel data of the same row of the same frame image, the read control module reads one U component from the second FIFO module and one V component from the third FIFO module every time it reads two Y components from the first FIFO module; then the current column Y component, the U component of the reference column and the V component of the reference column among the Y components of the preset front and rear columns of the pixel data of the current row are combined into one pixel data conforming to a specific YUV format, and the latter column Y component, the U component of the same reference column and the V component of the same reference column among the Y components of the preset front and rear columns of the pixel data of the current row are combined into another pixel data conforming to a specific YUV format.

3. The read-write control system according to claim 2, characterized in that: Among the pixel data of the current row, the Y components of the preset front and rear columns of the pixel data of the current row read from the first FIFO module in different rounds are the Y components of the pixel data of the same row with different column orders; In two adjacent rounds of reading, the Y component of the next column of the pixel data of the same row read from the first FIFO module in the current round and the Y component of the current column of the pixel data of the same row read from the first FIFO module in the next round are Y components of adjacent columns; The absolute value of the difference between the U component of the reference column of the same row of pixel data read from the second FIFO module in the current round and the U component of the reference column of the same row of pixel data read from the second FIFO module in the next round in the same frame image is 2; the absolute value of the difference between the V component of the reference column of the same row of pixel data read from the third FIFO module in the current round and the V component of the reference column of the same row of pixel data read from the third FIFO module in the next round in the same frame image is 2.

4. The read-write control system according to claim 1, characterized in that: Among the Y components of each column of the preset upper and lower rows of pixel data, the Y components of the preset upper and lower rows of pixel data read from the first FIFO module in different rounds are Y components with different row orderings among the pixel data of the same frame of image; in two adjacent rounds of reading, the Y component of the pixel data of the next row read from the first FIFO module in the current round and the Y component of the pixel data of the current row read from the first FIFO module in the next round are Y components with adjacent row orderings; The absolute value of the difference in row number between the U component of the reference column of the same row of pixel data read from the second FIFO module in the current round and the U component of the reference column of the same row of pixel data read from the second FIFO module in the next round within the same frame image is 2; the absolute value of the difference in row number between the V component of the reference column of the same row of pixel data read from the third FIFO module in the current round and the V component of the reference column of the same row of pixel data read from the third FIFO module in the next round within the same frame image is 2.

5. The read-write control system according to claim 4, characterized in that: A read control module, used for triggering the first FIFO module to cache the Y components of each column of a new row of pixel data to update the Y components of each column of a row of pixel data originally stored, triggering the second FIFO module to cache the U components of the reference columns of a new row of pixel data to update the U components of the reference columns of a row of pixel data originally stored, and triggering the third FIFO module to cache the V components of the reference columns of a new row of pixel data to update the V components of the reference columns of a row of pixel data originally stored, whenever the Y components of each column of the preset upper and lower rows of pixel data are read, the U components of the reference columns of the current row of pixel data are read from the second FIFO module, and the V components of the reference columns of the current row of pixel data are read from the third FIFO module.

6. The read-write control system according to claim 1 or 2, characterized in that: If the read control module starts from row 0 and sequentially reads the Y components of each column of each row of pixel data from the first FIFO module, the pixel data of the matching row is set to the pixel data of the even row of the same frame image, and the reference column of the pixel data of the matching row is set to the odd column or the even column of the pixel data of the even row of the same frame image; If the read control module starts from the first row and sequentially reads the Y components of each column of the pixel data of each row from the first FIFO module, the pixel data of the matching row is set as the pixel data of the odd row of the same frame image in the second FIFO module and the third FIFO module, and the reference column of the pixel data of the matching row is set as the odd column or the even column of the pixel data of the odd row of the same frame image in the second FIFO module and the third FIFO module; The depth of the first FIFO module is equal to the number of all Y components in a row of pixel data, the depth of the second FIFO module is equal to the number of U components of all reference columns in a row of pixel data, and the depth of the third FIFO module is equal to the number of V components of all reference columns in a row of pixel data; Among them, half of the depth size of the first FIFO module is equal to the depth size of the second FIFO module, and the depth size of the second FIFO module is equal to the depth size of the third FIFO module.

7. The read-write control system according to claim 6, characterized in that: If the reference column of the pixel data of the matching row is set to the odd column of the pixel data of the even row of the same frame image, the read control module synchronously reads out the Y component of the odd column of the pixel data of the same even row from the first FIFO module, reads out the U component of the odd column of the pixel data of the same even row from the second FIFO module, and reads out the V component of the odd column of the pixel data of the same even row from the third FIFO module, so that among the preset front and rear two columns of the pixel data of the same even row, the pixel data of the odd column is read first relative to the pixel data of the even column; If the reference column of the pixel data of the matching row is set to the even column of the pixel data of the even row of the same frame image, the read control module synchronously reads the Y component of the even column of the pixel data of the same even row from the first FIFO module, reads the U component of the even column of the pixel data of the same even row from the second FIFO module, and reads the V component of the even column of the pixel data of the same even row from the third FIFO module, so that among the preset front and rear two columns of the pixel data of the same even row, the pixel data of the even column is read first relative to the pixel data of the odd column; If the reference column of the pixel data of the matching row is set to the odd column of the pixel data of the odd row of the same frame image, the read control module synchronously reads the Y component of the odd column of the pixel data of the same odd row from the first FIFO module, reads the U component of the odd column of the pixel data of the same odd row from the second FIFO module, and reads the V component of the odd column of the pixel data of the same odd row from the third FIFO module, so that the pixel data of the odd column is read first relative to the pixel data of the even column among the preset front and rear columns of the pixel data of the same odd row; If the reference column of the pixel data of the matching row is set to the even column of the pixel data of the odd row of the same frame image, the read control module synchronously reads out the Y component of the even column of the pixel data of the same odd row from the first FIFO module, reads out the U component of the even column of the pixel data of the same odd row from the second FIFO module, and reads out the V component of the even column of the pixel data of the same odd row from the third FIFO module, so that among the preset front and rear two columns of the pixel data of the same odd row, the pixel data of the even column is read first relative to the pixel data of the odd column.

8. The read-write control system according to claim 1, characterized in that: A write control module, used for not controlling the U component of the reference column of the next row of pixel data to be written into the second FIFO module to retain the U component of the same column of the previously cached pixel data of the current row, and not controlling the V component of the reference column of the next row of pixel data to be written into the third FIFO module to retain the V component of the same column of the previously cached pixel data of the current row, in the process of successively writing the Y components of each column of the preset upper and lower rows of pixel data into the first FIFO module in each round; wherein the current row is the matching row.

9. The read-write control system according to claim 8, characterized in that: Among the Y components of each column of the preset upper and lower rows of pixel data, the Y components of the preset upper and lower rows of pixel data written into the first FIFO module in different rounds are Y components with different row orderings among the pixel data of the same frame image; in two adjacent rounds of writing, the Y component of the pixel data of the next row written into the first FIFO module in the current round and the Y component of the pixel data of the current row written into the first FIFO module in the next round are Y components with adjacent row orderings; the absolute value of the difference between the U component of the reference column of the pixel data of the same row written into the second FIFO module in the current round and the U component of the reference column of the pixel data of the same row written into the second FIFO module in the next round in the same frame of image is 2; the absolute value of the difference between the V component of the reference column of the pixel data of the same row written into the third FIFO module in the current round and the V component of the reference column of the pixel data of the same row written into the third FIFO module in the next round in the same frame of image is 2; Among them, the first FIFO module first caches the Y components of all columns of the pixel data of the current row in each round of writing, and then refreshes the Y components of all columns of the previously cached row of pixel data to cache the Y components of all columns of the pixel data of the next row; the second FIFO module caches at most the U components of all reference columns of one row of pixel data in each round of writing; the third FIFO module caches at most the V components of all reference columns of one row of pixel data in each round of writing.

10. The read-write control system according to claim 9, characterized in that: A write control module, used for writing the Y components of each column of a new row of pixel data to the first FIFO module to update the Y components of each column of a row of pixel data originally stored therein, writing the U component of the reference column of a new row of pixel data to the second FIFO module to update the U component of the reference column of a row of pixel data originally stored therein, and writing the V component of the reference column of a new row of pixel data to the third FIFO module to update the V component of the reference column of a row of pixel data originally stored therein, whenever the Y components of each column of the preset upper and lower rows of pixel data are written to the first FIFO module, the U component of the reference column of the current row of pixel data is written to the second FIFO module, and the V component of the reference column of the current row of pixel data is written to the third FIFO module.

11. The read-write control system according to claim 1, characterized in that: A write control module, used for, in each round of writing the Y components of the preset front and rear two columns of the pixel data of the current row to the first FIFO module, only writing the U component of the reference column of the pixel data of the current row to the second FIFO module once and triggering the read control module to perform a read operation, and only writing the V component of the reference column of the pixel data of the current row to the third FIFO module once and triggering the read control module to perform a read operation; wherein the current row is the matching row.

12. The read-write control system according to claim 11, characterized in that: Among the pixel data of the current row, the Y components of the preset front and rear two columns of the pixel data of the current row written to the first FIFO module in different rounds are Y components with different column sorting among the pixel data of the same row; in the process of writing into the first FIFO module in two adjacent rounds, the Y component of the rear column of the pixel data of the same row written into the first FIFO module in the current round and the Y component of the current column of the pixel data of the same row written into the first FIFO module in the next round are Y components with adjacent column sorting; The absolute value of the difference in column numbers between the U component of the reference column of the same row of pixel data written to the second FIFO module in the current round and the U component of the reference column of the same row of pixel data written to the second FIFO module in the next round in the same frame image is 2; the absolute value of the difference in column numbers between the V component of the reference column of the same row of pixel data written to the third FIFO module in the current round and the V component of the reference column of the same row of pixel data written to the third FIFO module in the next round in the same frame image is 2.

13. The read-write control system according to claim 1, characterized in that: A frame of image stored in advance is composed of a group of pixel data blocks or multiple groups of pixel data blocks; Each group of pixel data blocks is composed of pixel data corresponding to a pixel array; in a pixel array, each row and column of pixels has a Y component; pixels of the same color are composed of four adjacent pixels up, down, left, and right, and pixels of the same color share the same U component and the same V component; The storage form of a frame of image in the memory of the read-write control system peripheral is as follows: for every 4 Y components stored, one U component and one V component are mapped to correspond.

14. A method for controlling the reading and writing of image data, characterized in that: The read-write control method is used to read and write pixel data; the read-write control method comprises: From a frame of image pre-stored externally, the Y components of each column of each row of pixel data are sequentially written into the first FIFO module, the U components of the reference columns of the pixel data of the matching row are sequentially written into the second FIFO module, and the V components of the reference columns of the pixel data of the matching row are sequentially written into the third FIFO module; Whenever the Y components of the preset two preceding and following columns of the pixel data of the same row are read continuously from the first FIFO module, the U component of the reference column of the pixel data of the same row is read from the second FIFO module, and the V component of the reference column of the pixel data of the same row is read from the third FIFO module, so as to form the pixel data conforming to the specific YUV format; In the process of continuously writing the Y components of the preset upper and lower rows of pixel data into the first FIFO module, the U component of the reference column of the pixel data of the same matching row is repeatedly read from the second FIFO module twice, and the V component of the reference column of the pixel data of the same matching row is repeatedly read from the third FIFO module twice, so as to form pixel data conforming to a specific YUV format; In each round of reading the Y components of each column of the preset upper and lower rows of pixel data, whenever the Y component of one column of the pixel data of the current row is read, the Y component of the corresponding column of the pixel data of the next row is controlled to be written into the first FIFO module, the U component of the pixel data of the next row is not controlled to be written into the second FIFO module, and the V component of the pixel data of the next row is not controlled to be written into the third FIFO module; After reading the Y components of all columns of the pixel data of the current row, repeatedly read the U components of the reference columns of the pixel data of the matching row from the second FIFO module to poll the same batch of U components pre-cached from the starting address of the second FIFO module, and repeatedly read the V components of the reference columns of the pixel data of the matching row from the third FIFO module to poll the same batch of V components pre-cached from the starting address of the third FIFO module; wherein the current row is the matching row.

15. The read-write control method according to claim 14, characterized in that: The read-write control method comprises: in each round of reading the Y components of the preset front and rear two columns of the pixel data of the current row from the first FIFO module, reading the U component of a reference column of the pixel data of the matching row from the second FIFO module, and reading the V component of a reference column of the pixel data of the matching row from the third FIFO module, so that in the pixel data of the same row of the same frame image, for every two Y components read from the first FIFO module, one U component is read from the second FIFO module, and one V component is read from the third FIFO module; then the current column Y component, the U component of the reference column, and the V component of the reference column among the Y components of the preset front and rear two columns of the pixel data of the current row are combined into a pixel data conforming to a specific YUV format, and the latter column Y component, the U component of the same reference column, and the V component of the same reference column among the Y components of the preset front and rear two columns of the pixel data of the current row are combined into another pixel data conforming to a specific YUV format.

16. The read-write control method according to claim 15, characterized in that: Among the pixel data of the current row, the Y components of the preset front and rear columns of the pixel data of the current row read from the first FIFO module in different rounds are the Y components of the pixel data of the same row with different column orders; In two adjacent rounds of reading, the Y component of the next column of the pixel data of the same row read from the first FIFO module in the current round and the Y component of the current column of the pixel data of the same row read from the first FIFO module in the next round are Y components of adjacent columns; The absolute value of the difference between the U component of the reference column of the same row of pixel data read from the second FIFO module in the current round and the U component of the reference column of the same row of pixel data read from the second FIFO module in the next round in the same frame image is 2; the absolute value of the difference between the V component of the reference column of the same row of pixel data read from the third FIFO module in the current round and the V component of the reference column of the same row of pixel data read from the third FIFO module in the next round in the same frame image is 2.

17. The read-write control method according to claim 14, characterized in that: Among the Y components of each column of the preset upper and lower rows of pixel data, the Y components of the preset upper and lower rows of pixel data read from the first FIFO module in different rounds are Y components with different row orderings among the pixel data of the same frame of image; in two adjacent rounds of reading, the Y component of the pixel data of the next row read from the first FIFO module in the current round and the Y component of the pixel data of the current row read from the first FIFO module in the next round are Y components with adjacent row orderings; The absolute value of the difference in row number between the U component of the reference column of the same row of pixel data read from the second FIFO module in the current round and the U component of the reference column of the same row of pixel data read from the second FIFO module in the next round within the same frame image is 2; the absolute value of the difference in row number between the V component of the reference column of the same row of pixel data read from the third FIFO module in the current round and the V component of the reference column of the same row of pixel data read from the third FIFO module in the next round within the same frame image is 2.

18. The read-write control method according to claim 17, characterized in that: Whenever the Y components of each column of the preset upper and lower rows of pixel data are read, the U components of the reference columns of the current row of pixel data are read from the second FIFO module, and the V components of the reference columns of the current row of pixel data are read from the third FIFO module, the first FIFO module is triggered to cache the Y components of each column of a new row of pixel data to update the Y components of each column of a row of pixel data originally stored, the second FIFO module is triggered to cache the U components of the reference columns of a new row of pixel data to update the U components of the reference columns of a row of pixel data originally stored, and the third FIFO module is triggered to cache the V components of the reference columns of a new row of pixel data to update the V components of the reference columns of a row of pixel data originally stored.

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