Method for manufacturing semiconductor element

Abstract

In the manufacturing method of the semiconductor element of the present invention, the first semiconductor part (SL1) has a protrusion (TS) protruding toward the base substrate (UK), the protrusion includes a nitride semiconductor, the protrusion is bonded to the base substrate, the semiconductor substrate (HK) has a hollow part (TK) located between the base substrate and the first semiconductor part, the hollow part is connected to the side of the protrusion and communicates with the outside of the semiconductor substrate, and before the first semiconductor part is separated from the semiconductor substrate, the laser (LZ) is irradiated to the protrusion (TS).

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor element. Background Art

[0002] In the method for manufacturing a semiconductor element, various techniques for separating a semiconductor layer formed on a substrate from the substrate have been proposed (for example, refer to Patent Document 1 listed below).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent No. 4638958 Summary of the Invention

[0006] The manufacturing method of the semiconductor element of the present invention includes: a forming step, forming a plurality of semiconductor layers by epitaxial growth on the first surface of a base substrate in a manner such that semiconductor layers adjacent to each other in the direction along the first surface are at least partially separated from each other in the direction along the first surface; a embrittlement step, irradiating the connection portions between each of the plurality of semiconductor layers and the first surface with laser light to embrittle the connection portions; and a separation step, separating the plurality of semiconductor layers from the base substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 These are diagrams for explaining a method for manufacturing a semiconductor element according to one embodiment of the present invention.

[0008] Figure 2 These are diagrams for explaining a forming process in a method for manufacturing a semiconductor element according to an embodiment of the present invention.

[0009] Figure 3 It is a plan view showing the pattern shapes of multiple semiconductor layers formed on a base substrate.

[0010] Figure 4 These are diagrams for explaining a modified example of the separation step in the method for manufacturing a semiconductor element according to one embodiment of the present invention.

[0011] Figure 5 This is a flowchart showing each step of a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0012] Figure 6A It is a cross-sectional view showing a state where a semiconductor element is formed on a base substrate via a mask layer.

[0013] Figure 6B It is a cross-sectional view showing a state where the mask is removed.

[0014] Figure 6CThis is a cross-sectional view for explaining the process of weakening the connection portion.

[0015] Figure 7 It is a top view showing the pattern shape of the mask.

[0016] Figure 8A It is a cross-sectional view for explaining the separation process.

[0017] Figure 8B It is a cross-sectional view for explaining the separation process.

[0018] Figure 8C It is a cross-sectional view for explaining the separation process.

[0019] Figure 9A It is a cross-sectional view showing the etching shape of the connection portion.

[0020] Figure 9B It is a cross-sectional view showing the etching shape of the connection portion.

[0021] Figure 9C It is a cross-sectional view showing the etching shape of the connection portion.

[0022] Figure 10 This is a cross-sectional view showing a method for manufacturing a semiconductor element according to a third embodiment.

[0023] Figure 11 This is a cross-sectional view showing a method for manufacturing a semiconductor element according to a third embodiment.

[0024] Figure 12 It is a cross-sectional view showing a structural example of a base substrate.

[0025] Figure 13 It is a plan view showing a structural example of a semiconductor substrate. DETAILED DESCRIPTION

[0026] [Implementation Method 1]

[0027] Hereinafter, Embodiment 1 of the present invention will be described with reference to the accompanying drawings. The accompanying drawings are schematically shown for the sake of illustration. Figures 1 to 4 To explain.

[0028] exist Figure 1 In the process "a" represents the forming process, the process "b" represents the embrittlement process, and the process "c" represents the separation process. Figure 2 In the embodiment, step "a1" indicates a mask forming step, step "a2" indicates a semiconductor layer forming step, and step "a3" indicates a mask removing step. Figure 4 In the figure, step "c1" represents a preparation step, step "c2" represents a bonding step, and step "c3" represents a peeling step.

[0029] The semiconductor device manufacturing method of this embodiment includes a formation step a, an embrittlement step b, and a separation step c. Formation step a is a step of forming a plurality of semiconductor layers 3 connected to base substrate 1 via connection portions 2 on base substrate 1 using, for example, the epitaxial lateral overgrowth (ELO) method, which is a type of epitaxial vapor phase growth. Furthermore, embrittlement step b is a step of irradiating connection portions 2 with laser light 5 to embrittle them. Separation step c is a step of separating the plurality of semiconductor layers 3 from base substrate 1.

[0030] Each semiconductor layer 3 is formed with, for example, a cleavage plane and is provided with electrodes, wiring conductors, etc., to form one or more semiconductor elements S. Examples of the semiconductor elements S include, but are not limited to, light emitting diodes (LEDs), semiconductor lasers (LDs), and photodiodes (PDs).

[0031] The base substrate 1 includes a flat principal surface (hereinafter also referred to as the first surface) 1a, which is the starting point for semiconductor crystal growth; another flat principal surface (hereinafter also referred to as the second surface) 1b, which is opposite the first surface 1a; and a side surface (hereinafter also referred to as the third surface) 1c connecting the first surface 1a and the second surface 1b. At least the first surface 1a of the base substrate 1 is composed of a nitride semiconductor. The base substrate 1 is preferably a substrate composed of a nitride semiconductor such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), or indium gallium nitride (InGaN).

[0032] The base substrate 1 used in this embodiment is a GaN substrate cut from a GaN single crystal ingot. The base substrate 1 is cut from the single crystal ingot so that the first surface 1a containing the starting point of semiconductor crystal growth is in a predetermined plane direction. The base substrate 1 can be an n-type substrate in which GaN is doped with impurities such as Si, or a p-type substrate in which GaN is doped with impurities such as Mg. The impurity density in the base substrate 1 is, for example, 1×10 19 cm -3 Left and right and below.

[0033] (a) Formation process

[0034] Formation step a is a step of forming a plurality of semiconductor layers 3 on the first surface 1a of the base substrate 1 by the ELO method. In formation step a, the plurality of semiconductor layers 3 are formed so that the semiconductor layers 3 adjacent to each other in the direction along the first surface 1a are at least partially separated from each other in the direction along the first surface 1a.

[0035] The formation step a includes a mask forming step a1 , a semiconductor layer forming step a2 , and a mask removing step a3 described below.

[0036] (a1) Mask Formation Process

[0037] Mask forming step a1 is a step of forming a deposition-inhibiting mask (hereinafter, simply referred to as a mask) 6 on base substrate 1 to inhibit crystallization of semiconductor crystals. In mask forming step a1, silicon oxide (e.g., SiO2), which will serve as the material for mask 6, is first deposited on first surface 1a of base substrate 1 using a plasma chemical vapor deposition (PCVD) method, for example, to a thickness of approximately 100 nm. Next, the silicon oxide layer is patterned using, for example, photolithography and wet etching with buffered hydrofluoric acid (BHF). In this manner, mask 6 is formed on first surface 1a in a predetermined pattern.

[0038] The mask 6 may be, for example, striped, with multiple strips 61 arranged in parallel at predetermined intervals. The width of the opening 62, also known as the mask window, between two adjacent strips 61 is, for example, approximately 2 μm to 20 μm. The width of the strips 61 is, for example, approximately 50 μm to 200 μm.

[0039] The edge region near the third surface 1c of the first surface 1a of the base substrate 1 may also be covered by the mask 6. Thus, the semiconductor layer 3 grown in the edge region of the first surface 1a can be completely and reliably separated from the base substrate 1. Furthermore, abnormal growth of semiconductor crystals in the edge region of the first surface 1a can be suppressed.

[0040] (a2) Semiconductor Layer Formation Step

[0041] In the semiconductor layer forming step a2 , GaN crystals are vapor-phase grown from the regions of the first surface 1 a of the base substrate 1 that are not covered by the mask 6 and are exposed to the openings 62 .

[0042] Semiconductor crystal growth methods include vapor phase epitaxy (VPE) using chloride as a Group III raw material, or metal organic chemical vapor deposition (MOCVD) using an organic metal as a Group III raw material. For example, by varying the ratio of the Group III element raw material gas and the ratio of the impurity raw material gas during GaN crystal growth, semiconductor layer 3 can be formed into a multilayer film capable of functioning as a light emitting diode (LED) or a semiconductor laser (LD).

[0043] When the grown semiconductor crystal exceeds the opening 62 of the mask 6, the semiconductor crystal also grows laterally along the upper surface of the mask 6. The growth of the semiconductor crystal can be stopped before the semiconductor crystal grown from the first surface 1a overlaps with the adjacent semiconductor crystal. Figure 1 、 2 As shown, a plurality of semiconductor layers 3 are obtained, each of which is connected to the first surface 1a through a connecting portion 2. The connecting portion 2 is composed of, for example, GaN crystals, similarly to the semiconductor layer 3. For the connecting portion 2, for example, the width is about 2μm to 20μm, and the height is about 100nm to 500nm. For each semiconductor layer 3, for example, the width is about 50μm to 200μm, and the height is about 10μm to 50μm. The growth of the semiconductor crystal can also continue until the semiconductor crystal grown laterally along the upper surface of the mask 6 overlaps with the adjacent semiconductor crystal. In this case, a semiconductor layer connected to the first surface 1a through a plurality of connecting portions 2 is obtained.

[0044] (a3) Mask Removal Process

[0045] The mask removal step a3 is a step for removing the mask 6 after the semiconductor layer formation step a2 is completed. In the mask removal step a3, the base substrate 1 on which the semiconductor layer 3 is formed is removed from the vapor phase growth apparatus (epitaxial apparatus), and the mask 6 is removed using an etchant that does not substantially erode the semiconductor layer 3.

[0046] For example, when the mask 6 is composed of a silicon oxide film, wet etching using BHF is performed to remove the mask 6. Figure 1 As shown, a plurality of semiconductor layers 3 are obtained, each of which is connected to the first surface 1 a via the connection portion 2 .

[0047] The plurality of semiconductor layers 3 may extend in a predetermined direction when viewed from above. Figure 3The plurality of semiconductor layers 3 may also be formed as shown in FIG. Figure 3 A stripe pattern extending in a predetermined direction is formed as shown in (a) of FIG. 1 . The plurality of semiconductor layers 3 may also be formed as shown in FIG. Figure 3 The plurality of semiconductor layers 3 may be arranged in a zigzag pattern as shown in (b) to form a so-called repeating pattern. Figure 3 As shown in (c), each semiconductor layer 3 is formed into a lattice pattern in which both ends thereof are connected to the adjacent semiconductor layers 3 .

[0048] (b) Embrittling process

[0049] The embrittlement step b is a step of irradiating the connection portion 2 with laser light 5 to embrittle the connection portion 2. In the embrittlement step b, the irradiation with laser light 5 can, for example, cause thermal denaturation of the connection portion 2, thereby changing the crystal structure of the connection portion 2. This can, for example, cause cracks or breakage in the connection portion 2, thereby reducing the mechanical strength of the connection portion 2. In the embrittlement step b, the irradiation with laser light 5 can also completely or partially sever the connection portion 2.

[0050] The wavelength of the laser light 5 can be, for example, 370 nm or less. As a light source for outputting the laser light 5, for example, an AlGAN semiconductor laser, a KrF excimer laser, an ArF excimer laser, a YAG laser (third harmonic), etc. can be used. The focal length and spot size of the laser light 5 can be appropriately selected based on the dimensions of the base substrate 1, the connecting portion 2, and the semiconductor layer 3.

[0051] The laser beam 5 may be irradiated from the first surface 1a side of the base substrate 1 or from the second surface 1b side of the base substrate 1. The laser beam 5 may also be irradiated from the third surface 1c side of the base substrate 1.

[0052] (c) Separation process

[0053] Separation step c is a step for separating the plurality of semiconductor layers 3 from the base substrate 1. In separation step c, for example, a blade is brought into contact with the semiconductor layer 3 or ultrasonic waves are irradiated onto the connection portion 2, thereby applying force to the weakened connection portion 2. This breaks the connection portion 2, thereby separating the semiconductor layer 3 from the base substrate 1.

[0054] When the connection portion 2 is completely cut by irradiation with the laser beam 5 in the embrittlement step b, the separation step c can be omitted.

[0055] According to the manufacturing method of the semiconductor element of this embodiment, for the plurality of semiconductor layers 3 formed on the first surface 1a of the base substrate 1, the semiconductor layers 3 adjacent to each other in the direction along the first surface 1a are at least partially separated from each other in the direction along the first surface 1a. Therefore, the decomposition gas or evaporated gas generated by the irradiation of the laser 5 to the connecting portion 2 and filling the space between the semiconductor layer 3 and the base substrate 1 can be discharged to the outside. The discharge of the gas to the outside can be, for example, as follows: Figure 1 As shown by the arrow in the middle, the discharge is carried out through the gaps (hereinafter also referred to as discharge paths) G between adjacent semiconductor layers 3. This reduces damage to the semiconductor layer 3 and the base substrate 1 caused by the pressure of decomposition gases or evaporated gases. As a result, high-quality semiconductor elements S can be manufactured. Furthermore, the base substrate 1 can be reused without polishing to remove damaged areas, or with only a small amount of polishing. This improves the production efficiency of semiconductor elements S and provides semiconductor elements S that can increase the number of times the base substrate 1 can be reused.

[0056] Furthermore, in the semiconductor device manufacturing method of this embodiment, it is not necessary to irradiate the entire base substrate 1 with the laser light 5. Instead, it is sufficient to irradiate only the connection portion 2 connecting each semiconductor layer 3 to the first surface 1a. Consequently, it is possible to suppress excessive heating of the semiconductor layer 3 and the base substrate 1, thereby reducing thermal damage to the semiconductor layer 3 and the base substrate 1. As a result, high-quality semiconductor devices S can be manufactured. Furthermore, the base substrate 1 can be reused without requiring polishing to remove damaged areas, or with only minimal polishing. This improves the production efficiency of semiconductor devices S and reduces the manufacturing cost of semiconductor devices S.

[0057] Furthermore, in the semiconductor device manufacturing method of this embodiment, the base substrate 1, connecting portion 2, and semiconductor layer 3 are composed of GaN crystals, and therefore have substantially the same refractive index. This reduces refraction and reflection of laser light 5 at the interface between the base substrate 1 and connecting portion 2, and at the interface between the connecting portion 2 and semiconductor layer 3. As a result, laser light 5 can be irradiated onto the connecting portion 2 with high precision and efficiency. This allows for the manufacture of high-quality semiconductor devices S. Furthermore, the production efficiency of semiconductor devices S can be improved.

[0058] In the semiconductor layer formation step a2, when semiconductor crystal growth is continued until adjacent semiconductor crystals overlap, forming a semiconductor layer connected to the first surface 1a via multiple connectors 2, through-holes can be formed in the semiconductor layer along its thickness before the embrittlement step b. This allows decomposition gases or evaporated gases that fill the space between the semiconductor layer and the base substrate 1 to be discharged to the outside through the through-holes. As a result, even when forming a semiconductor layer connected to the first surface 1a via multiple connectors 2, high-quality semiconductor devices S can be manufactured, and the production efficiency of semiconductor devices S can be improved.

[0059] In the embrittlement step (b), laser light 5 may be irradiated from the second surface 1b of the base substrate 1, and the laser light 5 may be incident on the base substrate 1 from this second surface 1b. Since the base substrate 1 is composed of substantially the same material, rather than a different substrate such as a sapphire substrate or SiC substrate with a GaN layer formed on its surface, the refractive index of the base substrate 1 is substantially constant. Therefore, by irradiating the laser light 5 from the second surface 1b of the base substrate 1, the laser light 5 can be focused onto the connection portion 2 with high precision. Furthermore, by irradiating the laser light 5 from the second surface 1b where the semiconductor layer 3 is not formed, the possibility of the laser light 5 modifying the semiconductor layer 3 can be reduced. Furthermore, since the refractive index of the base substrate 1 is substantially constant, a simple lens system can be used as the optical system for focusing the laser light 5 onto the connection portion 2. This improves the production efficiency of the semiconductor devices S. It should be noted that this description does not preclude the use of different substrates such as sapphire substrates or SiC substrates as the base substrate 1 in the present invention.

[0060] In the embrittlement step (b), the connection portion 2 may be irradiated with a picosecond pulse laser or a femtosecond pulse laser. This can induce ablation due to multiphoton absorption at the connection portion 2, which serves as the focal point of the laser light 5. This can suppress the occurrence of thermal damage in the semiconductor layer 3 and the base substrate 1 while precisely embrittled the connection portion 2.

[0061] In the embrittlement step b, the connection portion 2 may be irradiated with sub-nanosecond pulse laser or nanosecond pulse laser. This improves the material removal rate compared to when the pulse width of the laser 5 is picosecond or femtosecond, thereby improving the processing efficiency in the embrittlement step b.

[0062] When the pulse width of the laser 5 is sub-nanosecond or nanosecond, a larger amount of decomposition gas or evaporated gas may be generated compared to when the pulse width of the laser 5 is picosecond or femtosecond. By optimizing the exhaust path G, the decomposition gas and evaporated gas can be effectively exhausted to the outside even when the pulse width of the laser 5 is sub-nanosecond or nanosecond. The exhaust path G can be optimized, for example, as follows: Figure 1 As shown in FIG. 1 , each semiconductor layer 3 is formed into a cross-sectional shape having a rounded corner portion on the bottom surface. For example, the discharge path G can be optimized as follows. Figure 3 As shown in (b), a plurality of semiconductor layers 3 are formed in a zigzag arrangement, and the intervals between adjacent semiconductor layers 3 are adjusted in two different directions.

[0063] The scanning path of the laser beam 5 in the embrittlement step (b) can be selected based on, for example, the pattern configuration of the plurality of semiconductor layers 3 formed on the base substrate 1 to improve the production efficiency of the semiconductor devices S. In the embrittlement step (b), for example, the laser beam 5 can be scanned from the outer periphery toward the center of the base substrate 1 while the base substrate 1 is rotated about an axis perpendicular to the first surface 1a. This eliminates the need for the laser beam 5 to make multiple reciprocating movements, thus shortening the time required for the embrittlement step (b). This, in turn, improves the production efficiency of the semiconductor devices S.

[0064] In the embrittlement step (b), the base substrate 1 can be heated to maintain the temperature of the base substrate 1 within a predetermined temperature range. This causes the Ga metal precipitated by the irradiation of the laser beam 5 to melt, making it less likely to adhere to the semiconductor layer 3. This maintains the quality of the semiconductor layer 3. The predetermined temperature range can be, for example, above room temperature (approximately 15°C to 35°C) and below 300°C.

[0065] In the embrittlement step b, the atmosphere, pressure, etc. within the laser processing device can be adjusted to suppress oxidation of the base substrate 1, which has reached a high temperature due to irradiation with the laser 5, and oxidation of the Ga metal precipitated due to irradiation with the laser 5. This can reduce damage to the base substrate 1 caused by oxidation. As a result, the base substrate 1 can be reused without polishing to remove damaged areas, or with only a small amount of polishing. This can improve the production efficiency of the semiconductor element S and reduce the manufacturing cost of the semiconductor element S. In addition, since the oxidized Ga metal can be suppressed from adhering to the semiconductor layer 3, the possibility of degradation of the quality of the semiconductor layer 3 can be reduced. As a result, high-quality semiconductor elements S can be manufactured.

[0066] In the embrittlement step (b), the focus of the laser beam 5 can also be aligned with the end portion 21 of the connection portion 2 on the base substrate 1 side. This can suppress undesirable thermal degradation of the semiconductor layer 3 caused by irradiation with the laser beam 5. As a result, polishing to remove thermally modified portions of the semiconductor layer 3 can be omitted, or the amount of polishing of the semiconductor layer 3 can be reduced. This, in turn, can improve the production efficiency of the semiconductor devices S.

[0067] In the embrittlement step (b), the laser beam 5 can also be focused on the end 22 of the connection portion 2 on the semiconductor layer 3 side. This can suppress undesirable thermal degradation of the base substrate 1 caused by irradiation with the laser beam 5. As a result, polishing to remove thermally modified portions of the base substrate 1 can be omitted, or the amount of polishing required for the base substrate 1 can be reduced. This, in turn, can improve the production efficiency of the semiconductor device S and reduce the manufacturing cost of the semiconductor device S.

[0068] In the embrittlement step b, the focus of the laser beam 5 can also be adjusted to the intermediate portion 23 between the end portion 21 of the connecting portion 2 on the base substrate 1 side and the end portion 22 on the semiconductor layer 3 side. This can suppress undesirable thermal degradation of the semiconductor layer 3 and the base substrate 1. As a result, high-quality semiconductor devices S can be manufactured, and the production efficiency of the semiconductor devices S can be improved and the manufacturing cost of the semiconductor devices S can be reduced.

[0069] When the connection portion 2 is not completely cut in the embrittlement step b, the separation step c may include a preparation step c1 , a joining step c2 , and a peeling step c3 .

[0070] The preparation step c1 is a step of preparing a support substrate 10 having an opposing surface 10a opposing the first surface 1a of the base substrate 1. The support substrate 10 has a bonding layer 10b made of solder using a material such as AuSn on the opposing surface 10a.

[0071] Bonding step c2 is the process of bonding the support substrate 10 to the upper surfaces of the plurality of semiconductor layers 3. In bonding step c2, the support substrate 10 is first placed on the plurality of semiconductor layers 3 formed on the base substrate 1 in forming step a. The support substrate 10 is positioned so that its facing surface 10a faces the first surface 1a of the base substrate 1. Next, the support substrate 10 is heated while being pressed toward the base substrate 1, bonding the support substrate 10 to the upper surfaces of the plurality of semiconductor layers 3.

[0072] The peeling step c3 is a step for peeling the plurality of semiconductor layers 3 from the base substrate 1. In the peeling step c3, the base substrate 1 and the support substrate 10 are relatively separated. This generates tensile stress in the connecting portion 2, which has been weakened by the irradiation of the laser beam 5, causing the connecting portion 2 to break, thereby allowing the plurality of semiconductor layers 3 to be peeled from the base substrate 1. By pre-fragmenting the connecting portion 2, the plurality of semiconductor layers 3 can be peeled from the base substrate 1 without damaging them. The peeling step c3 may also include the steps of forming cleavage planes in the semiconductor layer 3 and forming electrodes, wiring conductors, etc. in the semiconductor layer 3.

[0073] It should be noted that the preparation step c1 and the bonding step c2 can also be performed between the formation step a and the embrittlement step b. In this case, the decomposition gas or evaporated gas generated by the irradiation of the laser 5 flows along the first surface 1a toward the outer edge of the base substrate 1 in the space between the semiconductor layer 3 and the base substrate 1 and is discharged to the outside. A gas flow path (not shown) for promoting the discharge of the decomposition gas or evaporated gas to the outside can also be formed on the support substrate 10. The gas flow path can be, for example, a through hole that penetrates the support substrate 10 in the thickness direction. The gas flow path can also be, for example, a groove formed on the opposing surface 10a of the support substrate 10.

[0074] A method for manufacturing a semiconductor element of the present invention includes: forming a plurality of semiconductor layers on a first surface of a base substrate by epitaxial growth so that semiconductor layers adjacent to each other in a direction along the first surface are at least partially separated from each other in the direction along the first surface;

[0075] an embrittlement step of irradiating a connection portion between each of the plurality of semiconductor layers and the first surface with a laser to embrittle the connection portion; and

[0076] The separation step is to separate the plurality of semiconductor layers from the base substrate.

[0077] In order to manufacture high-quality semiconductor devices, there is still room for improvement in the method of separating semiconductor layers from substrates.

[0078] The method for manufacturing a semiconductor element of the present invention can reduce damage to the substrate and the semiconductor layer when separating the semiconductor layer from the substrate, thereby enabling the manufacture of high-quality semiconductor elements and improving semiconductor element production efficiency.

[0079] [Implementation Method 2]

[0080] Hereinafter, another embodiment of the present invention will be described with reference to the schematically shown drawings.

[0081] like Figure 5As shown in FIG. 1 , the method for manufacturing a semiconductor element of this embodiment includes an element forming step S1, a light irradiation step S2 (or also called a brittle step), and a separation step S3. Figure 6A 、 Figure 6B as well as Figure 6C As shown, element formation step S1 is a step of forming semiconductor element 33 bonded via connector 2 on base substrate 1 using the ELO method. Light irradiation step S2 is a step of bringing connector 2 into contact with etching solution 4 and irradiating at least a portion of connector 2 with light such as laser 5 to dissolve or embrittle connector 2. Separation step S3 is a step of separating semiconductor element 33, whose connector 2 has been embrittled by light irradiation step S2, from base substrate 1.

[0082] The element forming step S1 and the light irradiation step S2 may not be performed in this order. For example, the element forming step S1 and the light irradiation step S2 may be performed in parallel. This can shorten the process time. Examples of the semiconductor element 33 include, but are not limited to, a light emitting diode (LED), a semiconductor laser (LD), and a photodiode (PD).

[0083] The base substrate 1 has a first surface 1a which is a flat principal surface that serves as a starting point for crystal growth of the semiconductor, and a second surface 1b which is another flat principal surface on the back side thereof. At least the surface of the first surface 1a is a nitride semiconductor. The base substrate 1 used in the embodiment is, for example, a GaN substrate cut out from a single crystal ingot of gallium nitride (GaN) in such a manner that the first surface 1a which serves as a growth surface becomes a predetermined plane direction. The GaN substrate can be either an n-type substrate or a p-type substrate in which impurities such as Si are doped in the semiconductor. The impurity density of the GaN substrate that can be used is, for example, 1×10 19 cm -3 The substrate below the left and right.

[0084] In addition, as the base substrate 1, in addition to the GaN substrate, a substrate having a GaN layer formed on the surface of a substrate other than GaN, such as a sapphire substrate or a SiC substrate, can also be used. The surface of the base substrate 1 is not limited to the GaN layer, and any substrate composed of a GaN-based semiconductor can be used. The "nitride semiconductor" mentioned here is composed of Al x Ga y In z N(0≤x≤1, 0≤y≤1, 0≤z≤1, 1).

[0085] A mask 6 is formed on the aforementioned base substrate 1. For the mask 6, silicon oxide (e.g., SiO2) is stacked on the first surface 1a of the base substrate 1 by, for example, PCVD (Plasma Chemical Vapor Deposition). Next, the SiO2 layer is patterned by, for example, photolithography and wet etching with buffered hydrofluoric acid (BHF), thereby forming a Figure 6A Mask 6 is shown.

[0086] The mask 6 is striped, with multiple strips 6a arranged in parallel at predetermined intervals. The width of the opening 7 between two adjacent strips 6a, also known as the mask window, is, for example, approximately 2 to 20 μm. The width of the strips 6a is, for example, approximately 50 to 200 μm.

[0087] Figure 7 : is a top view showing the pattern shape of the mask. As a mask material for forming the mask 6, in addition to SiO2, any material that does not grow a semiconductor layer from the mask material due to vapor phase growth can be used. For example, ZrO2 that can be patterned can be used as the mask material. X 、TiO X or AlO X Oxides such as W or Cr, or transition metals such as W or Cr. In addition, the mask layer can be laminated using a method suitable for the mask material, such as evaporation, sputtering, or coating curing. As a specific example, a SiO2 layer with a thickness of about 100 to 500 nm is formed as the mask 6. For the formation of the SiO2 layer, first, silicon oxide (SiO2) with a thickness of about 100 to 500 nm, which becomes the material of the mask 6, is laminated on the first surface 1a by a PCVD (Plasma Chemical Vapor Deposition) method or the like.

[0088] As the mask pattern of the mask 6, except Figure 7 In addition to the stripe or stripe shape shown in the reference numeral 7a, the pattern may be a lattice shape formed by arranging a plurality of strips orthogonally in the vertical and horizontal directions as shown in the reference numeral 7b. In addition, the pattern may be a so-called repeating pattern (design) in which the openings 7 are repeated multiple times at a constant interval (repeating pitch) as shown in the reference numeral 7c.

[0089] Considering the ease of peeling and separating the semiconductor layer 3 described later, the edge region near the end face (side face) 1c of the base substrate 1 on the first surface 1a of the base substrate 1 may also be covered by the aforementioned mask 6. This also makes it possible to easily peel off the semiconductor layer located near the edge of the end portion of the base substrate 1.

[0090] Next, if Figure 6B As shown, a semiconductor element layer 8 as a semiconductor crystal growth layer is vapor-grown from the first surface 1a exposed from the opening 7. The semiconductor element layer 8 is a nitride semiconductor layer in this embodiment, but other materials may be used.

[0091] The crystal growth method can be vapor phase epitaxy (VPE), which uses chloride as a Group III raw material, or metal organic chemical vapor deposition (MOCVD), which uses an organic metal as a Group III raw material. The ratio of the Group III element raw material gas and the ratio of the impurity raw material gas can also be varied during the growth process to form semiconductor element layer 8 into a multilayer film that functions as a semiconductor element 33 such as an LED or LD.

[0092] When the grown crystal exceeds the opening 7 of the mask 6, the crystal also grows laterally along the upper surface of the mask 6. Crystal growth can be completed before the semiconductor crystal grown from the first surface 1a overlaps with the adjacent semiconductor crystal. In this way, a semiconductor element layer 8 is obtained by growing a nitride semiconductor using the ELO method. The width of the semiconductor element layer 8 is, for example, about 50 μm to 200 μm, and the height is about 10 μm to 50 μm.

[0093] For example, after forming the adhesive layer 9 as a metal layer, the base substrate 1, the mask 6 formed on the base substrate 1, the semiconductor element layer 8 and the adhesive layer 9 are immersed in BHF for about 10 minutes to remove the mask 6. Figure 6C As shown, a semiconductor element 33 is formed on a base substrate 1. The semiconductor element 33 and the base substrate 1 are connected to each other via a portion of a semiconductor element layer 8 grown in an opening 7 of a mask 6, namely, a columnar connection portion 2. The adhesive layer 9 can serve as an electrode for the semiconductor element 33.

[0094] However, depending on the structure of the semiconductor element 33, the adhesive layer 9 does not necessarily have to be used as an electrode. The semiconductor element layer 8 has an upper surface 8a and a lower surface 8b located on the opposite side. In addition, the mask 6 can be removed before the connection between the semiconductor element 33 and the support substrate 10 described later, or it can be removed after the connection between the semiconductor element 33 and the support substrate 10 described later, preferably by using BHF corrosion to dissolve at least a portion of the adhesive layer 9. The adhesive layer 9 can also bond the upper surface of the semiconductor element 33 to the support substrate 10. Alternatively, the adhesive layer 9 can also be used as a metal layer that also serves as an electrode of the semiconductor element 33 after its corrosion protection is performed.

[0095] Next, if Figure 6CAs shown, in the light irradiation step, the connection portion 2 is brought into contact with an etching solution 4, and light (in this example, laser light 5) having a wavelength that causes dissolution due to a photochemical reaction is irradiated onto the connection portion 2 or its periphery, thereby dissolving or embrittlement of the connection portion 2.

[0096] Here, light emitted from an LED or a halogen lamp may be used instead of the laser light 5. However, in order to obtain wavelength selectivity and a high reaction rate of the photochemical reaction, it is preferable to use the laser light 5 that can irradiate a small area with high intensity.

[0097] The laser beam 5 may also be irradiated onto a region including the semiconductor element 33 side of the connection portion 2 or a portion of the semiconductor element 33 side. In this case, when the semiconductor element 33 side of the connection portion 2 is separated from the base substrate 1, separation can be performed without leaving a protruding structure on the semiconductor element 33 side, thereby reducing process constraints when mounting the separated semiconductor element 33.

[0098] Alternatively, the laser beam 5 may be directed to an area on the base substrate 1 side or a portion of the base substrate 1 side including the connection portion 2. By limiting the irradiation area of ​​the laser beam 5 in this manner, the effects of thermal shock and the like on the semiconductor element 33 side can be reduced, and the focus position control of the laser beam 5 does not require high-precision alignment.

[0099] Furthermore, the laser beam 5 can also be irradiated onto the intermediate portion between the end portion of the connection portion 2 on the base substrate 1 side and the end portion on the semiconductor element 33 side. This minimizes the area to be etched away, thereby reducing the output of the laser beam 5 or shortening the etching time, thereby improving productivity.

[0100] Furthermore, the laser light 5 may be focused on the above-mentioned position and scanned in any direction within the substrate surface of the base substrate 1. In this case, the other light sources mentioned above may be used instead of the laser light 5.

[0101] The method of irradiating the laser beam 5 while the connecting portion 2 is in contact with an etching solution as an electrolyte is called photoelectrochemical etching (PEC). In this PEC etching, when the semiconductor (GaN) is irradiated with laser beam in an etching solution, an "oxidation reaction" represented by the following formula (1) and an "oxide film dissolution reaction" represented by the following formula (2) occur. "h" in the formula (1) is + ” indicates a hole.

[0102] <Oxidation Reaction>

[0103] 2GaN+6OH - +6h +→Ga2O3+3H2O+N2…(1)

[0104] <Dissolution Reaction>

[0105] Ga2O3+6OH - →2GaO3 3- +3H2O…(2)

[0106] When the connecting portion 2 is irradiated with the laser beam 5 in the etching solution 4 due to the above-mentioned oxidation reaction and oxide film dissolution reaction, an electric field is generated from the inside of the connecting portion 2 toward the surface, and the connecting portion 2 is dissolved by the acid or alkali from the surface or becomes brittle.

[0107] Such PEC etching is a photosensitive etching method that etches only layers containing photogenerated carriers. Therefore, low damage can be ensured by controlling the etching rate caused by the oxidation reaction occurring on the semiconductor surface using the amount of passed charge.

[0108] The photocarriers (holes) generated in the GaN layer enter the etching solution and are used in the etching reaction as described above. Therefore, as the GaN layer becomes thinner due to etching, the number of carriers decreases, and the reaction current path is completely cut off due to the depletion of the current supply path within the semiconductor, thereby causing the etching reaction to self-stop. This self-stopping process increases process margins and reduces yield reductions caused by process variations within the substrate and between batches.

[0109] like Figure 8A 、 Figure 8B as well as Figure 8C As shown, the semiconductor element 33 irradiated with the laser beam 5 at the connection portion 2 is connected to the support substrate 10 using a substrate bonding apparatus (not shown). When bonding the support substrate 10 and the semiconductor element 33, the base substrate 1 and the support substrate 10 are mounted on the substrate bonding apparatus so that the first surface 1a of the base substrate 1 and the opposing surface 10a of the support substrate 10 are parallel.

[0110] Next, the opposing surface 10a of the support substrate 10 is brought into contact with the upper surface of the semiconductor element 33 (the upper surface of the adhesive layer 9). The support substrate 10 is pressed so that the adhesive layer 9 and the support substrate 10 are in close contact. After the pressing, the support substrate 10 is heated to 300°C and AuSn bonding is performed, for example. Figure 8A As shown, the support substrate 10 is bonded to the semiconductor element 33. This bonding is not limited to AuSn bonding, and various bonding methods using other materials may be used.

[0111] like Figure 8BAs shown in FIG. 1 , the connection portion 2 is irradiated with laser light as described above to weaken the connection portion 2. After the substrate bonding apparatus is cooled, the base substrate 1 is removed from the substrate bonding apparatus and the support substrate 10 is moved away from the base substrate 1. As a result, a large tensile stress is generated in the connection portion 2 weakened by the irradiation of the laser beam 5. Figure 8C As shown, the connection portion 2 is broken. At this point, the connection portion 2 is in a fragile state, making it easy to separate the base substrate 1. Separation can be performed using appropriate methods. Depending on the location of the fragile connection portion 2, it is possible that the connection portion 2 may remain on the base substrate 1 side, the semiconductor element 33 side, or both. Therefore, after separation, any remaining fragments of the connection portion 2 on the semiconductor element 33 are removed by polishing or other means.

[0112] This dissolves or weakens the connection 2 between the semiconductor element 33 and the base substrate 1, thereby reducing the risk of cracks and crystal defects during the separation process, enabling a larger diameter of the base substrate 1 and improving the yield of the separation process. Furthermore, during the separation process, a roughened surface region with multiple crystal planes can be formed on at least one of the semiconductor element 33 and the base substrate 1. This can reduce the risk of cracks initiating or propagating during separation of the semiconductor element 33 from the base substrate 1.

[0113] Figures 9A to 9C : is a diagram showing the etching shape of the connection portion. When the laser 5 is irradiated on the connection portion 2 from the side, an electric field in the direction of arrow E is generated from the base substrate 1 toward the semiconductor element 33. The first surface 1a of the base substrate 1 has polarity as a Ga pole surface, and the opposite surface 3a of the semiconductor element 33 facing the base substrate 1 has polarity as an N pole surface. As a result, compared with the oxidation of the opposite surface 3a as an N pole surface, the oxidation of the first surface 1a as a Ga pole surface is promoted, and etching proceeds rapidly. Therefore, as shown in FIG. Figure 9A As shown, the width b1 of the connection portion 2 on the base substrate 1 side is smaller, and the width b2 on the semiconductor element 33 side is larger, and the cross section is etched into an inverted trapezoidal shape.

[0114] The inventors of this case confirmed that at an electron density of 3×10 17 cm -3 In the case of, for example, when a GaN test piece is immersed in a KOH etching solution of pH 13 and irradiated with laser light of a HeCd laser having a wavelength λ=325 nm, an etching rate of 525 nm / min is obtained.

[0115] In this embodiment, semiconductor element layer 8 is formed using a material with an energy band structure that creates an energy barrier, such as n-GaN / i-GaN / n-GaN. Laser light is then irradiated on a selective area to generate optical excitation, current flow, polarization due to electric field strain, and the like. This allows selective etching of connection portion 2 or a portion thereof using an etchant such as KOH or TMAH, which promotes a chemical etching reaction in areas where charge is localized.

[0116] In addition, in this embodiment, the connection portion 2 is made into a structure having pores by using the VAS (Void-Assisted Separation) method, the formation of a coarse initial nucleus, the porosity by anodic oxidation, the In droplet method, etc. As a result, the surface area is increased, and the rigidity is reduced compared to the ELO structure without pores. In addition, by increasing the etching rate at the same time, selective embrittlement can be performed. For example, Figure 9B As shown, the width b2 of the connection portion 2 on the semiconductor element 33 side is small, and the width b1 on the base substrate 1 side is large, so that the cross section can be etched into a trapezoidal shape.

[0117] By controlling the porosity (void density) of the connector 2 on both the semiconductor element 33 side and the base substrate 1 side, the etching rate can be controlled, thereby also controlling the width b1 and width b2. This allows the etching rate of the connector 2 to be varied so that width b1 is greater than width b2. Furthermore, the cavitation of the interface between the connector 2 and the base substrate 1 (the initial growth layer of the ELO structure) can be easily achieved by adjusting epitaxial growth conditions, using the VAS method, and the like.

[0118] In addition, if Figure 9C As shown, the width b3 of the middle portion, more specifically the center portion, between the end portion on the base substrate 1 side of the connection portion 2 and the end portion on the semiconductor element 33 side can be made smaller than the widths b1 and b2 at the two ends of the connection portion 2, thereby achieving higher operability in the fragile area. In order to change the etching rate of the connection portion 2 so that the widths b1 and b2 are greater than the width b3, this can be achieved, for example, by controlling the electron concentration difference between the connection portion 2, the semiconductor element 33 side sandwiching the connection portion 2, and the base substrate 1 side. Alternatively, layers with different band gaps based on heteroepitaxial growth can be inserted. Similarly, by inserting a stress layer that generates strain at the interface between the semiconductor element 33 side and the base substrate 1 side of the connection portion 2, the etching rate can also be controlled. Alternatively, the etching rate can be controlled by giving the connection portion 2 a multilayer structure as described above.

[0119] As previously described, the semiconductor device manufacturing method of this embodiment utilizes a support substrate in addition to weakening the connection portion. This reduces the risk of cracks and crystal defects caused by the separation process, enables a larger base substrate diameter, and improves the yield of the separation process.

[0120] The manufacturing method of the semiconductor element of the present invention includes: an element forming step, forming a semiconductor element located on the base substrate via a connecting portion; a light irradiation step, irradiating the connecting portion with light while the connecting portion is in contact with an etching solution, thereby dissolving or brittle it; and a separation step, separating the semiconductor element from the base substrate.

[0121] In the prior art described in Patent Document 1, it is considered that cracks and crystal defects occurring in both the semiconductor element and the substrate can lead to a decrease in the characteristics of the semiconductor element and the manufacturing yield. Therefore, a method for manufacturing a semiconductor element is desired that can reduce the occurrence of cracks and crystal defects in both the semiconductor element and the substrate, thereby minimizing the decrease in the characteristics of the semiconductor element and the manufacturing yield.

[0122] The semiconductor device manufacturing method of the present invention can reduce the occurrence of cracks and crystal defects caused by the separation process, and can achieve a larger diameter of the base substrate, thereby improving the yield of the separation process and thus increasing productivity.

[0123] [Implementation Method 3]

[0124] Figure 10 as well as Figure 11 : is a cross-sectional view showing a method for manufacturing a semiconductor element according to Embodiment 3. Figure 10 as well as Figure 11 As shown, the method for manufacturing a semiconductor device according to the third embodiment includes the steps of forming a semiconductor substrate HK having a base substrate UK and a layered first semiconductor portion SL1 bonded to the base substrate UK, and separating the first semiconductor portion SL1 from the base substrate UK. The first semiconductor portion SL1 includes a nitride semiconductor. The first semiconductor portion SL1 may also be a first semiconductor layer.

[0125] The first semiconductor portion SL1 has a protrusion TS that protrudes toward the base substrate UK. This protrusion TS comprises a nitride semiconductor. The protrusion TS is located in the center of the first semiconductor portion SL1 when viewed from above and has an elongated shape. The protrusion TS is bonded to the base substrate UK, forming a hollow portion TK between the base substrate UK and the first semiconductor portion SL1 in the semiconductor substrate HK. The hollow portion TK is in contact with the side surface SF of the protrusion TS and communicates with the exterior of the semiconductor substrate HK, serving as a flow path for gases and liquids.

[0126] Specific examples of nitride semiconductors include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). The Z direction is the normal direction to the c-plane, or (0001), of the nitride semiconductor in the convex portion TS. The X direction is the normal direction to the a-plane, or (11-20) plane, of the nitride semiconductor in the convex portion TS. The Y direction is the normal direction to the m-plane, or (1-100) plane, of the nitride semiconductor in the convex portion TS.

[0127] exist Figure 10 In the embodiment, before separating the first semiconductor portion SL1 from the base substrate UK, the convex portion TS is irradiated with laser light (laser ablation). Figure 11 In the embodiment, before the first semiconductor portion SL1 is separated, the etching solution EH is injected into the hollow portion TK and the laser light is irradiated onto the projection TS (photoexcitation).

[0128] In embodiment 3, as Figure 10 、 Figure 11 As shown, the first semiconductor portion SL1 is formed on a mask ML located on a base substrate UK and including mask portions M1 and M2 and openings K1 and K2 using an ELO (Epitaxial Lateral Overgrowth) method. Mask portions M1 and M2 are then removed by etching, thereby forming a hollow portion TK. Mask ML can also be a mask layer. A protrusion TS is formed in the opening K1. The protrusion TS can also have a shape with its longitudinal direction being the <1-100> direction (Y direction) of the nitride semiconductor it contains.

[0129] The first semiconductor portion SL1 includes a low-dislocation portion WG that does not overlap with the convex portion TS when viewed from above and has a threading dislocation density of less than 1 / 5 of that of the convex portion TS. The semiconductor substrate HK includes a second semiconductor portion SL2, and the first and second semiconductor portions SL1 and SL2 are arranged along the <11-20> direction (X direction) of the nitride semiconductor. The second semiconductor portion SL2 may also be a second semiconductor layer. The semiconductor substrate HK has a device portion DL formed on the first semiconductor portion SL1. Although not shown, the device portion DL includes, for example, a p-type semiconductor portion, an n-type semiconductor portion, an active portion including a light-emitting region, and an electrode portion. The p-type semiconductor portion, the n-type semiconductor portion, the active portion, and the electrode portion are each formed in a layered form, and the device portion DL is formed by stacking. That is, the device portion DL may also be a device layer. The light-emitting region may also be formed in a manner that overlaps with the low-dislocation portion WG when viewed from above.

[0130] like Figure 10 as well as Figure 11As shown, the semiconductor substrate HK may include a support substrate SK facing the base substrate UK, with the first semiconductor portion SL1 located between the base substrate UK and the support substrate SK. Alternatively, the electrode portion of the device portion DL may be bonded to the support substrate SK.

[0131] Figure 12 : is a cross-sectional view showing a structural example of a base substrate. Figure 12 As shown, the nitride semiconductor contained in the convex portion TS is a GaN-based semiconductor, and the base substrate UK may also have a heterogeneous substrate MK having a lattice constant different from that of the GaN-based semiconductor of the convex portion TS, and a seed portion SD formed on the heterogeneous substrate MK and containing a nitride semiconductor. In this case, the base substrate UK may be composed of a main substrate MK as a silicon substrate and a seed portion SD (for example, an AlN portion), or may be composed of a main substrate MK as a silicon carbide substrate and a seed portion SD (for example, a GaN-based semiconductor portion). In addition, the base substrate UK may be composed of a main substrate MK as a silicon substrate, a buffer portion BF on the main substrate (for example, including at least one of an AlN portion and a SiC portion), and a seed portion SD on the buffer portion (for example, a GaN-based semiconductor portion). It should be noted that the present invention is not limited to these structures, and the base substrate UK may also be a bulk GaN substrate or a bulk SiC substrate (hexagonal system). The seed portion SD may also be a seed layer, and the buffer portion BF may also be a buffer layer.

[0132] Figure 13 FIG is a top view showing a structural example of a semiconductor substrate. Figure 13 As shown, in the semiconductor substrate HK, the first semiconductor portion SL1 and the device portion DL may be divided into a plurality of semiconductor element portions HB. The semiconductor element portion HB functions as, for example, an LED (light emitting diode) or a semiconductor laser.

[0133] exist Figure 10 After the semiconductor substrate HK is formed, laser light LZ is irradiated to cause laser ablation of the nitride semiconductor projection TS, thereby weakening or cross-cutting (cutting parallel to the c-plane) the projection TS. The width of the projection TS (dimension in the X direction) is smaller than the width of the first semiconductor portion SL1, making it easier to perform the process of separating the first semiconductor portion SL1 from the base substrate UK (fragmentation or cutting). Gases (decomposition products) generated by laser ablation are discharged to the outside of the semiconductor substrate HK through the hollow portion TK. For example, a nanosecond pulse laser can be used as the laser.

[0134] exist Figure 11In the process, after the semiconductor substrate HK is formed, anisotropic etching is performed from the side of the protrusion TS toward the inside by irradiating the protrusion TS with laser light LZ while contacting the side of the protrusion TS with the etching solution EH. Specifically, the nitride semiconductor (e.g., GaN-based semiconductor) of the protrusion TS is converted into an oxide (e.g., Ga2O3) using holes generated by light excitation and anions (e.g., hydroxide ions) of the etching solution EH. This oxide is ionized and dissolved in the etching solution EH, thereby embrittlement or cross-cutting (cutting parallel to the c-plane) of the protrusion TS. The width of the protrusion TS is smaller than the width of the first semiconductor portion SL1, making it easier to perform the process of separating the first semiconductor portion SL1 from the base substrate UK (embrittlement or cutting).

[0135] Electron-hole pairs are generated in the convex portion TS due to the irradiation of the laser LZ, but the holes are used to oxidize the nitride semiconductor, and the electrons are consumed by the reaction in the etching solution EH (electrodes may be provided in the etching solution EH, but this is not limited to this). Figure 11 By performing anisotropic wet etching as shown, the projections TS can be etched while suppressing the progress of etching in the Z direction (damage to the low dislocation portions WG).

[0136] exist Figure 11 In the embodiment, the protrusion TS may include a target portion TL where etching preferentially proceeds. The target portion TL may also be a target layer. The nitride semiconductor (e.g., a GaN-based semiconductor) included in the target portion TL can have a smaller band gap than the nitride semiconductors included in the adjacent portions above and below. In this case, the laser light LZ can employ UV light having an energy greater than the band gap of the nitride semiconductor included in the target portion TL. For example, a HeCd laser with a wavelength of 325 nm can be used as such a UV laser.

[0137] The target portion TL may also contain indium and gallium (for example, an InGaN layer). The target portion TL may also have a higher porosity and lower rigidity than the adjacent portions above and below. The target portion TL does not need to be located in the middle of the protrusion TS and may be located to include the base of the protrusion TS or the tip (the portion bonded to the base substrate UK).

[0138] In the third embodiment, the step of separating the first semiconductor portion SL1 from the base substrate UK can be performed after the embrittlement of the protrusion TS, or can be performed by transversely cutting the protrusion TS. The laser light LZ can be irradiated from the base substrate UK or from the support substrate SK. However, the latter is preferred when the base substrate UK is light-shielding (e.g., a silicon substrate).

[0139] In the third embodiment, a process of forming a semiconductor substrate HK having a base substrate UK and a first semiconductor portion (semiconductor layer) SL1 bonded to the base substrate UK, and a process of separating the first semiconductor portion (semiconductor layer) SL1 from the base substrate UK can be performed. Here, the following structure can be adopted: the first semiconductor portion (semiconductor layer) SL1 has a protrusion TS protruding toward the base substrate UK, the protrusion TS comprising a nitride semiconductor, the protrusion TS bonded to the base substrate UK, and a hollow portion TK formed in the semiconductor substrate HK between the base substrate UK and the first semiconductor portion (semiconductor layer) SL1. The hollow portion TK is in contact with the side surface of the protrusion TS and communicates with the exterior of the semiconductor substrate HK. Furthermore, before separating the first semiconductor portion (semiconductor layer) SL1, at least one of irradiating the protrusion TS with a laser or injecting an etching solution into the hollow portion TK can be performed.

[0140] [Additional Notes]

[0141] As mentioned above, the method for manufacturing a semiconductor element of the present invention has been described in detail. However, the present invention is not limited to the above-described embodiment, and various changes and improvements can be made without departing from the gist of the present invention.

[0142] For example, in Embodiment 1, a GaN substrate is described as an example of a base substrate. However, as described in Embodiments 2 and 3, a base substrate made of a material different from the semiconductor material included in the semiconductor layer 3 may be used. In this case, for example, the base substrate may be formed of sapphire (Al2O3), silicon carbide (SiC), silicon (Si), or the like. In this case, a buffer portion or a seed crystal portion may also be provided on the base substrate.

[0143] Furthermore, for example, in the above example, the laser irradiation is performed after the mask is removed. However, the mask may be removed after the laser irradiation and before the semiconductor layer 3 is peeled off.

[0144] Description of Reference Numerals

[0145] 1: Base substrate; 1a: One principal surface (first surface); 1b: Other principal surface (second surface); 1c: Side surface (third surface), end surface; 2: Connecting portion; 21, 22: End portion; 23: Middle portion; 3: Semiconductor layer; 4: Etching solution; 5: Laser; 6: Deposition suppression mask (mask); 6a: Strip portion; 7: Opening; 8: Semiconductor element layer; 8a: Upper surface; 8b: Lower surface; 9: Adhesive layer; 10: Support substrate; 10a: Countersunk Placement surface; 10b: bonding layer; 33: semiconductor element; 61: strip portion; 62: opening portion; G: gap (discharge path); S: semiconductor element; a: formation process; a1: mask formation process; a2: semiconductor layer formation process; a3: mask removal process; b: embrittlement process; c: separation process; c1: preparation process; c2: bonding process; c3: peeling process; S1: element formation process; S2: light irradiation process; S3: separation process.

Claims

1. A method for manufacturing a semiconductor element, comprising: A step of preparing a semiconductor substrate, the semiconductor substrate comprising a base substrate, a mask, and a first semiconductor portion, the mask being located on the base substrate and comprising a plurality of mask portions and an opening, the first semiconductor portion comprising a downwardly facing protrusion located in the opening and connected to the base substrate, and a low dislocation portion located on each mask portion and having a wider width than the protrusion and a low dislocation density; a step of irradiating the convex portion with a laser beam to weaken the convex portion, the convex portion being located between the plurality of mask portions, comprising a nitride semiconductor, and having a width smaller than that of the low dislocation portion; as well as a step of breaking the fragile protrusion to separate the first semiconductor portion from the base substrate.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: A hollow portion is formed between the base substrate and the low dislocation portion by removing the plurality of mask portions.

3. The method for manufacturing a semiconductor device according to claim 1, wherein The first semiconductor portion is formed on the mask by an ELO method.

4. The method for manufacturing a semiconductor device according to claim 1, wherein The protrusion is cut along the <11-20> direction of the nitride semiconductor.

5. The method for manufacturing a semiconductor element according to any one of claims 1 to 4, wherein: The convex portion has a shape with the <1-100> direction of the nitride semiconductor as its longitudinal direction.

6. The method for manufacturing a semiconductor element according to any one of claims 1 to 4, wherein: The low dislocation portion does not overlap with the convex portion in a plan view, and has a threading dislocation density that is 1 / 5 or less of that of the convex portion.

7. The method for manufacturing a semiconductor element according to any one of claims 1 to 4, wherein: The semiconductor substrate has a second semiconductor portion including a nitride semiconductor. The first semiconductor portion and the second semiconductor portion each include a downwardly facing convex portion located in the opening and connected to the base substrate, and a low dislocation portion located on each mask portion and having a wider width than the convex portion and a low dislocation density. The first semiconductor portion includes a nitride semiconductor, The convex portion has a <1-100> direction of the nitride semiconductor as its long side direction, The first semiconductor portion and the second semiconductor portion are arranged separately along the <11-20> direction of the nitride semiconductor. When observing a cross section perpendicular to the <1-100> direction, each of the first semiconductor portion and the second semiconductor portion has a cross-sectional shape in which corners of a lower surface along the <11-20> direction of the nitride semiconductor are rounded.

8. The method for manufacturing a semiconductor element according to any one of claims 1 to 4, wherein: The semiconductor substrate has a device portion formed on the first semiconductor portion.

9. The method for manufacturing a semiconductor element according to claim 8, wherein: In the semiconductor substrate, the first semiconductor portion and the device portion are divided into a plurality of semiconductor element portions.

10. The method for manufacturing a semiconductor element according to any one of claims 1 to 4, wherein: The semiconductor substrate includes a support substrate facing the base substrate, and the first semiconductor portion is located between the base substrate and the support substrate.

11. The method for manufacturing a semiconductor element according to any one of claims 1 to 4, wherein: The nitride semiconductor is a GaN-based semiconductor, The base wafer includes a heterogeneous substrate having a lattice constant different from that of the GaN-based semiconductor, and a seed crystal portion formed on the heterogeneous substrate and containing a nitride semiconductor.

12. The method for manufacturing a semiconductor device according to claim 2, wherein: The convex portion is laser ablated by the irradiation of the laser. Gas generated by laser ablation is exhausted to the outside of the semiconductor substrate through the hollow portion.

13. The method for manufacturing a semiconductor element according to any one of claims 1 to 4, wherein: Anisotropic etching progressing from the side surface of the convex portion toward the inside is performed by irradiating the convex portion with laser light while an etching liquid is brought into contact with the side surface of the convex portion.

14. The method for manufacturing a semiconductor element according to claim 13, wherein: The nitride semiconductor of the protrusion is converted into an oxide using holes generated by photoexcitation and anions in the etching solution, and the oxide is dissolved in the etching solution.

15. The method for manufacturing a semiconductor device according to claim 13, wherein: The protrusions include target portions where etching preferentially progresses.

16. The method for manufacturing a semiconductor element according to claim 15, wherein: The nitride semiconductor included in the target portion has a smaller band gap than the nitride semiconductors included in the upper and lower adjacent portions.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: The laser light is UV light having energy greater than a band gap of the nitride semiconductor included in the target portion.

18. The method for manufacturing a semiconductor device according to claim 16, wherein: The target portion contains indium and gallium.

19. The method for manufacturing a semiconductor device according to claim 15, wherein: The target portion has a higher porosity than the adjacent portions above and below.

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