Epitaxial wafer, LED chip and display screen

Abstract

An epitaxial wafer, an LED chip and a display screen, the epitaxial wafer comprising: an improvement layer (210), a first buffer layer (220), a first conductive layer (230), a light emitting layer (240) and a second conductive layer (250), the improvement layer (210) comprising a solid portion (211) and at least one void portion (212), the void portion (212) being towards the first buffer layer (220), the light emitting layer (240) being located entirely within a region above the solid portion (211) of the improvement layer (210). The epitaxial wafer comprises first lattice defects (270) and second lattice defects (280) generated between the void portion (212) of the improvement layer (210) and a region where the improvement layer (210) is in contact with a substrate (260). The first lattice defects (270) extend along a growth direction of the epitaxial wafer, and the second lattice defects (280) are located in the first buffer layer (220), or in the first buffer layer (220) and the first conductive layer (230). The first lattice defects (270) and the second lattice defects (280) do not reach the light emitting layer (240), and do not affect the light emitting recombination of electrons and holes in the light emitting layer (240). Therefore, the epitaxial wafer has fewer lattice defects in the light emitting layer (240), and accordingly, the epitaxial wafer has a higher light emitting efficiency.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to an epitaxial wafer, an LED chip, and a display screen. Background Technology

[0002] Light-emitting diode (LED) displays offer advantages such as long lifespan and high color stability, leading to their increasingly widespread application. LED displays typically include multiple LED chips, which are obtained through the fabrication of epitaxial wafers.

[0003] In the fabrication of epitaxial wafers, a substrate is typically prepared first, and then an epitaxial wafer is grown on the substrate. The substrate is usually made of sapphire, while the epitaxial wafer is typically made of gallium nitride (GaN). Referring to Figure 1(a), the top two layers are GaN lattices, and the bottom two layers are sapphire lattices. As shown in Figure 1(a), GaN has a smaller lattice constant, while sapphire has a larger lattice constant, resulting in a significant lattice constant mismatch between GaN and sapphire. In this case, referring to the schematic diagram in Figure 1(b), the top three layers are GaN lattices, and the bottom two layers are sapphire lattices. Due to the lattice constant mismatch between GaN and sapphire, lattice defects will appear in the epitaxial wafer, affecting the luminous efficiency of the LED chip and further impacting the display effect of the LED chip screen.

[0004] To reduce lattice defects, two methods are commonly used. The first method involves placing a buffer layer between the substrate and the epitaxial wafer. The lattice constant of the buffer layer lies between the lattice constants of the substrate and the epitaxial wafer, thus mitigating the lattice constant mismatch between them. The second method involves patterning the sapphire substrate (PSS).

[0005] However, during the research process of this application, the inventors discovered that although the above two methods help reduce lattice defects in epitaxial wafers, epitaxial wafers using these two methods still have a relatively large number of lattice defects, resulting in reduced luminous efficiency. For example, when using the first method, the defect density of the epitaxial wafer's lattice defects is above 1E8~1E9 / cm2, and when using the second method, the defect density of the epitaxial wafer's lattice defects is still above 1E18 / cm2. Summary of the Invention

[0006] To address the problem that epitaxial wafers have numerous lattice defects in existing technologies, leading to reduced luminous efficiency of LED chips, this application discloses an epitaxial wafer, a light-emitting diode, a display screen, and a method for fabricating the same, in order to reduce lattice defects in the epitaxial wafer and improve the luminous efficiency of the LED chip.

[0007] In a first aspect, embodiments of this application disclose an epitaxial wafer, comprising:

[0008] Improvement layer, first buffer layer, first conductive layer, light-emitting layer and second conductive layer;

[0009] The improvement layer is disposed above the substrate, and the improvement layer includes a solid portion and at least one void portion;

[0010] The first buffer layer, the first conductive layer, the light-emitting layer, and the second conductive layer are sequentially disposed above the improvement layer, and the at least one void portion faces the first buffer layer;

[0011] The entire light-emitting layer is located within the area directly above the solid portion of the improvement layer;

[0012] The lattice defects between the void portion of the improved layer and the region in contact with the substrate include a first lattice defect and a second lattice defect. The first lattice defect is a lattice defect extending along the epitaxial growth direction, and the second lattice defect is a lattice defect extending to both sides of the void portion.

[0013] The second lattice defect is located in the first buffer layer, or the second lattice defect is located in both the first buffer layer and the first conductive layer.

[0014] In the epitaxial wafer disclosed in this application, the first lattice defect and the second lattice defect do not reach the light-emitting layer, and therefore do not affect the luminescent recombination of electrons and holes in the light-emitting layer. Therefore, the epitaxial wafer disclosed in this application has fewer lattice defects in its light-emitting layer, and correspondingly, the epitaxial wafer has higher luminous efficiency.

[0015] In one alternative design, a void layer is included between the solid portion of the improvement layer and the substrate;

[0016] Alternatively, a gap layer may be included between the improvement layer and the first buffer layer.

[0017] In the epitaxial wafers disclosed in this application, when the solid portion of the improvement layer is not in close contact with the substrate, or when the improvement layer is not in close contact with the first buffer layer, lattice defects will not be generated in the solid portion of the improvement layer. Compared with epitaxial wafers in the prior art, the epitaxial wafers disclosed in this application have fewer lattice defects, thereby further improving luminous efficiency.

[0018] An alternative design also includes:

[0019] First electrode layer and second electrode layer;

[0020] The first electrode layer is disposed above the first conductive layer;

[0021] The second electrode layer is disposed above the second conductive layer.

[0022] In one alternative design, the first electrode layer is located in the region directly above both the void portion and the solid portion of the improvement layer.

[0023] Alternatively, the entire first electrode layer may be located in the region directly above the void portion of the improved layer.

[0024] Since the first electrode layer is located in the region directly above the void portion and solid portion of the improvement layer, or in the region directly above the void portion of the improvement layer, the cross-sectional area of ​​the light-emitting layer can occupy a larger area. Consequently, the area available for realizing the light-emitting recombination of electrons and holes increases, thereby improving the area utilization of the epitaxial wafer and further improving the light-emitting efficiency of the epitaxial wafer.

[0025] In one alternative design, the first electrode layer is located in a region directly above a void portion of the improved layer.

[0026] In this case, the first electrode layer is affected by at most one lattice defect in a void portion.

[0027] In one alternative design, at least one of the first conductive layers occupies the same first electrode layer.

[0028] In this case, with the area of ​​the epitaxial wafer remaining unchanged, the cross-sectional area of ​​the light-emitting layer can be increased, thereby further improving the luminous efficiency of the epitaxial wafer.

[0029] An alternative design also includes:

[0030] A sacrificial layer is set in the first buffer layer;

[0031] The sacrificial layer is used to reduce damage to the epitaxial wafer during the stripping process when the substrate and the epitaxial wafer are stripped.

[0032] During the process of separating the substrate and the epitaxial wafer, the sacrificial layer can damage other structures in the epitaxial wafer in order to protect other structures in the epitaxial wafer and improve the yield of LED chips.

[0033] An alternative design also includes:

[0034] Insulating coating;

[0035] The insulating coating is a dielectric material;

[0036] The insulating coating is located on the surface of the target layer in an area that does not contact other layers, and the target layer is at least one of the first conductive layer, the light-emitting layer, the second conductive layer, the first electrode layer, and the second electrode layer.

[0037] The insulating coating layer can repair defects on the surface of the epitaxial wafer, reduce the probability of leakage, improve the safety of the epitaxial wafer, and increase the probability of electron recombination, thereby further improving the luminous efficiency of the epitaxial wafer.

[0038] In one optional design, the contact surface between the first buffer layer and the improvement layer is an uneven surface;

[0039] The side of the first buffer layer that contacts the improvement layer is convex.

[0040] When the side of the first buffer layer that contacts the improvement layer is convex, the light extraction efficiency and collimation of the epitaxial wafer can be improved.

[0041] In one alternative design, when the improvement layer includes two or more void portions, the two or more void portions are arranged in a regular periodic pattern, including a strip pattern, a mesh pattern, and / or a honeycomb pattern.

[0042] Secondly, embodiments of this application disclose an LED chip.

[0043] The LED chip includes the epitaxial wafer described in the first aspect.

[0044] Thirdly, embodiments of this application disclose a display screen.

[0045] The display screen includes the LED chip described in the second aspect.

[0046] In this application embodiment, an epitaxial wafer, an LED chip, and a display screen are disclosed. The epitaxial wafer includes: an improvement layer, a first buffer layer, a first conductive layer, a light-emitting layer, and a second conductive layer. In this epitaxial wafer, the improvement layer includes a solid portion and at least one void portion, the at least one void portion facing the first buffer layer, and the light-emitting layer is entirely located in the region directly above the solid portion of the improvement layer.

[0047] In the epitaxial wafer disclosed in this application, a first lattice defect and a second lattice defect are generated between the void portion of the improvement layer and the region in contact with the substrate. The first lattice defect extends along the growth direction of the epitaxial wafer, and the second lattice defect is located in the first buffer layer, or the second lattice defect is located in both the first buffer layer and the first conductive layer.

[0048] Since the first lattice defect extends along the epitaxial growth direction, and the entire light-emitting layer is located directly above the solid portion of the improvement layer, the first lattice defect will not reach the light-emitting layer. Consequently, the first lattice defect will not affect the luminescent recombination of electrons and holes in the light-emitting layer. Furthermore, the second lattice defect is located in the first buffer layer, or in both the first buffer layer and the first conductive layer. Therefore, the second lattice defect will also not reach the light-emitting layer, and consequently, it will not affect the luminescent recombination of electrons and holes in the light-emitting layer. Therefore, compared to the prior art, the epitaxial wafer disclosed in this application has fewer lattice defects in its light-emitting layer, resulting in higher luminous efficiency. Attached Figure Description

[0049] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1(a) is a schematic diagram of the connection relationship between an epitaxial wafer and a substrate disclosed in the prior art;

[0051] Figure 1(b) is a schematic diagram of the connection relationship between an epitaxial wafer and a substrate disclosed in the prior art;

[0052] Figure 2 A schematic diagram of the structure of an epitaxial wafer disclosed in the prior art;

[0053] Figure 3 This is a schematic diagram of the structure of an epitaxial wafer disclosed in an embodiment of this application;

[0054] Figure 4 This is a schematic diagram of a lattice defect in an epitaxial wafer disclosed in an embodiment of this application;

[0055] Figure 5 This is a schematic diagram of another epitaxial wafer structure disclosed in an embodiment of this application;

[0056] Figure 6 This is a schematic diagram of another epitaxial wafer structure disclosed in an embodiment of this application;

[0057] Figure 7 This is a schematic diagram of another epitaxial wafer structure disclosed in an embodiment of this application;

[0058] Figure 8 This is a top view of an epitaxial wafer disclosed in an embodiment of this application;

[0059] Figure 9(a) is a front view of an epitaxial wafer disclosed in an embodiment of this application;

[0060] Figure 9(b) is a top view of an epitaxial wafer disclosed in an embodiment of this application;

[0061] Figure 10 This is a schematic diagram of another epitaxial wafer structure disclosed in an embodiment of this application;

[0062] Figure 11(a) is a schematic diagram of the structure of an epitaxial wafer disclosed in an embodiment of this application;

[0063] Figure 11(b) is a schematic diagram of a scenario of an epitaxial wafer receiving laser irradiation as disclosed in an embodiment of this application;

[0064] Figure 11(c) is a schematic diagram of the structure of an epitaxial wafer after separation from the substrate, as disclosed in an embodiment of this application;

[0065] Figure 12(a) is a schematic diagram of the structure of an epitaxial wafer disclosed in an embodiment of this application;

[0066] Figure 12(b) is a schematic diagram of a scenario of an epitaxial wafer receiving laser irradiation as disclosed in an embodiment of this application;

[0067] Figure 12(c) is a schematic diagram of the structure of an epitaxial wafer after separation from the substrate, as disclosed in an embodiment of this application;

[0068] Figure 13(a) is a schematic diagram of the structure of an epitaxial wafer disclosed in an embodiment of this application;

[0069] Figure 13(b) is a schematic diagram of another epitaxial wafer structure disclosed in an embodiment of this application;

[0070] Figure 14(a) is a top view of an improved layer in an epitaxial wafer disclosed in an embodiment of this application;

[0071] Figure 14(b) is a top view of an improved layer in another epitaxial wafer disclosed in an embodiment of this application;

[0072] Figure 14(c) is a top view of an improved layer in another epitaxial wafer disclosed in an embodiment of this application. Detailed Implementation

[0073] To ensure clarity and conciseness in the description of the following embodiments, a brief introduction to the related technologies is given first:

[0074] Epitaxial wafers used in existing technologies are typically as follows: Figure 2 As shown, see Figure 2 Epitaxial wafers in the prior art typically include: a buffer layer 120, a first conductive layer 130, a light-emitting layer 140, and a second conductive layer 150 sequentially disposed on a substrate 110. The materials of each layer in the epitaxial wafer are typically gallium nitride (GaN), indium gallium nitride (InGaN), or other compound semiconductor materials.

[0075] Furthermore, in existing epitaxial wafers, due to a significant lattice constant mismatch between the epitaxial wafer material and the substrate material, lattice misalignments often occur when the crystals of the epitaxial wafer and the substrate are aligned. When the number of crystals in the epitaxial wafer and the substrate is large, these lattice misalignments accumulate, leading to lattice defects in the epitaxial wafer, also known as crystal defects. Figure 2 Even with the addition of a buffer layer between the epitaxial wafer and the substrate, or by patterning the substrate, significant lattice defects still exist within the epitaxial wafer, as shown. Furthermore, these lattice defects extend along the growth direction of the epitaxial wafer. For example, see... Figure 2 The schematic diagram shown in the figure represents lattice defects. As the epitaxial wafer grows in the vertical direction, the lattice defects also extend in the vertical direction. In this case, a large number of lattice defects will pass through the light-emitting layer 140 in the epitaxial wafer. That is, there are usually a large number of lattice defects in the light-emitting layer 140 of the epitaxial wafer in the prior art.

[0076] In an ideal state, during the application of a light emitting diode (LED) chip, electrons and electron holes recombine and form light as they pass through the epitaxial layer of the LED chip. This recombination of electrons and electron holes is also called light-emitting recombination. The recombination of electrons and electron holes usually occurs in the light-emitting layer of the epitaxial layer.

[0077] In this case, if there are lattice defects in the light-emitting layer, when electrons and holes pass through the region where the lattice defects are located, they will not recombine in that region. Therefore, these electrons and holes will not be used to form light. The potential energy of these electrons and holes is often converted into heat energy or other energy, resulting in wasted potential energy and reduced luminous efficiency of the LED chip. That is, in the epitaxial wafers of the prior art, there are many lattice defects in the light-emitting layer, which leads to a decrease in the luminous efficiency of the LED chip.

[0078] In particular, when LED chips are used in low-current applications, the total number of electrons and holes reaching the epitaxial wafer in the LED chip is relatively small. In this case, the ratio between the number of electrons and holes that cannot emit light due to lattice defects in the light-emitting layer and the total number of electrons and holes reaching the epitaxial wafer is relatively large, and the lattice defects in the light-emitting layer have a greater impact on the luminous efficiency of the LED chip.

[0079] To address the problem of large lattice defects between the epitaxial wafer and the substrate in the prior art, this application discloses an epitaxial wafer, a light-emitting diode, a display screen, and a method for fabricating the same, in order to reduce lattice defects in the epitaxial wafer and improve the luminous efficiency of the LED chip.

[0080] The terms "first," "second," and "third," etc., used in this application specification, claims, and drawings are used to distinguish different objects, not to limit a specific order.

[0081] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0082] This application discloses an epitaxial wafer. See also... Figure 3 The schematic diagram shown indicates that the epitaxial wafer includes: an improvement layer 210, a first buffer layer 220, a first conductive layer 230, a light-emitting layer 240, and a second conductive layer 250.

[0083] The improvement layer 210 is disposed above the substrate 260. See also... Figure 3 The schematic diagram shown indicates that the improvement layer includes a solid portion 211 and at least one void portion 212.

[0084] The first buffer layer 220, the first conductive layer 230, the light-emitting layer 240, and the second conductive layer 250 are sequentially disposed above the improvement layer 210. Furthermore, the at least one void portion 212 faces the first buffer layer 220.

[0085] When the epitaxial wafer is peeled off from the substrate, an external force is usually applied to the epitaxial wafer. The first buffer layer 220 is used to decompose under the action of the external force, thereby separating the first conductive layer 230, the light-emitting layer 240, and the second conductive layer 250 from the substrate. For example, when the epitaxial wafer is peeled off from the substrate by laser lift-off technology, the first buffer layer 220 can vaporize and decompose after absorbing the laser, thereby achieving the separation of the epitaxial wafer from the substrate.

[0086] To facilitate the disassembly of the first buffer layer 220, the first buffer layer 220 is typically made of a material that is easy to disassemble. For example, when an epitaxial wafer is peeled off from a substrate using laser lift-off technology, the first buffer layer 220 is typically made of a material with a high laser absorption rate.

[0087] Furthermore, in this embodiment, the material of the improvement layer 210 is typically different from that of the first buffer layer 220. The improvement layer 210 is generally made of a material that is not easily decomposed during the stripping process of the epitaxial wafer and substrate, to avoid contamination of the first conductive layer 230, the light-emitting layer 240, and the second conductive layer 250 due to decomposition during the stripping process.

[0088] For example, the improved layer 210 can be made of silicon oxide (SiOx) or silicon nitride (SiNx). Alternatively, the improved layer 210 can be made of other materials that are not easily decomposed; this embodiment of the application does not limit this. For instance, if laser lift-off technology is used to peel off the epitaxial wafer from the substrate, the improved layer 210 can be made of a material with low laser absorption.

[0089] Additionally, in this embodiment, the at least one void portion 212 in the improvement layer 210 faces the first buffer layer 220. In a feasible implementation, the first buffer layer 220 can contact the substrate 260 through the at least one void portion 212.

[0090] The first conductive layer 230 is typically an N-type semiconductor, the second conductive layer 250 is typically a P-type semiconductor, and the light-emitting layer 240 typically includes structures such as pn junctions and quantum wells. The quantum well can be a single-layer quantum well or a multi-layer quantum well, and this application does not limit this.

[0091] Furthermore, in the epitaxial wafer disclosed in this application embodiment, the entire light-emitting layer 240 is located within the region directly above the solid portion of the improvement layer 210. That is, when the light-emitting layer 240 and the improvement layer 210 are projected in the vertical direction, the projection surface of the light-emitting layer 240 is within the range of the projection surface of the solid portion of the improvement layer 210.

[0092] In the description of the various embodiments of this application, the term "above" is used, for example, A is disposed above B. In this case, "above" in the embodiments of this application generally refers to the growth direction of the epitaxial wafer. For example, in... Figure 3In the schematic diagram shown, the growth direction of the epitaxial wafer is: improvement layer - first buffer layer - first conductive layer - light-emitting layer - second conductive layer. It can be assumed that the first buffer layer is located above the improvement layer; the first conductive layer is located above the improvement layer and the first buffer layer; the light-emitting layer is located above the improvement layer, the first buffer layer and the first conductive layer; and the second conductive layer is located above the improvement layer, the first buffer layer, the first conductive layer and the light-emitting layer.

[0093] To clarify the advantages of the epitaxial wafers disclosed in the embodiments of this application, Figure 4 The document also discloses lattice defects generated in the epitaxial wafers disclosed in the embodiments of this application. Figure 4 In the figure, lattice defects generated within the epitaxial wafer are represented by curves.

[0094] In the epitaxial wafer of this application embodiment, an improvement layer 210 is provided between the substrate 260 and the first buffer layer 220. The improvement layer 210 includes a solid portion 211 and at least one void portion 212. Since the void portion 212 causes the position of the atoms that should be in the epitaxial wafer to be vacant, it will cause lattice defects to be generated between the void portion 212 and the area in contact with the substrate 260.

[0095] The lattice defects generated in the void portion extend along the growth direction of the epitaxial wafer, and also extend towards the solid portions 211 on both sides of the void portion 212. That is, the lattice defects between the void portion of the improved layer and the region in contact with the substrate include a first lattice defect 270 and a second lattice defect 280. The first lattice defect 270 is a lattice defect extending along the growth direction of the epitaxial wafer, and the second lattice defect 280 is a lattice defect extending towards both sides of the void portion.

[0096] See Figure 4 In the epitaxial wafer disclosed in this application embodiment, the second lattice defect 280 is located in the first buffer layer 220. Alternatively, the second lattice defect 280 is located in the first buffer layer 220 and the first conductive layer 230.

[0097] In the epitaxial wafer fabrication process, the height of the second lattice defect 280 within the epitaxial wafer can be adjusted by controlling the manufacturing process parameters, including the temperature and / or pressure during the manufacturing process. Therefore, the second lattice defect 280 in the epitaxial wafer of this embodiment can be controlled to be located either within the first buffer layer 220 or within both the first buffer layer 220 and the first conductive layer 230. In other words, the second lattice defect 280 will not reach the light-emitting layer 240.

[0098] Since the second lattice defect 280 does not reach the light-emitting layer 240, it does not affect the light-emitting layer 240. The light-emitting layer 240 is the region where electrons and holes recombine for light emission; therefore, when the second lattice defect 280 does not reach the light-emitting layer 240, it does not affect the recombination of electrons and holes in the light-emitting layer 240.

[0099] Further, see Figure 4 The lattice defect shown in this embodiment extends along the growth direction of the epitaxial wafer. In this case, when the entire light-emitting layer 240 is located directly above the solid portion 211 of the improvement layer 210, even if the first lattice defect 270 extends along the growth direction of the epitaxial wafer, it will avoid the light-emitting layer 240. Therefore, the first lattice defect 270 will not affect the luminous recombination of electrons and holes in the light-emitting layer 240, thereby further improving the luminous efficiency of the LED chip.

[0100] Alternatively, the first conductive layer 230 may be entirely located in the region directly above the solid portion 211 of the improvement layer 210. Or, since the first conductive layer 230 is not used for electron-hole recombination, it may be located simultaneously in the region directly above both the solid portion 211 and the void portion 212 of the improvement layer 210. In this case, because the first conductive layer 230 is not a region where light-emitting recombination occurs, it will not affect the luminous efficiency of the LED chip.

[0101] In this application embodiment, an epitaxial wafer is disclosed, comprising: an improvement layer, a first buffer layer, a first conductive layer, a light-emitting layer, and a second conductive layer. In this epitaxial wafer, the improvement layer includes a solid portion and at least one void portion, the at least one void portion facing the first buffer layer, and the light-emitting layer is entirely located in the region directly above the solid portion of the improvement layer.

[0102] In the epitaxial wafer disclosed in this application, a first lattice defect and a second lattice defect are generated between the void portion of the improvement layer and the region in contact with the substrate. The first lattice defect extends along the growth direction of the epitaxial wafer, and the second lattice defect is located in the first buffer layer, or the second lattice defect is located in both the first buffer layer and the first conductive layer.

[0103] Since the first lattice defect extends along the epitaxial growth direction, and the entire light-emitting layer is located directly above the solid portion of the improvement layer, the first lattice defect will not reach the light-emitting layer. Consequently, the first lattice defect will not affect the luminescent recombination of electrons and holes in the light-emitting layer. Furthermore, the second lattice defect is located in the first buffer layer, or in both the first buffer layer and the first conductive layer. Therefore, the second lattice defect will also not reach the light-emitting layer, and consequently, it will not affect the luminescent recombination of electrons and holes in the light-emitting layer. Therefore, compared to the prior art, the epitaxial wafer disclosed in this application has fewer lattice defects in its light-emitting layer, resulting in higher luminous efficiency.

[0104] Furthermore, in another embodiment of the epitaxial wafer disclosed in this application, a void layer is included between the solid portion 211 of the improvement layer 210 and the substrate 260; or, a void layer is included between the improvement layer 210 and the first buffer layer 220.

[0105] The heights of the two types of void layers are relatively small. For example, the height of the void layer between the solid portion 211 and the substrate 260 is less than a first threshold, or the height of the void layer between the improvement layer 210 and the first buffer layer 220 is less than a second threshold. The first and second thresholds can be set based on empirical values ​​or according to the requirements of the epitaxial wafer.

[0106] Wherein, there is a gap layer between the solid portion 211 and the substrate 260, indicating that the solid portion 211 and the substrate 260 are not in close contact or completely bonded; in addition, there is a gap layer between the improvement layer 210 and the first buffer layer 220, indicating that the improvement layer 210 and the first buffer layer 220 are not in close contact or completely bonded.

[0107] When the solid portion 211 of the improvement layer 210 is not in close contact or fully bonded to the substrate, or when the improvement layer 210 is not in close contact or fully bonded to the first buffer layer 220, lattice defects will not be generated in the solid portion 211 of the improvement layer 210. Compared with epitaxial wafers in the prior art, the epitaxial wafers disclosed in this application have fewer lattice defects, thereby further improving luminous efficiency.

[0108] In the above embodiments of this application, an epitaxial wafer including an improvement layer 210, a first buffer layer 220, a first conductive layer 230, a light-emitting layer 240, and a second conductive layer 250 is disclosed. Furthermore, the epitaxial wafer can be processed to provide electrodes.

[0109] In this case, this application also discloses another embodiment, see [link to embodiment]. Figure 5 The schematic diagram shown in this embodiment indicates that the epitaxial wafer also includes:

[0110] First electrode layer 310 and second electrode layer 320.

[0111] The first electrode layer 310 is disposed above the first conductive layer 230;

[0112] The second electrode layer 320 is disposed above the second conductive layer 250.

[0113] The first conductive layer 230 is not used for the recombination of electrons and holes. Therefore, the first conductive layer 230 can be entirely located in the region directly above the solid portion 211 of the improvement layer 210. Alternatively, the first conductive layer 230 can be located in the region directly above both the solid portion 211 and the void portion 212 of the improvement layer 210. In this case, even if the first lattice defect 270 passes through the first conductive layer 230, as long as the first lattice defect 270 does not pass through the light-emitting layer 240, the first lattice defect 270 will not affect the luminous efficiency of the LED chip.

[0114] Furthermore, in this embodiment, the position of the first electrode layer 310 can also be flexibly set. In one possible implementation, see [link to relevant documentation]. Figure 5 and Figure 6 The first electrode layer 310 is entirely located in the area directly above the solid portion of the improvement layer.

[0115] Furthermore, compared to standard-sized LED chips, micro-LED chips offer advantages such as higher brightness, lower power consumption, and longer lifespan. Therefore, applying micro-LED chips in LED displays is a relatively ideal technology. Micro-LED chips typically refer to LED chips with dimensions of tens or even hundreds of micrometers. However, LED displays often include multiple LED chips. The smaller the size of the individual LED chips, the higher the ratio between the area of ​​the gaps between them and the total area of ​​all the LED chips. Since the gaps between the LED chips have no effect on their luminous performance, a higher ratio indicates greater area waste due to these gaps.

[0116] To improve area utilization, see Figure 7 The schematic diagram illustrates an alternative implementation where the first electrode layer 310 is located directly above both the void portion 212 and the solid portion 211 of the improvement layer 210. In this case, with Figure 6Compared to the epitaxial wafer in the previous example, the area that the cross-section of the light-emitting layer 240 can occupy is increased while keeping the size of the epitaxial wafer constant. For example, in Figure 6 In the cross-section of the light-emitting layer 240, one side has a length of L, while... Figure 7 In this case, the side length of this side in the cross-section of the light-emitting layer 240 can reach L+l, and the area of ​​the cross-section of the light-emitting layer 240 is increased accordingly. The cross-section of the light-emitting layer 240 can be the side of the light-emitting layer 240 that contacts the solid portion of the improvement layer.

[0117] The light-emitting layer 240 is a region for realizing the luminescent recombination of electrons and holes. The larger the cross-sectional area of ​​the light-emitting layer 240, the larger the area available for realizing the luminescent recombination of electrons and holes, and correspondingly, the higher the luminous efficiency of the epitaxial wafer. Therefore, the solution of this application embodiment can improve the area utilization of the epitaxial wafer, and further improve the luminous efficiency of the epitaxial wafer.

[0118] Alternatively, in another feasible implementation, the first electrode layer 310 is entirely located in the region directly above the void portion of the improvement layer. In this case, the cross-sectional area of ​​the light-emitting layer 240 can be up to equal the cross-sectional area of ​​the solid portion of the improvement layer. Accordingly, since the cross-sectional area of ​​the light-emitting layer 240 is increased in this implementation, the area available for luminescent recombination of electrons and holes is increased, further improving the luminous efficiency of the epitaxial wafer.

[0119] Furthermore, in one feasible implementation, the first electrode layer 310 is located at most within a region directly above a void portion of the improved layer.

[0120] To ensure the utilization area of ​​the light-emitting layer 240, the first electrode layer 310 can be disposed in the region directly above the void portion of the improvement layer. However, the void portion of the improvement layer can generate first lattice defects extending along the growth direction of the epitaxial wafer. In this case, to reduce the impact of the first lattice defects on the first electrode layer 310, in this embodiment, the first electrode layer 310 is located only in the region directly above one void portion of the improvement layer; that is, the first electrode layer 310 is only affected by the first lattice defects of one void portion.

[0121] Furthermore, in the epitaxial wafer disclosed in the embodiments of this application, at least one of the first conductive layers 230 occupies the same first electrode layer 310. That is, one first conductive layer 230 may occupy a single first electrode layer 310, or two or more first conductive layers 230 may occupy the same first electrode layer 310.

[0122] When a first conductive layer 230 occupies a single first electrode layer 310, the side view of the epitaxial wafer can be as follows: Figure 6 and Figure 7 As shown, the top view of the epitaxial wafer can be seen as follows: Figure 8 As shown. In this case, different first electrode layers 310 are respectively disposed above different first conductive layers 230.

[0123] When two or more first conductive layers 230 occupy the same first electrode layer 310, referring to the front view of the epitaxial wafer shown in FIG. 9(a) and the top view of the epitaxial wafer shown in FIG. 9(b), different portions of the same first electrode layer 310 are respectively disposed above different first conductive layers 230, and the different first conductive layers 230 share the same electrode layer. For example, in FIG. 9(a) and FIG. 9(b), four first conductive layers 230 occupy the same first electrode layer 310.

[0124] When two or more first conductive layers 230 occupy the same first electrode layer 310, the area that the light-emitting layer 240 can occupy increases while the area of ​​the epitaxial wafer remains unchanged. Correspondingly, the area used for the luminescent recombination of electrons and holes increases, leading to an increase in the luminous efficiency of the epitaxial wafer. Therefore, the solution of this application embodiment can improve the area utilization of the epitaxial wafer and further improve its luminous efficiency.

[0125] In addition, the epitaxial wafer disclosed in the embodiments of this application also includes an insulating coating layer, wherein the insulating coating layer is a dielectric material.

[0126] The insulating coating layer is located on the surface of the target layer in an area that does not contact other layers, and the target layer is at least one of the first conductive layer, the light-emitting layer, the second conductive layer, the first electrode layer, and the second electrode layer.

[0127] The fabrication process of an epitaxial wafer typically includes the following steps: First, an improvement layer is fabricated above the substrate using etching technology, followed by the sequential deposition of a first buffer layer, a first conductive layer, a light-emitting layer, and a second conductive layer above the improvement layer. Then, partial areas of the first and second conductive layers are exposed using etching technology, with a first electrode layer deposited in the exposed area of ​​the first conductive layer and a second electrode layer deposited in the exposed area of ​​the second conductive layer. This etching step in the fabrication process is likely to introduce surface defects into the various layers of the epitaxial wafer.

[0128] Electrons and holes can recombine on the surface of the light-emitting layer of the epitaxial wafer. When defects occur on the surface of each layer of the epitaxial wafer, the probability of electrons and holes reaching the light-emitting layer is reduced, as is the probability of electrons and holes recombinating on the surface of the light-emitting layer. Furthermore, the probability of leakage current in the epitaxial wafer is increased.

[0129] In this case, the epitaxial wafer disclosed in the embodiments of this application is further provided with an insulating coating layer. The insulating coating layer is made of dielectric material, which can repair defects on the surface of the epitaxial wafer, reduce the probability of leakage, improve the safety of the epitaxial wafer, and increase the probability of electron holes undergoing luminescent recombination, thereby further improving the luminescent efficiency of the epitaxial wafer.

[0130] Furthermore, in this embodiment, the insulating coating layer is located on the surface of the target layer in a region that does not contact other layers. The target layer is at least any one of the first conductive layer, the light-emitting layer, the second conductive layer, the first electrode layer, and the second electrode layer. In other words, the non-electrical connection regions of the epitaxial wafer disclosed in this embodiment can all be provided with an insulating coating layer.

[0131] The insulating coating can be made of dielectric materials such as silicon oxide (SiOx) or silicon nitride (SiNx). Of course, the insulating coating can also be made of other dielectric materials, and this application does not limit this.

[0132] In some applications, it is necessary to separate the epitaxial wafer from the substrate. For this situation, see [link to relevant documentation]. Figure 10 The schematic diagram shown further includes, in the epitaxial wafer disclosed in the embodiments of this application:

[0133] A sacrificial layer 330 is set in the first buffer layer 220.

[0134] When the substrate and the epitaxial wafer are stripped, the sacrificial layer 330 is used to reduce damage to the epitaxial wafer during the stripping process.

[0135] During the process of peeling off the substrate and the epitaxial wafer, it is usually necessary to apply external force to the substrate and the epitaxial wafer. During this process, the external force may damage the epitaxial wafer.

[0136] For example, the commonly used lift-off technique is laser lift-off. Referring to the schematic diagram in Figure 11(a), when lifting the epitaxial wafer using laser lift-off, an adhesive layer 340 is placed on top of the epitaxial wafer, and the epitaxial wafer is adhered to the first substrate 350 through the adhesive layer 340. Then, referring to the schematic diagram in Figure 11(b), a laser irradiates the epitaxial wafer from the substrate direction. During the irradiation process, the first buffer layer 220 absorbs the laser and vaporizes and decomposes under the action of the laser, thereby achieving the separation of the epitaxial wafer from the substrate, obtaining the epitaxial wafer shown in Figure 11(c).

[0137] When the LED chip size is small, such as when the LED chip is a Micro-LED chip, the size of the epitaxial wafer is correspondingly small. In this case, when the laser irradiates the epitaxial wafer, the force generated at the moment when the first buffer layer is vaporized and decomposed by the laser may damage the structure of the epitaxial wafer and may also cause the epitaxial wafer to be displaced on the first substrate 350, thereby affecting the yield of the LED chip.

[0138] In this case, the epitaxial wafer disclosed in the embodiments of this application also includes a sacrificial layer 330 disposed in the first buffer layer 220. The sacrificial layer 330 may be made of a material with poor resistance to external forces, so that during the process of peeling off the substrate and the epitaxial wafer, the sacrificial layer 330 is damaged instead of other structures in the epitaxial wafer, so as to protect the other structures in the epitaxial wafer.

[0139] For example, when the stripping technique used is laser stripping, the sacrificial layer 330 can also be made of a material with a high laser absorption rate. In this case, during the stripping process, the sacrificial layer 330 absorbs most of the laser and preferentially vaporizes and decomposes, thereby reducing damage to other structures in the epitaxial wafer.

[0140] For example, when separating the epitaxial wafer and the substrate using laser lift-off technology, referring to the schematic diagram shown in FIG12(a), the epitaxial wafer is adhered to the first substrate 350 by an adhesive layer 340, and a sacrificial layer 330 is disposed in the first buffer layer 220 of the epitaxial wafer. Then, referring to the schematic diagram shown in FIG12(b), a laser irradiates the epitaxial wafer from the substrate direction. During the irradiation process, the sacrificial layer 330 absorbs most of the laser and vaporizes and decomposes under the action of the laser, thereby obtaining the epitaxial wafer shown in FIG12(c), realizing the separation of the epitaxial wafer from the substrate, and reducing damage to the epitaxial wafer because the sacrificial layer 330 absorbs most of the laser.

[0141] Furthermore, since the sacrificial layer disposed in the first buffer layer 220 can reduce the damage to the epitaxial wafer during the stripping process, it can also improve the yield of LED chips.

[0142] In another feasible design, referring to the schematic diagram shown in FIG13(a), in the epitaxial wafer disclosed in the embodiments of this application, the contact surface between the first buffer layer 220 and the improvement layer 210 is a concave-convex surface.

[0143] Furthermore, referring to the schematic diagram shown in FIG13(b), the side of the first buffer layer 220 that is in contact with the improvement layer 210 is convex.

[0144] Since the improvement layer 210 is typically made of silicon oxide (SiOx) or silicon nitride (SiNx), while other layers in the epitaxial wafer (e.g., the first buffer layer 220, the first conductive layer 230, the light-emitting layer 240, and the second conductive layer 250) are typically made of gallium nitride (GaN), the absorption rate of the improvement layer 210 to laser light is often lower than that of the first buffer layer 220. Therefore, when the epitaxial wafer and substrate are separated using laser lift-off technology, the surface of the first buffer layer 220 facing the laser irradiation is more prone to vaporization and decomposition. Thus, making the side of the first buffer layer 220 that contacts the improvement layer 210 convex helps prevent the other layers above the first buffer layer 220 from vaporizing and decomposing when laser lift-off technology is applied.

[0145] Furthermore, after the epitaxial wafer is peeled off from the substrate, the underside of the epitaxial wafer is typically used as the light-emitting surface. A convex light-emitting surface facilitates light emission from the epitaxial wafer, improving its light extraction efficiency and collimation. Therefore, the first buffer layer 220 can also be configured such that one side of it contacts the improvement layer 210 is convex.

[0146] The first buffer layer 220 is used to contact the side of the improvement layer 210, and can be a convex surface in various forms. In the schematic diagram shown in FIG13(b), the convex surface of the first buffer layer is a polygonal convex surface, or, in practical applications, the convex surface can also be an arc-shaped convex surface with different curvatures. This application embodiment does not limit this.

[0147] In the epitaxial wafer disclosed in the embodiments of this application, an improvement layer is provided. The material of the improvement layer is typically silicon oxide or silicon nitride, etc.

[0148] Furthermore, the improved layer includes void portions. When the improved layer includes two or more void portions, these void portions can be arranged in various forms. Feasibly, the two or more void portions can exhibit a regular, periodic arrangement, including strip-like, mesh-like, and / or honeycomb-like arrangements.

[0149] For example, referring to the top view of the improved layer shown in FIG14(a), the two or more void portions 221 are arranged in a strip-like pattern; or referring to the top view of the improved layer shown in FIG14(b), the two or more void portions 221 are arranged in a mesh-like pattern; or referring to the top view of the improved layer shown in FIG14(c), the two or more void portions 221 are arranged in a honeycomb-like pattern.

[0150] Of course, the two or more gap portions 221 can also be arranged in other ways, and this application embodiment does not limit this.

[0151] Accordingly, in another embodiment of this application, an LED chip is also disclosed, which includes the epitaxial wafer disclosed in the above embodiments.

[0152] Because the luminous efficiency of the epitaxial wafer is improved, the luminous efficiency of the LED chip disclosed in the embodiments of this application is also improved accordingly.

[0153] In another embodiment of this application, a display screen is also disclosed, which includes the LED chip disclosed in the above embodiments of this application. Compared with the display screens in the prior art, the LED chip used in the display screen disclosed in the embodiments of this application has higher luminous efficiency; therefore, the luminous efficiency of the display screen disclosed in the embodiments of this application is also correspondingly improved.

[0154] In summary, this application discloses an epitaxial wafer, a corresponding LED chip, and a display screen using the LED chip. The epitaxial wafer includes a first lattice defect and a second lattice defect, and these defects do not reach the light-emitting layer, which is a defect resulting from the recombination of electrons and holes. Therefore, compared to epitaxial wafers in the prior art, the epitaxial wafer of this application has fewer lattice defects in its light-emitting layer, and furthermore, it has higher luminous efficiency. Consequently, the LED chip obtained using the epitaxial wafer of this application has higher luminous efficiency.

[0155] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application.

[0156] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An epitaxial wafer, characterized by, Comprising: an improvement layer, a first buffer layer, a first conductive layer, a light emitting layer, and a second conductive layer; the improvement layer is disposed above a substrate, the improvement layer comprises a solid portion and at least one void portion; the first buffer layer, the first conductive layer, the light emitting layer, and the second conductive layer are sequentially disposed above the improvement layer, the at least one void portion is towards the first buffer layer; the light emitting layer is entirely within the range of the area above the solid portion of the improvement layer; lattice defects between the void portion of the improvement layer and the area where the improvement layer is in contact with the substrate comprise first lattice defects and second lattice defects, the first lattice defects are lattice defects extending along the growth direction of the epitaxial wafer, and the second lattice defects are lattice defects extending to both sides of the void portion; the second lattice defects are located in the first buffer layer, or the second lattice defects are located in the first buffer layer and the first conductive layer; wherein the solid portion of the improvement layer and the substrate comprise a void layer; or, the improvement layer and the first buffer layer comprise a void layer.

2. The epitaxial wafer of claim 1, wherein Further comprising: a first electrode layer and a second electrode layer; the first electrode layer is disposed above the first conductive layer; the second electrode layer is disposed above the second conductive layer.

3. The epitaxial wafer of claim 2, wherein: the first electrode layer is simultaneously within the range of the area above the void portion and the solid portion of the improvement layer; or, the first electrode layer is entirely within the range of the area above the void portion of the improvement layer.

4. The epitaxial wafer of claim 3, wherein: the first electrode layer is at most within the range of the area above one void portion of the improvement layer.

5. The epitaxial wafer of any one of claims 2 to 4, wherein: at least one of the first conductive layers occupies the same first electrode layer.

6. The epitaxial wafer of claim 1, wherein, Further comprising: a sacrificial layer disposed in the first buffer layer; when the substrate and the epitaxial wafer are peeled off, the sacrificial layer is used to reduce damage to the epitaxial wafer during the peeling process.

7. The epitaxial wafer of claim 2, wherein, Further comprising: an insulating coating layer; the insulating coating layer is a dielectric material; the insulating coating layer is located on the surface of the area where the target layer is not in contact with other layers, and the target layer is at least any one of the first conductive layer, the light emitting layer, the second conductive layer, the first electrode layer, and the second electrode layer.

8. The epitaxial wafer of claim 1, wherein: the contact surface between the first buffer layer and the improvement layer is a concave-convex surface; the surface of the first buffer layer for contacting the improvement layer is a convex surface.

9. The epitaxial wafer of claim 1, wherein: when the improvement layer comprises two or more void portions, the two or more void portions are arranged in a regular period, including strip arrangement, net arrangement, and / or honeycomb arrangement.

10. An LED chip, comprising: the LED chip comprises the epitaxial wafer of any one of claims 1 to 9.

11. A display screen, comprising: the display screen comprises the LED chip of claim 10.

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