Power supply voltage difference detection circuit, chip, electronic component and electronic equipment

Abstract

The present application provides a power supply voltage difference detection circuit, chip, electronic component and electronic device. The power supply voltage difference detection circuit includes: a first follower circuit connected to a first power supply, for scaling a first voltage output by the first power supply according to a first coefficient to obtain a first target voltage; a second follower circuit connected to a second power supply, for scaling a second voltage output by the second power supply according to a second coefficient to obtain a second target voltage; a first detection circuit connected to a signal output end of the first follower circuit and a signal output end of the second follower circuit, respectively, for outputting a first signal representing that the voltage difference is abnormal when the absolute value of the difference between the first target voltage and the second target voltage does not meet a preset threshold condition. The present application can detect whether the voltage difference between different power supplies is normal, which makes up for the deficiency of the existing POR circuit that can only detect whether the voltage of a single power supply is normal.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a power supply voltage difference detection circuit, chip, electronic component, and electronic equipment. Background Art

[0002] With advancements in process technology and increased chip integration, a large number of different functional modules are integrated into a single chip. These modules have varying operating speed and power consumption requirements. To meet design requirements and the overall system power consumption, chips are placing increasingly stringent demands on power supplies, evolving from a single power supply to multiple power supplies. The power supply sequence between the power supplies has also changed from simultaneous power-up to sequential power-up. To ensure proper functioning of all chip modules and prevent chip damage, designers must ensure a consistent power-up sequence and interval between power supplies.

[0003] In current chip design, POR (Power On Reset) circuit is usually used to manage power supply. Its functions are as follows: Figure 1 As shown in the figure. When the power supply voltage VDD rises to a certain voltage value (VPOR), the POR begins timing and waits for a period of time, T0, before the POR exits the reset state (the PowerOK signal changes to VDD). T0 is the time required for the power supply to stabilize. If the power supply voltage drops below VPOR again during the T0 waiting period, the POR remains in the reset state (i.e., the PowerOK signal remains low) until the next voltage rise. After the power supply is operating normally, to prevent a reset from occurring due to a very brief, unexpected drop in the power supply voltage, which could cause a system failure, the POR typically incorporates a hysteresis voltage and a filter to filter out the corresponding pulses. The POR will not output a reset signal (i.e., the PowerOK signal goes low) until the power supply voltage drops below VPOR for a period greater than T1.

[0004] In some applications, multiple POR circuits are placed inside the chip to detect the power supply status of different power supply voltages to prevent abnormal working conditions.

[0005] However, the POR can only detect the voltage of a single power supply. In a multi-power supply system, when the power supply of each power supply is higher than the VPOR of its corresponding POR, each POR will end the reset state, indicating that the system can operate normally. However, for modules sensitive to power supply voltage differences, abnormalities may be caused by excessive or insufficient voltage differences between the power supplies. The POR circuit cannot detect such abnormalities. Summary of the Invention

[0006] The purpose of the embodiments of the present application is to provide a power supply voltage difference detection circuit, chip, electronic component and electronic device to solve the above-mentioned problems.

[0007] An embodiment of the present application provides a unidirectional power supply voltage difference detection circuit, including: a first follower circuit, connected to a first power supply, for scaling a first voltage output by the first power supply according to a first coefficient to obtain a first target voltage; a second follower circuit, connected to a second power supply, for scaling a second voltage output by the second power supply according to a second coefficient to obtain a second target voltage; when the first power supply and the second power supply are normal, the first target voltage and the second target voltage are common mode; a first detection circuit, respectively connected to a signal output end of the first follower circuit and a signal output end of the second follower circuit, for outputting a first signal indicating that the voltage difference is abnormal when the absolute value of the difference between the first target voltage and the second target voltage does not meet a preset threshold condition, and outputting a second signal indicating that the voltage difference is normal when the absolute value of the difference between the first target voltage and the second target voltage meets a preset threshold condition.

[0008] In the above implementation process, the first voltage of the first power supply and the second voltage of the second power supply are converted into a common-mode voltage through the first follower circuit and the second follower circuit, so that the first power supply and the second power supply are comparable, and then the absolute value of the difference between the converted first target voltage and the second target voltage is compared with the preset threshold condition. Therefore, engineers only need to reasonably design the threshold condition according to the design requirements of the chip to realize the detection of whether the voltage difference between the first power supply and the second power supply is normal. It can realize the detection of anomalies caused by excessive or insufficient voltage difference between the power supplies for power supply voltage difference sensitive modules, which makes up for the deficiency of the existing POR circuit that can only detect whether the voltage of a single power supply is normal.

[0009] Furthermore, the first detection circuit is specifically used to: output a first signal indicating that the voltage difference is abnormal when the absolute value of the difference between the first target voltage and the second target voltage is greater than a preset first threshold voltage; and output a second signal indicating that the voltage difference is normal when the absolute value of the difference between the first target voltage and the second target voltage is less than or equal to the first threshold voltage.

[0010] The above implementation method can realize the detection of excessive voltage difference. Once the absolute value of the difference between the first target voltage and the second target voltage is greater than the preset first threshold voltage, a first signal indicating that the voltage difference is abnormal is output.

[0011] Furthermore, the first detection circuit is specifically used to: output a first signal indicating that the voltage difference is abnormal when the absolute value of the difference between the first target voltage and the second target voltage is less than a preset second threshold voltage; and output a second signal indicating that the voltage difference is normal when the absolute value of the difference between the first target voltage and the second target voltage is greater than or equal to the second threshold voltage.

[0012] By the above implementation, it is possible to detect a voltage difference that is too small. Once the absolute value of the difference between the first target voltage and the second target voltage is greater than a preset first threshold voltage, a first signal indicating that the voltage difference is abnormal is output.

[0013] Furthermore, the first follower circuit includes: a plurality of first resistive elements connected in series between the first power supply and the ground; the signal output end of the first follower circuit is arranged between the two first resistive elements to divide the plurality of first resistive elements into two parts; wherein: the ratio between the total resistance value of the first target part and the total resistance value of the plurality of first resistive elements is equal to the first coefficient; the first target part is composed of each of the first resistive elements located between the output end of the first follower circuit and the ground.

[0014] In the above implementation, the first voltage can be divided using multiple first resistive elements. Thus, the desired first coefficient can be easily achieved in the circuit simply by designing the position of the output terminal of the first follower circuit and the resistance value of each first resistive element as required. This implementation method is simple in structure and facilitates on-chip deployment.

[0015] Furthermore, the second follower circuit includes: a plurality of second resistive elements connected in series between the second power supply and ground; the signal output end of the second follower circuit is arranged between the two second resistive elements to divide the plurality of second resistive elements into two parts; wherein: the ratio between the total resistance value of the second target part and the total resistance value of the plurality of second resistive elements is equal to the second coefficient; the second target part is composed of each second resistive element located between the output end of the second follower circuit and the ground.

[0016] In the above implementation, multiple second resistive elements can be used to divide the second voltage. Thus, simply by designing the position of the output terminal of the second follower circuit and the resistance value of each second resistive element as required, the desired second coefficient can be easily achieved in the circuit. This implementation method is simple in structure and facilitates on-chip deployment.

[0017] The present application also provides a bidirectional power supply voltage difference detection circuit, comprising: two of the aforementioned unidirectional power supply voltage difference detection circuits; and a first arbitration circuit, the input end of which is connected to the output ends of the two unidirectional power supply voltage difference detection circuits, respectively, and configured to output the first signal when any one of the unidirectional power supply voltage difference detection circuits outputs a first signal indicating an abnormal voltage difference, and output the second signal when both of the unidirectional power supply voltage difference detection circuits output a second signal indicating a normal voltage difference; wherein:

[0018] The first detection circuit of the first unidirectional power supply voltage difference detection circuit is configured to output the first signal when the absolute value of the difference between the first target voltage and the second target voltage is greater than a preset first threshold voltage, and output the second signal when the absolute value of the difference between the first target voltage and the second target voltage is less than or equal to the first threshold voltage;

[0019] The first detection circuit of the second unidirectional power supply voltage difference detection circuit is configured to output the first signal when the absolute value of the difference between the first target voltage and the second target voltage is less than a preset second threshold voltage, and output the second signal when the absolute value of the difference between the first target voltage and the second target voltage is greater than or equal to the second threshold voltage;

[0020] The second threshold voltage is lower than the first threshold voltage.

[0021] In the above implementation structure, two unidirectional power supply voltage difference detection circuits are used to respectively detect an excessive voltage difference and a too-small voltage difference. Through the action of the first arbitration circuit, when any unidirectional power supply voltage difference detection circuit detects an abnormality, a signal representing the abnormality will be output, thereby achieving a bidirectional detection effect.

[0022] The embodiment of the present application further provides a unidirectional power supply voltage difference detection circuit, comprising:

[0023] A third follower circuit is connected to a third power supply and is configured to scale a third voltage output by the third power supply according to a third coefficient to obtain a third target voltage; a second detection circuit has a power supply terminal connected to a fourth power supply and a signal input terminal connected to the output terminal of the third follower circuit, and is configured to output a first signal indicating that the voltage difference is abnormal when a preset threshold condition is not satisfied between the third target voltage and the threshold voltage of the second detection circuit, and output a second signal indicating that the voltage difference is normal when a preset threshold condition is satisfied between the third target voltage and the threshold voltage of the second detection circuit; wherein:

[0024] The threshold voltage of the second detection circuit includes a third threshold voltage V+ and a fourth threshold voltage V-; the V+ is equal to x1 times the fourth voltage, and the V- is equal to x2 times the fourth voltage; the x1 is greater than the x2, and the fourth voltage is the voltage output by the fourth power supply; the third target voltage is common mode with the median voltage of the second detection circuit, and the median voltage of the second detection circuit is equal to the product of (x1+x2) / 2 and the fourth voltage.

[0025] In the above implementation, the voltage of the third power supply can be adjusted to a common mode with the second detection circuit through the action of the third follower circuit. Since the two threshold voltages of the second detection circuit follow the fourth voltage of the fourth power supply, it is possible to detect whether the voltage difference is normal based on the two threshold voltages of the second detection circuit. Therefore, engineers only need to reasonably design the threshold conditions according to the design requirements of the chip to detect whether the voltage difference between the third power supply and the fourth power supply is normal. This can detect abnormalities caused by excessive or insufficient voltage differences between power supplies in modules sensitive to power supply voltage differences, thereby making up for the deficiency of the existing POR circuit in being able to detect whether the voltage of a single power supply is normal. In addition, in the above implementation, by utilizing V+ and V- with a certain difference, it is possible to avoid the second detection circuit frequently switching between the first signal and the second signal due to glitches in the voltage signal itself, thereby avoiding misjudgment.

[0026] Furthermore, the second detection circuit is specifically configured to: output a first signal indicating that the voltage difference is abnormal when the third target voltage is greater than the V+; and output a second signal indicating that the voltage difference is normal when the third target voltage is less than the V-.

[0027] The above implementation enables detection of excessive voltage differences. Once the voltage difference between the third and fourth power supplies exceeds the designed range, a first signal indicating a normal voltage difference is output. Furthermore, in this implementation, by utilizing V+ and V- with a certain difference, a second signal indicating a normal voltage difference is output only when the third target voltage is less than V-. This prevents the second detection circuit from frequently switching between the first and second signals due to glitches in the voltage signal itself, potentially leading to misjudgments.

[0028] Furthermore, the second detection circuit is specifically configured to: output a first signal indicating that the voltage difference is abnormal when the third target voltage is less than the V-, and output a second signal indicating that the voltage difference is normal when the third target voltage is greater than the V+.

[0029] The above implementation enables detection of excessively small voltage differences. If the voltage difference between the third and fourth power supplies falls below the designed range, a first signal indicating a normal voltage difference is output. Furthermore, in the above implementation, by utilizing V+ and V- with a certain difference, a second signal indicating a normal voltage difference is output only when the third target voltage is greater than V+. This prevents the second detection circuit from frequently switching between the first and second signals due to glitches in the voltage signal itself, potentially leading to misjudgments.

[0030] Furthermore, the third follower circuit includes: a plurality of third resistive elements connected in series between the third power supply and ground; a signal output terminal of the third follower circuit is arranged between the two third resistive elements to divide the plurality of third resistive elements into two parts;

[0031] Wherein: the ratio between the total resistance value of the third target part and the total resistance value of the plurality of third resistive elements is equal to the third coefficient; the third target part is composed of the third resistive elements located between the output end of the third follower circuit and the ground.

[0032] In the above implementation, multiple third resistive elements can be used to divide the third voltage. Thus, the desired third coefficient can be easily achieved in the circuit simply by designing the position of the output terminal of the third follower circuit and the resistance value of each third resistive element as required. This implementation method is simple in structure and facilitates on-chip deployment.

[0033] Furthermore, the unidirectional power supply voltage difference detection circuit further includes: a buffer, an input end of which is connected to the output end of the second detection circuit.

[0034] In the above implementation, by connecting a buffer to the output end of the second detection circuit, the driving performance of the circuit can be enhanced through the buffer, thereby ensuring the stability of the first signal or the second signal that is finally output.

[0035] Furthermore, the second detection circuit is a Schmitt trigger.

[0036] In the above implementation, since the characteristics of the Schmitt trigger itself determine that it has two threshold voltages that follow the input signal at the power supply end, and can compare the input signal with the two thresholds, the Schmitt trigger can be sampled as the second detection circuit. The circuit implementation structure is simple and is conducive to deployment in the chip.

[0037] The present application also provides a bidirectional power supply voltage difference detection circuit, comprising: two of the aforementioned unidirectional power supply voltage difference detection circuits; and a second arbitration circuit, the input end of which is connected to the output ends of the two unidirectional power supply voltage difference detection circuits, respectively, and configured to output the first signal when any one of the unidirectional power supply voltage difference detection circuits outputs a first signal indicating an abnormal voltage difference, and output the second signal when both of the unidirectional power supply voltage difference detection circuits output a second signal indicating a normal voltage difference; wherein:

[0038] The second detection circuit of the first unidirectional power supply voltage difference detection circuit is configured to output the first signal when the third target voltage is greater than V+ of the first unidirectional power supply voltage difference detection circuit, and output the second signal when the third target voltage is less than V- of the first unidirectional power supply voltage difference detection circuit;

[0039] The second detection circuit of the second unidirectional power supply voltage difference detection circuit is configured to output the first signal when the third target voltage is less than V- of the second unidirectional power supply voltage difference detection circuit, and output the second signal when the third target voltage is greater than V+ of the second unidirectional power supply voltage difference detection circuit;

[0040] The V+ of the first unidirectional power supply voltage difference detection circuit is greater than the V+ of the second unidirectional power supply voltage difference detection circuit, and the V- of the first unidirectional power supply voltage difference detection circuit is greater than the V- of the second unidirectional power supply voltage difference detection circuit.

[0041] In the above implementation structure, two unidirectional power supply voltage difference detection circuits are used to respectively detect an excessive voltage difference and a too-small voltage difference. Through the action of the second arbitration circuit, when any unidirectional power supply voltage difference detection circuit detects an abnormality, a signal representing the abnormality will be output, thereby achieving a bidirectional detection effect.

[0042] An embodiment of the present application further provides a chip comprising any one of the aforementioned unidirectional power supply voltage difference detection circuits, or comprising any one of the aforementioned bidirectional power supply voltage difference detection circuits.

[0043] An embodiment of the present application also provides an electronic component, including the aforementioned chip.

[0044] An embodiment of the present application further provides an electronic device comprising the aforementioned chip, or comprising the aforementioned electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 A schematic diagram of the signal timing when the POR circuit manages power in the background technology;

[0047] Figure 2 This is a structural diagram of a unidirectional power supply voltage difference detection circuit provided in Example 1 of the present application;

[0048] Figure 3 A schematic structural diagram of a first follower circuit provided in an embodiment of the present application;

[0049] Figure 4a A schematic diagram of a first voltage signal and a second voltage signal provided in Example 1 of the present application;

[0050] Figure 4b A schematic diagram of a first target voltage V1 and a second target voltage V2 provided in the first embodiment of the present application;

[0051] Figure 4c A waveform comparison diagram of the difference between V1 and V2 and the first threshold voltage VREF1, as well as a waveform diagram of the output signal VO, provided in the first embodiment of the present application;

[0052] Figure 4d A waveform comparison diagram of another signal obtained by subtracting V1 from V2 and the first threshold voltage VREF1, as well as a waveform diagram of the output signal VO, provided in the first embodiment of the present application;

[0053] Figure 5 A schematic structural diagram of a bidirectional power supply voltage difference detection circuit provided in Example 1 of the present application;

[0054] Figure 6 This is a structural diagram of a unidirectional power supply voltage difference detection circuit provided in Example 2 of the present application;

[0055] Figure 7 A schematic structural diagram of a specific unidirectional power supply voltage difference detection circuit provided in Example 2 of the present application;

[0056] Figure 8 A structural diagram of a more specific unidirectional power supply voltage difference detection circuit provided in Example 2 of the present application;

[0057] Figure 9aA schematic diagram of a signal waveform provided in Example 2 of the present application;

[0058] Figure 9b Another signal waveform diagram provided in Example 2 of the present application;

[0059] Figure 10 This is a structural diagram of a bidirectional power supply voltage difference detection circuit provided in Example 2 of the present application. DETAILED DESCRIPTION

[0060] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0061] Example 1:

[0062] In order to solve the current problem of being unable to detect abnormalities caused by excessive or insufficient voltage differences between power supplies, a unidirectional power supply voltage difference detection circuit is provided in the embodiment of the present application. Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of the unidirectional power supply voltage difference detection circuit provided in the first embodiment of the present application, comprising: a first follower circuit, a second follower circuit and a first detection circuit.

[0063] The first follower circuit is connected to the first power supply, and is configured to scale the first voltage VDD1 output by the first power supply according to a first coefficient A to obtain a first target voltage V1.

[0064] The second follower circuit is connected to the second power supply, and is configured to scale the second voltage VDD2 output by the second power supply according to a second coefficient B to obtain a second target voltage V2.

[0065] It should be understood that in actual applications, the voltage signals output by different power supplies may have different phases and amplitudes, making direct comparison impossible. Therefore, the voltage signals output by the two power supplies must first be converted to a common-mode signal. To convert the voltage signals output by the first and second power supplies to a common-mode signal, the first coefficient A and the second coefficient B must satisfy the following relationship: A*VDD1(ideal) = B*VDD2(ideal) = VCM. VCM is the common-mode voltage, VDD1(ideal) refers to the voltage value output by the first power supply under ideal conditions, and VDD2(ideal) refers to the voltage value output by the second power supply under ideal conditions. VDD1(ideal) and VDD2(ideal) can be the rated voltages of the first and second power supplies, respectively. Thus, when the first and second power supplies are operating normally, the first target voltage V1 and the second target voltage V2 are common-mode, making them comparable. The specific values ​​of the first coefficient A and the second coefficient B can be pre-set by engineers and implemented through circuit structure.

[0066] Exemplarily, the first follower circuit may include: a plurality of first resistive elements. The plurality of first resistive elements are connected in series between a first power supply and ground. The signal output terminal of the first follower circuit is disposed between two of the first resistive elements to divide the plurality of first resistive elements into two portions. The ratio between the total resistance value of the first target portion and the total resistance value of the plurality of first resistive elements is equal to a first coefficient A; and the first target portion is formed by the first resistive elements located between the output terminal of the first follower circuit and ground.

[0067] For example, Figure 3 Taking the circuit shown as an example, each black block in the figure represents a first resistive element, the total resistance of each first resistive element is equal to (R1+R2+R3), OUT represents the signal output end of the first follower circuit, then the first coefficient A is equal to (R2+R3) / (R1+R2+R3).

[0068] Similarly, the second follower circuit may include: a plurality of second resistive elements. The plurality of second resistive elements are connected in series between a second power supply and ground. The signal output terminal of the second follower circuit is disposed between two of the second resistive elements to divide the plurality of second resistive elements into two portions. The ratio between the total resistance value of the second target portion and the total resistance value of the plurality of second resistive elements is equal to a second coefficient B; and the second target portion is formed by each of the second resistive elements located between the output terminal of the second follower circuit and ground.

[0069] It should be noted that in the embodiments of the present application, the first resistive element and the second resistive element can be implemented by a pure resistor, a MOS tube (such as a PMOS tube, an NMOS tube, etc.), a MOS tube combined with a diode, a capacitor, etc., and this is not limited in the embodiments of the present application. It should be noted that when a MOS tube or a MOS tube combined with a diode is used to implement the first resistive element or the second resistive element, it is necessary to connect the gate of the MOS tube to the corresponding ground voltage VSS or the corresponding power supply voltage according to the conduction characteristics of the MOS tube, for example, VDD1 or VDD2.

[0070] It should be understood that the above circuit implementation structure is only one feasible implementation method provided in the embodiments of the present application, and can realize the design of the first coefficient A or the second coefficient B within the range of 0 to 1, but is not intended to be limiting. For example, in the embodiments of the present application, the design of the first coefficient A greater than 1 can be realized by providing an operational amplifier circuit between the first power supply and the output terminal of the first follower circuit, and the design of the second coefficient B greater than 1 can be realized by providing an operational amplifier circuit between the second power supply and the output terminal of the second follower circuit.

[0071] It should also be noted that in the embodiment of the present application, if the first coefficient A is 1, the first follower circuit can be directly implemented using a signal line, so that the first voltage VDD1 of the first voltage output is directly connected to the first detection circuit, without the need to design corresponding resistive elements for voltage division.

[0072] Similarly, if the second coefficient A is 1, the second follower circuit can also be directly implemented using a signal line, so that the second voltage VDD2 of the second voltage output is directly connected to the first detection circuit without designing corresponding resistive elements for voltage division.

[0073] Still see Figure 2 As shown, in an embodiment of the present application, the first detection circuit is respectively connected to the signal output end of the first follower circuit and the signal output end of the second follower circuit, and is used to output a first signal representing that the voltage difference is abnormal when the absolute value of the difference between the first target voltage V1 and the second target voltage V2 does not meet the preset threshold condition, and output a second signal representing that the voltage difference is normal when the absolute value of the difference between the first target voltage and the second target voltage meets the preset threshold condition.

[0074] In a feasible implementation manner of an embodiment of the present application, the first detection circuit can be specifically used to: when the absolute value of the difference between the first target voltage V1 and the second target voltage V2 is greater than the preset first threshold voltage VREF1, output a first signal indicating that the voltage difference is abnormal; when the absolute value of the difference between the first target voltage and the second target voltage is less than or equal to the first threshold voltage VREF1, output a second signal indicating that the voltage difference is normal.

[0075] For example, the first signal may be a high level signal, and the second signal may be a low level signal. Figures 4a to 4c As shown, Figure 4a shows the voltage signals of VDD1 and VDD2, Figure 4b shows the voltage signals of V1 and V2, Figure 4c The waveform relationship between the signal after the difference between V1 and V2 and the first threshold voltage VREF1 is shown, as well as the waveform of the output signal VO of the first detection circuit at this time. Figure 4c As can be seen, when the sum of V1 and V2 is between -VREF1 and VREF1, a low-level signal is output, indicating that the voltage difference between the first and second power supplies is normal. When the sum of V1 and V2 is outside -VREF1 and VREF1, a high-level signal is output, indicating that the voltage difference between the first and second power supplies is normal. This achieves detection of excessive voltage differences (i.e., if the absolute value of the voltage difference exceeds a certain threshold, it is determined to be abnormal).

[0076] In another feasible implementation manner of the embodiment of the present application, the first detection circuit can be specifically used to: when the absolute value of the difference between the first target voltage V1 and the second target voltage V2 is less than the preset second threshold voltage VREF2, output a first signal indicating that the voltage difference is abnormal; when the absolute value of the difference between the first target voltage and the second target voltage is greater than or equal to the second threshold voltage VREF2, output a second signal indicating that the voltage difference is normal.

[0077] For example, the first signal may be a high level signal, and the second signal may be a low level signal. Figure 4a 、 Figure 4b and Figure 4d As shown, Figure 4a and Figure 4b The contents shown are as described above and will not be repeated here. Figure 4d The waveform relationship between the signal diagram after the difference between V1 and V2 and the second threshold voltage VREF2 is shown, as well as the waveform diagram of the output signal VO of the first detection circuit at this time. Figure 4c As can be seen, when the sum of V1-V2 is outside -VREF2 and VREF2, a low-level signal is output, indicating that the voltage difference between the first and second power supplies is normal. When the sum of V1-V2 is between -VREF2 and VREF2, a high-level signal is output, indicating that the voltage difference between the first and second power supplies is normal. This achieves detection of a voltage difference that is too small (i.e., an abnormal voltage is determined when the absolute value of the voltage difference falls below a certain threshold).

[0078] Optionally, the first detection circuit in this embodiment can be implemented by a signal circuit such as a subtractor and a comparator. For example, the inputs of the subtractor are connected to V1 and V2, respectively, and the output is connected to one input of the comparator. The other input of the comparator is connected to a threshold voltage (i.e., VREF1 or VREF2) to implement a comparison function.

[0079] It should be understood that the above-mentioned unidirectional power supply voltage difference detection circuit can only detect when the absolute value of the voltage difference between V1 and V2 is less than a certain threshold voltage, or can only detect when the absolute value of the voltage difference between V1 and V2 is greater than a certain threshold voltage. When the absolute value of the voltage difference between V1 and V2 is required to be less than a certain threshold voltage and greater than another threshold voltage at the same time, the above-mentioned unidirectional power supply voltage difference detection circuit cannot achieve detection.

[0080] To this end, this embodiment also provides a bidirectional power supply voltage difference detection circuit, such as Figure 5 The bidirectional power supply voltage difference detection circuit includes two unidirectional power supply voltage difference detection circuits of the structure shown above, and a first arbitration circuit.

[0081] The two unidirectional power supply voltage difference detection circuits are connected to the first power supply and the second power supply respectively, and the first threshold voltage and the second threshold voltage are set respectively, and the second threshold voltage is smaller than the first threshold voltage. The following configuration is performed:

[0082] The first detection circuit of the first unidirectional power supply voltage difference detection circuit is used to: output a first signal indicating that the voltage difference is abnormal when the absolute value of the difference between V1 and V2 is greater than a preset first threshold voltage; and output a second signal indicating that the voltage difference is normal when the absolute value of the difference between V1 and V2 is less than or equal to the first threshold voltage.

[0083] The first detection circuit of the second unidirectional power supply voltage difference detection circuit is used to: when the absolute value of the difference between V1 and V2 is less than a preset second threshold voltage, output a first signal indicating that the voltage difference is abnormal; when the absolute value of the difference between V1 and V2 is greater than or equal to the second threshold voltage, output a second signal indicating that the voltage difference is normal.

[0084] The input end of the first arbitration circuit is respectively connected to the output ends of the two unidirectional power supply voltage difference detection circuits, and is used to output the first signal when any one of the unidirectional power supply voltage difference detection circuits outputs the first signal, and output the second signal when both of the unidirectional power supply voltage difference detection circuits output the second signal indicating that the voltage difference is normal.

[0085] For example, when the first signal is a high-level signal and the second signal is a low-level signal, the first arbitration circuit can be implemented by an OR gate circuit. When the first signal is a low-level signal and the second signal is a high-level signal, the first arbitration circuit can be implemented by an AND gate circuit.

[0086] The unidirectional power supply voltage difference detection circuit and the bidirectional power supply voltage difference detection circuit provided in this embodiment can detect whether the voltage difference between the first power supply and the second power supply is normal. It can also detect abnormalities caused by excessively large or small voltage differences between the power supplies in power supply voltage difference-sensitive modules, thereby overcoming the deficiency of the existing POR circuit in that it can only detect whether the voltage of a single power supply is normal.

[0087] Example 2:

[0088] In order to solve the problem that it is currently impossible to detect anomalies caused by excessive or insufficient voltage differences between power supplies, another unidirectional power supply voltage difference detection circuit is provided in the embodiment of the present application. Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of the unidirectional power supply voltage difference detection circuit provided in the second embodiment of the present application, including: a third follower circuit and a second detection circuit.

[0089] The third follower circuit is connected to the third power supply, and is configured to scale the third voltage VDD3 output by the third power supply according to a third coefficient x0 to obtain a third target voltage N0.

[0090] The power supply terminal of the second detection circuit is connected to the fourth power supply, and the signal input terminal is connected to the output terminal of the third follower circuit. The second detection circuit is configured to output a first signal indicating that the voltage difference is abnormal when the third target voltage N0 and the threshold voltage of the second detection circuit do not meet a preset threshold condition, and output a second signal indicating that the voltage difference is normal when the third target voltage N0 and the threshold voltage of the second detection circuit meet a preset threshold condition.

[0091] The threshold voltages of the second detection circuit include a third threshold voltage V+ and a fourth threshold voltage V-. V+ equals x1 times the fourth voltage VDD4, and V- equals x2 times the fourth voltage VDD4, where x1 is greater than x2, and the fourth voltage VDD4 is the voltage output by the fourth power supply. x0, x1, and x2 satisfy the following relationship: x0*VDD3 and [(x1+x2) / 2]*common mode with VDD4. The specific values ​​of x0, x1, and x2 can be pre-set by engineers and implemented through circuit structure.

[0092] Exemplarily, the third follower circuit may include: a plurality of third resistive elements. The plurality of third resistive elements are connected in series between a third power supply and ground. The signal output terminal of the third follower circuit is disposed between two of the third resistive elements, thereby dividing the plurality of third resistive elements into two sections. The ratio between the total resistance value of the third target section and the total resistance value of the plurality of third resistive elements is equal to a third coefficient x0; and the third target section is formed by each of the third resistive elements located between the output terminal of the third follower circuit and ground.

[0093] For example, still Figure 3 Taking the circuit shown as an example, the black blocks in the figure represent the third resistive elements, the total resistance of the third resistive elements is equal to (R1+R2+R3), OUT represents the signal output end of the third follower circuit, then the third coefficient x0 is equal to (R2+R3) / (R1+R2+R3).

[0094] It should be understood that in the embodiment of the present application, a fourth follower circuit may be further provided between the fourth power supply and the power supply terminal of the second detection circuit to scale the fourth voltage VDD4 according to a certain coefficient (referred to as the fourth coefficient).

[0095] Similar to the above, the fourth follower circuit may include: a plurality of fourth resistive elements. The plurality of fourth resistive elements are connected in series between a fourth power supply and ground. The signal output terminal of the fourth follower circuit is disposed between two of the fourth resistive elements, thereby dividing the plurality of fourth resistive elements into two portions. The ratio between the total resistance value of the fourth target portion and the total resistance value of the plurality of fourth resistive elements is equal to a fourth coefficient; and the fourth target portion is formed by each of the fourth resistive elements located between the output terminal of the fourth follower circuit and ground.

[0096] In the embodiment of the present application, the third resistive element or the fourth resistive element may also be implemented using a pure resistor, a MOS transistor (such as a PMOS transistor, an NMOS transistor, etc.), a MOS transistor combined with a diode, a capacitor, etc., and this is not limited in the embodiment of the present application. It should be noted that when a MOS transistor or a MOS transistor combined with a diode is used to implement the first resistive element or the second resistive element, it is necessary to connect the gate of the MOS transistor to the corresponding ground voltage VSS or the corresponding power supply voltage according to the conduction characteristics of the MOS transistor, for example, VDD3 or VDD4.

[0097] It should also be understood that the above circuit implementation structure is only one feasible implementation method provided in the embodiments of the present application, and can realize the design of the third coefficient or the fourth coefficient within the range of 0 to 1, but is not intended to be limiting. For example, in the embodiments of the present application, the design of the third coefficient greater than 1 can also be realized by providing an op amp circuit between the third power supply and the output terminal of the third follower circuit.

[0098] It should be noted that, in one feasible implementation of this embodiment, the second detection circuit can be specifically configured to: output a first signal indicating an abnormal voltage difference when the third target voltage N0 is greater than V+, and output a second signal indicating a normal voltage difference when the third target voltage N0 is less than V-. In this way, once the voltage difference between the third power supply and the fourth power supply exceeds the design range, the first signal indicating an abnormal voltage difference is output, thereby enabling detection of excessive voltage differences. Furthermore, by utilizing V+ and V-, which have a certain difference, the second signal indicating a normal voltage difference is output only when the third target voltage is less than V-. This avoids frequent switching between the first and second signals by the second detection circuit due to glitches in the voltage signal itself, which could lead to misjudgments.

[0099] It should be noted that in another feasible implementation of this embodiment, the second detection circuit can also be configured to: output a first signal indicating an abnormal voltage difference when the third target voltage N0 is less than V-, and output a second signal indicating a normal voltage difference when the third target voltage N0 is greater than V+. In this way, if the voltage difference between the third power supply and the fourth power supply does not fall within the designed range, the first signal indicating an abnormal voltage difference will be output, thereby detecting an excessively small voltage difference. Furthermore, by utilizing V+ and V-, which have a certain difference, the second signal indicating a normal voltage difference is output only when the third target voltage is greater than V+. This can avoid frequent switching between the first and second signals by the second detection circuit due to glitches in the voltage signal itself, which could cause misjudgments.

[0100] In an optional implementation of the embodiment of the present application, Figure 7 As shown, the unidirectional power supply voltage difference detection circuit may further include a buffer. The input end of the buffer is connected to the output end of the second detection circuit, so that the driving performance of the circuit can be enhanced by the buffer to ensure the stability of the first signal or the second signal finally output.

[0101] It should be noted that in the embodiments of the present application, the second detection circuit can be implemented using a Schmitt trigger. Since the characteristics of the Schmitt trigger determine that it has two threshold voltages that follow the input signal from the power supply terminal and can compare the input signal with the two thresholds, the Schmitt trigger can be sampled as the second detection circuit. The circuit implementation structure is simple and easy to deploy on the chip.

[0102] Of course, the embodiment of the present application may also use other circuits or devices to implement the second detection circuit, for example, it may be implemented by a sampling comparator, but this is not a limitation.

[0103] In order to facilitate understanding of the solution of this embodiment, Figure 8 The unidirectional power supply voltage difference detection circuit shown is used as an example for explanation.

[0104] See also Figure 8 As shown, the unidirectional power supply voltage difference detection circuit includes a third follower circuit composed of three PMOS transistors (PM0, PM1 and PM2), a Schmitt trigger I0 and a buffer I1.

[0105] The waveforms of VDD3, VDD4, N0, the output N1 of the Schmitt trigger I0, and the output Y of the buffer I1 are as follows: Figure 9a or Figure 9b As shown:

[0106] When the circuit is working, N0 is x0*VDD3, and the V+ and V- of the Schmitt trigger are x1*VDD4 and x2*VDD4 respectively.

[0107] Assume that the circuit implements overvoltage difference detection, then:

[0108] When the circuit is working, refer to Figure 9a As shown, when VDD3 increases, N0 increases accordingly, or when VDD4 decreases, both V+ and V- of the Schmitt trigger decrease accordingly. When N0 < V-, the final output Y = 0; when the voltage of N0 is higher than V+, it is determined that the voltage difference between VDD4 and VDD3 exceeds the set range, then the output Y jumps to 1, indicating an abnormal voltage difference. Until the voltage difference between VDD4 and VDD3 decreases and makes N0 lower than the V- voltage of the Schmitt trigger, the output Y resumes to 0, indicating that the voltage difference is within the normal range.

[0109] Assume that the circuit implements undervoltage difference detection, then:

[0110] When the circuit is working, refer to Figure 9b As shown, when VDD3 increases, N0 increases accordingly, or when VDD4 decreases, both V+ and V- of the Schmitt trigger decrease accordingly. When N0 > V+, the final output Y = 0; when the voltage of N0 is less than V-, it is determined that the voltage difference between VDD4 and VDD3 is lower than the set range, then the output Y jumps to 1, indicating an abnormal voltage difference. Until the voltage difference between VDD4 and VDD3 decreases and makes N0 higher than the V+ voltage of the Schmitt trigger, the output Y resumes to 0, indicating that the voltage difference is within the normal range.

[0111] It should be understood that the above-mentioned unidirectional power supply voltage difference detection circuit can only implement overvoltage difference detection or undervoltage difference detection. When it is required that the voltage difference between VDD4 and VDD3 is less than a certain threshold voltage and at the same time greater than another threshold voltage, the above-mentioned unidirectional power supply voltage difference detection circuit cannot implement the detection.

[0112] Therefore, this embodiment also provides a bidirectional power supply voltage difference detection circuit, as shown in Figure 10 As shown. The bidirectional power supply voltage difference detection circuit includes two unidirectional power supply voltage difference detection circuits with the structures shown above, and a second arbitration circuit. The two unidirectional power supply voltage difference detection circuits are both connected to the third power supply and the fourth power supply respectively. Among them:

[0113] The second detection circuit of the first unidirectional power supply voltage difference detection circuit is used to output a first signal indicating an abnormal voltage difference when the third target voltage N0 is greater than V+ of the first unidirectional power supply voltage difference detection circuit, and output a second signal indicating a normal voltage difference when the third target voltage is less than V- of the first unidirectional power supply voltage difference detection circuit.

[0114] The second detection circuit of the second unidirectional power supply voltage difference detection circuit is used to output a first signal indicating that the voltage difference is abnormal when the third target voltage N0 is less than V- of the second unidirectional power supply voltage difference detection circuit, and to output a second signal indicating that the voltage difference is normal when the third target voltage N0 is greater than V+ of the second unidirectional power supply voltage difference detection circuit.

[0115] The V+ of the first unidirectional power supply voltage difference detection circuit is greater than the V+ of the second unidirectional power supply voltage difference detection circuit, and the V- of the first unidirectional power supply voltage difference detection circuit is greater than the V- of the second unidirectional power supply voltage difference detection circuit. The V+ and V- of the two unidirectional power supply voltage difference detection circuits are set according to the required voltage difference range.

[0116] Continue to see Figure 10 As shown, the input end of the second arbitration circuit is respectively connected to the output end of the two unidirectional power supply voltage difference detection circuits, and is used to output a first signal when any one of the unidirectional power supply voltage difference detection circuits outputs a first signal indicating that the voltage difference is abnormal, and output a second signal when both of the unidirectional power supply voltage difference detection circuits output a second signal indicating that the voltage difference is normal.

[0117] For example, when the first signal is a high-level signal and the second signal is a low-level signal, the second arbitration circuit can be implemented by an OR gate circuit. When the first signal is a low-level signal and the second signal is a high-level signal, the second arbitration circuit can be implemented by an AND gate circuit.

[0118] This solution can detect anomalies caused by excessive or insufficient voltage differences between power supplies in modules sensitive to power supply voltage differences, overcoming the limitation of existing POR circuits that can only detect the normal voltage of a single power supply. Furthermore, by utilizing the slightly different V+ and V- signals, this implementation avoids misjudgments caused by the second detection circuit frequently switching between the first and second signals due to inherent glitches in the voltage signals.

[0119] Example 3:

[0120] Based on the same inventive concept, the embodiment of the present application further provides a chip on the basis of embodiment one and embodiment two. The chip may include the unidirectional power supply voltage difference detection circuit provided in embodiment one or embodiment two, or may include the bidirectional power supply voltage difference detection circuit provided in embodiment one or embodiment two.

[0121] Exemplarily, the chip provided in the embodiments of the present application can be a computer chip (such as a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), an MCU (Microcontroller Unit), etc.), or a storage chip (such as a DRAM (Dynamic Random Access Memory), an SDRAM (Synchronous Dynamic Random Access Memory), a ROM (Read-Only Memory), etc.), or a communication chip (such as a Bluetooth chip, a WiFi chip, etc.), but is not limited to this.

[0122] Based on the same inventive concept, an embodiment of the present application further provides an electronic component, which includes the aforementioned chip.

[0123] For example, the electronic components provided in the embodiments of the present application may be communication modules, storage modules, data processing modules, and other components that can be produced and sold separately, but this is not intended to be limiting.

[0124] Based on the same inventive concept, an embodiment of the present application further provides an electronic device, which includes the aforementioned chip, or includes the aforementioned electronic component.

[0125] For example, the electronic device provided in the embodiments of the present application may be a terminal (such as a smart phone, a computer, a smart bracelet, etc.), a server, a relay device (such as a router, a switch, etc.), etc., but is not limited thereto.

[0126] In the embodiments provided herein, it should be understood that the disclosed devices may be implemented in other ways, and the device embodiments described above are merely illustrative. Furthermore, the connections shown or discussed may be through some interface, which may be electrical, mechanical, or other forms of connection.

[0127] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0128] As used herein, a plurality refers to two or more than two.

[0129] The above description is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, various modifications and variations of the present application are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A unidirectional power supply voltage difference detection circuit, characterized in that: include: a first follower circuit connected to the first power supply, configured to scale the first voltage output by the first power supply according to a first coefficient to obtain a first target voltage; A second follower circuit is connected to a second power supply and is configured to scale a second voltage output by the second power supply according to a second coefficient to obtain a second target voltage; when the first power supply and the second power supply are normal, the first target voltage and the second target voltage are in common mode; wherein the first coefficient A and the second coefficient B satisfy the following relationship: A*VDD1ideal=B*VDD2ideal=VCM; VCM is the common mode voltage, VDD1ideal is the voltage value output by the first power supply under ideal conditions, and VDD2ideal is the voltage value output by the second power supply under ideal conditions; The first detection circuit is respectively connected to the signal output end of the first follower circuit and the signal output end of the second follower circuit, and is used to output a first signal indicating that the voltage difference is abnormal when the absolute value of the difference between the first target voltage and the second target voltage does not meet the preset threshold condition, and output a second signal indicating that the voltage difference is normal when the absolute value of the difference between the first target voltage and the second target voltage meets the preset threshold condition.

2. The unidirectional power supply voltage difference detection circuit according to claim 1, wherein: The first detection circuit is specifically used for: When the absolute value of the difference between the first target voltage and the second target voltage is greater than a preset first threshold voltage, a first signal indicating that the voltage difference is abnormal is output; when the absolute value of the difference between the first target voltage and the second target voltage is less than or equal to the first threshold voltage, a second signal indicating that the voltage difference is normal is output.

3. The unidirectional power supply voltage difference detection circuit according to claim 1, wherein: The first detection circuit is specifically used for: When the absolute value of the difference between the first target voltage and the second target voltage is less than a preset second threshold voltage, a first signal indicating that the voltage difference is abnormal is output; when the absolute value of the difference between the first target voltage and the second target voltage is greater than or equal to the second threshold voltage, a second signal indicating that the voltage difference is normal is output.

4. The unidirectional power supply voltage difference detection circuit according to any one of claims 1 to 3, wherein: The first follower circuit includes: a plurality of first resistive elements connected in series between the first power source and ground; The signal output terminal of the first follower circuit is arranged between two of the first resistive elements to divide the plurality of first resistive elements into two parts; wherein: a ratio between a total resistance value of the first target portion and a total resistance value of the plurality of first resistive elements is equal to the first coefficient; The first target portion is formed by each of the first resistive elements located between an output terminal of the first follower circuit and ground.

5. The unidirectional power supply voltage difference detection circuit according to any one of claims 1 to 3, wherein: The second follower circuit includes: a plurality of second resistive elements connected in series between the second power supply and ground; The signal output terminal of the second follower circuit is arranged between two of the second resistive elements to divide the plurality of second resistive elements into two parts; wherein: a ratio between a total resistance value of the second target portion and a total resistance value of the plurality of second resistive elements is equal to the second coefficient; The second target portion is formed by each of the second resistive elements located between the output terminal of the second follower circuit and ground.

6. A bidirectional power supply voltage difference detection circuit, characterized in that: include: Two unidirectional power supply voltage difference detection circuits as claimed in claim 1; The first arbitration circuit has an input end connected to the output ends of the two unidirectional power supply voltage difference detection circuits, and is configured to output the first signal when any one of the unidirectional power supply voltage difference detection circuits outputs a first signal indicating an abnormal voltage difference, and output the second signal when both of the unidirectional power supply voltage difference detection circuits output a second signal indicating a normal voltage difference; wherein: The first detection circuit of the first unidirectional power supply voltage difference detection circuit is configured to output the first signal when the absolute value of the difference between the first target voltage and the second target voltage is greater than a preset first threshold voltage, and output the second signal when the absolute value of the difference between the first target voltage and the second target voltage is less than or equal to the first threshold voltage; The first detection circuit of the second unidirectional power supply voltage difference detection circuit is configured to output the first signal when the absolute value of the difference between the first target voltage and the second target voltage is less than a preset second threshold voltage, and output the second signal when the absolute value of the difference between the first target voltage and the second target voltage is greater than or equal to the second threshold voltage; The second threshold voltage is lower than the first threshold voltage.

7. A unidirectional power supply voltage difference detection circuit, characterized in that: include: a third follower circuit, connected to a third power supply, and configured to scale a third voltage output by the third power supply according to a third coefficient to obtain a third target voltage; The second detection circuit has a power supply terminal connected to a fourth power supply, a signal input terminal connected to the output terminal of the third follower circuit, and is configured to output a first signal indicating that the voltage difference is abnormal when a preset threshold condition is not satisfied between the third target voltage and the threshold voltage of the second detection circuit, and output a second signal indicating that the voltage difference is normal when a preset threshold condition is satisfied between the third target voltage and the threshold voltage of the second detection circuit; wherein: The threshold voltage of the second detection circuit includes a third threshold voltage V+ and a fourth threshold voltage V-; the V+ is equal to x1 times the fourth voltage, and the V- is equal to x2 times the fourth voltage; the x1 is greater than the x2, and the fourth voltage is the voltage output by the fourth power supply; the third target voltage and the median voltage of the second detection circuit are common mode, and the median voltage of the second detection circuit is equal to the product of (x1+x2) / 2 and the fourth voltage; wherein the third coefficient x0 and the x1 and the x2 satisfy the following relationship: x0*VDD3ideal=(x1+x2) / 2*VDD4ideal=VCM; the VCM is the common mode voltage, the VDD3ideal is the voltage value output by the third power supply under ideal conditions, and the VDD4ideal is the voltage value output by the fourth power supply under ideal conditions.

8. The unidirectional power supply voltage difference detection circuit according to claim 7, wherein: The second detection circuit is specifically used for: When the third target voltage is greater than the V+, a first signal indicating that the voltage difference is abnormal is output; when the third target voltage is less than the V-, a second signal indicating that the voltage difference is normal is output.

9. The unidirectional power supply voltage difference detection circuit according to claim 7, wherein: The second detection circuit is specifically used for: When the third target voltage is less than the V-, a first signal indicating that the voltage difference is abnormal is output; when the third target voltage is greater than the V+, a second signal indicating that the voltage difference is normal is output.

10. The unidirectional power supply voltage difference detection circuit according to claim 7, wherein: The third follower circuit includes: a plurality of third resistive elements connected in series between the third power source and ground; The signal output terminal of the third follower circuit is arranged between two of the third resistive elements to divide the plurality of third resistive elements into two parts; wherein: a ratio between a total resistance value of the third target portion and a total resistance value of the plurality of third resistive elements is equal to the third coefficient; The third target portion is formed by each of the third resistive elements located between the output terminal of the third follower circuit and ground.

11. The unidirectional power supply voltage difference detection circuit according to any one of claims 7 to 10, wherein: The unidirectional power supply voltage difference detection circuit further includes: The buffer has an input end connected to the output end of the second detection circuit.

12. The unidirectional power supply voltage difference detection circuit according to any one of claims 7 to 10, wherein: The second detection circuit is a Schmitt trigger.

13. The unidirectional power supply voltage difference detection circuit according to claim 11, wherein: The second detection circuit is a Schmitt trigger.

14. A bidirectional power supply voltage difference detection circuit, characterized in that: include: Two unidirectional power supply voltage difference detection circuits as claimed in claim 7; The second arbitration circuit has an input end connected to the output ends of the two unidirectional power supply voltage difference detection circuits, and is configured to output the first signal when any one of the unidirectional power supply voltage difference detection circuits outputs a first signal indicating an abnormal voltage difference, and output the second signal when both of the unidirectional power supply voltage difference detection circuits output a second signal indicating a normal voltage difference; wherein: The second detection circuit of the first unidirectional power supply voltage difference detection circuit is configured to output the first signal when the third target voltage is greater than V+ of the first unidirectional power supply voltage difference detection circuit, and output the second signal when the third target voltage is less than V- of the first unidirectional power supply voltage difference detection circuit; The second detection circuit of the second unidirectional power supply voltage difference detection circuit is configured to output the first signal when the third target voltage is less than V- of the second unidirectional power supply voltage difference detection circuit, and output the second signal when the third target voltage is greater than V+ of the second unidirectional power supply voltage difference detection circuit; The V+ of the first unidirectional power supply voltage difference detection circuit is greater than the V+ of the second unidirectional power supply voltage difference detection circuit, and the V- of the first unidirectional power supply voltage difference detection circuit is greater than the V- of the second unidirectional power supply voltage difference detection circuit.

15. A chip, characterized in that: The method comprises the unidirectional power supply voltage difference detection circuit according to any one of claims 1 to 5 and 7 to 13, or the bidirectional power supply voltage difference detection circuit according to claim 6 or 14.

16. An electronic component, characterized in that: Comprising the chip as claimed in claim 15.

17. An electronic device, characterized in that: comprising the chip according to claim 15, or comprising the electronic component according to claim 16.

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