Integrated vertical emitter structure with controlled wavelength

Abstract

An optoelectronic device (22) includes: (i) a semiconductor substrate (24) having a first level of n-type dopant; (ii) a contact semiconductor layer (25) disposed above the semiconductor substrate (24) and doped with a second level of n-type dopant greater than the first level; (iii) an upper distributed Bragg reflector (DBR) (79) stack disposed above the contact semiconductor layer (25) and including alternating first and second epitaxial semiconductor layers (55) having corresponding first and second refractive indices different from each other in a predetermined wavelength band; (iv) an epitaxial layer group (35, 36) disposed above the upper DBR (79), the epitaxial layer group (35, 36) including one or more III-V semiconductor materials and defining: (a) a quantum well structure (33) and (b) a confinement layer (44); and (v) a lower DBR (78) stack disposed on the epitaxial layer group (35, 36), opposite to the upper DBR (79) and including alternating dielectric and semiconductor layers (52, 54).

Description

Technical Field

[0001] The embodiments described herein relate generally to semiconductor devices, and more specifically to methods and systems for manufacturing and integrating optoelectronic devices. Background Technology

[0002] A vertical-cavity surface-emitting semiconductor laser (VCSEL) is a semiconductor laser in which highly directional laser radiation is emitted from the top or bottom of the laser in a direction perpendicular to the substrate. VCSELs are fabricated as a single laser or an array of lasers, and they are capable of having high emission power. Summary of the Invention

[0003] One embodiment described herein provides an optoelectronic device comprising: (i) a semiconductor substrate doped with a first level of n-type dopant; (ii) a contact semiconductor layer disposed above the semiconductor substrate and doped with a second level of n-type dopant greater than the first level; (iii) an upper distributed Bragg reflector (DBR) stack disposed above the contact semiconductor layer and comprising alternating first and second epitaxial semiconductor layers having corresponding first and second refractive indices different from each other in a predetermined wavelength band; (iv) an epitaxial layer group disposed above the upper DBR, the epitaxial layer group comprising one or more III-V semiconductor materials and defining: (a) a quantum well structure and (b) a confinement layer; and (v) a lower DBR stack disposed on the epitaxial layer group, opposite to the upper DBR, and comprising alternating dielectric and semiconductor layers.

[0004] In some embodiments, the quantum well structure is configured to emit a light beam having a wavelength within the predetermined wavelength band. In other embodiments, at least one of the semiconductor substrate, the contact semiconductor layer, and the epitaxial layer group comprises indium phosphide, and the emitted light beam has a wavelength between 1.2 μm and 2 μm. In other embodiments, at least one of the semiconductor substrate, the contact semiconductor layer, and the epitaxial layer group comprises gallium antimonide, and the emitted light beam has a wavelength greater than 2 μm.

[0005] In one embodiment, at least one of (i) the semiconductor substrate, (ii) the contact semiconductor layer, and (iii) the epitaxial layer group comprises gallium arsenide, and the emitted light beam has a wavelength between 0.63 μm and 1.1 μm. In another embodiment, at least one of (i) the semiconductor substrate, (ii) the contact semiconductor layer, and (iii) the epitaxial layer group comprises gallium nitride, and the emitted light beam has a wavelength less than 0.6 μm. In yet another embodiment, the device includes an electrode coupled to apply an excitation current to a quantum well structure.

[0006] In some embodiments, the electrode includes a first electrode and a second electrode, and the device further includes (i) a first bump electrically coupled between the first electrode and the contact semiconductor layer, and (ii) a second bump coupled between the second electrode and an additional contact semiconductor layer, and the first and second bumps are configured to conduct excitation current applied to the quantum well structure. In other embodiments, in addition to alternating dielectric and semiconductor layers, the lower DBR includes alternating third and fourth epitaxial semiconductor layers having corresponding third and fourth refractive indices that are different from each other in the predetermined wavelength band.

[0007] In one embodiment, the quantum well structure is configured to detect light of a predetermined wavelength. In another embodiment, the device includes electrodes coupled to receive signals from the quantum well structure indicative of the detected light beam.

[0008] Another embodiment described herein provides a method for manufacturing an optoelectronic device, the method comprising disposing a contact semiconductor layer over a semiconductor substrate doped with a first level of n-type dopant, and doping the contact semiconductor layer with a second level of n-type dopant greater than the first level. An upper distributed Bragg reflector (DBR) stack is disposed over the contact semiconductor layer. The upper DBR includes alternating first and second epitaxial semiconductor layers having corresponding first and second refractive indices different from each other in a predetermined wavelength band. An epitaxial layer group is disposed over the upper DBR, the epitaxial layer group including one or more group III-V semiconductor materials defining a quantum well structure and a confinement layer. A lower DBR stack, comprising alternating dielectric and semiconductor layers, is disposed over the epitaxial layer group, opposite to the upper DBR.

[0009] Another embodiment described herein provides a method comprising operating an optoelectronic device. The optoelectronic device includes: (i) a semiconductor substrate doped with a first level of n-type dopant; (ii) a contact semiconductor layer disposed above the semiconductor substrate and doped with a second level of n-type dopant greater than the first level; (iii) an upper distributed Bragg reflector (DBR) stack disposed above the contact semiconductor layer and comprising alternating first and second epitaxial semiconductor layers having corresponding first and second refractive indices different from each other in a predetermined wavelength band; (iv) an epitaxial layer group disposed above the upper DBR, the epitaxial layer group comprising one or more III-V semiconductor materials and defining: (a) a quantum well structure and (b) a confinement layer; and (v) a lower DBR stack disposed above the epitaxial layer group, opposite the upper DBR, and comprising alternating dielectric and semiconductor layers. An excitation current is applied to a quantum well structure, which is used to emit a light beam with a wavelength in a predetermined wavelength band.

[0010] These and other embodiments of the invention will be more fully understood from the following detailed description of embodiments of the invention taken in conjunction with the accompanying drawings, in which: Attached Figure Description

[0011] Figure 1 This is a schematic cross-sectional view of an integrated optoelectronic module (IOM) according to one embodiment described herein; and

[0012] Figures 2 to 6 This is a schematic cross-sectional view of the process sequence for manufacturing IOM according to one embodiment described herein. Detailed Implementation

[0013] Overview

[0014] Vertical-cavity surface-emitting semiconductor lasers (VCSELs) based on III-V compound semiconductor materials are configured to emit beams within a predetermined wavelength (WL) range. For example, indium phosphide (InP)-based VCSELs are configured to emit beams within a WL range between 1.2 μm and 2 μm. The InP chip carrying the VCSEL can be bonded to a carrier substrate (such as a silicon (Si) substrate) to utilize complementary metal-oxide-semiconductor (CMOS) control circuitry on a Si wafer.

[0015] In this example, the Si wafer includes a backplane driver with an electrode array, also referred to herein as an anode and a cathode, which are configured to provide excitation current to selectively operate one or more InP VCSELs of the bonded InP chip.

[0016] In the context of this specification and in the claims, the term "substrate" may refer to a whole wafer or a portion thereof, such as in a semiconductor die or chip.

[0017] In some implementations, InP-based VCSELs can be fabricated by depositing an epitaxial layer stack on an n-type InP substrate using the following sequential process. In a first step, a heavily doped n-type contact InP layer is disposed on the InP substrate. In a second step, an upper reflector, referred herein as an upper distributed Bragg reflector (DBR) stack, is disposed on the contact InP layer. This upper DBR comprises alternating first and second n-type epitaxial semiconductor layers (e.g., alternating AlGaInAs and InP layers with a gradient layer in between), also referred herein as an nDBR. The first and second layers of the nDBR have corresponding first and second refractive indices that are different from each other in a predetermined wavelength band. In this configuration, the upper reflector is configured to have a reflectivity exceeding 99% in the aforementioned wavelength range (WL).

[0018] In the third step, an epitaxial group III-V semiconductor layer group is disposed on the upper DBR, defining a quantum well (QW) structure, and a lightly doped p-type semiconductor layer is deposited on the QW. This QW structure (including the quantum well and the blocking layer) is configured to emit a beam of light in a predetermined wavelength band. Furthermore, electrical and optical confinement is provided. The electrical and optical confinement, also referred to herein as the confinement layer (or multilayer structure), can be achieved, for example, by buried tunnel junction (BTJ) or lateral oxidation, ion implantation, or other techniques known in the art. Taking BTJ as an example, a semiconductor layer serving as a tunnel junction (TJ) is deposited on a p-type doped semiconductor layer.

[0019] In some implementations, the TJ may comprise a thin, heavily p-type doped semiconductor layer and a heavily n-type doped semiconductor layer, thereby forming the TJ and providing low resistance. Low optical loss can be achieved by placing the TJ at a standing wave node where the light intensity is close to zero. A BTJ is formed by patterning and selectively etching away the TJ to reach the p-type semiconductor layer on top, and then depositing an n-type semiconductor layer on the TJ. The BTJ achieves electrical and optical confinement. Under a forward electrical bias on the BTJ, current will flow only within the BTJ aperture and is blocked outside the aperture due to the reverse-biased pn junction, thus achieving electrical confinement. Due to the effective optical refractive index contrast inside and outside the BTJ aperture, the light field is laterally confined within the BTJ aperture.

[0020] Subsequently, a lower reflector, also referred to herein as a lower DBR stack, is disposed on the epitaxial layer group. Note that the upper DBR is disposed on the first side of the epitaxial III-V semiconductor layer group, while the lower DBR is disposed on its second side opposite to the first side.

[0021] In some embodiments, the lower DBR comprises repeating pairs (e.g., about 5 or 6 pairs) of alternating high-refractive-index and low-refractive-index layers. In this example, the alternating layers comprise a dielectric material (e.g., silicon oxide and amorphous silicon), such that the structure is referred to herein as a dielectric DBR (DD). In this configuration, the DD is configured to have a reflectivity exceeding 99.9% over the aforementioned WL range.

[0022] In other embodiments, the lower DBR may comprise an nDBR (having several pairs of alternating n-type epitaxial semiconductor layers) disposed on an epitaxial group III-V semiconductor layer group, and several pairs of DD layers disposed on the nDBR. This combination of dielectric DBR and nDBR in a single reflector is also referred to herein as a hybrid reflector. In some cases, the thickness of the alternating DD layers (e.g., about a quarter of the local wavelength of light emitted by an InP VCSEL) may not be precise enough. In such cases, the combination of DD and nDBR in a hybrid reflector can improve the uniformity of the WL reflected from the lower reflector while maintaining over 99% reflection within the aforementioned WL range of an InP-based VCSEL.

[0023] Good thermal conductivity between the VCSEL and the substrate is important for dissipating the heat generated by the VCSEL excitation current. Thermal conductivity can be influenced by the choice of materials and thicknesses of the other layers of the upper and lower reflectors at the VCSEL / substrate interface.

[0024] Optimizing the performance of InP-based VCSELs requires both high electrical and optical confinement, as well as good thermal conductivity from the VCSEL to the silicon and InP substrate. In some embodiments, the InP substrate is used as a thermal mass to reduce the temperature at the thermal junction (TJ) or thermal junction (BTJ) of the QW structure and the VCSEL. The embodiments of the present invention described herein address these requirements to enable the fabrication of InP-based VCSELs with high output power and high efficiency, as well as good optical mode confinement.

[0025] In some embodiments, metal layers (e.g., traces and vias) are deposited and patterned onto and through the epitaxial layer to apply an excitation current to the quantum well structure. In some embodiments, to enhance heat removal from the active region, one or both of the metal layers include a ring (also referred to herein as a mesa) positioned very close to and surrounding the quantum well. Metal vias pass through one or both of the DBR stacks to connect the metal ring at the inner side of the DBR stack to electrical contacts on the outer side of the DBR stack. As described above, the chip including the VCSEL is bonded to a Si wafer, and a passivation layer is disposed therebetween to improve the mechanical, electrical, and environmental (e.g., moisture) stability of the VCSEL-based integrated optoelectronic module.

[0026] In other embodiments, instead of manufacturing VCSELs, resonant cavity silicon-based photodetectors (RCPD-on-Si) can be manufactured using the above-described production method with necessary modifications, for example, by reducing the number of nDBR pairs in the upper reflector.

[0027] Although the disclosed embodiments use an InP substrate and an InP-based epitaxial stack, other III-V semiconductor materials and / or compounds, such as, but not limited to, gallium arsenide (GaAs), gallium antimony (GaSb), gallium nitride (GaN), and indium arsenide (InAs), may alternatively be used at least for the substrate and epitaxial stack. In some embodiments, GaAs-based, GaSb-based, InAs-based, and GaN-based VCSELs can be used to generate beams with a wider spectral range. For example, a GaSb-based VCSEL is configured to emit a wavelength range (WL) of about 2 μm or longer, while a GaN-based VCSEL is configured to emit a WL of about 0.6 μm or shorter.

[0028] System Description

[0029] Figure 1 This is a schematic cross-sectional view of an integrated optoelectronic module (IOM) referred to herein as module 11 according to one embodiment described herein. In some embodiments, module 11 includes a light source (in this example, a vertical-cavity surface-emitting semiconductor laser (VCSEL) device (VD) 22) and a backplane driver (in this example, a backplane silicon driver (BSD) 12).

[0030] In some embodiments, the BSD 12 includes a plurality of electrodes, referred to herein as anode 16 and cathode 18, fabricated on a silicon wafer 14 (or any other suitable type of substrate) using any suitable complementary metal-oxide-semiconductor (CMOS) process. In some embodiments, pairs of anodes 16 and cathodes 18 are arranged in an array spanning the BSD 12.

[0031] In some embodiments, the BSD 12 includes a trace 105 configured to conduct current between a power source and various components of the BSD 12, such as anode 16 and cathode 18. In such embodiments, based on the wiring of the trace 105, the BSD 12 is configured to conduct current to or from a selected pair of anodes 16 and cathodes 18.

[0032] In some embodiments, BSD 12 is configured to power VD 22 for emitting a beam 32 having a predetermined wavelength (WL) from VD 22 of module 11, which will be described in detail below. In the context of this specification and in the claims, the terms “optical radiation,” “beam,” “light,” and “light beam” are used interchangeably and generally refer to any and all visible, infrared, and ultraviolet radiation.

[0033] Indium phosphide-based VCSELs integrated on silicon for emission in the WL range between approximately 1.2 μm and 2 μm.

[0034] In some embodiments, VD 22 includes an epitaxial layer group comprising one or more III-V semiconductor materials and defining (i) one or more light-emitting layer stacks, which include quantum well (QW) structures as described in detail below, and (ii) one or more confinement layers.

[0035] In some embodiments, VD 22 includes a multilayer structure comprising an active region (AR) 33 (described in detail in illustration 30 below), a lightly p-type doped semiconductor layer (e.g., indium phosphide (InP), indium gallium arsenide (InGaAsP), or aluminum indium gallium arsenide (AlInGaAs), aluminum gallium antimony arsenide (AlGaAsSb)), referred to herein as layer 45), and a buried tunnel junction (TJ) 44 (described in detail in illustration 36 below).

[0036] Advanced VCSELs, such as VD 22, employ methods and structures to confine current and optical radiation within the VD 22. Current confinement introduces charge carriers into a tightly defined volume within the central region of the multilayer quantum well (QW) stack of the VD 22, while optical confinement controls the spatial pattern of optical radiation generated by the VD 22. The QW stack is described in detail in Figure 30 below. One method for confining current in an InP-based VCSEL involves implanting ions in a region around the desired current path. Another method uses a BTJ, which comprises a TJ covered with a laterally etched epitaxially regrown n-type doped semiconductor layer for both optical and electrical confinement. In this example, the confinement structure is implemented in the VD 22 using the tunnel junction (TJ) structure described herein.

[0037] Referring now to illustration 36. In some embodiments, TJ 44 may comprise a tunnel junction (TJ) of homogeneous or heterogeneous type. Figure 1 In the example, TJ 44 comprises a heterogeneous type TJ comprising a stack of two heavily doped semiconductor layers. For example, (i) a layer 48 comprising aluminum gallium antimony arsenide (AlGaAsSb) or any other suitable material or compound heavily doped with p-type ions, and (ii) a layer 46 comprising indium gallium gallium phosphide (InGaAsP) or aluminum indium gallium arsenide (AlInGaAs) heavily doped with n-type ions, each of which is heavily doped with n-type ions.

[0038] In other embodiments, instead of TJ 44, the confinement structure in VD 22 can be achieved by forming oxide pores filled with layers formed by an atomic layer deposition (ALD) process, or by doping the semiconductor layer using a suitable ion implantation process.

[0039] In the context of the embodiments described herein and in the claims, the term "heavily doped" refers to doping at approximately 1 × 10⁻⁶. 19 cm -3 Or any other suitable doping level or higher within the range of n-type or p-type carrier concentration, where the term "doping" refers to a concentration of approximately 10-1... 15 cm -3 With 10 19 cm -3 Or any other suitable range of n-type or p-type carrier concentrations. Note that (a) the doping levels can be substantially different for different materials receiving the dopant, and (b) based on the specific optical and / or electrical properties (e.g., conductivity, mobility, refractive index) of the material receiving the dopant.

[0040] In the context of the embodiments described herein and in the claims, the term “about” or “approximately” used for any numerical value or range indicates a suitable dimensional tolerance that allows a portion or assembly of parts to be used for its intended purpose as described herein. More specifically, “about” or “approximately” may refer to a range of values ​​within ±20% of the stated value; for example, “about 90%” may refer to a numerical range of 71% to 99%.

[0041] Referring now to illustration 30, which shows a single junction of AR 33. In some embodiments, each junction comprises multiple pairs (e.g., between 3 and 7 pairs) of alternating quantum well (QW) layers 36 and barrier layers 35. In some embodiments, the QW layers 36 comprise any suitable material, such as, but not limited to, In... x Ga 1-x As, In x Al y Ga 1-x-y As, In x Ga1-x As y P 1-y and / or In x Ga 1- x As y N 1-y In some embodiments, barrier layers 35 are alternately located between adjacent QW layers 36, as shown in Illustration 30. Each barrier layer 35 may include InP, Al x Ga 1-x As y Sb 1-y In a Al 1-a As, In a Al b Ga 1-a-b As, In a Ga 1-a As b P 1-b and / or In a Ga 1-a As b N 1-b Or any other suitable type of barrier material. In some embodiments, the typical thickness of each QW layer 36 and barrier layer 35 is in the nanometer range (e.g., between 1 nm and 15 nm).

[0042] Now return to the reference Figure 1 A general view. When module 11 is powered, current (also referred to herein as excitation current) is conducted between BSD 12 and the light-emitting layer stack (e.g., AR 33, layer 45, and TJ 44) via conductive paths (referred to herein as current paths 62 and 64, described in detail below). Now returning to reference illustration 30. In some embodiments, the excitation current applied to the QW layer of AR 33 causes recombination 39 between electrons 37 and holes 38, resulting in the emission of beam 32.

[0043] In other embodiments, AR 33 may include a plurality of nodes having TJ 44 arranged between adjacent nodes of AR 33, as described below. Figure 2 This configuration is shown and described in detail.

[0044] Now return to the reference Figure 1 The overall view is shown. In some embodiments, VD 22 includes a distributed Bragg reflector (DBR) stack, referred to herein as the lower DBR 78, located between TJ 44 and one or more metal layers 88. The lower DBR 78 is configured to reflect the beam 32 emitted from AR 33 to lens 28 and / or any other suitable optical components to guide the beam 32 to a target scene outside VD 22.

[0045] In some implementations, the lower DBR 78 comprises one or more types of DBR stacks, referred herein as (i) a dielectric DBR (DD) 66 and (ii) a semiconductor epitaxial n-type DBR (nDBR). In this example, layer 31 (and possibly layer 34) is also referred herein as an nDBR. Implementations related to nDBRs are described in detail below.

[0046] In some implementations, DD 66 comprises repeating pairs of high and low refractive index materials, wherein the thickness of each layer is one-quarter of the local wavelength of the light emitted by AR 33 (i.e., the free space wavelength divided by the refractive index of the material at that wavelength).

[0047] Referring now to illustration 50, the structure of DD 66 is shown. In some embodiments, DD 66 comprises a stack of multiple pairs (e.g., about 5 or 6 pairs) of alternating layers 52 and 54 having substantially different refractive indices from each other. For example, DD 66 may comprise pairs of amorphous silicon and silicon dioxide (a-Si / SiO2), amorphous silicon and aluminum nitride (a-Si / AlN), amorphous silicon and aluminum oxide (a-Si / Al2O3), or any other suitable layer pairs.

[0048] In some implementations, the differences in geometry and refractive index between layers 52 and 54 result in a high refractive index contrast (DBR). In such implementations, the stack of DD 66 is designed to have a reflectivity exceeding 99.9% under the WL of beam 32.

[0049] For example, the dielectric DBR is described in detail in PCT patent application PCT / US2020 / 18475, the disclosure of which is incorporated herein by reference.

[0050] Now return to the reference Figure 1 An overall view. In some embodiments, VD 22 includes an upper DBR 79 having epitaxially grown alternating high-refractive-index and low-refractive-index n-type layers (not shown) to define an epitaxial n-type DBR (referred to herein as ED55). In such embodiments, ED 55 can have a high refractive index contrast (e.g., Δn > 0.35) by selecting a combination of materials and / or compounds for use in the nDBR, some nDBR material combinations may be, but are not limited to:

[0051] (a)Al x Ga 1-x As y Sb 1-y (where x < 0.3), and

[0052] Al x Ga 1-x Asy Sb 1-y (where x > 0.8); or

[0053] (b) InGaAs and indium aluminum arsenide (InAlAs); or

[0054] (c) Indium gallium arsenide (AlGaInAs) and indium phosphide (InP).

[0055] In other embodiments, the aforementioned nDBR can be obtained by selecting compounds with direct band gaps for the low-refractive-index and high-refractive-index layers and the graded layer, thereby defining a so-called direct band gap nDBR. In such embodiments, ED 55 may include combinations of materials and / or compounds, such as:

[0056] Al x Ga 1-x As y Sb 1-y (where x < 0.3) is used as a high refractive index layer, InP is used as a low refractive index layer, and a direct bandgap graded layer (e.g., AlInAs, AlInAsSb, AlInAsP, GaPSb, GaAsSb, AlGaPSb) is used to obtain a high optical refractive index contrast with improved resistivity, for example, with a lower resistivity compared to the combinations of (a), (b) and (c) above.

[0057] The inventors believe that the fundamental cause of the increased resistance is electron scattering between the valleys of the conductive bands in the continuous layers of the nDBR lattice. Electron scattering can be mitigated by selecting different compositions of the semiconductor compounds that constitute all the layers of the nDBR, resulting in compounds with direct band gaps.

[0058] In the context of this specification and in the claims, a "direct bandgap" semiconductor material is a semiconductor material in which the Γ-valley in the energy-momentum (Ek) curve is the point of lowest energy in the conduction band (below the X-valley and L-valley). In contrast, an "indirect bandgap" semiconductor material is a material in which the Γ-valley in the Ek curve is not the point of lowest energy in the conduction band (but has an energy higher than the X-valley and / or L-valley).

[0059] For example, various types of nDBRs and direct bandgap nDBRs are described in detail in U.S. Provisional Application 62 / 892,613, filed August 28, 2019, and U.S. Provisional Application 62 / 958,732, filed January 9, 2020, the disclosures of which are incorporated herein by reference in their entirety.

[0060] In some embodiments, by using a combination of the compounds described above and / or direct bandgap nDBRs, the ED 55 of the upper DBR79 can achieve the aforementioned refractive index contrast of Δn > 0.35. In such embodiments, an nDBR with fewer than 25 pairs of layers can achieve a reflectivity of over 99% at the WL of beam 32.

[0061] Typically, III-V semiconductor alloys have relatively low thermal conductivity; for example, InP has a thermal conductivity of approximately 0.68 W / cm². -1 ℃ -1 Furthermore, the thermal conductivity of the aforementioned nDBR structure decreases with the thickness of such compounds. InP-based VCSELs known in the art (also referred to herein as conventional InP-based VCSELs) use more than 45 pairs of nDBR layers as end mirror reflectors to achieve a reflectivity exceeding approximately 99.99% at the WL of beam 32. This large number of nDBR layer pairs limits effective heat dissipation from the active region to the heat sink (not shown) of module 11. In the example of VD 22, the inventors can use nDBR for a transmission side mirror, which requires the transmission side mirror to have a reflectivity exceeding 99% at the WL of beam 32 (less than the required reflectivity of over 99.9% at the same WL, which is the end mirror reflector requirement). In this configuration, nDBR with fewer than 25 pairs of layers is sufficient to meet the reflectivity requirements of the transmission side mirror. Moreover, in this configuration, the thermal resistance of the nDBR of this disclosure is substantially less than that of conventional InP-based VCSELs, and is therefore referred to herein as "acceptable thermal resistance".

[0062] In some embodiments, the lower DBR 78 may comprise only DD 66. Alternatively, the lower DBR 78 may comprise a hybrid reflector having a combination of DD 66 and several pairs of nDBR layers. In this example, layer 31 comprises an nDBR layer. Alternatively, the hybrid reflector may comprise any suitable combination of DD 66 with one or more n-type semiconductor layers of any suitable kind.

[0063] In some cases, insufficient thickness uniformity of layers 52 and 54 may affect (e.g., reduce) the WL uniformity of the beam 32 reflected from DD 66. In some embodiments, the above-described combination of DD 66 and nDBR can compensate for insufficient thickness uniformity of layers 52 and 54 in order to improve the WL uniformity of beam 32.

[0064] In some embodiments, VD 22 includes a semi-insulating (SI) substrate (referred to herein as substrate 24) typically made of a III-V compound semiconductor material and a contact layer (referred herein as layer 25 deposited on substrate 24). In some embodiments, substrate 24 provides a heat storage medium for reducing the temperature in TJ 44, AR 33, and the other layers of VD 22. Substrate 24 is also configured to reduce the absorption of charge carriers in VD 22, and thus improve the efficiency of module 11. In other words, by using the same input power and reducing the number of absorbed charge carriers, VD 22 is configured to (a) emit a beam 32 of greater intensity and (b) reduce the heat level induced during operation of module 11.

[0065] In some implementations, the VCSEL wavelength can be determined based on (i) the layers and structure of AR 33, and (ii) the cavity resonant wavelength (WL) as described herein. The composition, thickness, and number of layers 35 and 36 of AR 33 determine the wavelength range from which beam 32 can be emitted from AR 33 via electron-hole recombination. The cavity resonant wavelength is determined based on the refractive index, absorption loss, and thickness of the aforementioned layers of VD 22 (e.g., ED 55, AR 33, layer 45, TJ44, layer 31, layer 34, DD 66, substrate 24, layer 25, and even metal layer 89). This cavity resonant wavelength must be within the spectrum emitted from AR 33 to achieve VCSEL operation. Once this requirement is met, the WL emitted from the VCSEL is determined by the cavity resonant wavelength (WL).

[0066] For VCSELs grown on InP substrates (referred to as InP-based VCSELs), the emission wavelength range (WL) is in the range of approximately 1.2 μm to 2 μm.

[0067] In some embodiments, module 11 includes bumps 20 (e.g., metal bumps, solder bumps, or any other suitable type of bumps) formed on the electrode pair (also referred to herein as anode 16 and cathode 18) using any suitable process. Module 11 also includes layers 88 and 89, both of which typically comprise metals such as aluminum or copper or suitable alloys thereof or any other suitable substance or alloy.

[0068] In some implementations, InP wafers (see below) Figure 6 (Shown and described) includes multiple dies fabricated on substrate 24. After fabrication of the dies, the InP wafer is diced and separated into individual InP chips, each InP chip including one or more VD 22s. The following... Figures 2 to 6 The process used to manufacture VD 22 is described in detail.

[0069] In some implementations, after manufacturing the VD 22, each InP chip having one or more VD 22s is placed on the BSD 12. For example... Figure 1 As shown, each VD 22 is bonded to a pair of bumps 20 formed on a corresponding pair of anodes 16 and cathodes 18, thereby selectively powering each VD 22 by applying the aforementioned power to the selected pair of anodes 16 and cathodes 18 of the BSD 12. This configuration enables a tight package of the optical emitter array (e.g., VCSEL device 22) and allows for individual addressing and operation of each VCSEL emitter.

[0070] In some implementations, the InP-based VCSEL array may have several optional configurations, such as, but not limited to: (i) each VCSEL emitter has its own anode 16 and all VCSEL emitters share one or more common cathodes 18, which is referred to herein as a common cathode configuration; (ii) similarly, the array may have a common anode configuration; and (iii) each emitter has a pair of corresponding anodes 16 and cathodes 18.

[0071] In some embodiments, the excitation current is conducted in current path 64 between the anode 16 and the aforementioned light-emitting layer stack (e.g., AR 33, layer 45, and TJ 44) via bump 20 and layers 88, 89, 31, and 34. This excitation current is also conducted in current path 62 between the cathode 18 and the light-emitting layer stack via bump 20 and layers 88 and 25. Note that layer 25 has sufficiently high conductivity to conduct current path 62 due to its high doping level.

[0072] In some implementations, to enhance heat dissipation from the light-emitting layer stack, some metal layers such as contact 91 include a ring disposed near the QW structure (below). Figure 6 (This is also shown as a tabletop feature). Figure 1 In the example, layer 89 passes through one or both of the DBR stacks (e.g., DD 66) to connect a metal ring on the inside of the DBR stack to an electrical contact on the outside of the DBR stack.

[0073] In some implementations, layers 88 and 89 may form an in-cavity contact with the electroplated metal through-hole to serve as a heat sink for dissipating heat generated in the light-emitting layer stack.

[0074] In some embodiments, VD 22 includes an anti-reflection (AR) layer 26 formed on substrate 24 (e.g., after a thinning process of substrate 24). AR layer 26 is configured to prevent light beam 32 from being reflected back to VD 22 from the interface between the surface of substrate 24 and air. Such optical reflections back into the cavity of VD 22 can undesirably interfere with the specified gain and other performance of VD 22, and can undesirably increase heat within VD 22 and module 11.

[0075] In some embodiments, VD 22 also includes filler 60, also referred to herein as “underfill adhesive”, which is typically made of a suitable polymer and configured to provide module 11 with improved mechanical stability, heat dissipation, and electrical insulation between some adjacent conductive parts.

[0076] In some embodiments, VD 22 includes a passivation layer 77, which typically comprises silicon nitride (SiN) x The compound or other compounds known in the art are configured to physically and electrically isolate adjacent layers. For example, to prevent unwanted diffusion and / or electrical leakage between adjacent layers.

[0077] In some embodiments, in addition to or in place of lens 28, VD 22 may have other optical elements, such as microlenses or diffractive optical elements (DOEs), which may be integrated with substrate 24 (e.g., on substrate 24) to achieve beam shaping and / or steering and / or any other manipulation of beam 32.

[0078] The wavelength emitted from a predetermined VCSEL structure can be controlled by selecting different materials.

[0079] In some implementations, the structure of the VD 22 described above can be used to fabricate various types of VCSELs such as BSD12, which are integrated on silicon and configured to emit different corresponding wavelengths.

[0080] Gallium antimonide-based VCSEL integrated on silicon for emitting wavelengths greater than 2 μm

[0081] In some embodiments, the structure of VD 22 can be used to fabricate a gallium antimonide (GaSb)-based VCSEL configured to emit a beam 32 at a WL greater than about 2 μm. In such embodiments, the substrate 24 and layer 25 may comprise a semi-insulating or n-type doped GaSb substrate, and the heavily doped GaSb layer 25 is configured to form an ohmic contact with the metal layer 96 to conduct current with low resistance.

[0082] In some embodiments, ED 55 may include a combination of nDBR materials and / or compounds, such as:

[0083] (a) GaSb and AlAsSb, or InGaAsSb and AlAsSb, or GaSb and AlPSb, or other suitable combinations of materials and / or compounds, as respective high-refractive-index layers and low-refractive-index layers and graded layers therebetween, or

[0084] (b) Direct bandgap nDBRs such as InGaAsSb and AlGaAsSb, as high-refractive-index layers and low-refractive-index layers, as well as direct bandgap graded layers. Compared to combination (a), this configuration can have a lower resistivity. In such embodiments, nDBRs with fewer than 25 pairs of layers can achieve reflectivity exceeding 99% and acceptable thermal resistance at the WL of beam 32, as described above for InP-based VCSELs.

[0085] In some implementations, the TJ 44 of the GaSb-based VCSEL can have a heterostructure comprising heavily doped p-type GaSb in layer 48 and heavily doped n-type InAsSb in layer 46. In some implementations, AR 33 can comprise a single junction or multiple junctions (with TJ 44 between each pair of adjacent junctions, as follows). Figure 2 (as described in the text). Each junction may include between approximately 3 and 7 pairs of layers 35 and 36. For example, each layer 36 may include InGaAsSbQW configured to emit a WL greater than approximately 2 μm, and each blocking layer 35 may include AlGaAsSb.

[0086] Gallium arsenide-based VCSELs integrated on silicon for emission in the WL range between approximately 0.63 μm and 1.1 μm.

[0087] In some embodiments, the structure of VD 22 can be used to fabricate a gallium arsenide (GaAs)-based VCSEL configured to emit a beam 32 in the WL range between approximately 0.63 μm and 1.1 μm. In such embodiments, substrate 24 may comprise an n-type doped or semi-insulating GaAs substrate. Layer 25 may comprise heavily n-type doped GaAs and is configured to form an ohmic contact with metal layer 96 to conduct current with low resistance.

[0088] In an alternative embodiment, by using a diluted nitride (DN) QW layer (e.g., InGaAsN and InGaAsNSb) in AR 33, the WL of the beam 32 emitted from VD 22 can be extended to a WL range between approximately 1 μm and 1.6 μm.

[0089] In some embodiments, ED 55 can achieve the aforementioned refractive index contrast (e.g., Δn > 0.35) by selecting a combination of materials and / or compounds of nDBR, for example:

[0090] (a)Al x Ga 1-xAs (where 0 ≤ x < 0.3) and Al x Ga 1-x As (where 0.7 ≤ x ≤ 1) serves as the corresponding high-refractive-index layer and low-refractive-index layer, as well as the gradient layer between each high-refractive-index layer and low-refractive-index layer; or

[0091] (b) Direct bandgap nDBR, for example:

[0092] GaAs and Al x Ga y In 1-x-y P (where x < 0.35) serves as a direct bandgap layer with correspondingly high and low refractive indices, as well as direct bandgap graded layers, such as InGaP and In x Ga 1-x As y P 1-y Therefore, it has a lower resistivity compared to (a).

[0093] In such implementations, an nDBR with fewer than 25 pairs of layers can achieve a reflectivity of over 99% and acceptable thermal resistance at the aforementioned WL of beam 32, as described above for InP-based VCSELs.

[0094] In some embodiments, the GaAs-based VCSEL DD 66 may comprise pairs of amorphous silicon and silicon dioxide (a-Si / SiO2), amorphous silicon and aluminum nitride (a-Si / AlN), amorphous silicon and aluminum oxide (a-Si / Al2O3), amorphous silicon and beryllium oxide (a-Si / BeO), or any other suitable layer pairs. In such embodiments, the stack of DD 66 is designed to have about 5 or 6 pairs of the aforementioned layers. In these configurations, DD 66 is configured to achieve a reflectivity exceeding 99.9% in the WL range of the beam 32, between about 0.9 μm and 1.6 μm.

[0095] When a GaAs-based VCSEL is designed to emit a wavelength range (WL) between approximately 0.63 μm and 0.9 μm, the amorphous silicon layer in DD 66 may cause high absorption of the beam 32, thereby undesirably reducing the reflectivity of DD 66. In some embodiments, DD 66, a GaAs-based VCSEL designed to emit a WL range between approximately 0.63 μm and 0.9 μm, may have paired titanium oxide (TiO2) and silicon dioxide (SiO2) layers or any other suitable compound. In such embodiments, DD 66 may comprise ten or more pairs of these layers to achieve a reflectivity exceeding 99.9% in the WL range of the beam 32 between approximately 0.63 μm and 0.9 μm.

[0096] In some implementations, TJ 44 may include a homogeneous or heterogeneous tunnel junction. Examples of heterogeneous TJ 44 may include layer 46 using heavily doped n-type InGaAsN and layer 48 using heavily doped p-type InGaAs.

[0097] In some implementations, the QW structure of AR 33 may include a single junction or multiple junctions (with TJ44 between each pair of adjacent junctions). Each junction may include between about 3 and 7 pairs of layers 35 and 36 and is configured to emit a beam 32 having any of the aforementioned WL ranges. For example, each layer 36 may include a suitable type of QW layer, such as, but not limited to, GaAs, In... x Ga 1-x As, In x Ga 1-x P, InGaAsN, or InGaAsNSb, and each barrier layer 35 may include, but is not limited to, GaAs, Al x Ga 1-x As, GaAs x P 1-x Al x Ga y In 1-x-y Layer P.

[0098] In some implementations, for GaAs-based VCSELs, other elements and layers of module 11 (e.g., in-cavity contacts, BSD 12, and optical elements) are similar to the corresponding elements and layers described above, for example, in InP-based and GaSb-based VCSELs.

[0099] Gallium nitride-based VCSEL integrated on silicon for emitting wavelengths (WL) smaller than 0.6 μm

[0100] In some embodiments, the structure of VD 22 can be used to fabricate a gallium nitride (GaN)-based VCSEL configured to emit a beam 32 with a WL of less than about 0.6 μm. In such embodiments, substrate 24 may comprise an n-type doped or semi-insulating GaN substrate. Layer 25 may comprise a heavily doped GaN layer forming an ohmic contact with metal layer 96 to conduct current with low resistance.

[0101] In some implementations, ED 55 may include a combination of materials and / or compounds selected from nDBR, such as: Al x In 1-x N (where x equals approximately 0.82) serves as the low-refractive-index layer, while GaN serves as the high-refractive-index layer, with an intermediate graded layer (e.g., Al) x Ga y In 1-x-y N).

[0102] In such implementations, an nDBR with fewer than 35 pairs of layers can achieve a reflectivity of over 99% at a designated WL of beam 32.

[0103] In some embodiments, the GaN-based VCSEL DD 66, designed to emit a WL of less than about 0.6 μm, may have pairs of titanium oxide (TiO2) or niobium pentoxide (Nb2O5) or any other suitable compound as a high-refractive-index layer and silicon dioxide (SiO2) layer or any other suitable compound as a low-refractive-index layer. In such embodiments, DD 66 may include eight or more pairs of these layers to achieve a reflectivity of more than 99.9% at a WL of less than about 0.6 μm for the beam 32.

[0104] In some implementations, TJ 44 may comprise a homogeneous or heterogeneous TJ. For a homogeneous TJ, layer 46 may comprise heavily doped n-type GaN, and layer 48 may comprise heavily doped p-type GaN or any other suitable type of compound.

[0105] In some implementations, AR 33 may include a single junction or multiple junctions (with TJ 44 between each pair of adjacent junctions). Each junction may include between approximately 3 and 7 pairs of layers 35 and 36. For example, each layer 36 may include a suitable type of QW layer, such as, but not limited to, InGaN, configured to emit a beam 32 having a WL of less than 0.6 μm, and each blocking layer 35 may include GaN.

[0106] In some implementations, for GaN-based VCSELs, other elements and layers of module 11 (e.g., in-cavity contacts, BSD 12, and optical elements) are similar to the corresponding elements and layers described above, for example, in InP-based, GaSb-based, and GaAs-based VCSELs.

[0107] Devices for emitting or detecting within a predetermined wavelength range, other than silicon-integrated VCSELs.

[0108] In some embodiments, instead of the VCSEL device described above (VD 22), module 11 may include any other suitable type of photodetector, such as, but not limited to, a silicon-based resonant cavity photodetector (RCPD-on-Si). This RCPD-on-Si is configured to detect the light beam at least within a predetermined WL or a predetermined WL range and generate a signal indicating the detected light beam. In some embodiments, anode 16 and cathode 18 are configured to be reverse-biased (the voltage at the cathode is higher than the voltage at the anode) to receive the signal via trace 105 and conduct the signal to any suitable processor. In such embodiments, the process for manufacturing module 11 with VD 22 (described below) Figures 2 to 6(As described in the text) With necessary modifications, it can be used to fabricate a module 11 or any other suitable device with RCPD-on-Si. For example, RCPD-on-Si can be formed by reducing the number of epitaxial nDBR layers close to the substrate 24. Furthermore, optical and electrical confinement are not required in RCPDs, so layers 44, 34, and 31 are not necessary. Instead, additional p-type doped semiconductor layers can be incorporated as anode metal contact layers. This configuration can yield RCPD arrays with tight design rules (e.g., pitch as small as approximately 5 μm).

[0109] Note that lens 28 or other suitable optical elements can also be used in conjunction with the aforementioned RCPD-on-Si device to collect the beam detected by the RCPD.

[0110] In an alternative implementation, for BSD 12, other semiconductor carrier substrates can be used instead of the 12” silicon wafer of substrate 14. However, the advantage of silicon is that, based on mature process technologies, CMOS circuits with very tight design rules (small lateral dimensions) can be fabricated at high yield on the surface of the substrate and coupled to drive VCSELs.

[0111] To illustrate certain problems addressed by the embodiments of the present invention, and to demonstrate the application of these embodiments in enhancing the performance of such VCSEL-based modules, this particular configuration of module 11 is shown by way of example. However, the embodiments of the present invention are by no means limited to this particular type of exemplary module, and the principles described herein can be similarly applied to other types of lasers or other types of light-emitting modules.

[0112] Process sequence for manufacturing silicon-based VCSELs

[0113] Figure 2 This is a cross-sectional view schematically illustrating the process sequence for manufacturing a silicon-based VCSEL (e.g., module 11) according to the embodiments described herein. In some embodiments, Figure 2 The process sequence describes the formation of the light-emitting layer stack (including AR 33, layer 45 and TJ 44) and the upper DBR 79 and lower DBR 78.

[0114] In some implementation schemes, the following Figures 2 to 6 The process described above is for manufacturing InP-based silicon-based VCSELs, which are shown, for example, as shown above. Figure 1 VD 22 and BSD 12. However, with the necessary changes, below Figures 2 to 6 The process can be used to manufacture any other suitable VCSEL, such as, but not limited to, those described above. Figure 1The VCSELs based on InP, GaSb, GaAs, and GaN described above. With necessary modifications, the following... Figures 2 to 6 The process can also be used to manufacture other devices, such as, but not limited to, the aforementioned RCPD-on-Si and any other suitable type of device formed on a silicon backplane, such as BSD 12.

[0115] The process begins with fabricating or receiving a substrate 24 with a stack of epitaxial layers, such as layer 25, ED 55, AR 33, layer 45, TJ 44, and layer 34. Note that in Figures 2 to 6 During the manufacturing process, the substrate 24 and the stacked epitaxial layer are relative to the top. Figure 1 Flipped (inverted). Furthermore, the epitaxial layer stack includes ED 55, which also forms the upper DBR 79, as shown above. Figure 1 As stated above.

[0116] In some implementation schemes, Figure 1 The light-emitting layer stack described herein may include a single stack of AR 33, layer 45 and TJ 44, which is also referred to herein as a single junction.

[0117] In other implementations, VD 22 may include a single stack repeated multiple times in a larger stack, referred to herein as a multi-junction (MJ)99 active region. Figure 2 In the example, MJ 99 includes a triple-junction stack having (i) three AR 33 stacks, (ii) two TJ 44s, and (iii) four layers 45 with alternating n-type and p-type doping arranged between each AR 33 and TJ 44.

[0118] In this configuration, in response to the power applied by BSD 12, the above... Figure 1 In the recombination process described herein (shown as recombination 39), VD 22 is configured to emit beam 32 from each junction. Note that each TJ 44 is configured to form an ohmic electrical connection between the n-type doped and p-type doped layers disposed on the respective sides of each junction, so as to provide electrical connection between adjacent junctions.

[0119] In some implementations, any suitable III-V semiconductor manufacturing process is used to perform the process. Figures 2 to 6The processes described herein include, but are not limited to: (a) thin film (TF) deposition using chemical vapor deposition (CVD), metal-organic CVD (MOCVD), physical vapor deposition (PVD) also referred to herein as sputtering, electroplating (EP) and electrochemical plating (ECP), and atomic layer deposition (ALD); (b) various types of reactive ion etching (RIE) and other types of etching processes; (c) photoresist-based lithography; (d) stripping; (e) hard mask-based lithography; and (f) various mask removal processes, such as, but not limited to, photoresist ashing, photoresist stripping, and HM etching.

[0120] In the hard mask and mesa (HMM) patterning step 1, a dielectric layer such as a silicon dioxide (SiO2) layer (referred to herein as layer 102) is deposited on layer 34, and then PR 100 is patterned at predetermined locations on the surface of layer 102.

[0121] In selective mesa etching step 2, the stack of layers 102 and 34, as well as TJ 44, is etched, exposing layer 45. In mask removal step 3, PR 100 and layer 102 are removed, allowing layer 34 and TJ 44 to be patterned on layer 45.

[0122] In epitaxial layer (EPI) regeneration step 4, layer 31 is deposited on layer 34. In some embodiments, layer 31 of the lower DBR 78 comprises an n-type semiconductor compound layer (e.g., made of InP or InAlGaAs) having a lattice matching the InP layer or substrate. In other embodiments, layer 31 of the lower DBR 78 may comprise several pairs of epitaxial n-type doped DBRs, also referred to herein as nDBRs, similar to the layers of ED 55.

[0123] In contact deposition and patterning step 5, contacts 91 made of any suitable metal alloy (e.g., gold-germanium-nickel-gold alloy) are deposited (e.g., using PVD or electron beam evaporation) and patterned (e.g., using photolithography and RIE processes) at predetermined locations on the surface of layer 31. In some embodiments, contacts 91 are configured to conduct the above-mentioned... Figure 1 The current in the current path 64 between layers 31 and 89 is shown.

[0124] In step 6 of the dielectric DBR formation, DD 66 is formed by depositing paired layers. (See above.) Figure 1 The DD 66 comprises repeating pairs of high-refractive-index and low-refractive-index materials, wherein the thickness of each layer is one-quarter of the local wavelength of light emitted by AR 33. Figure 2 In the example, DD 66 includes repeating pairs of amorphous silicon and SiO2 layers.

[0125] In some implementations, after step 6 (which ends the formation of the lower DBR 78), a stack of light-emitting layers (e.g., AR 33, layer 45, and TJ 44) and both the upper DBR 79 and the lower DBR 78 are formed, but they are not electrically connected to each other or to BSD 12.

[0126] Figures 3 to 6 This is a schematic cross-sectional view illustrating the process sequence for manufacturing module 11 according to the embodiments described herein. In some embodiments, the process is as follows: Figure 2 Following the aforementioned light-emitting stack (AR 33, layer 45 and TJ44) and the upper DBR 79 and lower DBR 78, Figure 3 and 4 The process sequence describes the formation of the electrical connection layers (e.g., layers 88 and 89) of VD 22.

[0127] Now for reference Figure 3 In the through-hole etching step 7, DD 66 is patterned, for example, using photolithography and etching processes, to expose the contact 91 formed in step 5 above. In the first cavity metal formation step 8, layer 89 is formed using a process sequence including the following steps: (a) seed metal deposition (e.g., using PVD or sputtering processes) and patterning (e.g., using photolithography and etching processes) of a thin metal seed layer (which is thin and therefore not shown), and (b) deposition (e.g., using EP or ECP processes) and patterning (e.g., using photolithography and etching processes) of a bulk metal layer on the seed layer. In some embodiments, layer 89 comprises a stack of a seed layer and a bulk metal layer. In some embodiments, layer 88 (on top of the seed layer) Figure 1 (shown in the figure) and 89 are configured to: (i) conduct current between the light-emitting layer stack (AR 33, layer 45 and TJ 44) and BSD 12, and (ii) conduct excess heat generated during the emission of beam 32.

[0128] In step 9 of HM pattern formation, SiN is deposited. x passivation layer 77 (in) Figure 1 (As described in the text) and PR 100, and patterned. In some embodiments, an HM is required to protect some layers of VD 22 during subsequent etching. In the deep etching step 10, the passivation layer 77, the light-emitting layer stack, and the DBR (i.e., the lower DBR 78 and the upper DBR 79) are deeply etched, thereby dividing VD 22 into two parts, part 116 which will be connected to the anode 16, and part 118 which will be connected to the cathode 18. In some embodiments, the deep etching step exposes layer 25 and forms a gap 117 separating parts 116 and 118.

[0129] In some embodiments, in section 116, the light-emitting layer stack (via layer 31 and contact 91) is electrically connected to layer 89 due to via etching and filling in steps 7 and 8, respectively. Conversely, in section 118, DD 66 disconnects the connection between contact 91 and layer 89, causing the light-emitting layer stack to be electrically disconnected and unable to emit beam 32. In such embodiments, beam 32 is emitted only from section 116 when VD 22 receives current from BSD 12, as described above. Figure 1 As shown.

[0130] In PR removal step 11, PR 100 is removed from passivation layer 77 of portions 116 and 118. In passivation formation and opening step 12, a second passivation layer 93 (which typically has the same SiN as passivation layer 77) is formed on the outer walls of portions 116 and 118 and on layer 25. x (Compound). Furthermore, the passivation layer 77 is patterned to open a portion of the passivation layer 77 to expose layer 89. Note that step 12 includes multiple processes that can be performed in any suitable order.

[0131] Now for reference Figure 4 In PR pattern definition step 13, PR 100 is patterned on portions 116 and 118. Note that PR 100 has a recessed profile 122 for patterning a first portion of layer 93 formed on layer 25. In passivation etching step 14, the first portion 124 of layer 93 (defined in step 13) is etched to expose layer 25. Note that due to the aforementioned recessed profile of PR 100, a second portion 128 of layer 93, very close to portions 116 and 118, remains on layer 25. For conceptual clarity, dashed lines 95 (virtual) separate the etched first portion 124 and second portion 128, where layer 93 is not etched.

[0132] In conductive layer deposition step 15, layer 96, typically made of a metal alloy, is deposited on the first portion 124 and PR 100. In some embodiments, layer 93 constitutes a hard mask for forming layer 96 at the second portion 128 of layer 93 as described in step 114 above. In other embodiments, layer 96 may comprise any other suitable type of conductive layer besides the metal alloy described above.

[0133] In the conductive layer stripping step 16, layer 96 is stripped by removing PR 100 using any suitable stripping process. In the seed metal deposition step 117, PR 100 is patterned on portion 116, and a seed layer 97 is deposited on PR 100. Note that PR 100 has a recessed profile 126 to enable the deposition of the seed layer 97 on layer 96.

[0134] In seed stripping step 18, PR 100 is removed and seed layer 97 is stripped, leaving only layer 96 as the seed layer. In the second cavity metal formation step 19, layer 88 (typically made of gold or copper or any other suitable metal or metal alloy) is formed using an EP or ECP electroplating process. Note that in the electroplating process, the metal may be formed only on the conductive surfaces. In the embodiment shown in step 19, layer 88 is formed on seed layers 97 and 89, but not on passivation layers 77 and 93. In this embodiment, layer 88 is formed on the wall of portion 118 (covered by seed layer 97), but not on the wall of portion 116 and in the second portion 128, both of which are covered by passivation layers 77 and 93. Note that portion 116 is electrically disconnected from conductive layers such as layers 88 and 96 and seed layer 97.

[0135] In the surface passivation and patterning step 20, an additional passivation layer 77 is deposited on the entire surface of VD 22, and an opening 130 is etched to expose a portion of layer 88. Note that passivation layers 77 and 93 prevent any electrical contact between portion 116 and conductive layers (e.g., layers 88 and 96) and seed layer 97 (particularly in the second portion 128).

[0136] Now for reference Figure 5 In wafer thinning step 21, the aforementioned InP wafer is thinned using a thinning process (e.g., by back-side grinding or wet etching) to reduce the thickness of substrate 24. In the example of step 21, the distance between layer 25 and surface 241 represents the original thickness of substrate 24, such that the thinning process reduces the original thickness of substrate 24 by approximately half or any suitable percentage.

[0137] In anti-reflective coating step 22, AR layer 26 is coated onto the surface of substrate 24. (As above) Figure 1 The AR layer 26 is configured to prevent the light beam 32 from being reflected back to VD 22 from the interface between the surface of the substrate 24 and the air.

[0138] Figures 2 to 5 The fabrication of multiple VDs 22 on substrate 24 is described. After passivation and patterning steps 20, the VDs 22 are ready to be assembled and packaged with BSD 12 to complete the fabrication of module 11.

[0139] Figure 6 This is a cross-sectional view schematically illustrating the process sequence for assembling VD 22 on BSD 12 to manufacture module 11 according to the embodiments described herein.

[0140] Referring now to illustration 140, a top view of an InP wafer 101 typically having a diameter of about 3” or 4” or any other suitable size or shape is shown. In some embodiments, dicing 98 is defined for physical separation between adjacent dies 132 of the VCSEL.

[0141] exist Figure 6 In the examples, each die may include a single VCSEL, for example Figure 1 VD 22 is shown. In other embodiments, each die may include multiple VCSELs arranged in a random or unordered array (not shown) or an ordered array such as array 135. In such embodiments, each VCSEL may have two concentric circular shapes, the outer circular shape referred to herein as a mesa (on the upper...). Figure 1 (as described in the illustration), and the inner circular shape indicated by the term "BTJ" in Illustration 140 represents the aperture of TJ 44.

[0142] Now for reference Figure 6 Overall view. In die separation step 23, the substrate 24 of the InP wafer 101 is diced in dicing groove 98 and optionally in the above... Figure 3 and Figure 4 Some layers are generated in order to separate the bare die formed on the InP wafer 101 into multiple individual VD 22.

[0143] In bump formation step 24, bumps 20 are formed on the anode 16 and cathode 18 of the BSD 12. In the example of step 24, bumps 20 are shown on a single pair of anodes 16 and cathodes 18, but this bump fabrication process is typically performed at the wafer level on all anodes 16 and cathodes 18, while the anodes and cathodes are fabricated on a silicon wafer 14 with a typical diameter of 12” or any other suitable diameter.

[0144] In assembly step 25, a die comprising a plurality of VD 22s (e.g., array 135), or in this example, a die comprising a single VD 22 device, is flipped (inverted) and subsequently mounted and coupled to the BSD 12. In some embodiments, layer 88 exposed in opening 130 of portion 116 is bonded to bump 20 formed on anode 16 (in step 22). Similarly, layer 88 exposed in opening 130 of portion 118 is bonded to bump 20 formed on anode 18 (in step 22).

[0145] Note that in other processes where VCSELs are integrated on a backplane silicon driver (BSD), the III-V semiconductor substrate can be removed (e.g., by wet etching), and various types of epitaxial layers or other layers can be formed on a thin and fragile III-V epitaxial film (less than about 15 μm thick) to fabricate VCSEL components, such as the top DBR. This process is challenging and often results in wafer breakage and low process yield. However, in the process of module 11, the substrate 24 is not removed, so the process does not involve handling or processing the thin III-V epitaxial wafer, thus minimizing wafer breakage and increasing process yield.

[0146] In some implementations, after step 25, BSD 12 and VD 22 are electrically connected such that by supplying power to BSD 12, VD 22 can receive current from anode 16 and cathode 18, and VD 22 can emit beam 32 by activating current paths 62 and 64. (See above.) Figure 1 As described, multiple VD 22s are assembled on BSD 12, and one or more VD 22s are selectively powered based on wiring of electrical trace 105. Such integrated modules can be implemented in mobile devices or can be portable; therefore, it is important to provide module 11 with improved mechanical stability, heat dissipation, and electrical insulation from the environment and some of its adjacent conductive parts.

[0147] In the filler forming step 26 of the method for manufacturing module 11, filler 60 is manufactured by immersing module 11 in a liquid polymer, and subsequently, the polymer is hardened to form solid filler 60. In other embodiments, filler 60 may comprise any suitable material other than a polymer, or may be combined with a polymer using any suitable manufacturing method.

[0148] In some embodiments, the filler 60 improves the mechanical stability of module 11, for example, by preventing relative movement between VD 22 and BSD 12. Furthermore, the filler 60 is configured to prevent deformation of module 11, such as bending of VD 22 relative to BSD 12, or any break in connection between layers or components of module 11 (e.g., break in connection between bump 20 and layer 88).

[0149] In some embodiments, the filler 60 comprises an electrically insulating material and is therefore configured to prevent undesirable electrical leakage between the module 11 and the environment, as well as between adjacent components and / or layers of the module 11. In some embodiments, the filler 60 is also configured to physically isolate the module 11 from moisture and other undesirable environmental conditions.

[0150] In some embodiments, after step 25 or step 26, one or more optical elements (e.g., but not limited to microlenses) can be added. Figure 1 The lens 28 (or diffractive optical element (DOE) shown) is integrated with the substrate 24. For example, the lens 28 or another suitable type of optical element may be formed on the substrate 24 before or after the formation of the AR layer 26. These optical elements may be used to shape and / or guide and / or otherwise manipulate the beam 32. Note that the optical elements may also be fabricated in or integrated with an RCPD-on-Si device for collecting the beam detected by the RCPD.

[0151] To illustrate certain problems solved by the embodiments of the disclosed technology, and to demonstrate the application of these embodiments in enhancing the performance of such a module, the specific process for manufacturing module 11 is simplified and illustrated by way of example (in...). Figures 2 to 6 (as shown in the diagram). However, embodiments of the present invention are by no means limited to this particular type of exemplary process, and the principles described herein can be similarly applied to other types of process flows for manufacturing integrated VCSELs, other types of lasers, or other types of light-emitting modules.

[0152] Although the embodiments described herein are primarily aimed at the integration of light-emitting and / or receiving devices and / or modules, the methods and systems described herein can also be used for other applications, such as silicon-based III-V electro- and photonic integrated circuits or heterogeneous integration of Si-CMOS circuits and III-V heterojunction bipolar transistors (HBTs) for high-performance mixed-signal applications.

[0153] Therefore, it should be understood that the above embodiments are cited by way of example, and the following claims are not limited to what has been specifically shown and described above. Rather, the scope includes both combinations and sub-combinations of the various features described above, as well as variations and modifications of the various features that would occur to a person skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. Documents incorporated herein by reference are considered an integral part of this application; however, if any term is defined in these incorporated documents in a way that conflicts with the definitions expressly or implicitly made herein, the definitions herein shall prevail.

Claims

1. An optoelectronic device comprising: a semiconductor substrate doped with a first level of n-type dopant; a contact semiconductor layer disposed above the semiconductor substrate and doped with a second level of n-type dopant greater than the first level; an upper distributed Bragg reflector (DBR) stack disposed above the contact semiconductor layer and comprising alternating first and second epitaxial semiconductor layers having respective first and second refractive indices different from one another in a predetermined wavelength band, the upper DBR comprising a direct bandgap n-type distributed Bragg reflector (nDBR) having fewer than thirty pairs of layers; an epitaxial layer group disposed above the upper DBR, wherein the epitaxial layer group comprises one or more group III-V semiconductor materials and defines: a quantum well (QW) structure comprising a plurality of pairs of alternating layers comprising (i) QW layers and (ii) barrier layers; a confinement layer comprising a first p-type layer having a third level of p-type dopant and an n-type layer; and a second p-type layer disposed between the QW structure and the confinement layer and having a fourth level of p-type dopant less than the third level; a lower DBR stack disposed above the epitaxial layer group, opposite the upper DBR, and comprising alternating dielectric and semiconductor layers, the lower DBR having a hybrid reflector having a combination of a dielectric distributed Bragg reflector (DD) and one or more n-type semiconductor layers; a cavity through the lower DBR filled with a conductive layer configured to: (i) conduct an excitation current between a power source and the quantum well structure, and (ii) dissipate heat generated by at least the quantum well structure; and a ring-shaped layer having a hollow center, wherein the ring-shaped layer is disposed within the cavity through the lower DBR between the conductive layer and the quantum well structure and is configured to: (i) conduct the excitation current between the conductive layer and the quantum well structure; and (ii) enhance removal of the heat from the quantum well structure.

2. The optoelectronic device of claim 1, wherein the quantum well structure is configured to emit a light beam having a wavelength in the predetermined wavelength band.

3. The optoelectronic device of claim 2, wherein at least one of (i) the semiconductor substrate, (ii) the contact semiconductor layer, and (iii) the epitaxial layer group comprises indium phosphide, and wherein the emitted light beam has a wavelength between 1.2 pm and 2 pm.

4. The optoelectronic device of claim 2, wherein at least one of (i) the semiconductor substrate, (ii) the contact semiconductor layer, and (iii) the epitaxial layer group comprises gallium antimonide, and wherein the emitted light beam has a wavelength greater than 2 pm.

5. The optoelectronic device of claim 2, wherein at least one of (i) the semiconductor substrate, (ii) the contact semiconductor layer, and (iii) the set of epitaxial layers comprises gallium arsenide, and wherein the emitted light beam has a wavelength between 0.63 pm and 1.1 pm.

6. The optoelectronic device of claim 2, wherein at least one of (i) the semiconductor substrate, (ii) the contact semiconductor layer, and (iii) the set of epitaxial layers comprises gallium nitride, and wherein the emitted light beam has a wavelength less than 0.6 pm.

7. The optoelectronic device of claim 2, and the device includes an electrode coupled to apply the excitation current to the quantum well structure.

8. The optoelectronic device of claim 7, wherein the electrode comprises a first electrode and a second electrode, and the device comprises: (i) a first bump electrically coupled between the first electrode and the contact semiconductor layer; and (ii) a second bump coupled between the second electrode and an additional contact semiconductor layer, and wherein the first bump and the second bump are configured to conduct the excitation current applied to the quantum well structure.

9. The optoelectronic device of claim 1 or 2, wherein the lower DBR further comprises alternating third and fourth epitaxial semiconductor layers in addition to the alternating dielectric and semiconductor layers, the third and fourth epitaxial semiconductor layers having respective third and fourth refractive indices different from each other in the predetermined wavelength band.

10. The optoelectronic device of claim 1, wherein the quantum well structure is configured to detect light of the predetermined wavelength.

11. The optoelectronic device of claim 10, and the device includes an electrode coupled to receive a signal from the quantum well structure indicative of the detected light beam.

12. A method for manufacturing an optoelectronic device, the method comprising: disposing a contact semiconductor layer over a semiconductor substrate doped with a first level of n-type dopant, and doping the contact semiconductor layer with a second level of n-type dopant greater than the first level; disposing an upper distributed Bragg reflector (DBR) stack over the contact semiconductor layer, the upper DBR stack comprising alternating first and second epitaxial semiconductor layers having respective first and second refractive indices different from each other in a predetermined wavelength band, wherein disposing the upper DBR comprises disposing a direct bandgap n-type distributed Bragg reflector (nDBR) having fewer than thirty pairs of layers; disposing a set of epitaxial layers over the upper DBR, the set of epitaxial layers comprising one or more III-V semiconductor materials and defining: a quantum well (QW) structure comprising a plurality of pairs of alternating layers comprising (i) a QW layer and (ii) a barrier layer; a confinement layer comprising a first p-type layer having a third level of p-type dopant and an n-type layer; and ​ a second p-type layer disposed between the QW structure and the confinement layer and having a fourth level of p-type dopant less than the third level; disposing a lower DBR stack opposite the upper DBR over the epitaxial layer set, the lower DBR comprising alternating dielectric layers and semiconductor layers, wherein disposing the lower DBR comprises disposing a hybrid reflector having a combination of a dielectric distributed Bragg reflector (DD) and one or more n-type semiconductor layers; forming a cavity through the lower DBR and filling the cavity through the lower DBR with a conductive layer for (i) conducting an excitation current between a power source and the quantum well structure and (ii) dissipating heat generated by at least the quantum well structure; and disposing a ring-shaped layer having a hollow center within the cavity through the lower DBR between the conductive layer and the quantum well structure, the ring-shaped layer for (i) conducting the excitation current between the conductive layer and the quantum well structure and (ii) dissipating the heat generated by at least the quantum well structure.

13. The method of claim 12, wherein disposing the epitaxial layer set comprises producing the quantum well structure for emitting a light beam having a wavelength in the predetermined wavelength band.

14. The method of claim 13, and the method comprises producing at least one of (i) the semiconductor substrate, (ii) the contact semiconductor layer, and (iii) the epitaxial layer set with indium phosphide for emitting the light beam having a wavelength between 1.2 pm and 2 pm.

15. The method of claim 13, and the method comprises producing at least one of (i) the semiconductor substrate, (ii) the contact semiconductor layer, and (iii) the epitaxial layer set with gallium arsenide for emitting the light beam having a wavelength between 0.63 pm and 1.1 pm.

16. The method of claim 13, and the method comprises producing an electrode coupled to apply the excitation current to the quantum well structure.

17. The method of claim 12 or 13, wherein providing the lower DBR comprises: In addition to the disposed alternating dielectric layers and semiconductor layers, alternating third and fourth epitaxial semiconductor layers are disposed, the third and fourth epitaxial semiconductor layers having respective third and fourth refractive indices different from each other in the predetermined wavelength band.

18. The method of claim 12, wherein disposing the epitaxial layer set comprises producing the quantum well structure for detecting light of the predetermined wavelength.

19. The method of claim 18, and the method comprises producing an electrode coupled to receive a signal from the quantum well structure indicative of the detected light beam.

20. A method for operating an optoelectronic device, comprising: Operating the optoelectronic device, the optoelectronic device comprising: (i) a semiconductor substrate doped with a first level of n-type dopant; (ii) a contact semiconductor layer disposed above the semiconductor substrate and doped with a second level of n-type dopant greater than the first level; (iii) an upper distributed Bragg reflector (DBR) stack disposed above the contact semiconductor layer and comprising alternating first and second epitaxial semiconductor layers having respective first and second refractive indices different from each other in a predetermined wavelength band, the upper DBR comprising a direct bandgap n-type distributed Bragg reflector (nDBR) having fewer than thirty pairs of layers; (iv) an epitaxial layer group disposed above the upper DBR, wherein the epitaxial layer group comprises one or more III-V semiconductor materials and defines: (a) a quantum well (QW) structure comprising a plurality of pairs of alternating layers comprising (i) a QW layer and (ii) a barrier layer; (b) a confinement layer comprising a first p-type layer having a third level of p-type dopant and an n-type layer; and a second p-type layer disposed between the QW structure and the confinement layer and having a fourth level of p-type dopant less than the third level; (v) a lower DBR stack disposed above the epitaxial layer group, opposite the upper DBR, and comprising alternating dielectric and semiconductor layers; (iv) a cavity through the lower DBR filled with a conductive layer configured to: (i) conduct an excitation current between a power source and the quantum well structure, and (ii) dissipate heat generated by at least the quantum well structure; wherein the lower DBR comprises a hybrid reflector having a combination of a dielectric distributed Bragg reflector (DD) and one or more n-type semiconductor layers; and (vii) a ring-shaped layer having a hollow center for: (i) conducting the excitation current between the conductive layer and the quantum well structure; and (ii) dissipating the heat generated by at least the quantum well structure; and applying an excitation current to the quantum well structure for emitting a light beam having a wavelength in the predetermined wavelength band.

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