Pulse receiving circuit and signal transmission device

Abstract

The pulse receiving circuit (221) constituting the signal transmission device (200) includes: a first pulse detector (221E) that receives a differential input between a first received pulse signal (S3), i.e., an internal signal (s21) at the secondary winding (231s) of the first transformer (231), and a second received pulse signal (S4), i.e., an internal signal (s22) at the secondary winding (232s) of the second transformer (232); a second pulse detector (221F) that receives a differential input between the first received pulse signal (S3) and the second received pulse signal (S4), wherein the input polarity is opposite to the input polarity of the first pulse detector (221E); and a logic unit (221H) that generates a received pulse signal (S5) based on the output signals (s23, s24) of the first and second pulse detectors (221E, 221F), respectively.

Description

Technical Field

[0001] The invention disclosed in this specification relates to a pulse receiving circuit and a signal transmission device. Background Art

[0002] Generally, signal transmission devices that transmit pulse signals while being electrically isolated between input and output are used in various applications (such as power supply devices and motor drive devices).

[0003] Note that Patent Document 1 applied for by this applicant exists as an example of a conventional technique related to the above description.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2018-011108 Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] However, there is room for further improvement in the conventional signal transmission device in terms of processing for reducing instantaneous transient common-mode noise that is superimposed on each received pulse signal input in parallel with the pulse receiving circuit on the secondary side.

[0009] In view of the above problems found by the inventors of the present application, an object of the invention disclosed in this specification is to provide a signal transmission device that is not easily affected by common-mode noise and a pulse receiving circuit used in the device.

[0010] Means for Solving the Problems

[0011] The signal transmission device disclosed in this specification includes: a first pulse detector configured to receive a differential input between a first received pulse signal at a secondary winding of a first transformer and a second received pulse signal at a secondary winding of a second transformer; a second pulse detector configured to receive a differential input between the first received pulse signal and the second received pulse signal, wherein the input polarity is opposite to that of the first pulse detector; and a logic unit configured to generate a received pulse signal based on the output signals of the first pulse detector and the second pulse detector.

[0012] Effects of the Invention

[0013] According to the invention disclosed in this specification, a signal transmission device that is not easily affected by common-mode noise can be provided. Brief Description of the Drawings

[0014] Figure 1 is a diagram showing an application example of the signal transmission device.

[0015] Figure 2 It is a diagram showing a first embodiment of a signal transmission device.

[0016] Figure 3 It is a diagram showing an example of a noise reduction operation in the first embodiment.

[0017] Figure 4 It is a diagram showing a second embodiment of a signal transmission device.

[0018] Figure 5 It is a diagram showing an example of a noise reduction operation in the second embodiment.

[0019] Figure 6 It is a diagram showing an example of a comparison operation of a comparator.

[0020] Figure 7 It is a diagram showing an example of the structure of a transformer chip in the second embodiment.

[0021] Figure 8 It is a diagram showing the dual-channelization of a signal transmission device.

[0022] Figure 9 It is used as Figure 8 A perspective view of a semiconductor device of the transformer chip shown.

[0023] Figure 10 It is Figure 9 A plan view of the semiconductor device shown.

[0024] Figure 11 It is a diagram showing a layer for forming a low-potential coil in the Figure 9 Semiconductor device shown.

[0025] Figure 12 It is a diagram showing a layer for forming a high-potential coil in the Figure 9 Semiconductor device shown.

[0026] Figure 13 It is a cross-sectional view taken along the Figure 12 Line VIII-VIII shown in.

[0027] Figure 14 It is a cross-sectional view taken along the Figure 12 Line IX-IX shown in.

[0028] Figure 15 It is Figure 12 An enlarged view of region X shown in.

[0029] Figure 16 It is Figure 12 An enlarged view of region XI shown in.

[0030] Figure 17 is Figure 12 an enlarged view of Region XII shown in

[0031] Figure 18 is Figure 13 an enlarged view of Region XIII shown in, and is a view showing a separated structure. DETAILED DESCRIPTION

[0032] <Signal Transmission Device (Application)>

[0033] Figure 1 is a view showing an application example of using the signal transmission device. The signal transmission device 200 of this structural example is a semiconductor integrated circuit device (so-called isolation gate driver IC) that transmits a pulse signal from a primary circuit system (VCC1-GND1 system) to a secondary circuit system (VCC2-GND2 system) while being electrically isolated between the primary circuit system and the secondary circuit system in order to drive the gate of a transistor provided in the secondary circuit system.

[0034] The signal transmission device 200 has a plurality of external terminals as devices for establishing electrical connections to the outside of the device (in this figure, input terminals INA and INB, output terminal OUT, power supply terminals VCC1 and VCC2, and ground terminals GND1 and GND2). These external terminals are externally connected to various discrete components (in this figure, N-channel metal oxide semiconductor (MOS) field effect transistor N1, capacitors C1 and C2, and resistor R1).

[0035] On the first side (in this figure, the left side) of the package of the signal transmission device 200, the ground terminal GND1, power supply terminal VCC1, input terminal INA, input terminal INB, and ground terminal GND1 are arranged in order from top to bottom. On the contrary, on the second side of the same package (the side opposite to the first side or the right side in this figure), the ground terminal GND2, power supply terminal VCC2, output terminal OUT, and ground terminal GND2 are arranged in order from top to bottom.

[0036] In this way, preferably, the external terminals (GND1, VCC1, INA, and INB) of the primary circuit system are grouped on the first side of the package, while the external terminals (GND2, VCC2, and OUT) of the secondary circuit system are grouped on the second side of the package.

[0037] Furthermore, preferably, the ground terminal GND1 and the ground terminal GND2 are respectively provided at both ends of the first side and the second side of the package. In other words, preferably, each of the ground terminals GND1 and GND2 has two terminals.

[0038] Outside the signal transmission device 200 (primary circuit system), the power supply terminal VCC1 is connected to the power supply line of the primary circuit system. Both ground terminals GND1 are connected to the ground line of the primary circuit system. The capacitor C1 is connected between the power supply line and the ground line of the primary circuit system. The input terminals INA and INB are respectively supplied with two input signals (e.g., gate control signal and enable signal).

[0039] In addition, outside the signal transmission device 200 (secondary circuit system), the power supply terminal VCC2 is connected to the power supply line of the secondary circuit system. Both ground terminals GND2 are connected to the ground line of the secondary circuit system. The capacitor C2 is connected between the power supply line and the ground line of the secondary circuit system. The output terminal OUT is connected to the first end of the resistor R1. The second end of the resistor R1 is connected to the gate of the transistor N1.

[0040] <Signal Transmission Device (Schematic Structure)>

[0041] In addition, refer to Figure 1 to describe the schematic structure of the signal transmission device 200. The signal transmission device 200 of this structural example includes a controller chip 210 (corresponding to the first chip), a driver chip 220 (corresponding to the second chip), and a transformer chip 230 (corresponding to the third chip) sealed in a single package.

[0042] The controller chip 210 is a semiconductor chip that operates with a power supply voltage VCC1 (e.g., up to 7V relative to GND1). Note that the controller chip 210 includes, for example, integrated Schmitt buffers 211A and 211B, an AND gate 211C, a pulse transmission circuit 212, and a low voltage protection circuit 213.

[0043] The Schmitt buffer 211A is an example of a waveform shaping device and is connected between the input terminal INA and the first input terminal (non-inverting input terminal) of the AND gate 211C.

[0044] The Schmitt buffer 211B is an example of a waveform shaping device and is connected between the input terminal INB and the second input terminal (inverting input terminal) of the AND gate 211C.

[0045] The AND gate 211C performs an AND operation between the input pulse signal INA and the inverted input pulse signal XINB (i.e., the logical inverted signal of the input pulse signal INB) to generate the input pulse signal S0, and outputs the input pulse signal S0 to the pulse transmission circuit 212. Therefore, if INB = H (the logical level when disabled) holds, then S0 = L (a fixed value) holds, and if INB = L (the logical level when enabled) holds, then S0 = INA holds.

[0046] The pulse transmission circuit 212 generates transmission pulse signals S1 and S2 based on the input pulse signal S0. More specifically, when notified that the input pulse signal S0 is at a high level, the pulse transmission circuit 212 performs pulse driving of the transmission pulse signal S1 (output of single or multiple transmission pulses), and when notified that the input pulse signal S0 is at a low level, it performs pulse driving of the transmission pulse signal S2. In other words, the pulse transmission circuit 212 performs pulse driving of either one of the transmission pulse signals S1 and S2 according to the logical level of the input pulse signal S0.

[0047] The low-voltage protection circuit 213 keeps the controller chip 210 in a standby state until the power supply voltage VCC1 reaches the undervoltage lockout (UVLO) release voltage to prevent malfunctions when a low voltage is input.

[0048] The driver chip 220 is a semiconductor chip that operates with a power supply voltage VCC2 (e.g., up to 30V relative to GND2). Note that, for example, the pulse reception circuit 221, the driver 222, and the low-voltage protection circuit 223 are integrated in the driver chip 220.

[0049] The pulse reception circuit 221 generates a received pulse signal S5 based on the received pulse signals S3 and S4 input from the transformer chip 230. More specifically, the pulse reception circuit 221 reduces the received pulse signal S5 to a low level in response to the pulse driving of the received pulse signal S3, and raises the received pulse signal S5 to a high level in response to the pulse driving of the received pulse signal S4. In other words, the pulse reception circuit 221 changes the logical level of the received pulse signal S5 according to the logical level of the input pulse signal S0.

[0050] The driver 222 generates an output pulse signal OUT (corresponding to the gate signal of the transistor N1) based on the received pulse signal S5 input from the pulse reception circuit 221. More specifically, when the received pulse signal S5 is at a low level, the driver 222 sets the output pulse signal OUT to a high level, and when the received pulse signal S5 is at a high level, the driver 222 sets the output pulse signal OUT to a low level.

[0051] Note that, as shown in the figure, a half-bridge output stage (CMOS (complementary MOS) inverter stage) composed of a P-channel MOS field-effect transistor 222H and an N-channel MOS field-effect transistor 222L can be used as the driver 222.

[0052] The connection relationship will be described below. The source of the transistor 222H is connected to the power supply terminal VCC2. The source of the transistor 222L is connected to the ground terminal GND2. The drains of the transistors 222H and 222L are both connected to the output terminal OUT.

[0053] The received pulse signal S5 is input to the gates of the transistors 222H and 222L. Therefore, when S5 = L holds, the transistor 222H is turned on while the transistor 222L is turned off, so OUT = H (= VCC2) holds. On the contrary, if S5 = H holds, the transistor 222H is turned off while the transistor 222L is turned on, so OUT = L (= GND2) holds.

[0054] The low-voltage protection circuit 223 keeps the driver chip 220 in the standby state until the power supply voltage VCC2 reaches the UVLO release voltage, so as to prevent failures from occurring when the input voltage is low.

[0055] The transformer chip 230 uses the transformers 231 and 232 to isolate the current between the controller chip 210 and the driver chip 220, and outputs the transmission pulse signals S1 and S2 input from the pulse transmission circuit 212 to the pulse receiving circuit 221 as the received pulse signals S3 and S4 respectively.

[0056] More specifically, according to the transmission pulse signal S1 input to the primary winding 231p, the transformer 231 outputs the received pulse signal S3 from the secondary winding 231s. On the contrary, according to the transmission pulse signal S2 input to the primary winding 232p, the transformer 232 outputs the received pulse signal S4 from the secondary winding 232s.

[0057] In this way, due to the characteristics of the spiral coil for insulated communication, the input pulse signal S0 is separated into two transmission pulse signals S1 and S2 (corresponding to the rising signal and the falling signal), and these two transmission pulse signals S1 and S2 are transmitted from the primary circuit system to the secondary circuit system via the transformers 231 and 232.

[0058] Note that, in addition to the controller chip 210 and the driver chip 220, the signal transmission device 200 of this structural example further includes a transformer chip 230, where only the transformers 231 and 232 are independently installed, and these three chips are sealed in a single package.

[0059] With this structure, both the controller chip 210 and the driver chip 220 can be manufactured using a conventional low to medium withstand voltage process (a few volts to several tens of volts) instead of using a dedicated high withstand voltage process (several thousand volts), thus reducing the manufacturing cost.

[0060] In addition, both the controller chip 210 and the driver chip 220 can be manufactured using existing processes with trace records without having to re - perform reliability tests, thus shortening the development cycle and reducing the development cost.

[0061] In addition, when using a DC isolation element other than a transformer (such as an optocoupler), it can be easily supported by simply replacing the transformer chip 230 without having to re - develop the controller chip 210 and the driver chip 220, thus shortening the development cycle and reducing the development cost.

[0062] In the following description, a more specific description is given by paying attention to the internal structure of the signal transmission device 200.

[0063] <Signal Transmission Device (First Embodiment)>

[0064] Figure 2 is a diagram showing the first embodiment of the signal transmission device 200. In this diagram, based on Figure 1 , the circuit structures of the pulse transmission circuit 212 and the pulse reception circuit 221 are specifically shown. The above input terminals INA and INB are replaced by a single input terminal IN. The above Schmitt buffers 211A and 211B and the AND gate 211C are replaced by a single Schmitt buffer 211. The above transistors 222H and 222L are omitted in the figure.

[0065] In addition, the transformer chip 230 is clearly provided with external terminals T11 to T18. The primary winding 231p of the transformer 231 is connected between the external terminal T11 and the external terminal T12. The primary winding 232p of the transformer 232 is connected between the external terminal T13 and the external terminal T14. The secondary winding 231s of the transformer 231 is connected between the external terminal T15 and the external terminal T16. The secondary winding 232s of the transformer 232 is connected between the external terminal T17 and the external terminal T18.

[0066] Note that due to the structures of the transformers 231 and 232, parasitic capacitances are formed between the primary winding 231p and the secondary winding 231s and between the primary winding 232p and the secondary winding 232s.

[0067] The pulse transmission circuit 212 includes a logic unit 212a, buffers 212b and 212c, and diodes 212d and 212e.

[0068] The logic unit 212a drives the buffers 212b and 212c according to the input pulse signal S0 (and thus corresponding to the input pulse signal IN). More specifically, when it is notified that the input pulse signal S0 is at a high level, the logic unit 212a drives the buffer 212b, and when it is notified that the input pulse signal S0 is at a low level, the logic unit 212a drives the buffer 212c.

[0069] The buffer 212b is driven by the logic unit 212a to generate a transmission pulse signal S1, and outputs the transmission pulse signal S1 to the external terminal T11 of the transformer chip 230.

[0070] The buffer 212c is driven by the logic unit 212a to generate a transmission pulse signal S2, and outputs the transmission pulse signal S2 to the external terminal T13 of the transformer chip 230.

[0071] The diode 212d is an example of an electrostatic protection element, which has a cathode connected to the external terminal T11 of the transformer chip 230 and an anode connected to the external terminals T12 and T14 of the transformer chip 230.

[0072] The diode 212e is an example of an electrostatic protection element, which has a cathode connected to the external terminal T13 of the transformer chip 230 and an anode connected to the external terminals T12 and T14 of the transformer chip 230.

[0073] The pulse receiving circuit 221 includes diodes 221a and 221b, buffers 221c to 221f, delay units 221g and 221h, AND gates 221i and 221j, and a logic unit 221k.

[0074] The diode 221a has a cathode connected to the external terminal T15 of the transformer chip 230. The diode 221a has an anode connected to the external terminals T16 and T18 of the transformer chip 230. The diode 221a connected in this way serves as an electrostatic protection element connected between both ends of the secondary winding 231s constituting the transformer 231.

[0075] The diode 221b has a cathode connected to the external terminal T17 of the transformer chip 230. The diode 221b has an anode connected to the external terminals T16 and T18 of the transformer chip 230. The diode 221b connected in this way serves as an electrostatic protection element connected between both ends of the secondary winding 232s constituting the transformer 232.

[0076] Buffers 221c and 221d are waveform shaping devices for receiving the pulse signal S3 (i.e., the internal signal s11). More specifically, for example, when the internal signal s11 is higher than the threshold voltage Vth, buffers 221c and 221d raise the output signal to a high level, and when the internal signal s11 is lower than the threshold voltage Vth, buffers 221c and 221d lower the output signal to a low level. Note that the output signal of buffer 221c is output as the internal signal s13 (i.e., the main signal) to the AND gate 221i.

[0077] Buffers 221e and 221f are waveform shaping devices for receiving the pulse signal S4 (i.e., the internal signal s12). More specifically, for example, when the internal signal s12 is higher than the threshold voltage Vth, buffers 221e and 221f raise the output signal to a high level, and when the internal signal s12 is lower than the threshold voltage Vth, buffers 221e and 221f lower the output signal to a low level. Note that the output signal of buffer 221f is output as the internal signal s16 (i.e., the main signal) to the AND gate 221j.

[0078] For example, when the output signal of buffer 221d is raised to a high level, the delay unit 221g raises the internal signal s17 (i.e., the masking signal) to a high level without delay, and thereafter when a predetermined masking time tm1 has elapsed, the delay unit 221g lowers the internal signal s17 to a low level.

[0079] For example, when the output signal of buffer 221e is raised to a high level, the delay unit 221h raises the internal signal s14 (i.e., the masking signal) to a high level without delay, and thereafter when a predetermined masking time tm1 has elapsed, the delay unit 221h lowers the internal signal s14 to a low level.

[0080] The AND gate 221i performs an AND operation between the internal signal s13 as a non-inverting input and the internal signal s14 as an inverting input to generate the internal signal s15. Therefore, if s14 = H (the logic level when masked) holds, then s15 = L (a fixed value) holds, and if s14 = L (the logic level when the masking is released) holds, then s15 = s13 holds. Note that, for example, the internal signal s15 corresponds to the setting signal of the logic unit 221k.

[0081] The AND gate 221j performs an AND operation between the internal signal s16 as a non-inverting input and the internal signal s17 as an inverting input to generate the internal signal s18. Therefore, if s17 = H (the logic level when masked) holds, then s18 = L (a fixed value) holds, and if s17 = L (the logic level when the masking is released) holds, then s18 = s16 holds. Note that, for example, the internal signal s15 corresponds to the reset signal of the logic unit 221k.

[0082] The logic unit 221k generates the reception pulse signal S5 (and thus generates the output pulse signal OUT) based on the internal signals s15 and s18. Specifically, for example, when the internal signal s15 rises to a high level, the logic unit 221k sets the reception pulse signal S5 to a high level, and when the internal signal s18 rises to a high level, the logic unit 221k resets the reception pulse signal S5 to a low level.

[0083] Note that among the components of the above-described pulse reception circuit 221, the buffers 221c to 221f, the delay units 221g and 221h, and the AND gates 221i and 221j function as noise eliminators for reducing the common-mode noise superimposed on the reception pulse signals S3 and S4 via the propagation paths shown by the thin arrow lines in the figure.

[0084] Figure 3 is a diagram showing an example of the noise reduction operation in the first embodiment, in which the input pulse signal IN, the internal signals s11 to s18, and the output pulse signal OUT are shown in the order from top to bottom.

[0085] First, consider the rise of the input pulse signal IN. For example, when the input pulse signal IN is raised to a high level at time t11, the transmission pulse signal S1 (not shown) is driven by a pulse. Therefore, at the next time t12, the normal pulse rises above the threshold voltage Vth of the buffers 221c and 221d in the reception pulse signal S3 (i.e., the internal signal s11) via the transformer 231. As a result, pulses are generated in the internal signals s13 and s17, respectively. In contrast, at time t12, the pulse does not rise in the reception pulse signal S4 (i.e., the internal signal s12), so the internal signals s14 and s16 remain at a low level.

[0086] Note that when the internal signal s14 (i.e., the masking signal) is at a low level, the internal signal s13 (i.e., the main signal) is not masked, but is output as itself as the internal signal s15 (i.e., the setting signal). As a result, at time t12, the output pulse signal OUT is set to a high level.

[0087] In addition, when the internal signal s17 (i.e., the masking signal) is at a high level, the internal signal s18 (i.e., the reset signal) is fixed at a low level regardless of the logic level of the internal signal s16 (i.e., the main signal). However, at time t12, the internal signal s18 should naturally remain at a low level, and thus there is no mismatch.

[0088] Next, consider the fall of the input pulse signal IN. For example, when the input pulse signal IN is lowered to a low level at time t15, the transmission pulse signal S2 (not shown) is driven by a pulse. Therefore, at the next time t16, a normal pulse rises above the threshold voltage Vth of the buffers 221e and 221f in the received pulse signal S4 (i.e., the internal signal s12) via the transformer 232. As a result, pulses are generated in the internal signals s14 and s16, respectively. In contrast, at time t16, the pulse does not rise in the received pulse signal S3 (i.e., the internal signal s11), and thus the internal signals s13 and s17 remain at a low level.

[0089] Note that when the internal signal s17 (i.e., the masking signal) is at a low level, the internal signal s16 (i.e., the main signal) is not masked, but is output as the internal signal s18 (i.e., the reset signal) itself. As a result, at time t16, the output pulse signal OUT is reset to a low level.

[0090] In addition, when the internal signal s14 (i.e., the masking signal) is at a high level, the internal signal s15 (i.e., the setting signal) is fixed at a low level regardless of the logic level of the internal signal s13 (i.e., the main signal). However, at time t16, the internal signal s15 should naturally remain at a low level, and thus there is no mismatch.

[0091] Furthermore, consider the case where common-mode noise is superimposed on each of the received pulse signals S3 and S4 (i.e., the internal signals s11 and s12). For example, at time t14, the noise pulse rises above the threshold voltage Vth of the buffers 221c to 221f in each of the internal signals s11 and s12, and then pulses are generated in the internal signals s13 and s16 (i.e., the main signals) and the internal signals s14 and s17 (i.e., the masking signals), respectively.

[0092] Here, when the internal signal s14 (i.e., the masking signal) is at a high level, the internal signal s15 (i.e., the setting signal) is fixed at a low level regardless of the logic level of the internal signal s13 (i.e., the main signal). Similarly, when the internal signal s17 (i.e., the masking signal) is at a high level, the internal signal s18 (i.e., the reset signal) is fixed at a low level regardless of the logic level of the internal signal s16 (i.e., the main signal). Therefore, the common-mode noise superimposed on each of the received pulse signals S3 and S4 (i.e., the internal signals s11 and s12) can be appropriately reduced, and thus the switching error of the logic level of the output pulse signal OUT can be suppressed.

[0093] Note that in order to safely reduce the common-mode noise, preferably, due to the superimposed noise, the masking time tm1 of the internal signals s14 and s17 (i.e., the masking signals) is greater than the pulse width W1 of the internal signals s13 and s16 (i.e., the main signals), and the masking time tm1 completely overlaps with the pulse width W1.

[0094] In other words, it is preferable to appropriately design the buffers 221c to 221f and the delay units 221g and 221h such that the internal signals s13 and s16 (i.e., the main signals) rise to a high level after the internal signals s14 and s17 (i.e., the masking signals) rise to a high level, and the internal signals s14 and s17 (i.e., the masking signals) fall to a low level after the internal signals s13 and s16 (i.e., the main signals) fall to a low level.

[0095] In addition, during the pulse drive of the internal signals s11 and s12 (i.e., during the reception of normal pulses), the regenerative current flowing in the transformers 231 and 232 makes the internal signals s11 and s12 become negative potentials (i.e., potentials lower than the normal low level) for a specific period. During this negative potential period, if common-mode noise is superimposed, a state may occur in which only one of the internal signals s11 and s12 is higher than the threshold voltage Vth of the buffers 221c to 221f.

[0096] For example, at time t13, when common-mode noise is superimposed on the internal signal s11 during the negative potential period, only the internal signal s12 among the internal signals s11 and s12 is higher than the threshold voltage Vth, and pulses are generated in the internal signals s14 and s16. On the contrary, the internal signal s11 is not higher than the threshold voltage Vth, so the internal signal s17 (i.e., the masking signal) is not triggered to rise to a high level again.

[0097] Therefore, in order to remove the pulses caused by the noise generated in the internal signal s16, the internal signal s17 (i.e., the masking signal) must be maintained at a high level, and the internal signal s17 is already at a high level due to the normal pulse of the internal signal s11.

[0098] Specifically, by setting the high-level period of the internal signal s17 (i.e., the masking time tm1) to be longer than the negative potential period of the internal signal s11, even in the worst case where common-mode noise is superimposed immediately before the end of the negative potential period, pulses caused by noise generated in the internal signal s16 can be appropriately removed.

[0099] Note that although repeated descriptions are omitted, it goes without saying that the above description also applies when common-mode noise is superimposed on the internal signal s12 during the negative potential period.

[0100] <Problems of the First Embodiment>

[0101] Now, in the pulse receiving circuit 221 of the first embodiment, the buffers 221c to 221f formed of CMOS circuits have a high threshold voltage Vth, so high energy is required to transmit signals. As a result, emission noise and power consumption increase. In addition, if the threshold voltage Vth of the buffers 221c to 221f is simply lowered, malfunctions due to noise may easily occur. Therefore, the following description presents a novel second embodiment that can solve the above problems.

[0102] <Signal Transmission Device (Second Embodiment)>

[0103] Figure 4 is a diagram showing a second embodiment of the signal transmission device 200. In this diagram, based on Figure 1 and Figure 2 , the circuit structure of the pulse receiving circuit 221 is modified. In addition, the number of external terminals of the transformer chip 230 is reduced from 8 to 6 (i.e., external terminals T21 to T26). In the following description, the modified points are described in detail.

[0104] First, the modified points of the pulse receiving circuit 221 are described. The pulse receiving circuit 221 of this embodiment includes diodes 221A and 221B, N-channel MOS field-effect transistors 221C and 221D, comparators 221E and 221F, a timer 221G, and a logic unit 221H.

[0105] The diode 221A has a cathode connected to the external terminal T24 of the transformer chip 230. The diode 221A has an anode connected to the external terminal T25 of the transformer chip 230. The diode 221A connected in this way serves as a first electrostatic protection element connected between both ends of the secondary winding 231s of the transformer 231.

[0106] The diode 221B has a cathode connected to the external terminal T26 of the transformer chip 230. The diode 221B has an anode connected to the external terminal T25 of the transformer chip 230. The diode 221B connected in this way serves as a second electrostatic protection element connected between both ends of the secondary winding 232s constituting the transformer 232.

[0107] The transistor 221C has a drain connected to the external terminal T24 of the transformer chip 230. The transistor 221C has a source connected to the external terminal T25 of the transformer chip 230. The transistor 221C has a gate connected to the application terminal of the internal signal s25 (i.e., the output terminal of the timer 221G). Therefore, if s25 = H holds, the transistor 221C conducts, and if s25 = L holds, the transistor 221C turns off. The transistor 221C connected in this way serves as a first switch connected between both ends of the secondary winding 231s constituting the transformer 231.

[0108] The transistor 221D has a drain connected to the external terminal T26 of the transformer chip 230. The transistor 221D has a source connected to the external terminal T25 of the transformer chip 230. The transistor 221D has a gate connected to the application terminal of the internal signal s25 (i.e., the output terminal of the timer 221G). Therefore, if s25 = H holds, the transistor 221D conducts, and if s25 = L holds, the transistor 221D turns off. The transistor 221D connected in this way serves as a second switch connected between both ends of the secondary winding 232s constituting the transformer 232.

[0109] The comparator 221E has a non-inverting input terminal (+) connected to the external terminal T24 of the transformer chip 230. The comparator 221E has an inverting input terminal ( - ) connected to the external terminal T26 of the transformer chip 230. The comparator 221E connected in this way corresponds to a first pulse detector. The comparator 221E receives the received pulse signal S3 (i.e., the internal signal s21) at the secondary winding 231s of the transformer 231 and receives the received pulse signal S4 (i.e., the internal signal s22) at the secondary winding 232s of the transformer 232 as a differential input (i.e., s21 - s22), and compares these signals to generate the internal signal s23. Note that, for example, the internal signal s23 corresponds to a setting signal of the logic unit 221H, and if s21 > s22 holds, the internal signal s23 is at a high level, while if s21 < s22 holds, the internal signal s23 is at a low level.

[0110] Comparator 221F has a non-inverting input terminal (+) connected to the external terminal T26 of the transformer chip 230. Comparator 221F has an inverting input terminal (−) connected to the external terminal T24 of the transformer chip 230. Comparator 221F connected in this way corresponds to the second pulse detector. Comparator 221F receives the received pulse signals S3 and S4 (i.e., internal signals s21 and s22) as differential inputs having an input polarity opposite to that of the inputs of comparator 221E, and compares these signals to generate the internal signal s24. Note that, for example, the internal signal s24 corresponds to the reset signal of the logic unit 221H, and if s21>s22 holds, the internal signal s24 is at a low level, while if s21<s22 holds, the internal signal s24 is at a high level.

[0111] Timer 221G receives the inputs of the internal signals s23 and s24, and sets the internal signal s25 to a high level for a predetermined masking time tm2 from the moment when each signal rises to a high level (corresponding to the pulse detection moment of each pulse detector in the first pulse detector and the second pulse detector), so as to turn on the transistors 221C and 221D.

[0112] Logic unit 221H generates the received pulse signal S5 (and thus generates the output pulse signal OUT) based on the internal signals s23 and s24. Specifically, for example, when the internal signal s23 rises to a high level, the logic unit 221H sets the received pulse signal S5 to a high level, and when the internal signal s24 rises to a high level, the logic unit 221H resets the received pulse signal S5 to a low level.

[0113] Figure 5 is a diagram showing an example of the noise reduction operation in the second embodiment, where the input pulse signal IN, the internal signals s21 to s25, and the output pulse signal OUT are shown in the order from top to bottom.

[0114] First, consider the rise of the input pulse signal IN. For example, when the input pulse signal IN is raised to a high level at time t21, the transmission pulse signal S1 (not shown) is driven by a pulse. Therefore, at the next time t22, a normal pulse rises in the received pulse signal S3 (i.e., the internal signal s21) via the transformer 231. In contrast, at time t22, no pulse rises in the received pulse signal S4 (i.e., the internal signal s12). Therefore, a pulse is generated in the internal signal s23, while the internal signal s24 remains at a low level. As a result, at time t22, the output pulse signal OUT is set to a high level.

[0115] Next, consider the fall of the input pulse signal IN. For example, when the input pulse signal IN drops to a low level at time t25, a transmission pulse signal S2 (not shown) is driven by a pulse. Thus, at the next time t26, a normal pulse rises in the received pulse signal S4 (i.e., the internal signal s22) via the transformer 232. In contrast, at time t26, the pulse does not rise in the received pulse signal S3 (i.e., the internal signal s21). Thus, a pulse is generated in the internal signal s24, while the internal signal s23 remains at a low level. As a result, at time t26, the output pulse signal OUT is reset to a low level.

[0116] In addition, consider the case where common-mode noise is superimposed on each of the received pulse signals S3 and S4 (i.e., the internal signals s21 and s22). For example, at time t24, noise pulses rise in both the internal signals s21 and s22. However, these noise pulses are input to the comparators 221E and 221F in-phase differentially. Thus, almost no unexpected pulses are generated in the internal signals s23 and s24, and thus switching errors in the logic level of the output pulse signal OUT can be suppressed.

[0117] Furthermore, with the structure in which the internal signals s21 and s22 are differentially detected, compared with the above-described first embodiment ( Figure 2 ), the threshold voltage Vth of the pulse receiving circuit 221 (in this figure, the input offset voltages Vofs1 and Vofs2 of the comparators 221E and 221F, respectively) can be set to a smaller value. Thus, common-mode noise can be reduced while suppressing emission noise and power consumption.

[0118] In addition, during the pulse driving of the internal signals s21 and s22 (i.e., during the reception of normal pulses), the regenerative current flowing in the transformers 231 and 232 makes the internal signals s21 and s22 become negative potentials for a specific period (see the dashed lines of the internal signals s21 and s22). When this negative potential period is generated, unnecessary pulses may be generated in the internal signals s23 and s24 generated in the comparators 221E and 221F, resulting in an erroneous detection of the received pulse signal S5 (and thus the output pulse signal OUT).

[0119] Therefore, when a pulse is detected in the internal signal s23 or s24 at time t22 or time t26, the internal signal s25 is set to a high level for a predetermined masking time tm2. In this way, the transistors 221C and 221D are turned on, and both terminals of the secondary windings 231s and 232s are short-circuited, and the differential input of each of the comparators 221E and 221F becomes zero. Thus, generation of unnecessary pulses in the internal signals s23 and s24 can be suppressed.

[0120] Note that the high-level period of the internal signal s25 (i.e., the masking time tm2) is preferably set to be longer than the negative potential periods of the internal signals s21 and s22.

[0121] Figure 6 FIG. is a diagram showing an example of the comparison operation of comparators 221E and 221F, in which the internal signals s21 and s22 (i.e., received pulse signals S3 and S4), the differential input signal COMP1 to the comparator 221E (i.e., s21−s22), the differential input signal COMP2 to the comparator 221F (i.e., s22−s21), and the internal signals s23 and s24 (i.e., the comparison output signals of the comparators 221E and 221F) are shown in order from top to bottom.

[0122] As shown in this figure, the circuits of the comparators 221E and 221F are designed to have input offset voltages Vofs1 and Vofs2, respectively. In other words, if COMP1>Vofs1 holds, the internal signal s23 is at a high level, and if COMP1<Vofs1 holds, the internal signal s23 is at a low level. Additionally, if COMP2>Vofs2 holds, the internal signal s24 is at a high level, and if COMP2<Vofs2 holds, the internal signal s24 is at a low level.

[0123] Therefore, even if the internal signals s21 and s22 change very little, as long as the differential input signals COMP1 and COMP2 are not higher than the input offset voltages Vofs1 and Vofs2, respectively, unnecessary pulses will not be generated in the internal signals s23 and s24. Therefore, false detection (unexpected switching of the logic level) of the output pulse signal OUT can be suppressed.

[0124] <Transformer chip>

[0125] Next, referring again to Figure 4 , the modification points of the transformer chip 230 in the second embodiment will be described. In the transformer chip 230 of this embodiment, compared with the first embodiment ( Figure 2 ), the number of external terminals is reduced from 8 to 6 (i.e., external terminals T21 to T26).

[0126] The primary winding 231p of the transformer 231 is connected between the external terminal T21 and the external terminal T22. The primary winding 232p of the transformer 232 is connected between the external terminal T23 and the external terminal T22. The secondary winding 231s of the transformer 231 is connected between the external terminal T24 and the external terminal T25. The secondary winding 232s of the transformer 232 is connected between the external terminal T26 and the external terminal T25.

[0127] In this manner, the transformer chip 230 includes an external terminal T21 connected to the first terminal of the primary winding 231p, an external terminal T22 connected to the second terminal of the primary winding 231p and the first terminal of the primary winding 232p, an external terminal T23 connected to the second terminal of the primary winding 232p, an external terminal T24 connected to the first terminal of the secondary winding 231s, an external terminal T25 connected to the second terminal of the secondary winding 231s and the first terminal of the secondary winding 232s, and an external terminal T26 connected to the second terminal of the secondary winding 232s.

[0128] Figure 7 FIG. is a diagram showing a structural example of the transformer chip 230 according to the second embodiment. In the transformer chip 230 of this structural example, the transformer 231 includes a primary winding 231p and a secondary winding 231s facing each other in the vertical direction. In addition, the transformer 232 includes a primary winding 232p and a secondary winding 232s facing each other in the vertical direction.

[0129] The primary windings 231p and 232p are formed in the first layer (lower layer) 230a of the transformer chip 230, while the secondary windings 231s and 232s are formed in the second layer (upper layer) 230b of the transformer chip 230. Note that the secondary winding 231s is disposed directly above the primary winding 231p so as to face the primary winding 231p. In addition, the secondary winding 232s is disposed directly above the primary winding 232p so as to face the primary winding 232p.

[0130] The primary winding 231p is formed in a spiral shape starting from the first terminal connected to the internal terminal X21 so as to surround the internal terminal X21 in the clockwise direction, and the second terminal corresponding to the end point is connected to the internal terminal X22. On the contrary, the primary winding 232p is formed in a spiral shape starting from the first terminal connected to the internal terminal X23 so as to surround the internal terminal X23 in the counterclockwise direction, and the second terminal corresponding to the end point is connected to the internal terminal X22. Note that the internal terminals X21, X22, and X23 are linearly aligned in the order shown in the figure.

[0131] The internal terminal X21 is connected to the external terminal T21 in the second layer 230b through the conductive wiring Y21 and the conductive via Z21. The internal terminal X22 is connected to the external terminal T22 in the second layer 230b through the conductive wiring Y22 and the conductive via Z22. The internal terminal X23 is connected to the external terminal T23 in the second layer 230b through the conductive wiring Y23 and the conductive via Z23. Note that the external terminals T21 to T23 are linearly aligned and are used for wire bonding with the controller chip 210.

[0132] The secondary winding 231s is formed in a spiral shape starting from a first terminal connected to the external terminal T24 so as to surround the external terminal T24 in the counterclockwise direction, and a second terminal corresponding to the end point is connected to the external terminal T25. On the contrary, the secondary winding 232s is formed in a spiral shape starting from a first terminal connected to the external terminal T26 so as to surround the external terminal T26 in the clockwise direction, and a second terminal corresponding to the end point is connected to the external terminal T25. Note that the external terminals T24, T25, and T26 are linearly aligned in the order shown in the figure and are used for wire bonding with the driver chip 220.

[0133] The secondary windings 231s and 232s are respectively AC-connected to the primary windings 231p and 232p by magnetic coupling and are DC-insulated from the primary windings 231p and 232p. In other words, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230 and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0134] <Signal transmission device (dual-channelization)>

[0135] Figure 8 It is a diagram showing the dual-channelization of the signal transmission device 200. As shown in this diagram, the signal transmission device 200 has two input terminals IN1 and IN2 and two output terminals OUT1 and OUT2, enabling dual-channel pulse transmission.

[0136] Note that the signal transmission path from the input terminal IN1 via the Schmitt buffer 211(1), the pulse transmission circuit 212, the transformers 231 and 232, the pulse receiving circuit 221, and the driver 222(1) to the output terminal OUT1 is for the first channel. On the contrary, the signal transmission path from the input terminal IN2 via the Schmitt buffer 211(2), the pulse transmission circuit 212, the transformers 233 and 234, the pulse receiving circuit 221, and the driver 222(2) to the output terminal OUT2 is for the second channel.

[0137] In addition to the transformers 231 and 232 for the first channel and the external terminals T21 to T26, the transformer chip 230 further includes transformers 233 and 234 for the second channel and external terminals T31 to T36.

[0138] The transformer 233 includes a primary winding 233p connected between an external terminal T31 and an external terminal T32. The transformer 234 includes a primary winding 234p connected between an external terminal T33 and an external terminal T32. The transformer 233 includes a secondary winding 233s connected between an external terminal T34 and an external terminal T35. The transformer 234 includes a secondary winding 234s connected between an external terminal T36 and an external terminal T35.

[0139] In this way, in addition to the above-described external terminals T21 to T26, the transformer chip 230 further includes an external terminal T31 connected to the first terminal of the primary winding 233p, an external terminal T32 connected to the second terminal of the primary winding 233p and the first terminal of the primary winding 234p, an external terminal T33 connected to the second terminal of the primary winding 234p, an external terminal T34 connected to the first terminal of the secondary winding 233s, an external terminal T35 connected to the second terminal of the secondary winding 233s and the first terminal of the secondary winding 234s, and an external terminal T36 connected to the second terminal of the secondary winding 234s.

[0140] <Dual-channel transformer chip (semiconductor device)>

[0141] Figure 9 is a perspective view showing the semiconductor device 5 that serves as Figure 8 the transformer chip 230 shown. Figure 10 is Figure 9 a plan view of the semiconductor device 5 shown. Figure 11 is a plan view showing Figure 9 a layer of the semiconductor device 5 shown, in which a low-potential coil 22 (corresponding to Figure 8 the primary windings 231p to 234p of the transformers 231 to 234 shown) is formed. Figure 12 is a plan view showing Figure 9 a layer of the semiconductor device 5 shown, in which a high-potential coil 23 (corresponding to Figure 8 the secondary windings 231s to 234s of the transformers 231 to 234 shown) is formed. Figure 13 is a cross-sectional view taken along the line VIII-VIII shown in Figure 12 . Figure 14 is a cross-sectional view taken along the line IX-IX shown in Figure 12 . Figure 15 is Figure 12 an enlarged view of the region X shown in Figure 16 is Figure 12 an enlarged view of the region XI shown in Figure 17 is Figure 12 an enlarged view of the region XII shown in Figure 18 isFigure 13 An enlarged view of region XIII shown in [reference], and a view showing the separation structure 130.

[0142] Reference Figures 9 to 13 , the semiconductor device 5 includes a semiconductor chip 41 having a rectangular parallelepiped shape. The semiconductor chip 41 contains at least one of silicon, a wide-bandgap semiconductor, and a compound semiconductor.

[0143] The wide-bandgap semiconductor is composed of a semiconductor having a wider bandgap than the bandgap of silicon (about 1.12 eV). The wide-bandgap semiconductor preferably has a bandgap of 2.0 eV or wider. The wide-bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a group III-V compound semiconductor. The compound semiconductor may contain at least one of aluminum nitride (AlN), indium nitride (InN), gallium nitride (GaN), and gallium arsenide (GaAs).

[0144] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may be an epitaxial substrate having a laminated structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0145] The semiconductor chip 41 includes a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrilateral shape (a rectangular shape in this embodiment) in a plan view observed along the normal direction Z thereof (hereinafter simply referred to as "in the plan view").

[0146] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend in the first direction X and face each other in the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face each other in the first direction X. The chip sidewalls 44A to 44D have a grounded surface.

[0147] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 includes an insulating main surface 52 and insulating sidewalls 53A to 53D. In the plan view, the insulating main surface 52 is formed in a quadrilateral shape (a rectangular shape in this embodiment) matching the first main surface 42. The insulating main surface 52 extends parallel to the first main surface 42.

[0148] The insulating sidewalls 53A to 53D include a first insulating sidewall 53A, a second insulating sidewall 53B, a third insulating sidewall 53C, and a fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 to the semiconductor chip 41 so as to extend to abut against the chip sidewalls 44A to 44D, respectively. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D, respectively. The insulating sidewalls 53A to 53D each have a grounding surface flush with the chip sidewalls 44A to 44D.

[0149] The insulating layer 51 has a multi-layer insulating laminate structure, which includes a bottom insulating layer 55, a top insulating layer 56, and a plurality (11 in this embodiment) of interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer directly covering the first main surface 42. The top insulating layer 56 is an insulating layer forming the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers provided between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 has a single-layer structure containing silicon oxide. The bottom insulating layer 55 and the top insulating layer 56 may have a thickness greater than or equal to 1 μm and less than or equal to 3 μm (e.g., about 2 μm).

[0150] Each of the plurality of interlayer insulating layers 57 has a laminate structure, which includes a first insulating layer 58 on one side of the bottom insulating layer 55 and a second insulating layer 59 on one side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etch stop layer for the second insulating layer 59. The first insulating layer 58 may have a thickness greater than or equal to 0.1 μm and less than or equal to 1 μm (e.g., about 0.3 μm).

[0151] The second insulating layer 59 is formed on the first insulating layer 58 and contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The second insulating layer 59 may have a thickness greater than or equal to 1 μm and less than or equal to 3 μm (e.g., about 2 μm). The thickness of the second insulating layer 59 is preferably greater than that of the first insulating layer 58.

[0152] The insulating layer 51 may have a total thickness DT greater than or equal to 5 μm and less than or equal to 50 μm. The total thickness DT of the insulating layer 51 and the number of layers of the interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric voltage (dielectric breakdown strength) to be achieved. Additionally, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to specific insulating materials.

[0153] The semiconductor device 5 includes a first functional device 45 formed in an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, a plurality of) transformers 21. In other words, the semiconductor device 5 is constituted by a multi-channel type device including a plurality of transformers 21. The plurality of transformers 21 are formed inside the insulating layer 51 and are spaced apart from insulating sidewalls 53A to 53D. The plurality of transformers 21 are spaced apart in the first direction X.

[0154] Specifically, the plurality of transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D (corresponding to the transformers 231 to 234 shown in Figure 8 ), which are sequentially formed from one side of the insulating sidewall 53C to one side of the insulating sidewall 53D in a plan view. The plurality of transformers 21A to 21D have the same structure. In the following description, the structure of the first transformer 21A is illustrated and described. The descriptions of the structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D are omitted because the description of the structure of the first transformer 21A also applies to the second transformer 21B, the third transformer 21C, and the fourth transformer 21D.

[0155] Referring to Figures 11 to 14 , the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23 (corresponding to the primary winding 231p and the secondary winding 231s of the transformer 231 shown in Figure 8 ). The low-potential coil 22 is formed in the insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region between a bottom insulating layer 55 and a top insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0156] In the insulating layer 51, the low-potential coil 22 is formed on one side of the bottom insulating layer 55 (semiconductor chip 41). Relative to the low-potential coil 22, the high-potential coil 23 is formed in the insulating layer 51 on one side of the top insulating layer 56 (insulating main surface 52). In other words, the high-potential coil 23 faces the semiconductor chip 41 via the low-potential coil 22. The low-potential coil 22 and the high-potential coil 23 are disposed at any positions. In addition, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 via one or more interlayer insulating layers 57.

[0157] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layer 57) is appropriately adjusted according to the dielectric voltage and the electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed in the third interlayer insulating layer 57 starting from the bottom insulating layer 55. In this embodiment, the high-potential coil 23 is formed in the first interlayer insulating layer 57 starting from the top insulating layer 56.

[0158] The low-potential coil 22 is embedded in the interlayer insulating layer 57 so as to penetrate the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that forms a spiral pattern between the first inner end 24 and the first outer end 25. In a plan view, the first spiral portion 26 is formed in an elliptical (oval) spiral shape pattern. In a plan view, the inner edge portion of the first spiral portion 26 defines an elliptical first inner region 66.

[0159] The number of turns of the first spiral portion 26 may be greater than or equal to 5 and less than or equal to 30. The first spiral portion 26 may have a width greater than or equal to 0.1 μm and less than or equal to 5 μm. The first spiral portion 26 preferably has a width greater than or equal to 1 μm and less than or equal to 3 μm. The width of the first spiral portion 26 is defined by the width in a direction perpendicular to the spiral direction. The first spiral portion 26 may have a first winding pitch greater than or equal to 0.1 μm and less than or equal to 5 μm. The first winding pitch is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The first winding pitch is defined by the distance between two adjacent portions of the first spiral portion 26 in a direction perpendicular to the spiral direction.

[0160] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to Figure 11 the shapes shown in etc. The first spiral portion 26 may have a polygonal winding shape such as a rectangular shape or a quadrilateral shape, or a circular shape in a plan view. The first inner region 66 may be defined as a polygonal shape such as a rectangular shape or a quadrilateral shape, or defined as a circular shape in a plan view, corresponding to the winding shape of the first spiral portion 26.

[0161] The low-potential coil 22 may contain at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a laminated structure including a barrier layer and a body layer. The barrier layer defines a recessed area in the interlayer insulating layer 57. The body layer is embedded in the recessed area defined by the barrier layer. The barrier layer may contain at least one of titanium and titanium nitride. The body layer may contain at least one of copper, aluminum, and tungsten.

[0162] The high-potential coil 23 is embedded in the interlayer insulating layer 57 so as to penetrate the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 that forms a spiral-shaped pattern between the second inner end 27 and the second outer end 28. In a plan view, the second spiral portion 29 is formed in an elliptical (oval) spiral shape pattern. In this embodiment, the inner edge portion of the second spiral portion 29 defines an elliptical second inner region 67 in a plan view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0163] The number of turns of the second spiral portion 29 may be greater than or equal to 5 and less than or equal to 30. The number of turns of the second spiral portion 29 is adjusted according to the voltage value to be increased with respect to the number of turns of the first spiral portion 26. The number of turns of the second spiral portion 29 is preferably greater than the number of turns of the first spiral portion 26. Of course, the number of turns of the second spiral portion 29 may be less than or equal to the number of turns of the first spiral portion 26.

[0164] The width of the second spiral portion 29 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The width of the second spiral portion 29 is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The width of the second spiral portion 29 is defined by the width in a direction perpendicular to the spiral direction. The width of the second spiral portion 29 is preferably equal to the width of the first spiral portion 26.

[0165] The second winding pitch of the second spiral portion 29 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The second winding pitch is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The second winding pitch is defined by the distance between two adjacent portions of the second spiral portion 29 in a direction perpendicular to the spiral direction. The second winding pitch is preferably equal to the first winding pitch of the first spiral portion 26.

[0166] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to Figure 12 the shapes shown in etc. The second spiral portion 29 may have a polygonal winding shape such as a rectangular shape or a quadrilateral shape, or a circular shape in a plan view. The second inner region 67 may be defined as a polygonal shape such as a rectangular shape or a quadrilateral shape, or defined as a circular shape in a plan view, corresponding to the winding shape of the second spiral portion 29.

[0167] The high-potential coil 23 is preferably formed of the same conductive material as the low-potential coil 22. In other words, the high-potential coil 23 preferably includes a barrier layer and a body layer similar to those of the low-potential coil 22.

[0168] Reference Figure 10, the semiconductor device 5 includes a plurality of (12 in this embodiment) low-potential terminals 11 (corresponding to the external terminals T21 to T23 and external terminals T31 to T33 shown in Figure 8 respectively), and a plurality of (12 in this embodiment) high-potential terminals 12 (corresponding to the external terminals T24 to T26 and external terminals T34 to T36 shown in Figure 8 respectively). The plurality of low-potential terminals 11 are respectively electrically connected to the low-potential coils 22 of the corresponding transformers 21A to 21D. The plurality of high-potential terminals 12 are respectively electrically connected to the high-potential coils 23 of the corresponding transformers 21A to 21D.

[0169] The plurality of low-potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low-potential terminals 11 are formed in a region on one side of the insulating sidewall 53B that is spaced apart from the plurality of transformers 21A to 21D in the second direction Y and are arranged at intervals in the first direction X.

[0170] The plurality of low-potential terminals 11 include a first low-potential terminal 11A, a second low-potential terminal 11B, a third low-potential terminal 11C, a fourth low-potential terminal 11D, a fifth low-potential terminal 11E, and a sixth low-potential terminal 11F. In this embodiment, each of the plurality of low-potential terminals 11A to 11F is formed in two. The number of the plurality of low-potential terminals 11A to 11F is arbitrary.

[0171] In a plan view, the first low-potential terminal 11A faces the first transformer 21A in the second direction Y. In a plan view, the second low-potential terminal 11B faces the second transformer 21B in the second direction Y. In a plan view, the third low-potential terminal 11C faces the third transformer 21C in the second direction Y. In a plan view, the fourth low-potential terminal 11D faces the fourth transformer 21D in the second direction Y. In a plan view, the fifth low-potential terminal 11E is formed in the region between the first low-potential terminal 11A and the second low-potential terminal 11B. In a plan view, the sixth low-potential terminal 11F is formed in the region between the third low-potential terminal 11C and the fourth low-potential terminal 11D.

[0172] The first low-potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low-potential coil 22). The second low-potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low-potential coil 22). The third low-potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low-potential coil 22). The fourth low-potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low-potential coil 22).

[0173] The fifth low-potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22). The sixth low-potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low-potential coil 22) and the first outer end 25 of the fourth transformer 21D (low-potential coil 22).

[0174] A plurality of high-potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51, spaced apart from the plurality of low-potential terminals 11. Specifically, the plurality of high-potential terminals 12 are formed in a region on one side of the insulating side wall 53A that is spaced apart from the plurality of low-potential terminals 11 in the second direction Y and are arranged at intervals in the first direction X.

[0175] In a plan view, the plurality of high-potential terminals 12 are respectively formed in regions adjacent to the corresponding transformers 21A to 21D. In a plan view, the high-potential terminal 12 being adjacent to the transformers 21A to 21D means that the distance between the high-potential terminal 12 and the transformers 21 is less than the distance between the low-potential terminal 11 and the high-potential terminal 12.

[0176] Specifically, in a plan view, the plurality of high-potential terminals 12 are formed at intervals in the first direction X so as to face the plurality of transformers 21A to 21D in the first direction X. More specifically, in a plan view, the plurality of high-potential terminals 12 are formed at intervals in the first direction X so as to be positioned in the region between the second inner region 67 of the high-potential coil 23 and the adjacent high-potential coil 23. In this way, in a plan view, the plurality of high-potential terminals 12 and the plurality of transformers 21A to 21D are arranged in a line in the first direction X.

[0177] The plurality of high-potential terminals 12 include a first high-potential terminal 12A, a second high-potential terminal 12B, a third high-potential terminal 12C, a fourth high-potential terminal 12D, a fifth high-potential terminal 12E, and a sixth high-potential terminal 12F. In this embodiment, each of the plurality of high-potential terminals 12A to 12F is formed in two. The number of the plurality of high-potential terminals 12A to 12F is arbitrary.

[0178] In the plan view, the first high-potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high-potential coil 23). In the plan view, the second high-potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high-potential coil 23). In the plan view, the third high-potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high-potential coil 23). In the plan view, the fourth high-potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high-potential coil 23). In the plan view, the fifth high-potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B. In the plan view, the sixth high-potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D.

[0179] The first high-potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high-potential coil 23). The second high-potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high-potential coil 23). The third high-potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high-potential coil 23). The fourth high-potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high-potential coil 23).

[0180] The fifth high-potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23). The sixth high-potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high-potential coil 23) and the second outer end 28 of the fourth transformer 21D (high-potential coil 23).

[0181] Reference Figures 11 to 14 , the semiconductor device 5 includes a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, and a second high-potential wiring 34 formed in the insulating layer 51. In this embodiment, a plurality of first low-potential wirings 31, a plurality of second low-potential wirings 32, a plurality of first high-potential wirings 33, and a plurality of second high-potential wirings 34 are formed.

[0182] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coils 22 of the first transformer 21A and the second transformer 21B at the same potential. In addition, the first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coils 22 of the third transformer 21C and the fourth transformer 21D at the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all the low-potential coils 22 of the transformers 21A to 21D at the same potential.

[0183] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coils 23 of the first transformer 21A and the high-potential coils 23 of the second transformer 21B at the same potential. In addition, the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coils 23 of the third transformer 21C and the high-potential coils 23 of the fourth transformer 21D at the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D at the same potential.

[0184] A plurality of first low-potential wirings 31 are respectively electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22). The plurality of first low-potential wirings 31 have the same structure. In the following description, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A is illustrated and described. The description of the structures of the other first low-potential wirings 31 is omitted because the description of the structure of the first low-potential wiring 31 connected to the first transformer 21A applies to the other first low-potential wirings 31.

[0185] The first low-potential wiring 31 includes a through-wiring 71, a low-potential connection wiring 72, a lead wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (a plurality in this embodiment) pad plug electrodes 76, and one or more (a plurality in this embodiment) substrate plug electrodes 77.

[0186] The through-wiring 71, the low-potential connection wiring 72, the lead wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrodes 76, and the substrate plug electrodes 77 are preferably formed of the same conductive material as the low-potential coil 22 and the like. In other words, each of the through-wiring 71, the low-potential connection wiring 72, the lead wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrodes 76, and the substrate plug electrodes 77 preferably includes a barrier layer and a main body layer, similar to the low-potential coil 22 and the like.

[0187] The through-wiring 71 penetrates a plurality of interlayer insulating layers 57 in the insulating layer 51 and extends like a column in the normal direction Z. In this embodiment, the through-wiring 71 is formed in the region between the bottom insulating layer 55 and the top insulating layer 56 in the insulating layer 51. The through-wiring 71 has a top end portion on the side of the top insulating layer 56 and a bottom end portion on the side of the bottom insulating layer 55. The top end portion of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the top insulating layer 56. The bottom end portion of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0188] In this embodiment, the through-wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through-wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are formed of the same conductive material as the low-potential coil 22 or the like. In other words, each of the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 includes a barrier layer and a main body layer, similar to the low-potential coil 22 or the like.

[0189] The first electrode layer 78 forms the top end portion of the through-wiring 71. The second electrode layer 79 forms the bottom end portion of the through-wiring 71. The first electrode layer 78 is formed to be similar to an island and faces the low-potential terminal 11 (the first low-potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed to be similar to an island and faces the first electrode layer 78 in the normal direction Z.

[0190] The plurality of wiring plug electrodes 80 are respectively embedded in a plurality of interlayer insulating layers 57 in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are laminated from the bottom insulating layer 55 to the top insulating layer 56 so as to be electrically connected to each other, and electrically connect the first electrode layer 78 and the second electrode layer 79. The area of the plurality of wiring plug electrodes 80 is smaller than the area of the first electrode layer 78 or the second electrode layer 79.

[0191] The number of layers of the plurality of wiring plug electrodes 80 is equal to the number of layers of the plurality of interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but any number of wiring plug electrodes 80 can be embedded in each interlayer insulating layer 57. Of course, one or more wiring plug electrodes 80 can be formed to penetrate the plurality of interlayer insulating layers 57.

[0192] The low-potential connection wiring 72 is formed in the first internal region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connection wiring 72 is formed to be similar to an island and faces the high-potential terminal 12 (the first high-potential terminal 12A) in the normal direction Z. The low-potential connection wiring 72 preferably has a larger area than the wiring plug electrodes 80. The low-potential connection wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0193] In the interlayer insulating layer 57, the lead wiring 73 is formed in the region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead wiring 73 is formed in the first interlayer insulating layer 57 starting from the bottom insulating layer 55. The lead wiring 73 includes a first terminal portion on one side, a second terminal portion on the other side, and a wiring portion connecting the first terminal portion and the second terminal portion. The first terminal portion of the lead wiring 73 is located in the region between the semiconductor chip 41 and the bottom end portion of the through wiring 71. The second terminal portion of the lead wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connection wiring 72. The wiring portion extends in a strip shape in the region between the first terminal portion and the second terminal portion along the first main surface 42 of the semiconductor chip 41.

[0194] In the interlayer insulating layer 57, the first connection plug electrode 74 is formed in the region between the through wiring 71 and the lead wiring 73, and is electrically connected to the through wiring 71 and the first terminal portion of the lead wiring 73. In the interlayer insulating layer 57, the second connection plug electrode 75 is formed in the region between the low-potential connection wiring 72 and the lead wiring 73, and is electrically connected to the low-potential connection wiring 72 and the second terminal portion of the lead wiring 73.

[0195] In the top insulating layer 56, a plurality of pad plug electrodes 76 are formed in the region between the low-potential terminal 11 (the first low-potential terminal 11A) and the through wiring 71, and are respectively electrically connected to the low-potential terminal 11 and the top end portion of the through wiring 71. In the bottom insulating layer 55, a plurality of substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the lead wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the first terminal portion of the lead wiring 73, and are respectively electrically connected to the semiconductor chip 41 and the first terminal portion of the lead wiring 73.

[0196] Reference Figure 14 , a plurality of second low-potential wirings 32 are respectively electrically connected to the corresponding low-potential terminals 11E and 11F and the first outer ends 25 of the low-potential coils 22 of the corresponding transformers 21A to 21D. The plurality of second low-potential wirings 32 have the same structure. In the following description, the structure of the second low-potential wiring 32 connected to the fifth low-potential terminal 11E and the first transformer 21A (the second transformer 21B) is illustrated and described. The description of the structures of the other second low-potential wirings 32 is omitted because the description of the structure of the second low-potential wiring 32 connected to the first transformer 21A (the second transformer 21B) is applicable to the other second low-potential wirings 32.

[0197] Similar to the first low-potential wiring 31, the second low-potential wiring 32 includes a through-wiring 71, a low-potential connection wiring 72, a lead wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, a pad plug electrode 76, and a substrate plug electrode 77. Except that the low-potential connection wiring 72 is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22), the second low-potential wiring 32 has the same structure as the first low-potential wiring 31.

[0198] The low-potential connection wiring 72 of the second low-potential wiring 32 is formed around the low-potential coil 22 in the same interlayer insulating layer 57 as the low-potential coil 22. Specifically, in a plan view, the low-potential connection wiring 72 is formed in a region between two adjacent low-potential coils 22. In the top insulating layer 56, the pad plug electrode 76 is formed in a region between the low-potential terminal 11 (fifth low-potential terminal 11E) and the low-potential connection wiring 72, and is electrically connected to the low-potential terminal 11 and the low-potential connection wiring 72.

[0199] Reference Figure 13 , a plurality of first high-potential wirings 33 are respectively electrically connected to corresponding high-potential terminals 12A to 12D and the second inner ends 27 of corresponding transformers 21A to 21D (high-potential coils 23). The plurality of first high-potential wirings 33 have the same structure. In the following description, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A is illustrated and described. The description of the structures of the other first high-potential wirings 33 is omitted because the description of the structure of the first high-potential wiring 33 connected to the first transformer 21A is applicable to the other first high-potential wirings 33.

[0200] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (a plurality in this embodiment) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrodes 82 are preferably formed of the same conductive material as the low-potential coil 22 and the like. In other words, similar to the low-potential coil 22 and the like, the high-potential connection wiring 81 and the pad plug electrodes 82 preferably include a barrier layer and a body layer.

[0201] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 in the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed to be island-like and faces the high-potential terminal 12 (the first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connection wiring 81 is spaced from the low-potential connection wiring 72 in the plan view and does not face the low-potential connection wiring 72 in the normal direction Z. In this way, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and thus the dielectric voltage of the insulating layer 51 is increased.

[0202] In the top insulating layer 56, a plurality of pad plug electrodes 82 are formed in the region between the high-potential terminal 12 (the first high-potential terminal 12A) and the high-potential connection wiring 81 and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81. In the plan view, the area of each of the plurality of pad plug electrodes 82 is smaller than the area of the high-potential connection wiring 81.

[0203] Reference Figure 14 , a plurality of second high-potential wirings 34 are respectively electrically connected to the corresponding high-potential terminals 12E and 12F and the second outer ends 28 of the corresponding transformers 21A to 21D (high-potential coils 23). The plurality of second high-potential wirings 34 have the same structure. In the following description, the structure of the second high-potential wiring 34 connected to the fifth high-potential terminal 12E and the first transformer 21A (the second transformer 21B) is illustrated and described. The description of the structures of the other second high-potential wirings 34 is omitted because the description of the structure of the second high-potential wiring 34 connected to the first transformer 21A (the second transformer 21B) is applicable to the other second high-potential wirings 34.

[0204] Similar to the first high-potential wiring 33, the second high-potential wiring 34 includes a high-potential connection wiring 81 and a pad plug electrode 82. Except that the high-potential connection wiring 81 is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23), the second high-potential wiring 34 has the same structure as the first high-potential wiring 33.

[0205] The high-potential connection wiring 81 of the second high-potential wiring 34 is formed to surround the high-potential coil 23 in the same interlayer insulating layer 57 as the high-potential coil 23. In the plan view, the high-potential connection wiring 81 is formed in the region between two adjacent high-potential coils 23 and faces the high-potential terminal 12 (the fifth high-potential terminal 12E) in the normal direction Z. In the plan view, the high-potential connection wiring 81 is spaced from the low-potential connection wiring 72 and does not face the low-potential connection wiring 72 in the normal direction Z.

[0206] In the top insulating layer 56, a plurality of pad plug electrodes 82 are formed in the region between the high potential terminal 12 (the fifth high potential terminal 12E) and the high potential connection wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connection wiring 81.

[0207] Reference Figure 13 and Figure 14 , the distance D1 between the low potential terminal 11 and the high potential terminal 12 is preferably greater than the distance D2 between the low potential coil 22 and the high potential coil 23 (D2 < D1). The distance D1 is preferably greater than the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be greater than or equal to 0.01 and less than or equal to 0.1. The distance D1 is preferably greater than or equal to 100 μm and less than or equal to 500 μm. The distance D2 may be greater than or equal to 1 μm and less than or equal to 50 μm. The distance D2 is preferably greater than or equal to 5 μm and less than or equal to 25 μm. The distances D1 and D2 may have any values and are appropriately adjusted according to the dielectric voltage to be achieved.

[0208] Reference Figures 12 to 17 , the semiconductor device 5 includes dummy patterns 85 embedded in the insulating layer 51 so as to be positioned around the transformers 21A to 21D in a plan view. In Figures 15 to 17 , the dummy patterns 85 are shown by hatched lines. The dummy patterns 85 include conductors. The dummy patterns 85 are preferably formed of the same conductive material as the low potential coil 22 or the like. In other words, similar to the low potential coil 22 or the like, the dummy patterns 85 preferably include a barrier layer and a main body layer.

[0209] The dummy patterns 85 are formed in a pattern different from that of the high potential coil 23 or the low potential coil 22 (a discontinuous pattern) and are independent of the transformers 21A to 21D. In other words, the dummy patterns 85 do not function as the transformers 21A to 21D. The dummy patterns 85 are formed to shield the conductor layer, which shields the electric field between the low potential coil 22 and the high potential coil 23 in the transformers 21A to 21D and suppresses the concentration of the electric field on the high potential coil 23.

[0210] In the plan view of this embodiment, the dummy patterns 85 are patterned with dense lines so as to partially cover and partially expose the area around one or more high potential coils 23. In this embodiment, the dummy patterns 85 are patterned with a line density equal to that per unit area of the high potential coil 23. The line density of the dummy patterns 85 being equal to the line density of the high potential coil 23 means that the line density of the dummy patterns 85 is within the range of ±20% of the line density of the high potential coil 23.

[0211] In the plan view, the dummy pattern 85 is preferably formed in a region adjacent to the high-potential coil 23 with respect to the low-potential terminal 11. In the plan view, the dummy pattern 85 being adjacent to the high-potential coil 23 means that the distance between the dummy pattern 85 and the high-potential coil 23 is smaller than the distance between the dummy pattern 85 and the low-potential terminal 11.

[0212] The depth position of the dummy pattern 85 in the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be alleviated. The dummy pattern 85 is preferably formed in a region adjacent to the high-potential coil 23 in the normal direction Z with respect to the low-potential coil 22. The dummy pattern 85 being adjacent to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is smaller than the distance between the dummy pattern 85 and the low-potential coil 22.

[0213] In this case, the electric field concentration on the high-potential coil 23 can be appropriately suppressed. In the normal direction Z, as the distance between the dummy pattern 85 and the high-potential coil 23 becomes smaller, the electric field concentration on the high-potential coil 23 can be more suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, the electric field concentration on the high-potential coil 23 can be more appropriately suppressed.

[0214] In the plan view, the dummy pattern 85 is preferably formed to surround a plurality of high-potential coils 23 so as to be located in the region between the plurality of adjacent high-potential coils 23. In this case, by using the region between the plurality of adjacent high-potential coils 23, the undesired electric field concentration on the plurality of high-potential coils 23 can be suppressed.

[0215] In the plan view, the dummy pattern 85 is preferably located in the region between the low-potential terminal 11 and the high-potential coil 23. In this case, the undesired continuity between the low-potential terminal 11 and the high-potential coil 23 due to the electric field concentration on the high-potential coil 23 can be suppressed. In the plan view, the dummy pattern 85 is preferably located in the region between the low-potential terminal 11 and the high-potential terminal 12. In this case, the undesired continuity between the low-potential terminal 11 and the high-potential terminal 12 due to the electric field concentration on the high-potential coil 23 can be suppressed.

[0216] In the plan view of this embodiment, the dummy pattern 85 is formed along a plurality of high-potential coils 23 and is located in the regions between the plurality of adjacent high-potential coils 23. Further, in the plan view, the dummy pattern 85 entirely surrounds the region including the plurality of high-potential coils 23 and the plurality of high-potential terminals 12. Further, in the plan view, the dummy pattern 85 is located in the regions between the plurality of low-potential terminals 11A to 11F and the plurality of high-potential coils 23. Further, in the plan view, the dummy pattern 85 is located in the regions between the plurality of low-potential terminals 11A to 11F and the plurality of high-potential terminals 12A to 12F.

[0217] Reference Figures 12 to 17 , the dummy pattern 85 includes a plurality of dummy patterns having different electrical states. The dummy pattern 85 includes a high-potential dummy pattern 86. The high-potential dummy pattern 86 is formed in the insulating layer 51 so as to be positioned around the transformers 21A to 21D in the plan view. The high-potential dummy pattern 86 is formed in a pattern (a discontinuous pattern) different from that of the high-potential coils 23 or the low-potential coils 22 and is independent of the transformers 21A to 21D. In other words, the high-potential dummy pattern 86 does not function as the transformers 21A to 21D.

[0218] In the plan view of this embodiment, the high-potential dummy pattern 86 is patterned with dense lines so as to partially cover and partially expose the region around the high-potential coils 23. In this embodiment, the high-potential dummy pattern 86 is patterned with a line density equal to that per unit area of the high-potential coils 23. The line density of the high-potential dummy pattern 86 being equal to the line density of the high-potential coils 23 means that the line density of the high-potential dummy pattern 86 is within the range of ±20% of the line density of the high-potential coils 23.

[0219] The high-potential dummy pattern 86 blocks the electric field between the low-potential coils 22 and the high-potential coils 23 in the transformers 21A to 21D and suppresses the concentration of the electric field on the high-potential coils 23. Specifically, the high-potential dummy pattern 86 blocks the electric field between the low-potential coils 22 and the high-potential coils 23 so as to keep the electric field leaking to the upper side of the high-potential coils 23 away from the high-potential coils 23. In this way, the concentration of the electric field on the high-potential coils 23 due to the electric field leaking to the upper side of the high-potential coils 23 is suppressed.

[0220] A high-potential dummy pattern 86 is applied with a voltage higher than the voltage applied to the low-potential coil 22. In this way, the voltage drop between the high-potential coil 23 and the high-potential dummy pattern 86 can be suppressed, and thus the electric field concentration on the high-potential coil 23 can be suppressed. The high-potential dummy pattern 86 is preferably applied with the voltage applied to the high-potential coil 23. In other words, the high-potential dummy pattern 86 is preferably fixed to the same potential as the high-potential coil 23. In this way, the voltage drop between the high-potential coil 23 and the high-potential dummy pattern 86 can be safely suppressed, and thus the electric field concentration on the high-potential coil 23 can be appropriately suppressed.

[0221] The depth position of the high-potential dummy pattern 86 in the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. The high-potential dummy pattern 86 is preferably formed in a region adjacent to the high-potential coil 23 in the normal direction Z with respect to the low-potential coil 22. The high-potential dummy pattern 86 being adjacent to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is smaller than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0222] In this case, the electric field concentration on the high-potential coil 23 can be appropriately suppressed. In the normal direction Z, as the distance between the high-potential dummy pattern 86 and the high-potential coil 23 becomes smaller, the electric field concentration on the high-potential coil 23 can be suppressed more. The high-potential dummy pattern 86 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, the electric field concentration on the high-potential coil 23 can be more appropriately suppressed.

[0223] In the plan view, the high-potential dummy pattern 86 is preferably formed in a region adjacent to the high-potential coil 23 with respect to the low-potential terminal 11. In the plan view, the high-potential dummy pattern 86 being adjacent to the high-potential coil 23 means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is smaller than the distance between the high-potential dummy pattern 86 and the low-potential terminal 11.

[0224] In the plan view, the high-potential dummy pattern 86 is preferably formed to surround a plurality of high-potential coils 23 so as to be located in the region between the plurality of adjacent high-potential coils 23. In this case, by using the region between the plurality of adjacent high-potential coils 23, the undesired electric field concentration on the plurality of high-potential coils 23 can be suppressed.

[0225] In the plan view, the high-potential dummy pattern 86 is preferably located in the region between the low-potential terminal 11 and the high-potential coil 23. In this case, the undesired continuity between the low-potential terminal 11 and the high-potential coil 23 due to the electric field concentration on the high-potential coil 23 can be suppressed. In the plan view, the high-potential dummy pattern 86 is preferably located in the region between the low-potential terminal 11 and the high-potential terminal 12. In this case, the undesired continuity between the low-potential terminal 11 and the high-potential terminal 12 due to the electric field concentration on the high-potential coil 23 can be suppressed.

[0226] In the plan view of this embodiment, the high-potential dummy pattern 86 is formed along a plurality of high-potential coils 23 and is located in the regions between the plurality of adjacent high-potential coils 23. Further, in the plan view, the high-potential dummy pattern 86 entirely surrounds the region including the plurality of high-potential coils 23 and the plurality of high-potential terminals 12. Further, in the plan view, the high-potential dummy pattern 86 is located in the regions between the plurality of low-potential terminals 11A to 11F and the plurality of high-potential coils 23. Further, in the plan view, the high-potential dummy pattern 86 is located in the regions between the plurality of low-potential terminals 11A to 11F and the plurality of high-potential terminals 12A to 12F.

[0227] In the plan view, the high-potential dummy pattern 86 forms a pattern around the high-potential terminals 12E and 12F so as to expose the region immediately below the high-potential terminals 12E and 12F in the region between the plurality of adjacent high-potential coils 23. A part of the high-potential dummy pattern 86 may extend in the normal direction Z towards the high-potential terminals 12A to 12F. In this case, similar to the high-potential dummy pattern 86, the high-potential terminals 12E and 12F block the electric field so as to suppress the leakage of the electric field to the upper side of the high-potential coil 23. In other words, the high-potential terminals 12E and 12F are formed as shielding conductor layers so as to suppress the electric field concentration on the high-potential coil 23 together with the high-potential dummy pattern 86.

[0228] The high-potential dummy pattern 86 is preferably formed to have ends. In this case, the formation of a current loop circuit (closed circuit) in the high-potential dummy pattern 86 can be suppressed. In this way, the noise caused by the current flowing in the high-potential dummy pattern 86 is suppressed. Therefore, the undesired electric field concentration due to the noise can be suppressed, and at the same time, the change in the electrical characteristics of the transformers 21A to 21D can be suppressed.

[0229] Specifically, the high-potential dummy pattern 86 includes a first high-potential dummy pattern 87 and a second high-potential dummy pattern 88. In a plan view, the first high-potential dummy pattern 87 is formed in a region between a plurality of adjacent transformers 21A to 21D (a plurality of adjacent high-potential coils 23). In a plan view, the second high-potential dummy pattern 88 is formed in a region outside a region between a plurality of adjacent transformers 21A to 21D (a plurality of high-potential coils 23).

[0230] In the following description, a region between an adjacent first transformer 21A (high-potential coil 23) and a second transformer 21B (high-potential coil 23) is referred to as a first region 89. In addition, a region between the second transformer 21B (high-potential coil 23) and the third transformer 21C (high-potential coil 23) is referred to as a second region 90. In addition, a region between the third transformer 21C (high-potential coil 23) and the fourth transformer 21D (high-potential coil 23) is referred to as a third region 91.

[0231] In this embodiment, the first high-potential dummy pattern 87 is electrically connected to the high-potential terminal 12 (the fifth high-potential terminal 12E) via the first high-potential wiring 33. Specifically, the first high-potential dummy pattern 87 includes a first connection portion 92 connected to the first high-potential wiring 33. The position of the first connection portion 92 is arbitrary. In this way, the first high-potential dummy pattern 87 is fixed to the same potential as the plurality of high-potential coils 23.

[0232] Specifically, the first high-potential dummy pattern 87 includes a first pattern 93 formed in the first region 89, a second pattern 94 formed in the second region 90, and a third pattern 95 formed in the third region 91. In this way, the first high-potential dummy pattern 87 suppresses an electric field leaking to the upper side of the high-potential coils 23 in the first region 89, the second region 90, and the third region 91, so as to suppress electric field concentration on the plurality of adjacent high-potential coils 23.

[0233] In this embodiment, the first pattern 93, the second pattern 94, and the third pattern 95 are formed as a unit and fixed to the same potential. The first pattern 93, the second pattern 94, and the third pattern 95 may be separated from each other as long as they are fixed to the same potential.

[0234] Reference Figure 12 and Figure 15, the first pattern 93 is connected to the first high-potential wiring 33 via the first connection portion 92. In the plan view, the first pattern 93 is formed of dense lines to cover and hide a part of the first region 89. In the plan view, the first pattern 93 is formed in the first region 89, spaced apart from the high-potential terminal 12 (the fifth high-potential terminal 12E), and does not face the high-potential terminal 12 in the normal direction Z. Further, in the plan view, the first pattern 93 is spaced apart from the low-potential connection wiring 72 and does not face the low-potential connection wiring 72 in the normal direction Z. In this way, the insulation distance between the first pattern 93 and the low-potential connection wiring 72 is increased, and the dielectric voltage of the insulating layer 51 is enhanced.

[0235] The first pattern 93 includes a first outer peripheral line 96, a second outer peripheral line 97, and a plurality of first intermediate lines 98. The first outer peripheral line 96 extends in a strip shape along the periphery of the high-potential coil 23 of the first transformer 21A. In the plan view of this embodiment, the first outer peripheral line 96 is formed in the first region 89 as an annular shape with an open end. The width of the open end of the first outer peripheral line 96 is smaller than the width of the high-potential coil 23 in the second direction Y.

[0236] The width of the first outer peripheral line 96 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The width of the first outer peripheral line 96 is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The width of the first outer peripheral line 96 is defined by the width in the direction perpendicular to the extending direction of the first outer peripheral line 96. The width of the first outer peripheral line 96 is preferably equal to the width of the high-potential coil 23. The width of the first outer peripheral line 96 being equal to the width of the high-potential coil 23 means that the width of the first outer peripheral line 96 is within the range of ±20% of the width of the high-potential coil 23.

[0237] The first spacing between the first outer peripheral line 96 and the high-potential coil 23 (the first transformer 21A) may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The first spacing is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The first spacing is preferably equal to the second winding pitch of the high-potential coil 23. The first spacing being equal to the first winding pitch means that the first spacing is within the range of ±20% of the first winding pitch.

[0238] The second outer peripheral line 97 extends in a strip shape along the periphery of the high-potential coil 23 of the second transformer 21B. In the plan view of this embodiment, the second outer peripheral line 97 is formed in the first region 89 as an annular shape with an open end. The width of the open end of the second outer peripheral line 97 is smaller than the width of the high-potential coil 23 in the second direction Y. The width of the open end of the second outer peripheral line 97 faces the open end of the first outer peripheral line 96 along the first direction X.

[0239] The width of the second outer peripheral line 97 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The width of the second outer peripheral line 97 is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The width of the second outer peripheral line 97 is defined by the width in the direction perpendicular to the extending direction of the second outer peripheral line 97. The width of the second outer peripheral line 97 is preferably equal to the width of the high-potential coil 23. The width of the second outer peripheral line 97 being equal to the width of the high-potential coil 23 means that the width of the second outer peripheral line 97 is within the range of ±20% of the width of the high-potential coil 23.

[0240] The second spacing between the second outer peripheral line 97 and the high-potential coil 23 (the second transformer 21B) may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The second spacing is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The second spacing is preferably equal to the second winding pitch of the high-potential coil 23. The second spacing being equal to the second winding pitch means that the second spacing is within the range of ±20% of the second winding pitch.

[0241] In the first region 89, a plurality of first intermediate lines 98 extend in a strip shape in the region between the first outer peripheral line 96 and the second outer peripheral line 97. The plurality of first intermediate lines 98 include at least one (one in this embodiment) first connection line 99 that electrically connects the first outer peripheral line 96 and the second outer peripheral line 97.

[0242] In view of preventing the formation of a current loop circuit, the plurality of first intermediate lines 98 preferably include only one first connection line 99. The position of the first connection line 99 is arbitrary. At least one of the plurality of first intermediate lines 98 is provided with a slit 100 that cuts off the current loop circuit. The position of the slit 100 is appropriately adjusted by designing the plurality of first intermediate lines 98.

[0243] The plurality of first intermediate lines 98 are preferably formed in a strip shape extending in the facing direction of the plurality of high-potential coils 23. In this embodiment, the plurality of first intermediate lines 98 are formed in a strip shape extending in the first direction X and are spaced apart in the second direction Y. In a plan view, the plurality of first intermediate lines 98 are formed in a bar shape extending in the first direction X as a whole.

[0244] Specifically, the plurality of first intermediate lines 98 include a plurality of first lead portions 101 and a plurality of second lead portions 102. The plurality of first lead portions 101 are led out from the first outer peripheral line 96 to the second outer peripheral line 97 in a bar shape. Intervals are formed at the ends of the plurality of first lead portions 101 from the first outer peripheral line 96 toward the second outer peripheral line 97.

[0245] A plurality of second lead portions 102 are led out in a strip shape from the second outer peripheral line 97 toward the first outer peripheral line 96. Intervals are formed at the ends of the plurality of second lead portions 102 from the second outer peripheral line 97 toward the first outer peripheral line 96. In this embodiment, the plurality of second lead portions 102 sandwich one first lead portion 101 therebetween and are alternately spaced apart from the plurality of first lead portions 101 in the second direction Y.

[0246] The plurality of second lead portions 102 may sandwich the plurality of first lead portions 101 therebetween. Additionally, a group of the plurality of second lead portions 102 may be formed adjacent to a group of the plurality of first lead portions 101. The slit 100, the plurality of first lead portions 101, and the plurality of second lead portions 102 suppress the formation of a current loop circuit in the first pattern 93.

[0247] In the second direction Y, the width of the first intermediate line 98 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The width of the first intermediate line 98 is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The width of the first intermediate line 98 is preferably equal to the width of the high - potential coil 23. The width of the first intermediate line 98 being equal to the width of the high - potential coil 23 means that the width of the first intermediate line 98 is within ±20% of the width of the high - potential coil 23.

[0248] The third pitch between two adjacent first intermediate lines 98 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The third pitch is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The third pitch is defined by the distance between a plurality of adjacent first intermediate lines 98 in the second direction Y. The third pitches are preferably equal to each other. The third pitches being equal to each other means that the third pitch is within ±20% of the third pitch. The third pitch is preferably equal to the second winding pitch of the high - potential coil 23. The third pitch being equal to the second winding pitch means that the third pitch is within ±20% of the second winding pitch.

[0249] Reference Figure 12 and Figure 16 , the second pattern 94 is electrically connected to the high - potential terminal 12 via the first high - potential wiring 33. In this embodiment, the second pattern 94 is electrically connected to the first high - potential wiring 33 (the fifth high - potential terminal 12E) via the second outer peripheral line 97 of the first pattern 93. The second pattern 94 forms a pattern with dense lines so as to cover and hide the second region 90.

[0250] The second pattern 94 includes a second outer peripheral line 97, a third outer peripheral line 103, and a plurality of second intermediate lines 104. The third outer peripheral line 103 extends in a strip shape along the periphery of the high-potential coil 23 of the third transformer 21C. In the plan view of this embodiment, the third outer peripheral line 103 is formed as an annular shape with an open end in the third region 91. The width of the open end of the third outer peripheral line 103 is smaller than the width of the high-potential coil 23 of the third transformer 21C in the second direction Y.

[0251] The width of the third outer peripheral line 103 can be greater than or equal to 0.1 μm and less than or equal to 5 μm. The width of the third outer peripheral line 103 is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The width of the third outer peripheral line 103 is defined by the width in the direction perpendicular to the extending direction of the third outer peripheral line 103. The width of the third outer peripheral line 103 is preferably equal to the width of the high-potential coil 23. The width of the third outer peripheral line 103 being equal to the width of the high-potential coil 23 means that the width of the third outer peripheral line 103 is within the range of ±20% of the width of the high-potential coil 23.

[0252] The fourth spacing between the third outer peripheral line 103 and the high-potential coil 23 (the third transformer 21C) can be greater than or equal to 0.1 μm and less than or equal to 5 μm. The fourth spacing is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The fourth spacing is preferably equal to the second winding pitch of the high-potential coil 23. The fourth spacing being equal to the second winding pitch means that the fourth spacing is within the range of ±20% of the second winding pitch.

[0253] In the second region 90, the plurality of second intermediate lines 104 extend in a strip shape in the region between the second outer peripheral line 97 and the third outer peripheral line 103. The plurality of second intermediate lines 104 include at least one (one in this embodiment) second connection line 105 that electrically connects the second outer peripheral line 97 and the third outer peripheral line 103.

[0254] In view of preventing the formation of a current loop circuit, the plurality of second intermediate lines 104 preferably include only one second connection line 105. The width of the second connection line 105 can be greater than the width of another second intermediate line 104. The position of the second connection line 105 is arbitrary. At least one of the plurality of second intermediate lines 104 is provided with a slit 106 for cutting off the current loop circuit. The position of the slit 106 is appropriately adjusted by designing the plurality of second intermediate lines 104.

[0255] The plurality of second intermediate lines 104 are preferably formed in a strip shape extending in the facing direction of the plurality of high-potential coils 23. In this embodiment, the plurality of second intermediate lines 104 are formed in a strip shape extending in the first direction X and are spaced apart in the second direction Y. In the plan view, the plurality of second intermediate lines 104 are formed as a bar extending as a whole in the first direction X.

[0256] Specifically, the plurality of second intermediate lines 104 include a plurality of third lead portions 107 and a plurality of fourth lead portions 108. The plurality of third lead portions 107 are led out in a strip shape from the second outer peripheral line 97 to the third outer peripheral line 103. Intervals are formed at the ends of the plurality of third lead portions 107 that face from the third outer peripheral line 103 toward the second outer peripheral line 97.

[0257] The plurality of fourth lead portions 108 are led out in a strip shape from the third outer peripheral line 103 to the second outer peripheral line 97. Intervals are formed at the ends of the plurality of fourth lead portions 108 that face from the second outer peripheral line 97 toward the third outer peripheral line 103. In this embodiment, one third lead portion 107 is sandwiched by the plurality of fourth lead portions 108, and they are alternately spaced apart in the second direction Y with the plurality of third lead portions 107.

[0258] The plurality of fourth lead portions 108 may sandwich the plurality of third lead portions 107. Additionally, a group of the plurality of fourth lead portions 108 may be formed adjacent to a group of the plurality of third lead portions 107. The slit 106, the plurality of third lead portions 107, and the plurality of fourth lead portions 108 suppress the formation of current loop circuits in the second pattern 94.

[0259] In the second direction Y, the width of the second intermediate line 104 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The width of the second intermediate line 104 is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The width of the second intermediate line 104 is preferably equal to the width of the high-potential coil 23. The width of the second intermediate line 104 being equal to the width of the high-potential coil 23 means that the width of the second intermediate line 104 is within ±20% of the width of the high-potential coil 23.

[0260] The fifth pitch between two adjacent second intermediate lines 104 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The fifth pitch is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The fifth pitch is defined by the distance between a plurality of adjacent second intermediate lines 104 in the second direction Y. The fifth pitches are preferably equal to each other. The fifth pitches being equal to each other means that the fifth pitch is within ±20% of the fifth pitch. The fifth pitch is preferably equal to the second winding pitch of the high-potential coil 23. The fifth pitch being equal to the second winding pitch means that the fifth pitch is within ±20% of the second winding pitch.

[0261] Reference Figure 12 and Figure 17, the third pattern 95 is electrically connected to the first high-potential wiring 33. In this embodiment, the third pattern 95 is electrically connected to the first high-potential wiring 33 via the second pattern 94 and the first pattern 93. The third pattern 95 is formed of dense lines so as to cover and hide a partial area of the third region 91. In a plan view, the third pattern 95 is formed in the third region 91, spaced apart from the high-potential terminal 12 (the sixth high-potential terminal 12F), and does not face the high-potential terminal 12 in the normal direction Z.

[0262] In a plan view, the third pattern 95 is spaced apart from the low-potential connection wiring 72 and does not face the low-potential connection wiring 72 in the normal direction Z. In this way, in the normal direction Z, the insulation distance between the third pattern 95 and the low-potential connection wiring 72 is increased, and the dielectric voltage of the insulating layer 51 is enhanced.

[0263] The third pattern 95 includes a third outer peripheral line 103, a fourth outer peripheral line 109, and a plurality of third intermediate lines 110. The fourth outer peripheral line 109 extends in a strip shape along the periphery of the high-potential coil 23 of the fourth transformer 21D. In the plan view of this embodiment, the fourth outer peripheral line 109 is formed in the third region 91 as an annular shape having an open end. The width of the open end of the fourth outer peripheral line 109 is smaller than the width of the high-potential coil 23 of the fourth transformer 21D in the second direction Y. The open end of the fourth outer peripheral line 109 faces the open end of the third outer peripheral line 103 in the first direction X.

[0264] The width of the fourth outer peripheral line 109 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The width of the fourth outer peripheral line 109 is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The width of the fourth outer peripheral line 109 is defined by the width in a direction perpendicular to the extending direction of the fourth outer peripheral line 109. The fourth outer peripheral line 109 is preferably equal to the width of the high-potential coil 23. The width of the fourth outer peripheral line 109 being equal to the width of the high-potential coil 23 means that the width of the fourth outer peripheral line 109 is within the range of ±20% of the width of the high-potential coil 23.

[0265] The sixth spacing between the fourth outer peripheral line 109 and the high-potential coil 23 (the fourth transformer 21D) may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The sixth spacing is preferably greater than or equal to 1 μm and less than or equal to 3 μm. This means that the sixth spacing is equal to the second winding pitch of the high-potential coil 23. The sixth spacing being equal to the second winding pitch means that the sixth spacing is within the range of ±20% of the second winding pitch.

[0266] In the third region 91, a plurality of third intermediate lines 110 extend in a strip shape in a region between the third outer peripheral line 103 and the fourth outer peripheral line 109. The plurality of third intermediate lines 110 include at least one (one in this embodiment) third connection line 111 that electrically connects the third outer peripheral line 103 and the fourth outer peripheral line 109.

[0267] In view of preventing the formation of a current loop circuit, the plurality of third intermediate lines 110 preferably include only one third connection line 111. The position of the third connection line 111 is arbitrary. At least one of the plurality of third intermediate lines 110 is provided with a slit 112 that cuts off the current loop circuit. The position of the slit 112 is appropriately adjusted by designing the plurality of third intermediate lines 110.

[0268] The plurality of third intermediate lines 110 are preferably formed in a strip shape extending in the facing direction of the plurality of high-potential coils 23. In this embodiment, the plurality of third intermediate lines 110 are formed in a strip shape extending in the first direction X and are spaced apart in the second direction Y. In a plan view, the plurality of third intermediate lines 110 are integrally formed in a bar shape.

[0269] In this embodiment, the plurality of third intermediate lines 110 include a plurality of fifth lead portions 113 and a plurality of sixth lead portions 114. The plurality of fifth lead portions 113 are led out in a bar shape from the third outer peripheral line 103 toward the fourth outer peripheral line 109. Intervals are formed at the ends of the plurality of fifth lead portions 113 that face from the fourth outer peripheral line 109 toward the third outer peripheral line 103.

[0270] The plurality of sixth lead portions 114 are led out in a bar shape from the fourth outer peripheral line 109 toward the third outer peripheral line 103. Intervals are formed at the ends of the plurality of sixth lead portions 114 that face from the third outer peripheral line 103 toward the fourth outer peripheral line 109. In this embodiment, the plurality of sixth lead portions 114 sandwich the fifth lead portions 113 and are alternately spaced apart from the plurality of fifth lead portions 113 in the second direction Y.

[0271] The plurality of sixth lead portions 114 may sandwich the plurality of fifth lead portions 113. Additionally, the group of the plurality of sixth lead portions 114 may be formed adjacent to the group of the plurality of fifth lead portions 113. The slit 112, the plurality of fifth lead portions 113, and the plurality of sixth lead portions 114 suppress the formation of a current loop circuit in the third pattern 95.

[0272] In the second direction Y, the width of the third intermediate line 110 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The width of the third intermediate line 110 is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The width of the third intermediate line 110 is preferably equal to the width of the high-potential coil 23. The width of the third intermediate line 110 being equal to the width of the high-potential coil 23 means that the width of the third intermediate line 110 is within the range of ±20% of the width of the high-potential coil 23.

[0273] The seventh pitch between two adjacent third intermediate lines 110 may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The seventh pitch is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The seventh pitch is defined by the distance between multiple adjacent third intermediate lines 110 in the second direction Y. The seventh pitches are preferably equal to each other. The seventh pitches being equal to each other means that the seventh pitch is within the range of ±20% of the seventh pitch. The seventh pitch is preferably equal to the second winding pitch of the high-potential coil 23. The seventh pitch being equal to the second winding pitch means that the seventh pitch is within the range of ±20% of the second winding pitch.

[0274] Reference Figures 12 to 17 , in this embodiment, the second high-potential dummy pattern 88 is electrically connected to the high-potential terminal 12 via the first high-potential dummy pattern 87. Specifically, the second high-potential dummy pattern 88 includes a second connection portion 115 connected to the first high-potential dummy pattern 87. The position of the second connection portion 115 is arbitrary. In this way, the second high-potential dummy pattern 88 is fixed to the same potential as the plurality of high-potential coils 23.

[0275] The second high-potential dummy pattern 88 suppresses the electric field on the upper side of the high-potential coil 23 leaking into the regions outside the first region 89, the second region 90, and the third region 91, and suppresses the electric field concentration on the plurality of high-potential coils 23. In this embodiment, the second high-potential dummy pattern 88 entirely surrounds the region including the plurality of high-potential coils 23 and the plurality of high-potential terminals 12A to 12F in the plan view. In the plan view of this embodiment, the second high-potential dummy pattern 88 is formed in an elliptical (oval) ring shape.

[0276] In this way, in the plan view, the second high-potential dummy pattern 88 is located in the region between the plurality of low-potential terminals 11A to 11F and the plurality of high-potential coils 23. Additionally, in the plan view, the second high-potential dummy pattern 88 is located in the region between the plurality of low-potential terminals 11A to 11F and the plurality of high-potential terminals 12A to 12F.

[0277] The second highest potential dummy pattern 88 includes a plurality of (six in this embodiment) high potential lines 116A, 116B, 116C, 116D, 116E, and 116F. The number of high potential lines is adjusted according to the electric field to be mitigated. The plurality of high potential lines 116A to 116F are sequentially spaced apart in a direction separated from the plurality of high potential coils 23.

[0278] In a plan view, the plurality of high potential lines 116A to 116F as a whole surround the plurality of high potential coils 23. Specifically, in a plan view, the plurality of high potential lines 116A to 116F as a whole surround the region including the plurality of high potential coils 23 and the plurality of high potential terminals 12A to 12F. In the plan view of this embodiment, the plurality of high potential lines 116A to 116F are formed in an oval (ovoid) ring shape.

[0279] Each of the plurality of high potential lines 116A to 116F includes a slit 117 that cuts off the current loop circuit. The position of the slit 117 is appropriately adjusted by designing the plurality of high potential lines 116A to 116F.

[0280] The width of the high potential lines 116A to 116F can be greater than or equal to 0.1 μm and less than or equal to 5 μm. The width of the high potential lines 116A to 116F is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The width of the high potential lines 116A to 116F is defined by the width in a direction perpendicular to the extending direction of the high potential lines 116A to 116F. The width of the high potential lines 116A to 116F is preferably equal to the width of the high potential coils 23. The width of the high potential lines 116A to 116F being equal to the width of the high potential coils 23 means that the width of the high potential lines 116A to 116F is within ±20% of the width of the high potential coils 23.

[0281] The eighth spacing between two adjacent high potential lines 116A to 116F can be greater than or equal to 0.1 μm and less than or equal to 5 μm. The eighth spacing is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The eighth spacings are preferably equal to each other. The eighth spacings being equal to each other means that the eighth spacings are within ±20% of the eighth spacing.

[0282] The ninth spacing between the adjacent first highest potential dummy pattern 87 and second highest potential dummy pattern 88 can be greater than or equal to 0.1 μm and less than or equal to 5 μm. The ninth spacing is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The ninth spacing is preferably equal to the second winding pitch of the high potential coils 23. The ninth spacing being equal to the second winding pitch means that the ninth spacing is within ±20% of the second winding pitch. The number or the width, spacing, etc. of the high potential lines 116A to 116F are arbitrary and are adjusted according to the electric field to be mitigated.

[0283] ReferenceFigures 12 to 17 In the plan view, the dummy pattern 85 includes a floating dummy pattern 121 formed in the insulating layer 51 in an electrically floating state so as to be positioned around the transformers 21A to 21D. The floating dummy pattern 121 is formed in a pattern (a discontinuous pattern) different from those of the high-potential coil 23 and the low-potential coil 22 and is independent of the transformers 21A to 21D. In other words, the floating dummy pattern 121 does not function as the transformers 21A to 21D.

[0284] In the plan view of this embodiment, the floating dummy pattern 121 is formed in a pattern of dense lines so as to partially cover and partially expose the area around the high-potential coil 23. The floating dummy pattern 121 may be formed to have ends or may be formed to have no ends.

[0285] The floating dummy pattern 121 is formed in a pattern with a line density per unit area equal to that of the high-potential coil 23. That the line density of the floating dummy pattern 121 is equal to the line density of the high-potential coil 23 means that the line density of the floating dummy pattern 121 is within the range of ±20% of the line density of the high-potential coil 23.

[0286] In addition, the floating dummy pattern 121 is formed in a pattern with a line density per unit area equal to that of the high-potential dummy pattern 86. That the line density of the floating dummy pattern 121 is equal to the line density of the high-potential dummy pattern 86 means that the line density of the floating dummy pattern 121 is within the range of ±20% of the line density of the high-potential dummy pattern 86.

[0287] The floating dummy pattern 121 blocks the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D so as to suppress the electric field concentration on the high-potential coil 23. Specifically, the floating dummy pattern 121 disperses the electric field leaking to the upper side of the high-potential coil 23 in a direction separating from the high-potential coil 23. In this way, the electric field concentration on the high-potential coil 23 can be suppressed.

[0288] In addition, the floating dummy pattern 121 disperses the electric field leaking to the upper side of the high-potential dummy pattern 86 around the high-potential dummy pattern 86 in a direction separating from the high-potential coil 23 and the high-potential dummy pattern 86. In this way, the electric field concentration on the high-potential dummy pattern 86 can be suppressed, and the electric field concentration on the high-potential coil 23 can be appropriately suppressed.

[0289] The depth position of the floating dummy pattern 121 in the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. The floating dummy pattern 121 is preferably formed in a region adjacent to the high-potential coil 23 in the normal direction Z with respect to the low-potential coil 22. The floating dummy pattern 121 being adjacent to the high-potential coil 23 in the normal direction Z means that the distance between the floating dummy pattern 121 and the high-potential coil 23 is smaller than the distance between the floating dummy pattern 121 and the low-potential coil 22 in the normal direction Z.

[0290] In this case, the electric field concentration on the high-potential coil 23 can be appropriately suppressed. In the normal direction Z, as the distance between the floating dummy pattern 121 and the high-potential coil 23 becomes smaller, more suppression of the electric field concentration on the high-potential coil 23 can be achieved. The floating dummy pattern 121 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, the electric field concentration on the high-potential coil 23 can be more appropriately suppressed.

[0291] In the plan view, the floating dummy pattern 121 is preferably located in the region between the low-potential terminal 11 and the high-potential coil 23. In this case, the undesired continuity between the low-potential terminal 11 and the high-potential coil 23 due to the electric field concentration on the high-potential coil 23 can be suppressed. In the plan view, the floating dummy pattern 121 is preferably located in the region between the low-potential terminal 11 and the high-potential terminal 12. In this case, the undesired continuity between the low-potential terminal 11 and the high-potential terminal 12 due to the electric field concentration on the high-potential coil 23 can be suppressed.

[0292] In the plan view of this embodiment, the floating dummy pattern 121 is formed along a plurality of high-potential coils 23. Specifically, in the plan view, the floating dummy pattern 121 entirely surrounds the region including a plurality of high-potential coils 23 and a plurality of high-potential terminals 12. In the plan view of this embodiment, the floating dummy pattern 121 surrounds the region including a plurality of high-potential coils 23 and a plurality of high-potential terminals 12 with the high-potential dummy pattern 86 (second high-potential dummy pattern 88) sandwiched therebetween.

[0293] In this way, in the plan view, the floating dummy pattern 121 is located in the region between the plurality of low-potential terminals 11A to 11F and the plurality of high-potential coils 23. Additionally, in the plan view, the floating dummy pattern 121 is located in the region between the plurality of low-potential terminals 11A to 11F and the plurality of high-potential terminals 12A to 12F.

[0294] The number of floating lines is arbitrary and is adjusted according to the electric field to be mitigated. In this embodiment, the floating dummy pattern 121 includes a plurality of (six in this embodiment) floating lines 122A, 122B, 122C, 122D, 122E, and 122F. The plurality of floating lines 122A to 122F are sequentially spaced apart in a direction separated from the plurality of high-potential coils 23.

[0295] In a plan view, the plurality of floating lines 122A to 122F surround the plurality of high-potential coils 23 as a whole. Specifically, in a plan view, the plurality of floating lines 122A to 122F surround as a whole a region including the plurality of high-potential coils 23 and the plurality of high-potential terminals 12A to 12F sandwiching the high-potential dummy pattern 86. In the plan view of this embodiment, the plurality of floating lines 122A to 122F are formed in an elliptical (oval) ring shape.

[0296] The width of the floating lines 122A to 122F can be greater than or equal to 0.1 μm and less than or equal to 5 μm. The width of the floating lines 122A to 122F is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The width of the floating lines 122A to 122F is defined by the width in a direction perpendicular to the extending direction of the floating lines 122A to 122F.

[0297] The tenth pitch between two adjacent floating lines 122A to 122F can be greater than or equal to 0.1 μm and less than or equal to 5 μm. The tenth pitch is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The width of the floating lines 122A to 122F is preferably equal to the width of the high-potential coil 23. The width of the floating lines 122A to 122F being equal to the width of the high-potential coil 23 means that the width of the floating lines 122A to 122F is within the range of ±20% of the width of the high-potential coil 23.

[0298] The eleventh pitch between the floating dummy pattern 121 and the high-potential dummy pattern 86 (second high-potential dummy pattern 88) can be greater than or equal to 0.1 μm and less than or equal to 5 μm. The eleventh pitch is preferably greater than or equal to 1 μm and less than or equal to 3 μm. The eleventh pitches are preferably equal to each other. The eleventh pitches being equal to each other means that the eleventh pitch is within the range of ±20% of the eleventh pitch.

[0299] The eleventh pitch is preferably equal to the second winding pitch of the high-potential coil 23. The eleventh pitch between the floating lines 122A to 122F being equal to the second winding pitch means that the eleventh pitch is within the range of ±20% of the second winding pitch. For clarity, Figures 10 to 12 An example where the eleventh pitch is greater than the second winding pitch is shown.

[0300] The twelfth pitch between the floating dummy pattern 121 and the high-potential dummy pattern 86 is preferably equal to the second winding pitch. The twelfth pitch being equal to the second winding pitch means that the twelfth pitch is within the range of ±20% of the second winding pitch. The number or the width, pitch, etc. of the plurality of floating lines 122A to 122F are adjusted according to the electric field to be mitigated and are not limited to specific values.

[0301] Reference Figure 13 and Figure 14 , the semiconductor device 5 includes a second functional device 60 formed in the device region 62 on the first main surface 42 of the semiconductor chip 41. The second functional device 60 is formed by using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region on the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (bottom insulating layer 55). In Figure 8 and Figure 9 , the second functional device 60 is simplified and shown by a dashed line on the surface layer portion of the first main surface 42.

[0302] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring and is electrically connected to the high-potential terminal 12 via a high-potential wiring. Except for forming a pattern in the insulating layer 51 for connection to the second functional device 60, the low-potential wiring has the same structure as the first low-potential wiring 31 (second low-potential wiring 32). Except for forming a pattern in the insulating layer 51 for connection to the second functional device 60, the high-potential wiring has the same structure as the first high-potential wiring 33 (second high-potential wiring 34). The detailed description of the low-potential wiring and the high-potential wiring of the second functional device 60 is omitted.

[0303] The second functional device 60 may include at least one of a passive device, a semiconductor rectifier device, and a semiconductor switching device. The second functional device 60 may include a circuit network in which any two or more of the passive device, the semiconductor rectifier device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0304] The passive device may include a semiconductor passive device. The passive device may include one or both of a resistor and a capacitor. The semiconductor rectifier device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a bipolar junction transistor (BJT), a metal-insulator field effect transistor (MISFET), an insulated gate bipolar junction transistor (IGBT), and a junction field effect transistor (JFET).

[0305] Reference Figure 13 and Figure 14 ,the semiconductor device 5 further includes a sealing conductor 61 embedded in the insulating layer 51. The sealing conductor 61 is embedded in the insulating layer 51 in a form similar to a wall spaced apart from the insulating sidewalls 53A to 53D in a plan view so as to divide the insulating layer 51 into a device region 62 and an external region 63. The sealing conductor 61 prevents moisture or cracks from invading the device region 62 from the external region 63.

[0306] The device region 62 is a region including the first functional device 45 (a plurality of transformers 21), the second functional device 60, a plurality of low-potential terminals 11, a plurality of high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and a dummy pattern 85. The external region 63 is a region outside the device region 62.

[0307] The sealing conductor 61 is electrically cut off from the device region 62. Specifically, the sealing conductor 61 is electrically cut off from the first functional device 45 (a plurality of transformers 21), the second functional device 60, a plurality of low-potential terminals 11, a plurality of high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. More specifically, the sealing conductor 61 is fixed in an electrically floating state. The sealing conductor 61 does not form a current path connected to the device region 62.

[0308] In a plan view, the sealing conductor 61 is formed in a strip shape along the insulating sidewalls 53A to 53D. In the plan view of this embodiment, the sealing conductor 61 is formed in a quadrilateral ring shape (specifically, a rectangular ring shape). In this way, the sealing conductor 61 defines the device region 62 in a quadrilateral ring shape (specifically, a rectangular ring shape) in a plan view. In addition, in a plan view, the sealing conductor 61 defines the external region 63 in a quadrilateral ring shape (specifically, a rectangular ring shape) surrounding the device region 62.

[0309] Specifically, the sealing conductor 61 includes a top end portion on one side of the insulating main surface 52, a bottom end portion on the side of the semiconductor chip 41, and a wall portion extending like a wall between the top end portion and the bottom end portion. In this embodiment, a space is formed in the top end portion of the sealing conductor 61 from the insulating main surface 52 toward the semiconductor chip 41, and the top end portion of the sealing conductor 61 is located in the insulating layer 51. In this embodiment, the top end portion of the sealing conductor 61 is covered with a top insulating layer 56. The top end portion of the sealing conductor 61 may be covered with one or more interlayer insulating layers 57. The top end portion of the sealing conductor 61 may be exposed from the top insulating layer 56. A space is formed in the bottom end portion of the sealing conductor 61 from the semiconductor chip 41 toward the top end portion.

[0310] Thus, in this embodiment, the sealing conductor 61 is embedded in the insulating layer 51 so as to be positioned on one side of the semiconductor chip 41 with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12. Further, the sealing conductor 61 faces the first functional device 45 (the plurality of transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating main surface 52 in the insulating layer 51. The sealing conductor 61 may face a part of the second functional device 60 in a direction parallel to the insulating main surface 52 in the insulating layer 51.

[0311] The sealing conductor 61 includes a plurality of sealing plug conductors 64 and one or more (a plurality in this embodiment) sealing via conductors 65. The number of the sealing via conductors 65 is arbitrary. The top sealing plug conductor 64 among the plurality of sealing plug conductors 64 forms the top end portion of the sealing conductor 61. Each of the plurality of sealing via conductors 65 forms the bottom end portion of the sealing conductor 61. The sealing plug conductor 64 and the sealing via conductor 65 are preferably made of the same conductive material as the low potential coil 22. In other words, the sealing plug conductor 64 and the sealing via conductor 65 preferably include a barrier layer and a main body layer, similar to the low potential coil 22 and the like.

[0312] In a plan view, the plurality of sealing plug conductors 64 are respectively embedded in the plurality of interlayer insulating layers 57 and are all formed in a quadrilateral ring shape (specifically, a rectangular ring shape) surrounding the device region 62. The plurality of sealing plug conductors 64 are laminated from the bottom insulating layer 55 to the top insulating layer 56 so as to be connected to each other. The number of layers of the plurality of sealing plug conductors 64 is equal to the number of layers of the plurality of interlayer insulating layers 57. Of course, one or more sealing plug conductors 64 penetrating the plurality of interlayer insulating layers 57 may be formed.

[0313] As long as the plurality of sealing plug conductors 64 jointly form a ring of the sealing conductor 61, it is not necessary to form all of the plurality of sealing plug conductors 64 in a ring shape. For example, at least one of the plurality of sealing plug conductors 64 may be formed to have an end portion. Further, at least one of the plurality of sealing plug conductors 64 may be divided into a plurality of strip-like portions having end portions. However, in view of the risk of moisture and cracks invading the device region 62, it is preferable that the plurality of sealing plug conductors 64 are formed without end portions (in a ring shape).

[0314] In the bottom insulating layer 55, a plurality of hermetic via conductors 65 are all formed in a region between the semiconductor chip 41 and the hermetic plug conductor 64. The plurality of hermetic via conductors 65 are formed to be spaced apart from the semiconductor chip 41 and are connected to the hermetic plug conductor 64. The plurality of hermetic via conductors 65 have an area smaller than that of the hermetic plug conductor 64. If a single hermetic via conductor 65 is formed, the area of the single hermetic via conductor 65 may be larger than that of the hermetic plug conductor 64.

[0315] The width of the hermetic conductor 61 may be greater than or equal to 0.1 μm and less than or equal to 10 μm. The width of the hermetic conductor 61 is preferably greater than or equal to 1 μm and less than or equal to 5 μm. The width of the hermetic conductor 61 is defined by the width in a direction perpendicular to the extending direction of the hermetic conductor 61.

[0316] Reference Figure 13 、 Figure 14 and Figure 18 Furthermore, the semiconductor device 5 further includes a separation structure 130 located between the semiconductor chip 41 and the hermetic conductor 61 to electrically disconnect the hermetic conductor 61 from the semiconductor chip 41. The separation structure 130 preferably includes an insulator. In this embodiment, the separation structure 130 is constituted by a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0317] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably constituted by a local oxidation of silicon (LOCOS) film, as an example of an oxide film formed by oxidation of the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as the semiconductor chip 41 and the hermetic conductor 61 can be insulated. The thickness of the field insulating film 131 may be greater than or equal to 0.1 μm and less than or equal to 5 μm.

[0318] The separation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a strip shape along the hermetic conductor 61 in a plan view. In the plan view of this embodiment, the separation structure 130 is formed in a quadrilateral ring shape (specifically, a rectangular ring shape). The separation structure 130 includes a connecting portion 132 connected to the bottom end portion of the hermetic conductor 61 (hermetic via conductor 65). The connecting portion 132 may be formed as an anchoring portion of the bottom end portion of the hermetic conductor 61 (hermetic via conductor 65), and this anchoring portion sinks into one side of the semiconductor chip 41. Of course, the connecting portion 132 may be formed flush with the main surface of the separation structure 130.

[0319] The separation structure 130 includes an inner end portion 130A located on one side of the device region 62, an outer end portion 130B located on one side of the external region 63, and a main body portion 130C located between the inner end portion 130A and the outer end portion 130B. In a plan view, the inner end portion 130A defines a region (i.e., the device region 62) where the second functional device 60 is formed. The inner end portion 130A may be integrally formed with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0320] The outer end portion 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is in contact with the chip sidewalls 44A to 44D of the semiconductor chip 41. Specifically, the outer end portion 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end portion 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in another embodiment, the outer end portion 130B may be formed to be spaced apart from the chip sidewalls 44A to 44D in the first main surface 42.

[0321] The main body portion 130C has a flat surface that extends substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body portion 130C includes a connection portion 132 that is connected to the bottom end portion of the sealing conductor 61 (sealing via conductor 65). The connection portion 132 is formed as a portion that is spaced apart from the inner end portion 130A and the outer end portion 130B in the main body portion 130C. The separation structure 130 may have various forms other than the field insulating film 131.

[0322] Reference Figure 13 and Figure 14 FIGS., the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating main surface 52 of the insulating layer 51 to cover the sealing conductor 61. The inorganic insulating layer 140 may be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 on the insulating main surface 52.

[0323] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains undoped silicate glass (USG) as impurity-free silicon oxide. The thickness of the first inorganic insulating layer 141 may be greater than or equal to 50 nm and less than or equal to 5,000 nm. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be greater than or equal to 500 nm and less than or equal to 5,000 nm. By increasing the total thickness of the inorganic insulating layer 140, the dielectric voltage on the high-potential coil 23 can be enhanced.

[0324] If the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the dielectric breakdown voltage (V / cm) of USG is higher than that of silicon nitride. Therefore, when thickening the inorganic insulating layer 140, it is preferable to form the first inorganic insulating layer 141 having a thickness greater than that of the second inorganic insulating layer 142.

[0325] The first inorganic insulating layer 141 may include at least one of boron-doped phosphosilicate glass (BPSG) and phosphosilicate glass (PSG) as an example of silicon oxide. However, in this case, since impurities (boron or phosphorus) are contained in the silicon oxide, it is preferable to form the first inorganic insulating layer 141 made of USG, especially for increasing the dielectric voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure composed of one of the first inorganic insulating layer 141 and the second inorganic insulating layer 142.

[0326] The inorganic insulating layer 140 covers the entire area of the sealed conductor 61 and includes a plurality of low-potential pad openings 143 and a plurality of high-potential pad openings 144 formed in the area outside the sealed conductor 61. The plurality of low-potential pad openings 143 respectively expose a plurality of low-potential terminals 11. The plurality of high-potential pad openings 144 respectively expose a plurality of high-potential terminals 12. The inorganic insulating layer 140 may include an overlapping portion overlapping the periphery of the low-potential terminal 11. The inorganic insulating layer 140 may include an overlapping portion overlapping the periphery of the high-potential terminal 12.

[0327] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be greater than or equal to 1 μm and less than or equal to 50 μm.

[0328] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. In addition, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably greater than or equal to the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably greater than or equal to 2 μm and less than or equal to 10 μm. Additionally, the thickness of the organic insulating layer 145 is preferably greater than or equal to 5 μm and less than or equal to 50 μm. With this structure, thickening of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, and the dielectric voltage on the high-potential coil 23 can be appropriately increased by the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145.

[0329] The organic insulating layer 145 includes a first portion 146 that covers the region on the low potential side and a second portion 147 that covers the region on the high potential side. The first portion 146 covers the sealing conductor 61 via the inorganic insulating layer 140. The first portion 146 includes a plurality of low potential terminal holes 148 that respectively expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the sealing conductor 61. The first portion 146 may include an overlapping portion that overlaps the periphery (overlapping portion) of the low potential pad opening 143.

[0330] The second portion 147 is spaced from the first portion 146 and exposes the inorganic insulating layer 140 between itself and the first portion 146. The second portion 147 includes a plurality of high potential terminal holes 149 that respectively expose a plurality of high potential terminals 12 (high potential pad openings 144). The second portion 147 may include an overlapping portion that overlaps the periphery (overlapping portion) of the high potential pad opening 144.

[0331] The second portion 147 entirely covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 entirely covers a plurality of high potential coils 23, a plurality of high potential terminals 12, a first high potential dummy pattern 87, a second high potential dummy pattern 88, and a floating dummy pattern 121.

[0332] If the organic insulating layer 145 is not formed, the filler contained in the package body 2 (molded resin) may damage a plurality of high potential coils 23, a plurality of high potential terminals 12, the sealing conductor 61, the first high potential dummy pattern 87, the second high potential dummy pattern 88, or the floating dummy pattern 121. This type of damage is called filler erosion.

[0333] The organic insulating layer 145 protects a plurality of high potential coils 23, a plurality of high potential terminals 12, the sealing conductor 61, the first high potential dummy pattern 87, the second high potential dummy pattern 88, and the floating dummy pattern 121 from the filler contained in the package body 2 (molded resin). The slit between the first portion 146 and the second portion 147 serves as an anchoring portion of the package body 2 (molded resin).

[0334] A part of the package body 2 (molded resin) enters the slit between the first portion 146 and the second portion 147 and is connected to the inorganic insulating layer 140. In this way, the adhesion of the package body 2 (molded resin) to the semiconductor device 5 can be enhanced. Of course, the first portion 146 and the second portion 147 may be integrally formed. Additionally, the organic insulating layer 145 may include only one of the first portion 146 and the second portion 147. However, in this case, attention should be paid to filler erosion.

[0335] Embodiments of the present invention can be implemented in another form. The above embodiments illustrate examples of forming the first functional device 45 and the second functional device 60. However, a form that does not include the first functional device 45 but only includes the second functional device 60 can be adopted. In this case, the dummy pattern 85 can be removed. With this structure, the same effects as those of the second functional device 60 described in the first embodiment (except for the effects of the dummy pattern 85) can be achieved.

[0336] In other words, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, an undesired continuity between the high-potential terminal 12 and the sealing conductor 61 can be suppressed. Additionally, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, an undesired continuity between the low-potential terminal 11 and the sealing conductor 61 can be suppressed.

[0337] Furthermore, the above embodiments illustrate examples of forming the second functional device 60. However, the second functional device 60 is not always necessary and can also be removed.

[0338] Moreover, the above embodiments illustrate examples of forming the dummy pattern 85. However, the dummy pattern 85 is not always necessary and can also be removed.

[0339] In addition, the above embodiments illustrate an example in which the first functional device 45 is a multi-channel type including a plurality of transformers 21. However, a single-channel type first functional device 45 including a single transformer 21 can be adopted.

[0340] <Summary>

[0341] The various embodiments described above are outlined below.

[0342] For example, the signal transmission device disclosed in this specification has a structure including a first pulse detector, a second pulse detector, and a logic unit. The first pulse detector is arranged to receive a differential input between a first received pulse signal at the secondary winding of a first transformer and a second received pulse signal at the secondary winding of a second transformer. The second pulse detector is arranged to receive a differential input between the first received pulse signal and the second received pulse signal, where the input polarity is opposite to that of the first pulse detector. The logic unit is arranged to generate a received pulse signal based on the output signals of the first pulse detector and the second pulse detector (the first structure).

[0343] Note that the pulse receiving circuit of the above first structure can have a structure in which the first pulse detector and the second pulse detector are each a comparator with an input offset (the second structure).

[0344] In addition, the pulse receiving circuit of the first structure or the second structure may have a structure further including a first switch, a second switch, and a timer. The first switch and the second switch are respectively connected between both ends of the secondary windings of the first transformer and the second transformer; the timer turns on the first switch and the second switch respectively for a predetermined masking period starting from the pulse detection moments of the first pulse detector and the second pulse detector (third structure).

[0345] In addition, the pulse receiving circuit of any one of the first structure to the third structure may have a structure further including a first electrostatic protection element and a second electrostatic protection element respectively connected between both ends of the secondary windings of the first transformer and the second transformer (fourth structure).

[0346] In addition, the pulse receiving circuit of any one of the first structure to the fourth structure may have the following structure, in which the logic unit sets the received pulse signal to a first logic level according to the first received pulse signal, and sets the received pulse signal to a second logic level according to the second received pulse signal (fifth structure).

[0347] In addition, for example, the signal transmission device disclosed in this specification has a structure including a pulse transmission circuit, a first transformer and a second transformer, a pulse receiving circuit of any one of the first structure to the fifth structure, and a driver. The pulse transmission circuit is configured to generate a first transmission pulse signal and a second transmission pulse signal according to an input pulse signal; the first transformer and the second transformer are configured to isolate input and output, and transmit the first transmission pulse signal and the second transmission pulse signal to the subsequent stage as a first received pulse signal and a second received pulse signal respectively; the pulse receiving circuit of any one of the first structure to the fifth structure is configured to generate a received pulse signal according to the first received pulse signal and the second received pulse signal; the driver is configured to generate an output pulse signal according to the received pulse signal (sixth structure).

[0348] In addition, the signal transmission device of the sixth structure may have a structure in which the pulse transmission circuit performs pulse driving of any one of the first transmission pulse signal and the second transmission pulse signal according to the logic level of the input pulse signal (seventh structure).

[0349] In addition, the signal transmission device of the sixth structure or the seventh structure may have a structure in which the pulse transmission circuit is integrated in the first chip, the pulse receiving circuit and the driver are integrated in the second chip, and the first transformer and the second transformer are integrated in the third chip (eighth structure).

[0350] In addition, the signal transmission device of the above eighth structure may have the following structure, where the third chip includes: a first terminal connected to a first terminal forming a primary winding of a first transformer; a second terminal connected to a second terminal forming a primary winding of the first transformer and a first terminal forming a primary winding of a second transformer; a third terminal connected to a second terminal forming a primary winding of the second transformer; a fourth terminal connected to a first terminal forming a secondary winding of the first transformer; a fifth terminal connected to a second terminal forming a secondary winding of the first transformer and a first terminal forming a secondary winding of the second transformer; and a sixth terminal connected to a second terminal forming a secondary winding of the second transformer (ninth structure).

[0351] In addition, the signal transmission device of any one of the sixth to ninth structures may have a structure including a plurality of sets of first transformers and second transformers (tenth structure).

[0352] <Other Variants>

[0353] In addition, the various technical features disclosed in this specification are not limited to the above embodiments, but can be variously modified within the scope of technical creation without departing from their spirit. For example, bipolar transistors and MOS field effect transistors can be replaced with each other, and the logic levels of various signals can be inverted. In other words, the above embodiments are examples of various aspects and should not be construed as restrictive. The technical scope of the present invention is not limited to the above embodiments, but should be understood to include all modifications within the meaning and scope equivalent to the claims.

[0354] Industrial Applicability

[0355] The present invention disclosed in this specification can be used in general applications that require signal transmission while electrically isolating between input and output, such as isolation gate drivers, motor drivers, isolators, or other ICs that handle high voltages.

[0356] Description of Reference Numerals

[0357] 5 Semiconductor Device

[0358] 11 Low-Potential Terminal

[0359] 12 High-Potential Terminal

[0360] 21 Transformer

[0361] 22 Low-Potential Coil

[0362] 23 High-Potential Coil

[0363] 41 Semiconductor Chip

[0364] 42 First Main Surface

[0365] 44A First chip sidewall

[0366] 44B Second chip sidewall

[0367] 44C Third chip sidewall

[0368] 44D Fourth chip sidewall

[0369] 45 First functional device

[0370] 51 Insulating layer

[0371] 53A First insulating sidewall

[0372] 53B Second insulating sidewall

[0373] 53C Third insulating sidewall

[0374] 53D Fourth insulating sidewall

[0375] 60 Second functional device

[0376] 61 Sealing conductor

[0377] 85 dummy pattern

[0378] 130 Separation structure

[0379] 131 Field insulating film

[0380] 140 Inorganic insulating layer

[0381] 145 Organic insulating layer

[0382] 200 Signal transmission device

[0383] 210 Controller chip (first chip)

[0384] 211, 211A, 211B, 211(1), 211(2) Schmitt buffer

[0385] 211C AND gate

[0386] 212 Pulse transmission circuit

[0387] 212a Logic unit

[0388] 212b, 212c Buffer

[0389] 212d, 212e Diode (electrostatic protection element)

[0390] 213 Low voltage protection circuit

[0391] 220 Driver chip (second chip)

[0392] 221 Pulse Receiving Circuit

[0393] 221a, 221b Diodes (Electrostatic Protection Components)

[0394] 221c, 221d, 221e, 221f Buffers

[0395] 221g, 221h Delay Units

[0396] 221i, 221j AND Gates

[0397] 221k Logic Unit

[0398] 221A, 221B Diodes (Electrostatic Protection Components)

[0399] 221C, 221D N-channel MOS Field Effect Transistors (Switches)

[0400] 221E, 221F Comparators (Pulse Detectors)

[0401] 221G Timer

[0402] 221H Logic Unit

[0403] 222, 222(1), 222(2) Drivers

[0404] 222H P-channel MOS Field Effect Transistor

[0405] 222L N-channel MOS Field Effect Transistor

[0406] 223 Low Voltage Protection Circuit

[0407] 230 Transformer Chip (Third Chip)

[0408] 230a First Layer (Lower Layer)

[0409] 230b Second Layer (Upper Layer)

[0410] 231, 232, 233, 234 Transformers

[0411] 231p, 232p Primary Windings

[0412] 231s, 232s Secondary Windings

[0413] C1, C2 Capacitors

[0414] GND1, GND2 Ground Terminals

[0415] IN, IN1, IN2, INA, INB Input Terminals

[0416] N1 N-channel MOS field effect transistor

[0417] OUT, OUT1, OUT2 Output terminals

[0418] R1 Resistor

[0419] T11 to T18, T21 to T26, T31 to T36 Terminals

[0420] VCC1, VCC2 Power supply terminals

[0421] X21, X22, X23 Internal terminals

[0422] Y21, Y22, Y23 Wiring

[0423] Z21, Z22, Z23 Through holes

Claims

1. A pulse receiving circuit, comprising: A first pulse detector configured to receive a differential input between a first received pulse signal at a secondary winding of a first transformer and a second received pulse signal at a secondary winding of a second transformer; A second pulse detector configured to receive a differential input between the first received pulse signal and the second received pulse signal, wherein the input polarity is opposite to that of the first pulse detector; A logic unit configured to generate a received pulse signal based on output signals of the first pulse detector and the second pulse detector; A first switch and a second switch, the first switch and the second switch being respectively connected between two ends of the secondary winding of the first transformer and two ends of the secondary winding of the second transformer; And A timer configured to turn on the first switch and the second switch respectively for a predetermined masking period starting from the pulse detection moments of the first pulse detector and the second pulse detector.

2. The pulse receiving circuit according to claim 1, wherein The first pulse detector and the second pulse detector are each a comparator with an input offset.

3. The pulse receiving circuit according to claim 1, further comprising a first electrostatic protection element and a second electrostatic protection element respectively connected between two ends of the secondary winding of the first transformer and two ends of the secondary winding of the second transformer.

4. The pulse receiving circuit according to any one of claims 1 to 3, wherein, The logic unit sets the received pulse signal to a first logic level according to the first received pulse signal, and sets the received pulse signal to a second logic level according to the second received pulse signal.

5. A signal transmission device, comprising: A pulse transmission circuit configured to generate a first transmission pulse signal and a second transmission pulse signal according to an input pulse signal; A first transformer and a second transformer configured to isolate input and output and transmit the first transmission pulse signal and the second transmission pulse signal to a subsequent stage as a first received pulse signal and a second received pulse signal respectively; The pulse receiving circuit according to any one of claims 1 to 4, configured to generate the received pulse signal according to the first received pulse signal and the second received pulse signal; And A driver configured to generate an output pulse signal according to the received pulse signal.

6. The signal transmission device according to claim 5, wherein, The pulse transmission circuit performs pulse driving of any one of the first transmission pulse signal and the second transmission pulse signal according to the logic level of the input pulse signal.

7. The signal transmission device according to claim 5, wherein The pulse transmission circuit is integrated in a first chip, The pulse receiving circuit and the driver are integrated in a second chip, and The first transformer and the second transformer are integrated in a third chip.

8. The signal transmission device according to claim 7, wherein, The third chip is provided with: A first terminal connected to a first terminal forming a primary winding of the first transformer; A second terminal connected to a second terminal forming a primary winding of the first transformer and a first terminal forming a primary winding of the second transformer; A third terminal connected to a second terminal forming a primary winding of the second transformer; A fourth terminal connected to a first terminal forming a secondary winding of the first transformer; A fifth terminal connected to a second terminal forming the secondary winding of the first transformer and a first terminal forming a secondary winding of the second transformer; And A sixth terminal connected to a second terminal forming the secondary winding of the second transformer.

9. The signal transmission device according to any one of claims 5 to 8, comprising a plurality of sets of the first transformer and the second transformer.

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