Interdigital super junction MIS structure for evaluating charge balance of super junction structure and test method

Abstract

The application discloses a kind of to evaluate interdigital super junction MIS structure and test method of charge balance of super junction structure, including silicon N+ type substrate, super junction N area, super junction P area, silicon oxide film, N area aluminum film, P area aluminum film, substrate back aluminum film;Including steps: (1) on N+ silicon substrate piece, super junction structure is prepared, then silicon oxide film is grown on the surface of super junction structure, then metal film is sputtered on the surface of silicon oxide film, while a layer of metal film is also sputtered on the back of N+ substrate, to obtain interdigital super junction MIS structure device;(2) under low frequency or high frequency condition, the C-V characteristic curve of N area and P area of interdigital super junction MIS structure is tested respectively;(3) by comparing the minimum value of high frequency C-V characteristic curve capacitance of super junction N area and P area, whether the charge balance of super junction structure is determined.The charge balance condition of super junction structure and the specific non-balance degree of N / P area can be judged using the application, and the judging method is simple and effective.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and in particular relates to an interdigitated superjunction MIS structure and a testing method for evaluating the charge balance of a superjunction structure. Background Technology

[0002] The core of next-generation power electronic devices—semiconductor power devices—faces higher standards and more stringent requirements. Traditional silicon unipolar power semiconductor devices exhibit a 2.5-power "silicon limit" relationship between specific on-resistance and breakdown voltage. Building upon this, superjunctions innovatively introduce a periodic charge balance mechanism, transforming the traditional single-conductive resistive voltage-bearing layer into a junction-type voltage-bearing layer composed of N / P regions. This structure breaks through the traditional "silicon limit," reducing it to a quasi-linear relationship of 1.32-power or even 1.03-power. Therefore, the application of superjunction technology to silicon power devices will enable their upgrading and represent a major breakthrough in the field of power devices. The MIS structure stands for Metal-Insulator-Semiconductor structure.

[0003] Superjunction structures must satisfy the charge balance principle, meaning the total amount of impurities doped in the N / P regions should be equal to ensure that the N / P regions are simultaneously depleted during blocking. Superjunction structures in a state of charge imbalance will fail to meet target requirements for breakdown voltage and specific on-resistance, making it difficult for superjunction devices to exhibit superior performance.

[0004] Therefore, when fabricating superjunction devices, it is crucial to accurately assess whether the superjunction region has reached charge balance, which is of great significance for subsequent device performance testing and the improvement and optimization of the superjunction process.

[0005] In the past, the charge balance of the superjunction region was often evaluated by testing the breakdown voltage of the superjunction breakdown layer during the fabrication of superjunction devices. However, this method has a strict requirement that breakdown must occur in the cellular region, which necessitates a very high termination efficiency in the termination region, significantly increasing the difficulty of designing superjunction devices. Furthermore, even if the superjunction region is not charge balanced, this method cannot determine whether the doping is excessive in the P-region or the N-region, making it difficult to carry out subsequent device structure optimization and process optimization.

[0006] Therefore, this study explores a simple and effective test method for evaluating the charge balance of superjunction structures, which will be of great significance for the design and fabrication of superjunction power devices. Summary of the Invention

[0007] The purpose of this invention is to propose a simple and effective method for evaluating the charge balance of interdigitated superjunction MIS structures and testing methods, thereby achieving accurate evaluation of the charge balance between the N-region and P-region of the superjunction during the fabrication of superjunction devices.

[0008] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0009] An interdigitated superjunction MIS structure for evaluating the charge balance of a superjunction structure includes an aluminum thin film 7 on the back side of a substrate, a silicon N+ type substrate 1 above the aluminum thin film 7, alternating superjunction N-regions 2 and P-regions 3 above the silicon N+ type substrate 1, a silicon oxide thin film 4 above the superjunction N-regions 2 and P-regions 3, and an N-region aluminum thin film 5 and a P-region aluminum thin film 6 above the silicon oxide thin film 4. The N-region aluminum thin film 5 and the P-region aluminum thin film 6 are interdigitated structures. Both the N-region aluminum thin film 5 and the P-region aluminum thin film 6 include a horizontal segment extending along the alternating direction of the superjunction N-regions 2 and P-regions 3, and multiple vertical segments perpendicular to the horizontal segment. Vertical segments of the P-region aluminum thin film 6 extend between the vertical segments of adjacent N-region aluminum thin films 5, and vertical segments of the N-region aluminum thin film 5 extend between the vertical segments of adjacent P-region aluminum thin films 6. The vertical segments of the N-region aluminum thin film 5 are located in the corresponding region above the superjunction N-region 2, and the vertical segments of the P-region aluminum thin film 6 are located in the corresponding region above the P-region 3. The N-region aluminum thin film 5 and the P-region aluminum thin film 6 are not in contact.

[0010] As a preferred embodiment, the superjunction N-region 2 and the superjunction P-region 3 are one of the following: strip cell, square cell, hexagonal cell, and grid cell.

[0011] This invention also provides a test method for evaluating the charge balance of interdigitated superjunction MIS structures, comprising the following steps:

[0012] (1) A superjunction structure is prepared on an N+ silicon substrate, and a silicon oxide thin film is grown on the surface of the superjunction structure. Then, a metal thin film is sputtered on the surface of the silicon oxide thin film corresponding to the N region of the superjunction and the surface of the silicon oxide thin film corresponding to the P region of the superjunction, respectively. At the same time, a metal thin film is also sputtered on the back side of the N+ substrate, thereby preparing an interdigitated superjunction MIS structure device for electrical testing.

[0013] (2) Test the CV characteristic curves of the superjunction N-region and superjunction P-region of the interdigitated superjunction MIS structure under low frequency or high frequency conditions respectively;

[0014] (3) Based on the tested low-frequency or high-frequency CV characteristic curves, the ratio of the minimum test capacitance of the superjunction N-region to the silicon oxide capacitance of the insulating layer, and the ratio of the minimum test capacitance of the superjunction P-region to the silicon oxide capacitance of the insulating layer are compared to determine whether the superjunction is charge balanced. If the two are equal, it indicates that the concentrations of the superjunction N-region and the superjunction P-region are equal, that is, the superjunction N-region and the superjunction P-region are charge balanced; if the ratio of the minimum test capacitance of the superjunction P-region to the silicon oxide capacitance of the insulating layer is greater than the ratio of the minimum test capacitance of the superjunction N-region to the silicon oxide capacitance of the insulating layer, the superjunction N-region is charge balanced. The ratio of the minimum capacitance of the superjunction N region to the capacitance of the insulating silicon oxide layer indicates that the superjunction P region concentration is greater than the superjunction N region concentration. If the ratio of the minimum capacitance of the superjunction N region to the capacitance of the insulating silicon oxide layer is greater than the ratio of the minimum capacitance of the superjunction P region to the capacitance of the insulating silicon oxide layer, it indicates that the superjunction N region concentration is greater than the superjunction P region concentration. If the superjunction N region and the superjunction P region are not in charge balance, the specific degree of imbalance can be derived using the formulas for the minimum capacitance of the superjunction N region and the superjunction P region at high frequencies.

[0015] As a preferred method, in step (3), the minimum value C of the superjunction N-region capacitance at high frequency is... N,min′ It can be obtained from the following formula:

[0016]

[0017] Minimum capacitance C of the superjunction P-region at high frequencies P,min′ It can be obtained from the following formula:

[0018]

[0019] The capacitance C0 of the insulating silicon oxide layer is obtained by the following formula:

[0020]

[0021] Where A is the area of ​​the metal film covering the insulating silicon oxide layer, C0 is the capacitance of the insulating silicon oxide layer, and d0 is the thickness of the insulating silicon oxide layer; ε r0 ε is the relative permittivity of silicon oxide. rs N is the relative permittivity of silicon, where ε0 is the permittivity; N It is the doping concentration of the N-region of the superjunction, N P It is the doping concentration of the superjunction P-region, A N It is the area of ​​the metal thin film covering the N-region of the superjunction, A P It is the area of ​​the metal thin film covering the P-region of the superjunction; q is the elementary charge, k0 is the Boltzmann constant, T is the temperature, and n i It is the intrinsic carrier concentration.

[0022] As a preferred method, in step (1), the process for preparing the superjunction structure is one of the following: trench etching-epitaxy backfilling method or multiple epitaxy-multiple etching method.

[0023] As a preferred embodiment, in step (1), the thickness of the silicon oxide film is 20-40 nm, and the thickness of the N-region aluminum film 5, the P-region aluminum film 6, and the substrate back aluminum film 7 is 50-100 nm.

[0024] As a preferred method, in step (1), the growth of the silicon oxide film is either dry oxidation or wet oxidation.

[0025] As a preferred method, in step (1), the growth of the metal thin film is selected from either magnetron sputtering or electron beam evaporation.

[0026] As a preferred embodiment, in step (2), the low frequency is 10-100Hz and the high frequency is 50k-500kHz.

[0027] As a preferred method, in step (2), the applied voltage range for testing the CV characteristic curve is between -20 and 20V.

[0028] The beneficial effects of this invention are as follows: It proposes a test method for evaluating the charge balance of the superjunction region based on an interdigitated superjunction MIS structure, enabling accurate evaluation of the charge balance between the N-region and P-region of the superjunction during the fabrication process. This facilitates further device structure and process optimization. Compared to methods that determine the charge balance of the superjunction region by testing the breakdown voltage of the superjunction breakdown layer, the test method proposed in this invention requires simpler test structure fabrication, yields more accurate test results, and is easier to promote and use in academia and industry. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the process of the present invention;

[0030] Figure 2 The image shows the test pattern of the strip cell interdigitated superjunction MIS structure in Example 3;

[0031] Figure 3 The low-frequency CV curve of the P-region of the interdigitated superjunction MIS structure in Example 3 is shown.

[0032] Figure 4 The low-frequency CV curve of the N-region test of the interdigitated superjunction MIS structure in Example 3;

[0033] Figure 5 The low-frequency CV curve of the interdigitated superjunction MIS structure in Example 3, where the N-region concentration is equal to the P-region concentration;

[0034] Figure 6 The low-frequency CV curve shows that the concentration in the P region of the interdigitated superjunction MIS structure in Example 3 is greater than the concentration in the N region.

[0035] Figure 7 The low-frequency CV curves show that the N-region concentration is greater than the P-region concentration in the interdigitated superjunction MIS structure of Example 3.

[0036] Figure 8 The high-frequency CV curves of the P-region of the interdigitated superjunction MIS structure in Example 3 are shown.

[0037] Figure 9 The high-frequency CV curves of the N-region of the interdigitated superjunction MIS structure in Example 3 are shown.

[0038] Figure 10 The high-frequency CV curves for the interdigitated superjunction MIS structure of Example 3, showing that the N-region concentration is equal to the P-region concentration;

[0039] Figure 11 The high-frequency CV curves for the interdigitated superjunction MIS structure of Example 3 show that the concentration in the P region is greater than that in the N region.

[0040] Figure 12 The high-frequency CV curves show that the N-region concentration is greater than the P-region concentration in the interdigitated superjunction MIS structure of Example 3.

[0041] 1 is a silicon N+ type substrate, 2 is a superjunction N region, 3 is a superjunction P region, 4 is a silicon oxide thin film, 5 is an N region aluminum thin film, 6 is a P region aluminum thin film, and 7 is an aluminum thin film on the back side of the substrate. Detailed Implementation

[0042] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments.

[0043] Example 1

[0044] This embodiment provides an interdigitated superjunction MIS structure for evaluating the charge balance of a superjunction structure, including an aluminum thin film 7 on the back side of a substrate, a silicon N+ type substrate 1 above the aluminum thin film 7, alternating superjunction N-regions 2 and P-regions 3 above the silicon N+ type substrate 1, a silicon oxide thin film 4 above the superjunction N-regions 2 and P-regions 3, and an N-region aluminum thin film 5 and a P-region aluminum thin film 6 above the silicon oxide thin film 4. The N-region aluminum thin film 5 and the P-region aluminum thin film 6 are interdigitated structures. Both include horizontal segments extending along the alternating arrangement direction of superjunction N-region 2 and superjunction P-region 3, and multiple vertical segments perpendicular to the horizontal segments. Vertical segments of P-region aluminum film 6 extend between the vertical segments of adjacent N-region aluminum film 5, and vertical segments of N-region aluminum film 5 extend between the vertical segments of adjacent P-region aluminum film 6. The vertical segments of N-region aluminum film 5 are located in the corresponding region above superjunction N-region 2, and the vertical segments of P-region aluminum film 6 are located in the corresponding region above P-region 3. N-region aluminum film 5 and P-region aluminum film 6 do not contact each other.

[0045] The superjunction N-region 2 and the superjunction P-region 3 are one of the following: strip cell, square cell, hexagonal cell, and grid cell.

[0046] Example 2

[0047] This embodiment provides a test method for evaluating the charge balance of interdigitated superjunction MIS structures, including the following steps:

[0048] (1) A superjunction structure is prepared on an N+ silicon substrate, and a silicon oxide thin film is grown on the surface of the superjunction structure. Then, a metal thin film is sputtered on the surface of the silicon oxide thin film corresponding to the N region of the superjunction and the surface of the silicon oxide thin film corresponding to the P region of the superjunction, respectively. At the same time, a metal thin film is also sputtered on the back side of the N+ substrate, thereby preparing an interdigitated superjunction MIS structure device for electrical testing.

[0049] (2) Test the CV characteristic curves of the superjunction N-region and superjunction P-region of the interdigitated superjunction MIS structure under low frequency or high frequency conditions respectively;

[0050] (3) Based on the tested low-frequency or high-frequency CV characteristic curves, the ratio of the minimum test capacitance of the superjunction N-region to the silicon oxide capacitance of the insulating layer, and the ratio of the minimum test capacitance of the superjunction P-region to the silicon oxide capacitance of the insulating layer are compared to determine whether the superjunction is charge balanced. If the two are equal, it indicates that the concentrations of the superjunction N-region and the superjunction P-region are equal, that is, the superjunction N-region and the superjunction P-region are charge balanced; if the ratio of the minimum test capacitance of the superjunction P-region to the silicon oxide capacitance of the insulating layer is greater than the ratio of the minimum test capacitance of the superjunction N-region to the silicon oxide capacitance of the insulating layer, the superjunction N-region is charge balanced. The ratio of the minimum capacitance of the superjunction N region to the capacitance of the insulating silicon oxide layer indicates that the superjunction P region concentration is greater than the superjunction N region concentration. If the ratio of the minimum capacitance of the superjunction N region to the capacitance of the insulating silicon oxide layer is greater than the ratio of the minimum capacitance of the superjunction P region to the capacitance of the insulating silicon oxide layer, it indicates that the superjunction N region concentration is greater than the superjunction P region concentration. If the superjunction N region and the superjunction P region are not in charge balance, the specific degree of imbalance can be derived using the formulas for the minimum capacitance of the superjunction N region and the superjunction P region at high frequencies.

[0051] In step (3), the minimum capacitance C of the superjunction N-region at high frequency is... N,min′ It can be obtained from the following formula:

[0052]

[0053] Minimum capacitance C of the superjunction P-region at high frequencies P,min′ It can be obtained from the following formula:

[0054]

[0055] The capacitance C0 of the insulating silicon oxide layer is obtained by the following formula:

[0056]

[0057] Where A is the area of ​​the metal film covering the insulating silicon oxide layer, C0 is the capacitance of the insulating silicon oxide layer, and d0 is the thickness of the insulating silicon oxide layer; ε r0 ε is the relative permittivity of silicon oxide. rs N is the relative permittivity of silicon, where ε0 is the permittivity; N It is the doping concentration of the N-region of the superjunction, N P It is the doping concentration of the superjunction P-region, A N It is the area of ​​the metal thin film covering the N-region of the superjunction, A P It is the area of ​​the metal thin film covering the P-region of the superjunction; q is the elementary charge, k0 is the Boltzmann constant, T is the temperature, and n i It is the intrinsic carrier concentration.

[0058] In step (1), the superjunction structure is prepared by one of the following methods: trench etching-epitaxy backfilling method or multiple epitaxy-multiple etching method.

[0059] In step (1), the thickness of the silicon oxide film is 20-40 nm, and the thickness of the N-region aluminum film 5, the P-region aluminum film 6, and the substrate back aluminum film 7 is 50-100 nm.

[0060] In step (1), the growth of the silicon oxide film is either dry oxidation or wet oxidation.

[0061] In step (1), the growth of the metal thin film is selected from either magnetron sputtering or electron beam evaporation.

[0062] In step (2), the low frequency is 10-100Hz; the high frequency is 50k-500kHz.

[0063] In step (2), the applied voltage range for testing the CV characteristic curve is between -20 and 20V.

[0064] Example 3

[0065] This embodiment provides an interdigitated superjunction MIS structure for evaluating the charge balance of a superjunction structure and a testing method therefor, including the following steps:

[0066] (1) A superjunction structure was fabricated on a silicon N+ type substrate 1 using the "trench etching-epitaxy backfilling method". Specifically, a strip-cell superjunction MIS structure was used. The N-region 2 and P-region 3 of the superjunction were required to have the same width. For structures where the N-region and P-region widths differed, the analysis method was similar to that for structures where the N-region and P-region widths were the same. Then, a 30 nm thick silicon oxide film 4 was grown on the surface of the fabricated superjunction structure using dry oxidation. Subsequently, a 50 nm N-region aluminum film 5 was sputtered onto the surface of the silicon oxide film corresponding to the N-region using magnetron sputtering, a 50 nm P-region aluminum film 6 was sputtered onto the surface of the silicon oxide film corresponding to the P-region, and a 50 nm back-side aluminum film 7 was sputtered onto the back side of the substrate, thus obtaining an aluminum-silicon oxide-silicon superjunction MIS structure, as shown below. Figure 2 As shown.

[0067] (2) The low-frequency and high-frequency CV characteristic curves of the prepared interdigitated superjunction MIS structure were tested for the N-region and P-region, respectively. The corresponding low-frequency test curve for the P-region is shown in Figure 1. Figure 3 As shown, the corresponding low-frequency test curve for region N is as follows: Figure 4 As shown, the corresponding high-frequency test curve for region P is as follows: Figure 8 As shown, the corresponding high-frequency test curves for region N are as follows: Figure 9 As shown, the horizontal axis represents voltage, and the vertical axis represents the ratio of the test capacitor C to the insulating silicon oxide capacitor C0. The ratio of the minimum value of the test capacitor C in region N to the insulating silicon oxide capacitor C0 and the ratio of the minimum value of the test capacitor C in region P to the insulating silicon oxide capacitor C0 are read respectively.

[0068] (3) Analyze the ratio of the minimum value of the superjunction N-region test capacitance to the silicon oxide capacitance of the insulating layer at low frequencies in step (2), and the ratio of the minimum value of the superjunction P-region test capacitance to the silicon oxide capacitance of the insulating layer. If the two are equal, it indicates that the concentrations of the superjunction N / P regions are equal, that is, the charge balance of the superjunction N / P regions. Figure 5 As shown; if the ratio of the minimum capacitance of the superjunction P-region to the silicon oxide capacitance of the insulating layer is greater than the ratio of the minimum capacitance of the superjunction N-region to the silicon oxide capacitance of the insulating layer at low frequencies, it indicates that the P-region concentration is greater than the N-region concentration. Figure 6 As shown; if the ratio of the minimum value of the superjunction N-region test capacitance to the silicon oxide capacitance of the insulating layer at low frequencies is greater than the ratio of the minimum value of the superjunction P-region test capacitance to the silicon oxide capacitance of the insulating layer, it indicates that the N-region concentration is greater than the P-region concentration. Figure 7 As shown.

[0069] (4) Analyze the ratio of the minimum value of the superjunction N-region test capacitance to the silicon oxide capacitance of the insulating layer, and the ratio of the minimum value of the superjunction P-region test capacitance to the silicon oxide capacitance of the insulating layer in step (2). If the two are equal, it indicates that the concentrations of the superjunction N / P regions are equal, that is, the charge balance of the superjunction N / P regions. Figure 10As shown; if the ratio of the minimum capacitance of the superjunction P-region to the silicon oxide capacitance of the insulating layer is greater than the ratio of the minimum capacitance of the superjunction N-region to the silicon oxide capacitance of the insulating layer, it indicates that the P-region concentration is greater than the N-region concentration. Figure 11 As shown; if the ratio of the minimum value of the superjunction N-region test capacitance to the silicon oxide capacitance of the insulating layer is greater than the ratio of the minimum value of the superjunction P-region test capacitance to the silicon oxide capacitance of the insulating layer, it indicates that the N-region concentration is greater than the P-region concentration. Figure 12 As shown.

[0070] (5) If the N / P region charge is unbalanced, the minimum value of the superjunction N-region test capacitance and the minimum value of the superjunction P-region test capacitance can be substituted into the minimum value C of the superjunction N-region capacitance. N,min′ The minimum capacitance C of the superjunction P-region P,min′ The formula is used to calculate the concentrations in the N-region and the P-region, thereby determining the specific non-equilibrium value.

[0071] In step (5), the minimum value C of the superjunction N-region capacitance at high frequency is... N,min′ It can be obtained from the following formula:

[0072]

[0073] Minimum capacitance C of the superjunction P-region at high frequencies P,min′ It can be obtained from the following formula:

[0074]

[0075] The capacitance C0 of the insulating silicon oxide layer is obtained by the following formula:

[0076]

[0077] Where A is the area of ​​the metal film covering the insulating silicon oxide layer, C0 is the capacitance of the insulating silicon oxide layer, and d0 is the thickness of the insulating silicon oxide layer; ε r0 ε is the relative permittivity of silicon oxide. rs N is the relative permittivity of silicon, where ε0 is the permittivity; N It is the doping concentration of the N-region of the superjunction, N P It is the doping concentration of the superjunction P-region, A N It is the area of ​​the metal thin film covering the N-region of the superjunction, A P It is the area of ​​the metal thin film covering the P-region of the superjunction; q is the elementary charge, k0 is the Boltzmann constant, T is the temperature, and n i It is the intrinsic carrier concentration.

[0078] The test structure required for evaluating the charge balance of superjunction structures proposed in this invention is simple to prepare, and the test results are more accurate, making it easier for academia and industry to promote its use.

[0079] The above description of silicon as the semiconductor material is merely a preferred embodiment of the present invention and is not intended to limit the invention. Other mainstream semiconductor materials are still applicable, and various modifications and variations can be made to the present invention by those skilled in the art. Any modifications made within the spirit and principles of the present invention are within the protection scope of the present invention.

Claims

1. An interdigital super junction MIS structure for evaluating charge balance of a super junction structure, comprising: The structure includes an aluminum film on the back side of the substrate (7), a silicon N+ type substrate (1) above the aluminum film on the back side of the substrate (7), alternating superjunction N-regions (2) and P-regions (3) above the silicon N+ type substrate (1), a silicon oxide film (4) above the superjunction N-regions (2) and P-regions (3), and an N-region aluminum film (5) and a P-region aluminum film (6) above the silicon oxide film (4). The N-region aluminum film (5) and the P-region aluminum film (6) are interdigitated structures. Both the N-region aluminum film (5) and the P-region aluminum film (6) include the superjunction N-region (2) The horizontal segments extending in the alternating direction with the superjunction P region (3) and the multiple vertical segments perpendicular to the horizontal segments, the vertical segments of the P region aluminum film (6) extending between the vertical segments of the adjacent N region aluminum film (5), and the vertical segments of the N region aluminum film (5) extending between the vertical segments of the adjacent P region aluminum film (6); the vertical segments of the N region aluminum film (5) are located in the corresponding area above the superjunction N region (2), and the vertical segments of the P region aluminum film (6) are located in the corresponding area above the P region (3). The N region aluminum film (5) and the P region aluminum film (6) do not contact each other.

2. The interdigitated superjunction MIS structure for evaluating the charge balance of the superjunction structure is characterized by: The superjunction N region (2) and the superjunction P region (3) are one of the following: strip cell, square cell, hexagonal cell, and grid cell.

3. The test method for evaluating the charge balance of an interdigitated superjunction MIS structure as described in claim 1 or 2, characterized in that... Includes the following steps: (1) A superjunction structure is prepared on an N+ silicon substrate, and a silicon oxide thin film is grown on the surface of the superjunction structure. Then, a metal thin film is sputtered on the surface of the silicon oxide thin film corresponding to the N region of the superjunction and the surface of the silicon oxide thin film corresponding to the P region of the superjunction, respectively. At the same time, a metal thin film is also sputtered on the back side of the N+ substrate, thereby preparing an interdigitated superjunction MIS structure device for electrical testing. (2) Test the CV characteristic curves of the superjunction N-region and superjunction P-region of the interdigitated superjunction MIS structure under low-frequency or high-frequency conditions respectively; the low-frequency frequency is 10-100Hz; the high-frequency frequency is 50k-500kHz. (3) Based on the low-frequency or high-frequency CV characteristic curves, the charge balance of the superjunction is determined by comparing the ratio of the minimum test capacitance of the superjunction N-region to the capacitance of the insulating silicon oxide layer, and the ratio of the minimum test capacitance of the superjunction P-region to the capacitance of the insulating silicon oxide layer. If the two are equal, it indicates that the concentrations of the superjunction N-region and the superjunction P-region are equal, i.e., the superjunction N-region and the superjunction P-region are charge balanced. If the ratio of the minimum test capacitance of the superjunction P-region to the capacitance of the insulating silicon oxide layer is greater than that of the superjunction N-region, it indicates that the concentration of the superjunction P-region is greater than that of the superjunction N-region. If the ratio of the minimum test capacitance of the superjunction N-region to the capacitance of the insulating silicon oxide layer is greater than that of the superjunction P-region, it indicates that the concentration of the superjunction N-region is greater than that of the superjunction P-region. If the superjunction N-region and the superjunction P-region are not charge balanced, the specific degree of non-balance is derived using the formulas for the minimum capacitance of the superjunction N-region and the superjunction P-region at high frequencies. In step (3), the minimum value of the super-junction N-region capacitance C N,min′ is obtained from the following equation: ； The minimum value of the super junction P region capacitance C under high frequency P,min′ is obtained from the following equation: ； The capacitance C0 of the insulating silicon oxide layer is obtained by the following formula: ； Where A is the area of ​​the metal film covering the insulating silicon oxide layer, C0 is the capacitance of the insulating silicon oxide layer, and d0 is the thickness of the insulating silicon oxide layer; ε r0 ε is the relative permittivity of silicon oxide. rs ε0 is the relative permittivity of silicon, and ε0 is the permittivity; N N It is the doping concentration of the N-region of the superjunction, N P It is the doping concentration of the superjunction P-region, A N It is the area of ​​the metal thin film covering the N-region of the superjunction, A P It is the area of ​​the metal thin film covering the P-region of the superjunction; q is the elementary charge, k0 is the Boltzmann constant, T is the temperature, and n i It is the intrinsic carrier concentration.

4. The test method for evaluating the charge balance of interdigitated superjunction MIS structures according to claim 3, characterized in that, In step (1), the superjunction structure is prepared by one of the following methods: trench etching-epitaxy backfilling method or multiple epitaxy-multiple etching method.

5. The test method for evaluating the charge balance of interdigitated superjunction MIS structures according to claim 3, characterized in that, In step (1), the thickness of the silicon oxide film is 20-40 nm, and the thickness of the N-region aluminum film (5), the P-region aluminum film (6), and the substrate back aluminum film (7) is 50-100 nm.

6. The test method for evaluating the charge balance of interdigitated superjunction MIS structures according to claim 3, characterized in that, In step (1), the growth of the silicon oxide film is either dry oxidation or wet oxidation.

7. The test method for evaluating the charge balance of interdigitated superjunction MIS structures according to claim 3, characterized in that, In step (1), the growth of the metal thin film is selected from either magnetron sputtering or electron beam evaporation.

8. The test method for evaluating the charge balance of an interdigitated superjunction MIS structure according to claim 3, characterized in that, In step (2), the applied voltage range for testing the CV characteristic curve is between -20 and 20V.

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