A power device and corresponding manufacturing method

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and discloses a power device and a corresponding manufacturing method, comprising a plurality of basic device units, each of which comprises a gate, a source and a drain located on both sides of the gate; wherein the source of at least one basic device unit comprises a first source and a second source, and the source of other basic device units comprises only the first source; the first source and the second source are isolated and arranged, and the first source and the gate and the drain of the corresponding basic device unit constitute a MainFET, and the second source and the gate and the drain of the corresponding basic device unit constitute a SenseFET; a novel distributed power device current sampling structure proposed in the present invention, compared with a traditional current sampling structure, can reduce the power consumption caused by the SenseFET while improving the accuracy of the SenseFET current detection.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and specifically provides a power device and a corresponding manufacturing method. Background Art

[0002] The current detection method based on the detection transistor SenseFET has the advantages of being fully integrated, low loss power consumption, relatively accurate detection, etc., and is therefore widely used in the current detection of power devices to reflect the defect distribution, device degradation, etc. of power devices. In this method, as Figure 1 shown, SenseFET1 and the main body MainFET2 of the power device form a current mirror structure. Among them, MainFET2 and SenseFET1 share the drain D and the gate G, but the first source S of MainFET and the second source SS of SenseFET do not share.

[0003] Specifically, in the existing power device technology, the power device is composed of n basic device units connected in parallel, and the current is distributed according to the number of units. Usually, m basic device units are taken as SenseFET, and the other basic device units form the main body MainFET of the power device. Among them, m << n, and m is usually 1. Therefore, the gate width of SenseFET will be much smaller than that of MainFET, and the manufacturing process of SenseFET and MainFET and the device structure of each unit are exactly the same. Therefore, the current flowing through SenseFET can be approximately m / n of the current flowing through the power device; for example, as Figure 2 shown are multiple units of the power device, where one unit is used as SenseFET, including the drain D, the gate G, and 1 second source SS, and the other units are all used as MainFET, including the drain D, the gate G, and the first source S.

[0004] However, the main defect of the above technology is that: due to the limited number of parallel basic device units of the power device, generally within 10 - 500, the proportion of the current flowing through SenseFET in the total current of the power device is relatively large, and the power consumption is large. Summary of the Invention

[0005] The purpose of the present invention is to overcome the problem that the SenseFET of the GaN power device under the existing design causes large power loss and low current detection accuracy of the power device, and provides a power device and a corresponding manufacturing method.

[0006] In order to achieve the above-mentioned purpose, the present invention provides a power device, including multiple basic device units, each basic device unit includes a gate, a source and a drain, the source of at least one basic device unit includes a first source and a second source, the source of other basic device units only includes a first source, and the first source and the second source in the corresponding basic device unit are isolated; wherein the first source and the gate and drain of the corresponding basic device unit constitute a MainFET, and the second source and the gate and drain of the corresponding basic device unit constitute a SenseFET.

[0007] As an implementation method, when the source of the basic device unit includes a first source and a second source, the length of the second source is smaller than the length of the first source in the corresponding basic device unit.

[0008] As an implementation method, when the source of the basic device unit includes a first source and at least one second source, the at least one second source is distributed in one or more sections corresponding to the middle of the first source.

[0009] As an implementation method, the isolation setting of the first source and the second source in the corresponding basic device unit is specifically as follows: an ion implantation region is provided in the barrier layer exposed between the first source and the second source in the corresponding basic device unit, and the isolation of the first source and the adjacent second source is achieved by utilizing the ion implantation region.

[0010] As an implementable embodiment, the isolation arrangement of the first source and the second source in the corresponding basic device unit is specifically as follows: the surface of the barrier layer between the first source and the second source in the corresponding basic device unit has a P-GaN isolation structure, and the isolation of the first source and the adjacent second source is achieved by the P-GaN isolation structure.

[0011] As an implementation method, each second source is connected together and then connected to the second source pad via a resistor, and each first source is connected together and then connected to the first source pad.

[0012] As an implementation method, the SenseFET and the MainFET share a gate and a drain, but the SenseFET and the MainFET do not share a source.

[0013] As an implementation method, the structures of the SenseFET and the MainFET are consistent, the SenseFET and the MainFET share a gate and a drain, and the SenseFET and the MainFET do not share a source.

[0014] Accordingly, the present invention also provides a method for manufacturing a power device, comprising the following steps:

[0015] A plurality of basic device units are formed on the surface of the barrier layer and the P-GaN layer, each of which includes a gate, a source and a drain located on both sides of the gate; wherein the source of at least one basic device unit includes a first source and a second source, and the source of other basic device units includes only the first source; the first source and the second source in the corresponding basic device unit are isolated, and the first source and the gate and drain of the corresponding basic device unit constitute a MainFET, and the second source and the gate and drain of the corresponding basic device unit constitute a SenseFET;

[0016] Subsequent manufacturing is completed based on the device manufacturing process to obtain a power device.

[0017] As an implementation method, when the source of the basic device unit includes a first source and a second source, the length of the second source is smaller than the length of the first source in the corresponding basic device unit.

[0018] As an implementable embodiment, the steps for implementing the isolation setting of the first source and the second source in the corresponding basic device unit include: performing ion implantation in the barrier layer exposed between the first source and the second source in the corresponding basic device unit to form an ion implantation region, and utilizing the ion implantation region to isolate the first source from the adjacent second source.

[0019] As an implementable embodiment, the steps for implementing the isolation setting of the first source and the second source in the corresponding basic device unit include: defining P-GaN on the surface of the barrier layer between the first source and the second source in the corresponding basic device unit to form a P-GaN isolation structure, and isolating the first source and the adjacent second source through the P-GaN isolation structure.

[0020] Beneficial effects of the invention: The present invention discloses a power device and a corresponding manufacturing method, wherein the source of at least one basic device unit in the present invention includes a first source and a second source, and the first source and the second source are isolated, wherein the first source and the gate and the drain of the corresponding basic device unit constitute a MainFET, and the second source and the gate and the drain of the corresponding basic device unit constitute a SenseFET. The present invention proposes a novel distributed GaN current sampling structure, which reduces the size of the SenseFET by dividing the complete source of the basic device unit into the first source of the MainFET and the second source of the SenseFET. Compared with the traditional current sampling structure, it can improve the accuracy of the SenseFET current detection while reducing the power consumption caused by the SenseFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1A schematic diagram of a current mirror structure formed by a SenseFET of a power device and a main body MainFET of the power device according to an embodiment of the present invention;

[0022] Figure 2 Schematic diagram of the unit distribution in a traditional power device;

[0023] Figure 3 A schematic diagram of unit distribution in a power device according to an embodiment of the present invention;

[0024] Figure 4 is a schematic diagram of the connection of different second sources in a power device according to an embodiment of the present invention;

[0025] Figure 5 It is a schematic diagram of isolating a first source electrode and a second source electrode by defining a P-GaN isolation structure in a method for manufacturing a power device according to an embodiment of the present invention;

[0026] Figure 6 It is a schematic diagram of isolating a first source electrode and a second source electrode by ion implantation in a method for manufacturing a power device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] This embodiment provides a technical solution: a power device, including multiple basic device units, each basic device unit including a gate, a source and a drain, the source of at least one basic device unit including a first source and a second source, the source of other basic device units only including a first source, the first source and the second source in the corresponding basic device unit are isolated; wherein the first source and the gate and drain of the corresponding basic device unit constitute a MainFET, and the second source and the gate and drain of the corresponding basic device unit constitute a SenseFET.

[0029] like Figure 3 As shown, each basic device unit includes a source, a gate G located on both sides of the source and a drain D located on one side of a gate G, and according to the design of the number of second sources SS, the source of different basic device units may include only the first source S, or may include the first source S and the second source SS at the same time, wherein the first source S and the gate and drain of the corresponding basic device unit constitute the MainFET, and the second source SS and the gate and drain of the corresponding basic device unit constitute the SenseFET.

[0030] Specifically, Figure 2 As shown in FIG. 1 , the second source electrode SS of the SenseFET in the prior art is originally a complete source electrode in a unit. However, Figure 3 As shown, the second source SS in this embodiment is no longer a complete source in a unit, but only a part of a complete source is used as the second source SS, and the other part is used as the first source S.

[0031] When the source of the basic device unit includes a first source and at least one second source, the at least one second source is distributed in one or more sections corresponding to the middle of the first source.

[0032] Specifically, in this embodiment, the number of the second source electrodes SS may be one or more; a basic device unit may include multiple second source electrodes SS, and multiple second source electrodes SS may also be distributed in different basic device units. For example, when there are three second source electrodes, the distribution of the three second source electrodes may be as follows: Figure 3 However, in other embodiments, the number, length and distribution position of the second source electrodes SS may be determined according to actual design, and this embodiment does not limit this.

[0033] Further, when the source of the basic device unit includes a first source and a second source, the length of the second source SS is less than the length of the first source S in the corresponding basic device unit, and the specific device structure includes a substrate, a GaN layer located on the surface of the substrate 1, an AlGaN layer located on the surface of the GaN layer, and a first source S and a second source SS located on the surface of the AlGaN layer. It can be seen that, as Figure 3 As shown, the length of the second source SS is smaller than the first source S;

[0034] In order to minimize the loss caused by SenseFET, the length of the second source SS can be much smaller than the length of the corresponding first source S, that is, a few hundred or a few thousandths of a complete source can be taken as the second source SS. Because generally speaking, the conventional gate width of a power device is several hundred mm, and the gate width corresponding to a basic device unit is generally 0.5mm~2mm. Therefore, when a basic device unit is used as SenseFET in the prior art, the current passing through the SenseFET may be a few hundredths, but in this embodiment, a few hundred or a few thousandths of a unit are taken as the SenseFET. Therefore, the current passing through the SenseFET can reach more than one ten-thousandth of the total current of the power device, and the power consumption is greatly reduced.

[0035] Furthermore, due to the unevenness of the epitaxial structure, defect distribution, and device degradation of GaN power devices at different locations on the chip, the SenseFET distributed only on individual units cannot represent the overall situation of the power device. The current flowing through only one unit will deviate from the m / n of the power device current, resulting in low current detection accuracy of the SenseFET. Therefore, in this embodiment, multiple second sources can be set and distributed in different basic device units; specifically, the epitaxial structure, defect distribution, and device degradation of GaN power devices at different locations on the chip are uneven. Therefore, in this embodiment, different third sources are designed to be distributed in different first sources, and thus distributed at different locations of the power device, so that detection of different locations of the power device can be achieved.

[0036] In this embodiment, due to the flexibility and uniformity of the position distribution of the SenseFET, its representativeness for power devices is significantly improved, and the current detection accuracy of the SenseFET is improved; and because m / n can be flexibly adjusted with a very small change range, the new distributed GaN current sampling structure can well balance the two key parameters of power consumption and current detection accuracy in current detection, that is, it can improve the accuracy of the SenseFET current detection while reducing the power consumption caused by the SenseFET.

[0037] It should be noted that, in this embodiment, the power device can be applied to all lateral power devices.

[0038] In this embodiment, the device structure and manufacturing process of SenseFET and MainFET are consistent. SenseFET and MainFET share a gate and a drain, but SenseFET and MainFET do not share a source. It should be noted that SenseFET and MainFET share a gate and a drain. Figure 2 and Figure 3 It is not shown directly, but for Figure 2 and Figure 3 , where the drains D of different units are actually connected, and the gates G of different units are also connected. Figure 2 and Figure 3 It is just a classification diagram for units.

[0039] Among them, the specific detection method of detecting current through SenseFET is: connect a resistor in series to the source of SenseFET, sample the voltage across the resistor through a voltmeter, and then convert it to obtain the current of SenseFET, and finally calculate the current on the power device based on the ratio of the number of SenseFET units m to the total number of power device units n, that is, m / n.

[0040] In this embodiment, as an implementation mode, the isolation arrangement of the first source and the second source in the corresponding basic device unit is specifically as follows: an ion implantation region is provided in the barrier layer exposed between the first source and the second source in the corresponding basic device unit, and the isolation of the first source and the adjacent second source is achieved by using the ion implantation region; Figure 6 The schematic diagram and the corresponding enlarged diagram after the first source and the second source are isolated by ion implantation are shown; it can be seen that an ion implantation region 2 is formed between the first source S and the second source SS by ion implantation, which is used to isolate the first source and the adjacent second source.

[0041] As another embodiment, the isolation arrangement of the first source and the second source in the corresponding basic device unit is specifically as follows: the surface of the barrier layer between the first source and the second source in the corresponding basic device unit has a P-GaN isolation structure, and the isolation of the first source and the adjacent second source is achieved by the P-GaN isolation structure; Figure 5 The schematic diagram and the corresponding enlarged diagram after the first source and the second source are isolated by defining P-GaN are shown; it can be seen that a P-GaN isolation structure 1 is formed between the first source S and the second source SS by defining P-GaN, which is used to isolate the first source and the adjacent second source; wherein the P-GaN isolation structure can be prepared together with the gate P-GaN.

[0042] In the prior art, a traditional SenseFET generally has only one source, and therefore only a complete source in a unit is connected to a resistor, which is then connected to the source pad of the power device through the resistor; however, in this embodiment, since the SenseFET may include multiple second sources, when multiple second sources are included, it is necessary to connect the multiple second sources together and then connect them to the second source pads through a resistor, while each first source is still directly connected to the first source pad.

[0043] Specifically, each second source is connected together through metal interconnection and then connected to the second source pad through a resistor, and each first source is connected together through metal interconnection and then connected to the first source pad; Figure 4 As shown, each second source includes a through hole 10, and different second sources of the SenseFET are connected through the through hole 10 and the metal interconnection.

[0044] However, it should be noted that metal interconnection is only one connection method, and in other embodiments, other feasible connection methods may be used.

[0045] Based on the same inventive concept, an embodiment of the present invention further provides a method for manufacturing a power device, comprising the following steps:

[0046] Providing a substrate, forming a GaN layer on the surface of the substrate, forming a barrier layer on the surface of the GaN layer, and forming a P-GaN layer in a gate region on the surface of the barrier layer;

[0047] A plurality of basic device units are formed on the surface of the barrier layer and the P-GaN layer, each of which includes a gate, a source and a drain located on both sides of the gate; wherein the source of at least one basic device unit includes a first source and a second source, and the source of other basic device units includes only the first source; the first source and the second source in the corresponding basic device unit are isolated, and the first source and the gate and drain of the corresponding basic device unit constitute a MainFET, and the second source and the gate and drain of the corresponding basic device unit constitute a SenseFET;

[0048] Subsequent manufacturing is completed based on the device manufacturing process to obtain a power device.

[0049] Wherein, when the source of the basic device unit includes a first source and a second source, the length of the second source is smaller than the length of the first source in the corresponding basic device unit.

[0050] In the process of preparing the metal electrodes on the surface of the barrier layer and the P-GaN layer in this embodiment, the second source electrode will be prepared according to the specifically designed distribution position and length, but the specific preparation process is still the existing process and will not be described in detail in this embodiment.

[0051] Furthermore, in order to achieve separation between the second source and the corresponding first source, before completing subsequent manufacturing steps based on the device manufacturing process, the implementation steps of the isolation setting of the first source and the second source in the corresponding basic device unit include: performing ion implantation in the barrier layer exposed between the first source and the second source in the corresponding basic device unit to form an ion implantation area, and utilizing the ion implantation area to achieve isolation between the first source and the adjacent second source.

[0052] As another embodiment, the steps for implementing the isolation setting of the first source and the second source in the corresponding basic device unit include: defining P-GaN on the surface of the barrier layer between the first source and the second source in the corresponding basic device unit to form a P-GaN isolation structure, and isolating the first source and the adjacent second source through the P-GaN isolation structure.

[0053] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A power device, characterized in that: It includes multiple basic device units, each of which includes a gate, a source and a drain; the source of at least one basic device unit includes a first source and a second source, and the sources of other basic device units only include the first source, and the first source and the second source in the corresponding basic device unit are isolated; wherein the first source and the gate and drain of the corresponding basic device unit constitute a MainFET, and the second source and the gate and drain of the corresponding basic device unit constitute a SenseFET, wherein when the source of the basic device unit includes the first source and the second source, the length of the second source is less than the length of the first source in the corresponding basic device unit.

2. The power device according to claim 1, characterized in that: When the source of the basic device unit includes a first source and at least one second source, the at least one second source is distributed in one or more sections corresponding to the middle of the first source.

3. The power device according to claim 1, characterized in that: The isolation arrangement of the first source and the second source in the corresponding basic device unit is specifically as follows: an ion implantation region is provided in the barrier layer exposed between the first source and the second source in the corresponding basic device unit, and the isolation of the first source and the adjacent second source is achieved by using the ion implantation region.

4. The power device according to claim 1, characterized in that: The isolation arrangement of the first source and the second source in the corresponding basic device unit is specifically as follows: the surface of the barrier layer between the first source and the second source in the corresponding basic device unit has a P-GaN isolation structure, and the isolation of the first source and the adjacent second source is achieved through the P-GaN isolation structure.

5. The power device according to claim 1, characterized in that: Each second source electrode is connected together and then connected to the second source electrode pad through a resistor, and each first source electrode is connected together and then connected to the first source electrode pad.

6. The power device according to claim 1, characterized in that: The SenseFET and the MainFET share a gate and a drain, but the SenseFET and the MainFET do not share a source.

7. A method for manufacturing a power device, characterized in that: The following steps are involved: Providing a substrate, forming a GaN layer on the surface of the substrate, forming a barrier layer on the surface of the GaN layer, and forming a P-GaN layer in a gate region on the surface of the barrier layer; A plurality of basic device units are formed on the surface of the barrier layer and the P-GaN layer, each of which includes a gate, a source and a drain located on both sides of the gate; wherein the source of at least one basic device unit includes a first source and a second source, and the source of other basic device units includes only the first source; the first source and the second source in the corresponding basic device unit are isolated, and the first source and the gate and drain of the corresponding basic device unit constitute a MainFET, and the second source and the gate and drain of the corresponding basic device unit constitute a SenseFET; Subsequent manufacturing is completed based on the device manufacturing process to obtain a power device.

8. The method for manufacturing a power device according to claim 7, characterized in that: When the source of the basic device unit includes a first source and a second source, the length of the second source is smaller than the length of the first source in the corresponding basic device unit.

9. The method for manufacturing a power device according to claim 7, characterized in that: The steps for implementing the isolation setting of the first source and the second source in the corresponding basic device unit include: performing ion implantation in the barrier layer exposed between the first source and the second source in the corresponding basic device unit to form an ion implantation area, and using the ion implantation area to isolate the first source and the adjacent second source.

10. The method for manufacturing a power device according to claim 7, characterized in that: The implementation steps of the isolation setting of the first source and the second source in the corresponding basic device unit include: defining P-GaN on the surface of the barrier layer between the first source and the second source in the corresponding basic device unit to form a P-GaN isolation structure, and isolating the first source and the adjacent second source through the P-GaN isolation structure.

Images