Display device, gate driving circuit, shift register unit and driving method thereof

Abstract

The present disclosure provides a display device, a gate drive circuit, a shift register unit and a driving method thereof. The shift register unit includes: an input subcircuit, coupled to an input control terminal and a pull-up node, for controlling the potential of the pull-up node under the potential control of the input control terminal; a plurality of signal output subcircuits, correspondingly coupled to a plurality of output control nodes, and correspondingly coupled to a plurality of signal output terminals, each of the signal output subcircuits being used to control the potential of the corresponding signal output terminal under the potential control of the corresponding output control node; a plurality of switch subcircuits, coupled to the pull-up node, and correspondingly coupled to a plurality of output control nodes, each of the switch subcircuits being used to control the pull-up node to be disconnected or connected to the corresponding output control node. The present disclosure can improve display quality.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display device, a gate driving circuit, a shift register unit and a driving method thereof. Background Art

[0002] The gate drive circuit is an important auxiliary circuit in an active matrix organic light-emitting diode (AMOLED) display. The existing gate drive circuit includes a plurality of cascaded shift register units. However, the gate drive circuit needs to be improved. Summary of the invention

[0003] The present disclosure aims to provide a display device, a gate driving circuit, a shift register unit and a driving method thereof.

[0004] According to one aspect of the present disclosure, there is provided a shift register unit, comprising:

[0005] An input subcircuit, coupled to the input control terminal and the pull-up node, for controlling the potential of the pull-up node under the potential control of the input control terminal;

[0006] A plurality of signal output subcircuits, coupled to the plurality of output control nodes and coupled to the plurality of signal output terminals, each of the signal output subcircuits being used to control the potential of the corresponding signal output terminal under the potential control of the corresponding output control node;

[0007] A plurality of switch sub-circuits are coupled to the pull-up node and correspondingly coupled to the plurality of output control nodes, and each of the switch sub-circuits is used to control the pull-up node to be disconnected or connected with the corresponding output control node.

[0008] Furthermore, the switch subcircuit is used to control the pull-up node and the output control node to be disconnected or connected according to the difference between the potential of the pull-up node and a preset value.

[0009] Furthermore, the switch subcircuit comprises:

[0010] A first switch transistor, wherein a first electrode of the first switch transistor is coupled to the pull-up node, a second electrode of the first switch transistor is coupled to the output control node, and a control electrode of the first switch transistor is coupled to a first power supply terminal.

[0011] Furthermore, the switch subcircuit further includes:

[0012] A second switch transistor, wherein a first electrode of the second switch transistor is coupled to the pull-up node, a second electrode of the second switch transistor is coupled to the output control node, and a control electrode of the second switch transistor is coupled to a second power supply terminal.

[0013] Furthermore, each of the switch sub-circuits further includes:

[0014] a first control transistor, wherein a first electrode of the first control transistor is coupled to the first power supply terminal, a second electrode of the first control transistor is coupled to a control electrode of the first switch transistor, and a control electrode of the first control transistor is coupled to a fixed power supply terminal;

[0015] A second control transistor, wherein a first electrode of the second control transistor is coupled to the second power supply terminal, a second electrode of the second control transistor is coupled to a control electrode of the second switch transistor, and a control electrode of the second control transistor is coupled to a fixed power supply terminal.

[0016] Further, the control electrodes of the first switch transistors of the plurality of switch subcircuits are coupled, the control electrodes of the second switch transistors of the plurality of switch subcircuits are coupled, and one of the plurality of switch subcircuits further includes:

[0017] a first control transistor, wherein a first electrode of the first control transistor is coupled to the first power supply terminal, a second electrode of the first control transistor is coupled to a control electrode of the first switch transistor, and a control electrode of the first control transistor is coupled to a fixed power supply terminal;

[0018] A second control transistor, wherein a first electrode of the second control transistor is coupled to the second power supply terminal, a second electrode of the second control transistor is coupled to a control electrode of the second switch transistor, and a control electrode of the second control transistor is coupled to a fixed power supply terminal.

[0019] Furthermore, the shift register unit further includes:

[0020] The cascade output subcircuit is coupled to the pull-up node and the cascade output terminal, and is used to control the potential of the cascade output terminal under the potential control of the pull-up node.

[0021] Furthermore, the shift register unit further includes:

[0022] A first inverting sub-circuit, coupled to the pull-up node, the first power supply terminal and the first pull-down node, and configured to control the first pull-down node to have an opposite phase to the pull-up node according to the potential of the first power supply terminal;

[0023] A first denoising sub-circuit is coupled to the first pull-down node and the reset power supply terminal, and is coupled to at least one of the cascade output terminal, the pull-up node and the signal output terminal, and is used to control the coupling of the reset power supply terminal to the signal output terminal under the potential control of the first pull-down node, and is also used to control the coupling of the reset power supply terminal to the cascade output terminal under the potential control of the first pull-down node, and is also used to control the coupling of the reset power supply terminal to the pull-up node under the potential control of the first pull-down node.

[0024] Furthermore, the shift register unit further includes:

[0025] A second inverting sub-circuit, coupled to the pull-up node, the second power supply terminal and the second pull-down node, for controlling the second pull-down node to have an opposite phase to the pull-up node according to the potential of the second power supply terminal;

[0026] A second denoising sub-circuit is coupled to the second pull-down node and the reset power supply terminal, and is coupled to at least one of the cascade output terminal, the pull-up node and the signal output terminal, and is used to control the coupling of the reset power supply terminal to the signal output terminal under the potential control of the second pull-down node, and is also used to control the coupling of the reset power supply terminal to the cascade output terminal under the potential control of the second pull-down node, and is also used to control the coupling of the reset power supply terminal to the pull-up node under the potential control of the second pull-down node.

[0027] Furthermore, the shift register unit further includes:

[0028] The reset subcircuit is coupled to the pull-up node, the reset power supply terminal and the reset control terminal, and is used for controlling the coupling of the reset power supply terminal and the pull-up node under the potential control of the reset control terminal.

[0029] According to one aspect of the present disclosure, a gate driving circuit is provided, comprising the shift register unit.

[0030] According to one aspect of the present disclosure, a display device is provided, comprising the gate driving circuit.

[0031] According to one aspect of the present disclosure, a driving method of a shift register unit is provided. The driving method adopts the shift register unit, and the driving method includes:

[0032] enabling the input subcircuit to control the potential of the pull-up node under the potential control of the input control terminal;

[0033] Enable each of the signal output sub-circuits to control the potential of the corresponding signal output terminal under the potential control of the corresponding output control node;

[0034] Each of the switch sub-circuits is used to control the pull-up node to be disconnected or connected with the corresponding output control node.

[0035] The display device, gate drive circuit, shift register unit and driving method disclosed in the present invention, during operation, when it is necessary to control the potential of each output control node according to the pull-up node, the switch subcircuit is set to be in the on state; when each signal output subcircuit outputs a signal, the switch subcircuit is set to be in the off state, so as to avoid the potential change of any output control node from affecting the potential of the pull-up node and other output control nodes, and at the same time avoid the potential change of the pull-up node from affecting the potential of the output control node, so that the falling time of the output signal of each signal output terminal tends to be consistent, and avoid the difference in display effects of different pixel rows of the display panel, so as to improve the display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a circuit diagram of a shift register unit in the related art.

[0037] Figure 2 yes Figure 1 Working timing diagram of the structure shown.

[0038] Figure 3 is a block diagram of a shift register unit according to an embodiment of the present disclosure.

[0039] Figure 4 is another block diagram of a shift register unit according to an embodiment of the present disclosure.

[0040] Figure 5-7 is a circuit diagram of a shift register unit according to an embodiment of the present disclosure.

[0041] Figure 8 1 is a timing diagram of the operation of the shift register unit according to an embodiment of the present disclosure.

[0042] Fig. 9 is a schematic diagram of a gate drive circuit according to an embodiment of the present disclosure.

[0043] Description of the accompanying drawings: 1. input subcircuit; 2. signal output subcircuit; 201. first signal output subcircuit; 202. second signal output subcircuit; 203. third signal output subcircuit; 204. fourth signal output subcircuit; 3. switch subcircuit; 4. cascade output subcircuit; 401. first cascade output subcircuit; 402. second cascade output subcircuit; 5. first inversion subcircuit; 6. first denoising subcircuit; 7. second inversion subcircuit; 8. second denoising subcircuit; 9. reset subcircuit; 10. anti-leakage electronic circuit; T1. first input transistor; T 2, the second input transistor; T3, the first output transistor; T4, the second output transistor; T5, the third output transistor; T6, the fourth output transistor; T7, the first switch transistor; T8, the second switch transistor; T9, the first control transistor; T10, the second control transistor; T11, the first cascade output transistor; T12, the second cascade output transistor; T13, the first de-noising transistor; T14, the second de-noising transistor; T15, the third de-noising transistor; T16, the fourth de-noising transistor; T17, the fifth de-noising transistor; T18, the sixth de-noising transistor tube; T19, the seventh de-noising transistor; T20, the eighth de-noising transistor; T21, the first reset transistor; T22, the second reset transistor; T23, the anti-leakage transistor; U1, the first inverter; U2, the second inverter; STU, the input control terminal; OUT1, the first signal output terminal; OUT2, the second signal output terminal; OUT3, the third signal output terminal; OUT4, the fourth signal output terminal; CLKE1, the first clock signal terminal; CLKF1, the second clock signal terminal; CLKE2, the third clock signal terminal; CLKF2, the fourth clock signal terminal; CLKD1, the fifth clock signal terminal; CLKD2, the sixth clock signal terminal; Vdda, the first power supply terminal; Vddb, the second power supply terminal; Vdd, the fixed power supply terminal; CR1, the first cascade output terminal; CR2, the second cascade output terminal; VGL1, the first reset power supply terminal; VGL2, the second reset power supply terminal; STD, the reset control terminal; PU, the pull-up node; Q1, the first output control node; Q2, the second output control node; Q3, the third output control node; Q4, the fourth output control node; QB1, the first pull-down node; QB2, the second pull-down node. DETAILED DESCRIPTION

[0044] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices consistent with some aspects of the present disclosure as detailed in the appended claims.

[0045] The terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the disclosure. Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the disclosure belongs. The words "first", "second" and similar words used in this disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantitative limit, but indicate that there is at least one. "Multiple" or "several" means two and more than two. Words such as "include" or "include" mean that the elements or objects appearing in front of "include" or "include" cover the elements or objects listed after "include" or "include" and their equivalents, and do not exclude other elements or objects. The singular forms of "one", "said" and "the" used in this disclosure and the attached claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0046] The transistors used in the present disclosure can be triodes, thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.

[0047] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0048] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0049] In related technologies, such as Figure 1As shown, the shift register unit may include a first output transistor T3 and a second output transistor T4. The control electrode of the first output transistor T3 is coupled to the pull-up node PU, the first electrode of the first output transistor T3 is coupled to the first clock signal terminal CLKE1, and the second electrode of the first output transistor T3 is coupled to the first signal output terminal OUT1. The control electrode of the second output transistor T4 is coupled to the pull-up node PU, the first electrode of the second output transistor T4 is coupled to the second clock signal terminal CLKF1, and the second electrode of the second output transistor T4 is coupled to the second signal output terminal OUT2. The first signal output terminal OUT1 and the second signal output terminal OUT2 are coupled to different pixel rows of the display panel. In addition, the first signal output terminal OUT1 and the second signal output terminal OUT2 are both coupled to the pull-up node PU with a first energy storage capacitor C1. As shown Figure 2 As shown, during the operation of the shift register unit, a high level is first written to the pull-up node PU. When the first clock signal terminal CLKE1 is high, the potential of the pull-up node PU is pulled up under the coupling effect of the first energy storage capacitor C1, and the first signal output terminal OUT1 outputs a high level; when the second clock signal terminal CLKF1 is high, the potential of the pull-up node PU is pulled up again under the coupling effect of the first energy storage capacitor C1, and the second signal output terminal OUT2 outputs a high level. It can be seen that the potential of the pull-up node PU has changed, resulting in the fall time t (Fall Time) of the output signal of the first signal output terminal OUT1 being less than the fall time t (Fall Time) of the output signal of the second signal output terminal OUT2, thereby causing the display effects of different pixel rows of the display panel to be different, reducing the display quality.

[0050] The present disclosure provides a shift register unit. Figure 3 and Figure 4 As shown, the shift register unit may include an input subcircuit 1, a plurality of signal output subcircuits 2, and a plurality of switch subcircuits 3, wherein:

[0051] The input subcircuit 1 is coupled to the input control terminal STU and the pull-up node PU, and is used to control the potential of the pull-up node PU under the potential control of the input control terminal STU. Figure 3 Q1, Q2, Q3, Q4) in one-to-one coupling, and with a plurality of signal output terminals ( Figure 3 The signal output sub-circuits 2 are coupled to the pull-up node PU and the output control nodes in a one-to-one manner. Each signal output sub-circuit 2 is used to control the potential of the corresponding signal output terminal under the potential control of the corresponding output control node. A plurality of switch sub-circuits 3 are coupled to the pull-up node PU and are coupled to the plurality of output control nodes in a one-to-one manner. Each switch sub-circuit 3 is used to control the pull-up node PU to be disconnected or connected to the corresponding output control node.

[0052] The shift register unit of the embodiment of the present disclosure, during operation, when it is necessary to control the potential of each output control node according to the pull-up node PU, the switch subcircuit 3 is set to be in the on state; when each signal output subcircuit 2 outputs a signal, the switch subcircuit 3 is set to be in the off state, so as to avoid the potential change of any output control node from affecting the potential of the pull-up node PU and other output control nodes, and at the same time avoid the potential change of the pull-up node PU from affecting the potential of the output control node, so that the falling time of the output signal of each signal output terminal is as consistent as possible, so as to avoid large differences in the display effects of different pixel rows of the display panel, so as to improve the display quality.

[0053] The following is a detailed description of each part of the shift register unit according to the embodiment of the present disclosure:

[0054] like Figure 3 , Figure 4 , Figure 5 as well as Figure 7 As shown, the input subcircuit 1 is coupled to the input control terminal STU and the pull-up node PU, and is used to control the potential of the pull-up node PU under the potential control of the input control terminal STU. The number of the input subcircuit 1 can be one or two. For example, each input subcircuit 1 may include a first input transistor T1 and a second input transistor T2. The control electrode of the first input transistor T1 is coupled to the input control terminal STU, and the first electrode of the first input transistor T1 is coupled to the input control terminal STU. The control electrode of the second input transistor T2 is coupled to the input control terminal STU, the first electrode of the second input transistor T2 is coupled to the second electrode of the first input transistor T1, and the second electrode of the second input transistor T2 is coupled to the pull-up node PU.

[0055] like Figure 3 and Figure 4 As shown, a plurality of signal output sub-circuits 2 are coupled to a plurality of output control nodes in a one-to-one correspondence, and are coupled to a plurality of signal output terminals in a one-to-one correspondence, and are coupled to a plurality of clock signal terminals ( Figure 31, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 110, 111, 109, 111, 112, 113, 114, 115, 116, 117, 118, 119, 119, 111, 112, 113

[0056] The first signal output subcircuit 201 may include a first output transistor T3, the second signal output subcircuit 202 may include a second output transistor T4, the third signal output subcircuit 203 may include a third output transistor T5, and the fourth signal output subcircuit 204 may include a fourth output transistor T6. The control electrode of the first output transistor T3 is coupled to the first output control node Q1, the first electrode of the first output transistor T3 is coupled to the first clock signal terminal CLKE1, and the second electrode of the first output transistor T3 is coupled to the first signal output terminal OUT1. The control electrode of the second output transistor T4 is coupled to the second output control node Q2, the first electrode of the second output transistor T4 is coupled to the second clock signal terminal CLKF1, and the second electrode of the second output transistor T4 is coupled to the second signal output terminal OUT2. The control electrode of the third output transistor T5 is coupled to the third output control node Q3, the first electrode of the third output transistor T5 is coupled to the third clock signal terminal CLKE2, and the second electrode of the third output transistor T5 is coupled to the third signal output terminal OUT3. The control electrode of the fourth output transistor T6 is coupled to the fourth output control node Q4, the first electrode of the fourth output transistor T6 is coupled to the fourth clock signal terminal CLKF2, and the second electrode of the fourth output transistor T6 is coupled to the fourth signal output terminal OUT4. In addition, each output sub-circuit may further include a first energy storage capacitor C1, and the first energy storage capacitor C1 may be coupled between the output control node and the signal output terminal.

[0057] A plurality of switch subcircuits 3 are coupled to the pull-up node PU and are coupled to the plurality of output control nodes in a one-to-one correspondence, and each switch subcircuit 3 is used to control the pull-up node PU to be disconnected or connected to the corresponding output control node. The switch subcircuit 3 is used to control the pull-up node PU to be disconnected or connected to the output control node according to the difference between the potential of the pull-up node PU and a preset value.

[0058] In one embodiment of the present disclosure, Figure 3-5 As shown, the shift register unit of the embodiment of the present disclosure may include a first shift register section 100 and a second shift register section 200. The first shift register section 100 and the second shift register section 200 may share at least one pull-up node PU, a signal input subcircuit 1, a reset subcircuit 9, a first denoising subcircuit 6, and one of the second denoising subcircuit 8. Of course, the first shift register section 100 and the second shift register section 200 may also have a pull-up node PU, a signal input subcircuit 1, a reset subcircuit 9, a first denoising subcircuit 6, and a second denoising subcircuit 8, respectively. For example, the first shift register section 100 has a first shift register section pull-up node PU, a first shift register section signal input subcircuit 1, a first shift register section reset subcircuit 9, a first shift register section first denoising subcircuit 6, and a first shift register section second denoising subcircuit 8; the second shift register section 200 has a second shift register section pull-up node PU, a second shift register section signal input subcircuit 1, a second shift register section reset subcircuit 9, a second shift register section first denoising subcircuit 6, and a second shift register section second denoising subcircuit 8. The first shift register section 100 has a first shift register section pull-up node PU, which is connected to the first cascade output subcircuit 401; the second shift register section 200 has a second shift register section pull-up node PU, which is connected to the second cascade output subcircuit 402. The voltages of the first shift register section pull-up node PU and the second shift register section pull-up node PU may be equal.

[0059] The switch subcircuit 3 may include a first switch transistor T7. The first electrode of the first switch transistor T7 is coupled to the pull-up node PU, the second electrode of the first switch transistor T7 is coupled to the output control node, and the control electrode of the first switch transistor T7 is coupled to the first power supply terminal Vdda. The switch subcircuit 3 may also include a second switch transistor T8. The first electrode of the second switch transistor T8 is coupled to the pull-up node PU, the second electrode of the second switch transistor T8 is coupled to the output control node, and the control electrode of the second switch transistor T8 is coupled to the second power supply terminal Vddb. The timing diagram of the first power supply terminal Vdda and the second power supply terminal Vddb is as shown in FIG. Figure 8As shown, the first power supply terminal Vdda and the second power supply terminal Vddb are alternately high level, and the potential of the first power supply terminal Vdda at the high level is the same as the potential of the second power supply terminal Vddb at the high level. The above-mentioned preset value can be the potential of the control electrode of the first switch transistor T7 or the second switch transistor T8. Among them, when the difference between the potential of the pull-up node PU and the preset value is less than the threshold voltage of the first switch transistor T7 or the second switch transistor T8, the switch subcircuit 3 is disconnected; when the difference between the potential of the pull-up node PU and the preset value is greater than the threshold voltage of the first switch transistor T7 or the second switch transistor T8, the switch subcircuit 3 is turned on. The threshold voltages of the first switch transistor T7 and the second switch transistor T8 can be the same.

[0060] In one embodiment of the present disclosure, Figure 5 As shown, each switch subcircuit 3 may further include a first control transistor T9 and a second control transistor T10. The first electrode of the first control transistor T9 is coupled to the first power supply terminal Vdda, the second electrode of the first control transistor T9 is coupled to the control electrode of the first switch transistor T7, and the control electrode of the first control transistor T9 is coupled to the fixed power supply terminal Vdd. The fixed power supply terminal Vdd can stably output a high level signal or a low level signal. The first electrode of the second control transistor T10 is coupled to the second power supply terminal Vddb, the second electrode of the second control transistor T10 is coupled to the control electrode of the second switch transistor T8, and the control electrode of the second control transistor T10 is coupled to the fixed power supply terminal Vdd.

[0061] In another embodiment of the present disclosure, Figure 6 As shown, the control electrodes of the first switch transistors T7 of the plurality of switch subcircuits 3 are coupled, the control electrodes of the second switch transistors T8 of the plurality of switch subcircuits 3 are coupled, and one switch subcircuit 3 among the plurality of switch subcircuits 3 further includes a first control transistor T9 and a second control transistor T10. The first electrode of the first control transistor T9 is coupled to the first power supply terminal Vdda, the second electrode of the first control transistor T9 is coupled to the control electrode of the first switch transistor T7, and the control electrode of the first control transistor T9 is coupled to the fixed power supply terminal Vdd. The first electrode of the second control transistor T10 is coupled to the second power supply terminal Vddb, the second electrode of the second control transistor T10 is coupled to the control electrode of the second switch transistor T8, and the control electrode of the second control transistor T10 is coupled to the fixed power supply terminal Vdd.

[0062] The shift register unit may further include a cascade output subcircuit 4. The cascade output subcircuit 4 is connected to the pull-up node PU and the clock signal terminal ( Figure 4 CLKD1, CLKD2) and the cascade output terminal ( Figure 4CR1, CR2) in the pull-up node PU, and is used to control the coupling of the cascade output terminal and the clock signal terminal under the potential control of the pull-up node PU. Wherein, the number of the cascade output sub-circuit 4 and the cascade output terminal are both two, that is, the shift register unit may include a first cascade output sub-circuit 401 and a second cascade output sub-circuit 402, the first cascade output sub-circuit 401 is coupled to the first cascade output terminal CR1, and the second cascade output sub-circuit 402 is coupled to the second cascade output terminal CR2. For example, the first cascade output sub-circuit 401 includes a first cascade output transistor T11, and the second cascade output sub-circuit 402 includes a second cascade output transistor T12. The control electrode of the first cascade output transistor T11 is coupled to the pull-up node PU, the first electrode of the first cascade output transistor T11 is coupled to the fifth clock signal terminal CLKD1, and the second electrode of the first cascade output transistor T11 is coupled to the first cascade output terminal CR1. The control electrode of the second cascade output transistor T12 is coupled to the pull-up node PU, the first electrode of the second cascade output transistor T12 is coupled to the sixth clock signal terminal CLKD2, and the second electrode of the second cascade output transistor T12 is coupled to the second cascade output terminal CR2. In addition, each cascade output sub-circuit 4 may further include a second energy storage capacitor C2, and the second energy storage capacitor C2 is coupled between the first cascade output terminal CR1 and the second cascade output terminal CR2 and the pull-up node PU.

[0063] The shift register unit of the embodiment of the present disclosure may include a first inverting sub-circuit 5 and a first denoising sub-circuit 6. The first inverting sub-circuit 5 is coupled to the pull-up node PU, the first power supply terminal Vdda and the first pull-down node QB1, and is used to control the first pull-down node QB1 to have a phase opposite to that of the pull-up node PU according to the potential of the first power supply terminal Vdda. The first inverting sub-circuit 5 may include a first inverter U1. The first denoising sub-circuit 6 is coupled to the first pull-down node QB1, the reset power supply terminal ( Figure 4 The first denoising sub-circuit 6 is coupled to the first pull-down node QB1, the reset power supply terminal (VGL1, VGL2) and the signal output terminal, and is used to control the reset power supply terminal to couple with the signal output terminal under the potential control of the first pull-down node QB1. Figure 4 The first denoising sub-circuit 6 is coupled to the first pull-down node QB1, the reset power supply terminal (VGL1, VGL2) and the cascade output terminal, and is used to control the reset power supply terminal to couple with the cascade output terminal under the potential control of the first pull-down node QB1. Figure 4 VGL1, VGL2) in the first pull-down node QB1 and the pull-up node PU are coupled to control the reset power supply terminal to be coupled to the pull-up node PU under the potential control of the first pull-down node QB1.

[0064] The first de-noising sub-circuit 6 may include a first de-noising transistor T13 and a second de-noising transistor T14. The control electrode of the first de-noising transistor T13 is coupled to the first pull-down node QB1, the first electrode of the first de-noising transistor T13 is coupled to the first reset power supply terminal VGL1, and the second electrode of the first de-noising transistor T13 is coupled to the cascade output terminal. The control electrode of the second de-noising transistor T14 is coupled to the first pull-down node QB1, the first electrode of the second de-noising transistor T14 is coupled to the second reset power supply terminal VGL2, and the second electrode of the second de-noising transistor T14 is coupled to the signal output terminal. The first de-noising sub-circuit 6 may also include a third de-noising transistor T15 and a fourth de-noising transistor T16. The control electrode of the third de-noising transistor T15 is coupled to the first pull-down node QB1, and the first electrode of the third de-noising transistor T15 is coupled to the first reset power supply terminal VGL1. The control electrode of the fourth de-noising transistor T16 is coupled to the first pull-down node QB1 , the first electrode of the fourth de-noising transistor T16 is coupled to the second electrode of the third de-noising transistor T15 , and the second electrode of the fourth de-noising transistor T16 is coupled to the pull-up node PU.

[0065] The shift register unit of the embodiment of the present disclosure may include a second inverting sub-circuit 7 and a second denoising sub-circuit 8. The second inverting sub-circuit 7 is coupled to the pull-up node PU, the second power supply terminal Vddb and the second pull-down node QB2, and is used to control the second pull-down node QB2 to have a phase opposite to that of the pull-up node PU according to the potential of the second power supply terminal Vddb. The second inverting sub-circuit 7 may include a second inverter U2. The second denoising sub-circuit 8 is coupled to the second pull-down node QB2, the reset power supply terminal ( Figure 4 VGL1, VGL2 in the circuit), the cascade output terminal, the pull-up node PU and the signal output terminal are coupled, and are used to control the coupling of the reset power supply terminal and the signal output terminal under the potential control of the second pull-down node QB2, and are also used to control the coupling of the reset power supply terminal and the cascade output terminal under the potential control of the second pull-down node QB2, and are also used to control the coupling of the reset power supply terminal and the pull-up node PU under the potential control of the second pull-down node QB2.

[0066] The second de-noising sub-circuit 8 may include a fifth de-noising transistor T17 and a sixth de-noising transistor T18. The control electrode of the fifth de-noising transistor T17 is coupled to the second pull-down node QB2, the first electrode of the fifth de-noising transistor T17 is coupled to the first reset power supply terminal VGL1, and the second electrode of the fifth de-noising transistor T17 is coupled to the cascade output terminal. The control electrode of the sixth de-noising transistor T18 is coupled to the second pull-down node QB2, the first electrode of the sixth de-noising transistor T18 is coupled to the second reset power supply terminal VGL2, and the second electrode of the sixth de-noising transistor T18 is coupled to the signal output terminal. The second de-noising sub-circuit 8 may also include a seventh de-noising transistor T19 and an eighth de-noising transistor T20. The control electrode of the seventh de-noising transistor T19 is coupled to the second pull-down node QB2, and the first electrode of the seventh de-noising transistor T19 is coupled to the first reset power supply terminal VGL1. The control electrode of the eighth de-noising transistor T20 is coupled to the second pull-down node QB2 , the first electrode of the eighth de-noising transistor T20 is coupled to the second electrode of the seventh de-noising transistor T19 , and the second electrode of the eighth de-noising transistor T20 is coupled to the pull-up node PU.

[0067] The shift register unit of the embodiment of the present disclosure may further include a reset subcircuit 9. The reset subcircuit 9 may be coupled to the pull-up node PU, the reset power supply terminal and the reset control terminal STD, and is used to control the reset power supply terminal to couple with the pull-up node PU under the potential control of the reset control terminal STD. The number of the reset subcircuit 9 may be one or two. For example, each reset subcircuit 9 may include a first reset transistor T21 and a second reset transistor T22. The control electrode of the first reset transistor T21 is coupled to the reset control terminal STD, and the first electrode of the first reset transistor T21 is coupled to the reset power supply terminal. The control electrode of the second reset transistor T22 is coupled to the reset control terminal STD, the first electrode of the second reset transistor T22 is coupled to the second electrode of the first reset transistor T21, and the second electrode of the second reset transistor T22 is coupled to the pull-up node PU.

[0068] The shift register unit of the embodiment of the present disclosure may also include an anti-leakage electronic circuit 10. The anti-leakage electronic circuit 10 may be coupled to the pull-up node PU, the fixed power supply terminal Vdd, the second pole of the first input transistor T1, the second pole of the first reset transistor T21, the second pole of the third de-noising transistor T15, and the second pole of the seventh de-noising transistor T19. The anti-leakage subcircuit is used to control the fixed power supply terminal Vdd to couple with the second pole of the first input transistor T1 under the potential control of the pull-up node PU. The anti-leakage subcircuit is used to control the fixed power supply terminal Vdd to couple with the second pole of the first reset transistor T21 under the potential control of the pull-up node PU. The anti-leakage subcircuit is used to control the fixed power supply terminal Vdd to couple with the second pole of the third de-noising transistor T15 under the potential control of the pull-up node PU. The anti-leakage subcircuit is used to control the fixed power supply terminal Vdd to couple with the second pole of the seventh de-noising transistor T19 under the potential control of the pull-up node PU. For example, the anti-leakage electronic circuit 10 may include an anti-leakage transistor T23. The control electrode of the anti-leakage transistor T23 can be coupled to the pull-up node PU, the first electrode of the anti-leakage transistor T23 can be coupled to the fixed power supply terminal Vdd, and the second electrode of the anti-leakage transistor T23 can be coupled to the second electrode of the first input transistor T1, the second electrode of the first reset transistor T21, the second electrode of the third de-noising transistor T15, and the second electrode of the seventh de-noising transistor T19.

[0069] Combine the following Figure 8 The circuit timing diagram shown and Figure 5 The circuit diagram shown describes the working process of the shift register unit provided by the present disclosure. All transistors in the shift register unit are N-type transistors.

[0070] Before the rising edge of the fifth clock signal terminal CLKD1, the input control terminal STU needs to be set to a high level to turn on the first transistor and the second transistor, thereby making the pull-up node PU a high level. Since the first power supply terminal Vdda and the second power supply terminal Vddb are alternately high levels, one of the first switch transistor T7 and the second switch transistor T8 must be turned on, and each output control node ( Figure 5 Q1, Q2, Q3, Q4) in are high level.

[0071] When the fifth clock signal terminal CLKD1 changes to a high level, the pull-up node PU is pulled up under the coupling effect of the second energy storage capacitor C2, and the difference between the control electrode potential of the first switch transistor T7 and the potential of the pull-up node PU is less than the threshold voltage of the first switch transistor T7, and the first switch transistor T7 is turned off. Similarly, the second switch transistor T8 is also in a disconnected state. At this time, each output control node ( Figure 5 The potential of Q1, Q2, Q3, Q4) will not be affected by the pull-up node PU.

[0072] When the first clock signal terminal CLKE1 becomes a high level, the potential of the first output control node Q1 is pulled up under the coupling effect of the first energy storage capacitor C1, and the first signal output terminal OUT1 outputs. At this time, since the first switch transistor T7 and the second switch transistor T8 are both disconnected, the potentials of other output control nodes will not be affected by the potential of the first output control node Q1; similarly, when the second clock signal terminal CLKF1, the third clock signal terminal CLKE2 and the fourth clock signal terminal CLKF2 become high levels in turn, the second signal output terminal OUT2, the third signal output terminal OUT3 and the fourth signal output terminal OUT4 output in turn. It can be seen that through the switch sub-circuit 3 disclosed in the present invention, each output control node and the pull-up node PU can be isolated, so that the falling time of the output signal of each signal output terminal tends to be consistent.

[0073] The present disclosure also provides a gate drive circuit. Fig. 9 As shown, the gate driving circuit may include a plurality of shift register units of any of the above embodiments. Figure 5 As shown, each shift register unit according to the embodiment of the present disclosure may include a first shift register section 100 and a second shift register section 200 . Fig. 9 A1, A3 and A5 represent the first shift register unit 100, and A2, A4 and A6 represent the second shift register unit 200, respectively. Fig. 9 CR in represents the cascade signal output terminal; Fig. 9 CR <n-2>represents the input control terminal STU of the first shift register unit 100, CR<N+2> represents a reset control terminal STD of the first shift register section 100; Fig. 9 CR <n-3>represents the input control terminal STU of the second shift register unit 200, CR<N+2> represents the reset control terminal STD of the second shift register section 200. In addition, each shift register unit corresponds to four pixel rows of the display panel.

[0074] The present disclosure also provides a display device, which may include the gate driving circuit of the above embodiment.

[0075] The embodiment of the present disclosure also provides a driving method of a shift register unit. The driving method adopts the shift register unit of the above embodiment. The driving method may include: enabling the input subcircuit 1 to control the potential of the pull-up node PU under the potential control of the input control terminal STU; enabling each signal output subcircuit 2 to control the potential of the corresponding signal output terminal under the potential control of the corresponding output control node; enabling each switch subcircuit 3 to control the pull-up node PU to be disconnected or connected with the corresponding output control node.

[0076] The display device, gate driving circuit, shift register unit and driving method thereof provided in the embodiments of the present disclosure belong to the same inventive concept, and the descriptions of relevant details and beneficial effects can be referred to each other and will not be repeated here.

[0077] The above is only a preferred implementation mode of the present disclosure, and does not limit the present disclosure in any form. Although the present disclosure has been disclosed as a preferred implementation mode as above, it is not used to limit the present disclosure. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent implementation modes without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above implementation modes based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still fall within the scope of the technical solution of the present disclosure.

Claims

1. A shift register unit, characterized in that: include: An input subcircuit, coupled to the input control terminal and the pull-up node, for controlling the potential of the pull-up node under the potential control of the input control terminal; A plurality of signal output subcircuits, coupled to the plurality of output control nodes and coupled to the plurality of signal output terminals, each of the signal output subcircuits being used to control the potential of the corresponding signal output terminal under the potential control of the corresponding output control node; A plurality of switch sub-circuits are coupled to the pull-up node and correspondingly coupled to the plurality of output control nodes, each of the switch sub-circuits is used to control the pull-up node to be disconnected or connected to the corresponding output control node; wherein, The switch subcircuit comprises: a first switch transistor, wherein a first electrode of the first switch transistor is coupled to the pull-up node, a second electrode of the first switch transistor is coupled to the output control node, and a control electrode of the first switch transistor is coupled to a first power supply terminal; a second switch transistor, wherein a first electrode of the second switch transistor is coupled to the pull-up node, a second electrode of the second switch transistor is coupled to the output control node, and a control electrode of the second switch transistor is coupled to a second power supply terminal; One of the plurality of switch sub-circuits includes: a first control transistor, wherein a first electrode of the first control transistor is coupled to the first power supply terminal, a second electrode of the first control transistor is coupled to a control electrode of the first switch transistor, and a control electrode of the first control transistor is coupled to a fixed power supply terminal; A second control transistor, wherein a first electrode of the second control transistor is coupled to the second power supply terminal, a second electrode of the second control transistor is coupled to a control electrode of the second switch transistor, and a control electrode of the second control transistor is coupled to a fixed power supply terminal.

2. The shift register unit according to claim 1, characterized in that: The switch subcircuit is used to control the pull-up node and the output control node to be disconnected or connected according to the difference between the potential of the pull-up node and a preset value.

3. The shift register unit according to claim 1, characterized in that: Each of the switch sub-circuits comprises: a first control transistor, wherein a first electrode of the first control transistor is coupled to the first power supply terminal, a second electrode of the first control transistor is coupled to a control electrode of the first switch transistor, and a control electrode of the first control transistor is coupled to a fixed power supply terminal; A second control transistor, wherein a first electrode of the second control transistor is coupled to the second power supply terminal, a second electrode of the second control transistor is coupled to a control electrode of the second switch transistor, and a control electrode of the second control transistor is coupled to a fixed power supply terminal.

4. The shift register unit according to claim 1, characterized in that: The control electrodes of the first switch transistors of the plurality of switch sub-circuits are coupled, and the control electrodes of the second switch transistors of the plurality of switch sub-circuits are coupled.

5. The shift register unit according to claim 1, characterized in that: The shift register unit also includes: The cascade output subcircuit is coupled to the pull-up node and the cascade output terminal, and is used to control the potential of the cascade output terminal under the potential control of the pull-up node.

6. The shift register unit according to claim 5, characterized in that: The shift register unit also includes: A first inverting sub-circuit, coupled to the pull-up node, the first power supply terminal and the first pull-down node, and configured to control the first pull-down node to have an opposite phase to the pull-up node according to the potential of the first power supply terminal; A first denoising sub-circuit is coupled to the first pull-down node and the reset power supply terminal, and is coupled to at least one of the cascade output terminal, the pull-up node and the signal output terminal, and is used to control the coupling of the reset power supply terminal to the signal output terminal under the potential control of the first pull-down node, and is also used to control the coupling of the reset power supply terminal to the cascade output terminal under the potential control of the first pull-down node, and is also used to control the coupling of the reset power supply terminal to the pull-up node under the potential control of the first pull-down node.

7. The shift register unit according to claim 6, characterized in that: The shift register unit also includes: A second inverting sub-circuit, coupled to the pull-up node, the second power supply terminal and the second pull-down node, for controlling the second pull-down node to have an opposite phase to the pull-up node according to the potential of the second power supply terminal; A second denoising sub-circuit is coupled to the second pull-down node and the reset power supply terminal, and is coupled to at least one of the cascade output terminal, the pull-up node and the signal output terminal, and is used to control the coupling of the reset power supply terminal to the signal output terminal under the potential control of the second pull-down node, and is also used to control the coupling of the reset power supply terminal to the cascade output terminal under the potential control of the second pull-down node, and is also used to control the coupling of the reset power supply terminal to the pull-up node under the potential control of the second pull-down node.

8. The shift register unit according to claim 1, characterized in that: The shift register unit also includes: The reset subcircuit is coupled to the pull-up node, the reset power supply terminal and the reset control terminal, and is used for controlling the coupling of the reset power supply terminal and the pull-up node under the potential control of the reset control terminal.

9. A gate drive circuit, characterized in that: The invention comprises the shift register unit as claimed in any one of claims 1 to 8.

10. A display device, characterized in that: Includes the gate drive circuit as claimed in claim 9.

11. A driving method of a shift register unit, characterized in that: The driving method adopts the shift register unit according to any one of claims 1 to 8, and the driving method comprises: enabling the input subcircuit to control the potential of the pull-up node under the potential control of the input control terminal; Enable each of the signal output sub-circuits to control the potential of the corresponding signal output terminal under the potential control of the corresponding output control node; Each of the switch sub-circuits is used to control the pull-up node to be disconnected or connected with the corresponding output control node.

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