Half-hole circuit board and its manufacturing method
By forming metal layers in blind holes and connecting them through a through-hole, the method strengthens bonding in circuit boards, reducing copper whisker formation and improving yield.
Patent Information
- Application Number
- CN202110700217.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-06-23
- Publication Date
- 2025-07-15
- Estimated Expiration
- 2041-06-23
AI Technical Summary
The weak bonding between copper skin and the substrate in metalized holes of circuit boards leads to copper whiskers during drilling, causing short circuits and reducing product yield.
A method involving the formation of metal layers in blind holes and connecting them through a through-hole, enhancing the bonding strength between the metal layers and the substrate, thereby reducing copper whisker formation during drilling.
The method improves the bonding strength between metal layers and the substrate, reducing copper whisker formation and enhancing the yield of circuit boards with metalized holes.
Smart Images
Figure CN115515304B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of printed circuit boards, and particularly to a printed circuit board half-hole board and a manufacturing method thereof. Background Art
[0002] A printed circuit board half-hole board refers to a printed circuit board having metallized half-holes at the board edge position. The metallized half-holes not only have the function of electrical conduction but also can be used for welding and fixing by means of the half-hole walls, realizing the fixation between the printed circuit board half-hole board and the to-be-connected components (such as other circuit boards, mother boards or electronic components). Currently, when a milling cutter cuts a metallized hole, since the bonding force between the copper foil in the metallized hole and the substrate layer is weak, it is easy to cause copper wires (burrs) to form in the hole and on the hole surface. Subsequently, when the printed circuit board half-hole board is connected to the to-be-connected components, the copper wires will cause short-circuit problems and reduce the product yield. Summary of the Invention
[0003] In view of this, the present application provides a manufacturing method of a printed circuit board half-hole board that can improve the yield.
[0004] In addition, the present application also provides a printed circuit board half-hole board manufactured by the above manufacturing method.
[0005] An embodiment of the present application provides a manufacturing method of a printed circuit board half-hole board, including the following steps:
[0006] Provide a copper-clad substrate, the copper-clad substrate including a base layer and a first copper foil layer and a second copper foil layer respectively formed on opposite two surfaces of the base layer;
[0007] Open at least one first blind hole and at least one second blind hole in the copper-clad substrate, each of the first blind holes and each of the second blind holes penetrating through the first copper foil layer and the base layer, and the bottom of each of the first blind holes and each of the second blind holes corresponding to the second copper foil layer;
[0008] Electroplate metal on the first copper foil layer and the second copper foil layer to respectively form a first copper plating layer and a second copper plating layer, and the metal also fills in the first blind hole and the second blind hole to form a first metal layer;
[0009] Etch the first copper plating layer and the first copper foil layer to form a first conductive circuit layer, and etch the second copper plating layer and the second copper foil layer to form a second conductive circuit layer, obtaining a first circuit substrate;
[0010] Open at least one through hole in the first circuit substrate to communicate the first blind hole and the second blind hole adjacent to the first blind hole;
[0011] Electroplate metal on the side wall of the through hole to form a second metal layer, and connect the second metal layer to the first metal layer to obtain a second circuit board; and
[0012] Cut the second circuit board along the aperture of the first blind hole, the aperture of the through hole, and the aperture of the second blind hole, so that the through hole forms a half hole after cutting, thereby obtaining the half hole board of the circuit board.
[0013] An embodiment of the present application further provides a half hole board of a circuit board, including:
[0014] A first conductive circuit layer;
[0015] A second conductive circuit layer; and
[0016] A base layer located between the first conductive circuit layer and the second conductive circuit layer;
[0017] Wherein, at least one first edge blind hole and at least one second edge blind hole are formed in the edge of the half hole board of the circuit board, each of the first edge blind holes and each of the second edge blind holes penetrate the base layer, and a first metal layer is provided in the first edge blind hole and the second edge blind hole;
[0018] Wherein, at least one half hole is further formed in the edge of the half hole board of the circuit board, the half hole communicates with the first edge blind hole and the second edge blind hole adjacent to the first edge blind hole, a second metal layer is provided on the side wall of the half hole, and the second metal layer is connected to the first metal layer.
[0019] In the present application, the first edge blind hole and the second edge blind hole are formed in the half hole board of the circuit board, and the first edge blind hole and the second edge blind hole are communicated with the through hole, which can improve the bonding force between the first metal layer and the second metal layer and the base layer, thereby reducing the copper wire burrs that are likely to appear during the process of cutting the metallized hole, and thus improving the yield of the half hole board of the circuit board. Description of the Drawings
[0020] Figure 1 is a cross-sectional view of a copper-clad substrate provided by an embodiment of the present application.
[0021] Figure 2A and Figure 2B are respectively a cross-sectional view and a top view after forming a first blind hole, a second blind hole, a seventh blind hole, and an eighth blind hole in the copper-clad substrate shown in Figure 1 The cross-sectional view and the top view after forming the first blind hole, the second blind hole, the seventh blind hole, and the eighth blind hole in the copper-clad substrate shown in
[0022] Figure 3A and Figure 3B are respectively in Figure 2A and Figure 2BCross-sectional view and top view after forming a first copper plating layer and a second copper plating layer on the shown first copper foil layer and second copper foil layer respectively.
[0023] Figure 4 It is a cross-sectional view after etching the first copper plating layer and the first copper foil layer shown in Figure 3, and etching the second copper plating layer and the second copper foil layer.
[0024] Figure 5 It is on Figure 4 Cross-sectional view after laminating a first adhesive layer and a third copper foil layer on the shown first conductive circuit layer, and laminating a second adhesive layer and a fourth copper foil layer on the second conductive circuit layer.
[0025] Figure 6 It is to Figure 5 Cross-sectional view after laminating the shown first adhesive layer and the third copper foil layer on the first conductive circuit layer, and laminating the second adhesive layer and the fourth copper foil layer on the second conductive circuit layer.
[0026] Figure 7A and Figure 7B They are respectively Figure 6 Cross-sectional view and top view after forming third blind holes, fourth blind holes, ninth blind holes, tenth blind holes, fifth blind holes, sixth blind holes, eleventh blind holes and twelfth blind holes in the shown first circuit board.
[0027] Figure 8A and Figure 8B They are respectively Figure 7A and Figure 7B Cross-sectional view and top view after forming vias in the shown first circuit board.
[0028] Figure 9A and Figure 9B They are respectively Figure 8A and Figure 8B Cross-sectional view and top view after forming a third copper plating layer and a fourth copper plating layer on the shown third copper foil layer and fourth copper foil layer respectively.
[0029] Figure 10A and Figure 10B They are respectively Figure 9A and Figure 9B Cross-sectional view and top view after etching the shown third copper plating layer and the third copper foil layer, and etching the fourth copper plating layer and the fourth copper foil layer.
[0030] Figure 11A and Figure 11B They are respectively Figure 10A and Figure 10B Cross-sectional view and top view after forming a first solder mask layer and a second solder mask layer on the shown third conductive circuit layer and fourth conductive circuit layer.
[0031] Figure 12A , Figure 12B and Figure 12C are respectively the sectional view, top view, and structural schematic diagram of the second circuit board shown in Figure 11A and Figure 11B after being cut.
[0032] Main component symbol description
[0033] Circuit board half-hole board 100
[0034] Copper-clad substrate 10
[0035] Base layer 101
[0036] First copper foil layer 102
[0037] Second copper foil layer 103
[0038] First blind via 11
[0039] Second blind via 12
[0040] Seventh blind via 13
[0041] Eighth blind via 14
[0042] First copper plating layer 20
[0043] Second copper plating layer 21
[0044] First metal layer 23
[0045] First conductive circuit layer 30
[0046] Second conductive circuit layer 31
[0047] First adhesive layer 40
[0048] Second adhesive layer 41
[0049] Third copper foil layer 50
[0050] Fourth copper foil layer 51
[0051] First circuit board 60
[0052] Third blind via 61
[0053] Fourth blind via 62
[0054] Ninth blind via 63
[0055] Tenth blind via 64
[0056] Fifth blind via 65
[0057] Sixth blind via 66
[0058] Through-hole 67
[0059] Third copper plating layer 70
[0060] Fourth copper plating layer 71
[0061] Third metal layer 72
[0062] Second metal layer 73
[0063] Fourth metal layer 74
[0064] Third conductive circuit layer 80
[0065] Fourth conductive circuit layer 81
[0066] First solder mask layer 90
[0067] Second solder mask layer 91
[0068] Second circuit board 92
[0069] Half hole 93
[0070] First edge blind hole 94
[0071] Second edge blind hole 95
[0072] Third edge blind hole 96
[0073] Fourth edge blind hole 97
[0074] Fifth edge blind hole 98
[0075] Sixth edge blind hole 99
[0076] The following specific embodiments will further illustrate the present application in conjunction with the above-mentioned drawings. Specific embodiments
[0077] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.
[0078] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0079] In order to further illustrate the technical means and effects adopted by the present application to achieve the predetermined purpose, the following detailed description of the present application is made in conjunction with the accompanying drawings and preferred embodiments.
[0080] An embodiment of the present application provides a method for manufacturing a half-hole circuit board, including the following steps:
[0081] Step S11, refer to Figure 1 , and provide a copper-clad substrate 10.
[0082] In this embodiment, the copper-clad substrate 10 includes a base layer 101, a first copper foil layer 102, and a second copper foil layer 103 formed on opposite surfaces of the base layer 101, respectively.
[0083] The material of the base layer 101 can be selected from one of resins such as epoxy resin, polypropylene (PP), BT resin, polyphenylene oxide (PPO), polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). In this embodiment, the material of the base layer 101 is polyimide. Among them, the thickness of the base layer 101 can be 75 - 200 μm.
[0084] Step S12, refer to Figure 2A and Figure 2B , and form at least one first blind hole 11, at least one second blind hole 12, at least one seventh blind hole 13, and at least one eighth blind hole 14 in the copper-clad substrate 10.
[0085] Among them, each of the first blind hole 11, the second blind hole 12, the seventh blind hole 13, and the eighth blind hole 14 penetrates through the first copper foil layer 102 and the base layer 101, and the bottom of each of the first blind hole 11, the second blind hole 12, the seventh blind hole 13, and the eighth blind hole 14 corresponds to the second copper foil layer 103. Among them, the first blind hole 11, the seventh blind hole 13, the second blind hole 12, and the eighth blind hole 14 are annularly distributed.
[0086] In one embodiment, along the direction from the first copper foil layer 102 to the second copper foil layer 103, the inner diameters of the first blind hole 11, the second blind hole 12, the seventh blind hole 13, and the eighth blind hole 14 all decrease. That is, along the direction from the first copper foil layer 102 to the second copper foil layer 103, the cross-sectional views of the first blind hole 11, the second blind hole 12, the seventh blind hole 13, and the eighth blind hole 14 are all approximately trapezoidal in reverse.
[0087] In one embodiment, the first blind hole 11, the second blind hole 12, the seventh blind hole 13, and the eighth blind hole 14 can all be formed by laser drilling.
[0088] Step S13, please refer to Figure 3A and Figure 3B , electroplate metal on the first copper foil layer 102 and the second copper foil layer 103 to form a first copper plating layer 20 and a second copper plating layer 21 respectively.
[0089] Wherein, the process of electroplating the metal also fills the metal in the first blind hole 11, the second blind hole 12, the seventh blind hole 13, and the eighth blind hole 14 to form a first metal layer 23.
[0090] Step S14, please refer to Figure 4 , etch the first copper plating layer 20 and the first copper foil layer 102 to form a first conductive circuit layer 30, and etch the second copper plating layer 21 and the second copper foil layer 103 to form a second conductive circuit layer 31.
[0091] Step S15, please refer to Figure 5 and Figure 6 , sequentially form a first adhesive layer 40 and a third copper foil layer 50 on the first conductive circuit layer 30, and sequentially form a second adhesive layer 41 and a fourth copper foil layer 51 on the second conductive circuit layer 31 to obtain a first circuit substrate 60.
[0092] Specifically, the first circuit substrate 60 can be formed by lamination. More specifically, the first adhesive layer 40 and the third copper foil layer 50 are sequentially laminated on the first conductive circuit layer 30, and the second adhesive layer 41 and the fourth copper foil layer 51 are sequentially laminated on the second conductive circuit layer 31, and then laminated to obtain the first circuit substrate 60.
[0093] Step S16, please refer to Figure 7A and Figure 7B , form at least one third blind hole 61, at least one fourth blind hole 62, at least one ninth blind hole 63, and at least one tenth blind hole 64 in the first circuit substrate 60.
[0094] Among them, each of the third blind holes 61, each of the fourth blind holes 62, each of the ninth blind holes 63, and each of the tenth blind holes 64 penetrate through the third copper foil layer 50 and the first adhesive layer 40, and the bottoms of each of the third blind holes 61, each of the fourth blind holes 62, each of the ninth blind holes 63, and each of the tenth blind holes 64 correspond to the first conductive circuit layer 30. Among them, the third blind hole 61 corresponds to the first blind hole 11, the fourth blind hole 62 corresponds to the second blind hole 12, the ninth blind hole 63 corresponds to the seventh blind hole 13, and the tenth blind hole 64 corresponds to the eighth blind hole 14.
[0095] In one embodiment, the third blind hole 61, the fourth blind hole 62, the ninth blind hole 63, and the tenth blind hole 64 can all be formed by laser drilling.
[0096] In one embodiment, along the direction from the third copper foil layer 50 to the first conductive circuit layer 30, the inner diameters of the third blind hole 61, the fourth blind hole 62, the ninth blind hole 63, and the tenth blind hole 64 all decrease. That is, along the direction from the third copper foil layer 50 to the first conductive circuit layer 30, the cross-sectional views of the third blind hole 61, the fourth blind hole 62, the ninth blind hole 63, and the tenth blind hole 64 are all approximately trapezoidal in reverse.
[0097] Step S17, at least one fifth blind hole 65, at least one sixth blind hole 66, at least one eleventh blind hole (not shown in the figure), and at least one twelfth blind hole (not shown in the figure) are formed in the first circuit board 60.
[0098] Among them, each of the fifth blind holes 65, each of the sixth blind holes 66, each of the eleventh blind holes, and each of the twelfth blind holes penetrate through the fourth copper foil layer 51 and the second adhesive layer 41, and the bottoms of each of the fifth blind holes 65, each of the sixth blind holes 66, each of the eleventh blind holes, and each of the twelfth blind holes correspond to the second conductive circuit layer 31. Among them, the fifth blind hole 65 corresponds to the first blind hole 11, the sixth blind hole 66 corresponds to the second blind hole 12, the eleventh blind hole corresponds to the seventh blind hole 13, and the twelfth blind hole corresponds to the eighth blind hole 14.
[0099] In one embodiment, the fifth blind hole 65, the sixth blind hole 66, the eleventh blind hole, and the twelfth blind hole can all be formed by laser drilling.
[0100] In one embodiment, along the direction from the fourth copper foil layer 51 to the second conductive circuit layer 31, the inner diameters of the fifth blind hole 65, the sixth blind hole 66, the eleventh blind hole, and the twelfth blind hole are all reduced. That is, along the direction from the fourth copper foil layer 51 to the second conductive circuit layer 31, the cross-sectional views of the fifth blind hole 65, the sixth blind hole 66, the eleventh blind hole, and the twelfth blind hole are all approximately trapezoidal.
[0101] Step S18, please refer to Figure 8A and Figure 8B , and at least one through hole 67 is formed in the first circuit board 60.
[0102] Wherein, the through hole 67 sequentially penetrates through the third copper foil layer 50, the first adhesive layer 40, the first conductive circuit layer 30, the base layer 101, the second conductive circuit layer 31, the second adhesive layer 41, and the fourth copper foil layer 51. Wherein, the through hole 67 communicates with the first blind hole 11, the second blind hole 12, the seventh blind hole 13, the eighth blind hole 14, the third blind hole 61, the fourth blind hole 62, the ninth blind hole 63, the tenth blind hole 64, the fifth blind hole 65, the sixth blind hole 66, the eleventh blind hole, and the twelfth blind hole.
[0103] In one embodiment, the through hole 67 can be formed by drilling.
[0104] Step S19, please refer to Figure 9A and Figure 9B , and metal is electroplated on the third copper foil layer 50 and the fourth copper foil layer 51 to form a third copper plating layer 70 and a fourth copper plating layer 71 respectively.
[0105] Wherein, during the electroplating of the metal, the metal is also filled in the third blind hole 61, the fourth blind hole 62, the ninth blind hole 63, and the tenth blind hole 64 to form a third metal layer 72, and filled on the side wall of the through hole 67 to form a second metal layer 73, and filled in the fifth blind hole 65, the sixth blind hole 66, the eleventh blind hole, and the twelfth blind hole to form a fourth metal layer 74.
[0106] Step S20, please refer to Figure 10A and Figure 10B , and the third copper plating layer 70 and the third copper foil layer 50 are etched to form a third conductive circuit layer 80, and the fourth copper plating layer 71 and the fourth copper foil layer 51 are etched to form a fourth conductive circuit layer 81.
[0107] Step S21, please refer to Figure 11A and Figure 11B, a first solder mask layer 90 and a second solder mask layer 91 are formed on the third conductive line layer 80 and the fourth conductive line layer 81 to obtain a second circuit board 92.
[0108] Among them, the materials of the first solder mask layer 90 and the second solder mask layer 91 can both be solder mask ink, such as green oil. The first solder mask layer 90 is used to protect the third conductive line layer 80, and the second solder mask layer 91 is used to protect the fourth conductive line layer 81.
[0109] Step S22, please refer to Figure 12A , Figure 12B and Figure 12C , the second circuit board 92 is cut along the aperture of the first blind hole 11, the aperture of the through hole 67 and the aperture of the second blind hole 12, so that the through hole 67 forms a half hole 93 after cutting, thereby obtaining the circuit board half hole board 100.
[0110] Among them, the second metal layer 73 is connected to the first metal layer 23, the third metal layer 72 and the fourth metal layer 74. That is, the first metal layer 23, the second metal layer 73, the third metal layer 72 and the fourth metal layer 74 jointly form the metal layer on the inner wall of the half hole 93.
[0111] Please refer to Figure 12A , Figure 12B and Figure 12C , an embodiment of the present application further provides a circuit board half hole board 100, which includes a base layer 101, a first conductive line layer 30, a second conductive line layer 31, a third conductive line layer 80, a first adhesive layer 40, a fourth conductive line layer 81, a second adhesive layer 41, a first solder mask layer 90 and a second solder mask layer 91.
[0112] The material of the base layer 101 can be selected from one of resins such as epoxy resin, polypropylene (PP), BT resin, polyphenylene oxide (PPO), polyimide (PI), polyethylene terephthalate (PET) and polyethylene naphthalate (PEN). In this embodiment, the material of the base layer 101 is polyimide. Among them, the thickness of the base layer 101 can be 75-200 μm.
[0113] The first conductive line layer 30 and the second conductive line layer 31 are respectively formed on opposite two surfaces of the base layer 101.
[0114] At least one first edge blind hole 94, at least one second edge blind hole 95, at least one seventh blind hole 13 and at least one eighth blind hole 14 are formed in the circuit board half-hole board 100.
[0115] Wherein, each of the first edge blind holes 94, each of the second edge blind holes 95, each of the seventh blind holes 13 and each of the eighth blind holes 14 penetrate through the base layer 101. Among them, the first edge blind holes 94, the seventh blind holes 13, the second edge blind holes 95 and the eighth blind holes 14 are annularly distributed.
[0116] In one embodiment, along the direction from the first conductive circuit layer 30 to the second conductive circuit layer 31, the inner diameters of the first edge blind holes 94, the second edge blind holes 95, the seventh blind holes 13 and the eighth blind holes 14 are all reduced. That is, along the direction from the first conductive circuit layer 30 to the second conductive circuit layer 31, the cross-sectional views of the first edge blind holes 94, the second edge blind holes 95, the seventh blind holes 13 and the eighth blind holes 14 are all approximately trapezoidal in reverse.
[0117] Among them, a first metal layer 23 is provided in the first edge blind holes 94, the second edge blind holes 95, the seventh blind holes 13 and the eighth blind holes 14.
[0118] The third conductive circuit layer 80 is disposed on the first conductive circuit layer 30 through the first adhesive layer 40.
[0119] At least one third edge blind hole 96, at least one fourth edge blind hole 97, at least one ninth blind hole 63 and at least one tenth blind hole 64 are further formed in the circuit board half-hole board 100.
[0120] Wherein, each of the third edge blind holes 96, each of the fourth edge blind holes 97, each of the ninth blind holes 63 and each of the tenth blind holes 64 penetrate through the first adhesive layer 40, and the bottoms of each of the third edge blind holes 96, each of the fourth edge blind holes 97, each of the ninth blind holes 63 and each of the tenth blind holes 64 correspond to the first conductive circuit layer 30. Among them, the third edge blind hole 96 corresponds to the first edge blind hole 94, the fourth edge blind hole 97 corresponds to the second edge blind hole 95, the ninth blind hole 63 corresponds to the seventh blind hole 13, and the tenth blind hole 64 corresponds to the eighth blind hole 14.
[0121] In one embodiment, along the direction from the third conductive line layer 80 to the first conductive line layer 30, the inner diameters of the third edge blind hole 96, the fourth edge blind hole 97, the ninth blind hole 63, and the tenth blind hole 64 are all reduced. That is, along the direction from the third conductive line layer 80 to the first conductive line layer 30, the cross-sectional views of the third edge blind hole 96, the fourth edge blind hole 97, the ninth blind hole 63, and the tenth blind hole 64 are all approximately inverted trapezoids.
[0122] Among them, a third metal layer 72 is provided in the third edge blind hole 96, the fourth edge blind hole 97, the ninth blind hole 63, and the tenth blind hole 64.
[0123] The fourth conductive line layer 81 is disposed on the second conductive line layer 31 through the second adhesive layer 41.
[0124] At least one fifth edge blind hole 98, at least one sixth edge blind hole 99, at least one eleventh blind hole (not shown in the figure), and at least one twelfth blind hole (not shown in the figure) are further formed in the circuit board half hole plate 100.
[0125] Among them, each of the fifth edge blind hole 98, each of the sixth edge blind hole 99, each of the eleventh blind hole, and each of the twelfth blind hole penetrates through the second adhesive layer 41, and the bottom of each of the fifth edge blind hole 98, each of the sixth edge blind hole 99, each of the eleventh blind hole, and each of the twelfth blind hole corresponds to the second conductive line layer 31. Among them, the fifth edge blind hole 98 corresponds to the first edge blind hole 94, the sixth edge blind hole 99 corresponds to the second edge blind hole 95, the eleventh blind hole corresponds to the seventh blind hole 13, and the twelfth blind hole corresponds to the eighth blind hole 14.
[0126] In one embodiment, along the direction from the fourth conductive line layer 81 to the second conductive line layer 31, the inner diameters of the fifth edge blind hole 98, the sixth edge blind hole 99, the eleventh blind hole, and the twelfth blind hole are all reduced. That is, along the direction from the fourth conductive line layer 81 to the second conductive line layer 31, the cross-sectional views of the fifth edge blind hole 98, the sixth edge blind hole 99, the eleventh blind hole, and the twelfth blind hole are all approximately trapezoids.
[0127] Among them, a fourth metal layer 74 is provided in the fifth edge blind hole 98, the sixth edge blind hole 99, the eleventh blind hole, and the twelfth blind hole.
[0128] At least one half-hole 93 is also provided at the edge of the circuit board half-hole board 100. Among them, the half-hole 93 sequentially penetrates through the third conductive circuit layer 80, the first adhesive layer 40, the first conductive circuit layer 30, the base layer 101, the second conductive circuit layer 31, the second adhesive layer 41, and the fourth conductive circuit layer 81. Among them, the half-hole 93 communicates with the first edge blind hole 94, the second edge blind hole 95, the seventh blind hole 13, the eighth blind hole 14, the third edge blind hole 96, the fourth edge blind hole 97, the ninth blind hole 63, the tenth blind hole 64, the fifth edge blind hole 98, the sixth edge blind hole 99, the eleventh blind hole, and the twelfth blind hole.
[0129] Among them, a second metal layer 73 is provided on the side wall of the half-hole 93. The second metal layer 73 is connected to the first metal layer 23, the third metal layer 72, and the fourth metal layer 74. That is, the first metal layer 23, the second metal layer 73, the third metal layer 72, and the fourth metal layer 74 jointly form the metal layer on the inner wall of the half-hole 93.
[0130] The first solder mask layer 90 and the second solder mask layer 91 are respectively located on the third conductive circuit layer 80 and the fourth conductive circuit layer 81.
[0131] Among them, the materials of the first solder mask layer 90 and the second solder mask layer 91 can both be solder mask inks, such as green oil. The first solder mask layer 90 is used to protect the third conductive circuit layer 80, and the second solder mask layer 91 is used to protect the fourth conductive circuit layer 81.
[0132] In this application, the first edge blind hole 94 and the second edge blind hole 95 are provided in the circuit board half-hole board 100, and the first edge blind hole 94 and the second edge blind hole 95 are communicated with the through hole 67, which can improve the bonding force between the first metal layer 23 and the second metal layer 73 and the base layer 101, thereby reducing the copper wire burrs that are likely to appear during the process of cutting the metallized hole, thereby improving the yield of the circuit board half-hole board 100. In addition, the production cycle of the circuit board half-hole board 100 in this application is short, thereby reducing the production cost.
[0133] The above description is only a specific implementation manner of an optimization of this application, but in the actual application process, it cannot be limited to this implementation manner only. For those of ordinary skill in the art, other deformations and changes made according to the technical concept of this application should all fall within the protection scope of this application.
Claims
1. A manufacturing method of a half-hole circuit board, characterized in that, Including the following steps: Providing a copper-clad substrate, the copper-clad substrate including a base layer and a first copper foil layer and a second copper foil layer respectively formed on opposite two surfaces of the base layer; Forming at least one first blind hole and at least one second blind hole in the copper-clad substrate, each of the first blind holes and each of the second blind holes penetrating through the first copper foil layer and the base layer, and the bottom of each of the first blind holes and each of the second blind holes corresponding to the second copper foil layer; Electroplating a metal on the first copper foil layer and the second copper foil layer to respectively form a first copper plating layer and a second copper plating layer, and the metal also filling in the first blind hole and the second blind hole to form a first metal layer; Etching the first copper plating layer and the first copper foil layer to form a first conductive circuit layer, and etching the second copper plating layer and the second copper foil layer to form a second conductive circuit layer, obtaining a first circuit substrate; Forming at least one through hole in the first circuit substrate to communicate the through hole with the first blind hole and a second blind hole adjacent to the first blind hole; Electroplating a metal on the side wall of the through hole to form a second metal layer, and the second metal layer being connected to the first metal layer, obtaining a second circuit substrate; And Cutting the second circuit substrate along the aperture of the first blind hole, the aperture of the through hole, and the aperture of the second blind hole, so that the through hole forms a half hole after cutting, thereby obtaining the circuit board half hole board.
2. The manufacturing method of the half-hole circuit board according to claim 1, characterized in that After forming the first conductive circuit layer, the manufacturing method further includes: Sequentially forming a first adhesive layer and a third copper foil layer on the first conductive circuit layer to obtain the first circuit substrate; Forming at least one third blind hole and at least one fourth blind hole in the first circuit substrate, each of the third blind holes and each of the fourth blind holes penetrating through the third copper foil layer and the first adhesive layer, and the bottom of each of the third blind holes and each of the fourth blind holes corresponding to the first conductive circuit layer, the third blind hole corresponding to the first blind hole, and the fourth blind hole corresponding to the second blind hole; Wherein, the through hole also communicates with the third blind hole and a fourth blind hole adjacent to the third blind hole; Electroplating a metal on the third copper foil to form a third copper plating layer, the metal also filling in the third blind hole and the fourth blind hole to form a third metal layer, and the third metal layer being connected to the second metal layer; Etching the third copper plating layer and the third copper foil layer to form a third conductive circuit layer, thereby obtaining the second circuit substrate.
3. The manufacturing method of the half-hole circuit board according to claim 2, characterized in that, After forming the second conductive circuit layer, the manufacturing method further includes: Sequentially forming a second adhesive layer and a fourth copper foil layer on the second conductive circuit layer to obtain the first circuit substrate; Forming at least one fifth blind hole and at least one sixth blind hole in the first circuit substrate, each of the fifth blind holes and each of the sixth blind holes penetrating through the fourth copper foil layer and the second adhesive layer, and the bottom of each of the fifth blind holes and each of the sixth blind holes corresponding to the second conductive circuit layer, the fifth blind hole corresponding to the first blind hole, and the sixth blind hole corresponding to the second blind hole; Wherein, the through hole also communicates with the fifth blind hole and the sixth blind hole adjacent to the fifth blind hole; Electroplate a metal on the fourth copper foil to form a fourth copper plating layer, and the metal also fills in the fifth blind hole and the sixth blind hole to form a fourth metal layer, and the fourth metal layer is connected to the second metal layer; Etch the fourth copper plating layer and the fourth copper foil layer to form a fourth conductive circuit layer, thereby obtaining the second circuit board.
4. The manufacturing method of the half-hole circuit board according to claim 3, characterized in that, It further includes: Form a first solder mask layer on the third conductive circuit layer; And Form a second solder mask layer on the fourth conductive circuit layer.
5. The manufacturing method of the half-hole circuit board according to claim 1, characterized in that, It further includes: At least one seventh blind hole and at least one eighth blind hole are further formed in the copper-clad substrate, each of the seventh blind holes and each of the eighth blind holes penetrate through the first copper foil layer and the base layer, and the bottom of each of the seventh blind holes and each of the eighth blind holes corresponds to the second copper foil layer, and the first blind hole, the seventh blind hole, the second blind hole and the eighth blind hole are annularly distributed; Wherein, in the process of electroplating the metal to form the first copper plating layer, the metal also fills in the seventh blind hole and the eighth blind hole to form the first metal layer; Wherein, the through hole also communicates with the seventh blind hole and the eighth blind hole adjacent to the seventh blind hole.
6. A half-hole circuit board, characterized in that, It includes: A first conductive circuit layer; A second conductive circuit layer; And A base layer, located between the first conductive circuit layer and the second conductive circuit layer; Wherein, at least one first edge blind hole and at least one second edge blind hole are formed in the edge of the half-hole board of the circuit board, each of the first edge blind holes and each of the second edge blind holes penetrate through the base layer, and a first metal layer is provided in the first edge blind hole and the second edge blind hole; the bottoms of the first edge blind hole and the second edge blind hole correspond to the second conductive circuit layer; Wherein, at least one half-hole is further formed in the edge of the half-hole board of the circuit board, the half-hole communicates with the first edge blind hole and the second edge blind hole adjacent to the first edge blind hole, a second metal layer is provided on the side wall of the half-hole, and the second metal layer is connected to the first metal layer.
7. The half-hole circuit board according to claim 6, wherein It further includes: A first adhesive layer, located on the first conductive circuit layer; And A third conductive circuit layer, located on the first adhesive layer; Wherein, at least one third edge blind hole and at least one fourth edge blind hole are formed in the edge of the half-hole board of the circuit board, each of the third edge blind holes and each of the fourth edge blind holes penetrate through the first adhesive layer, and the bottom of each of the third edge blind holes and each of the fourth edge blind holes corresponds to the first conductive circuit layer, the third edge blind hole corresponds to the first edge blind hole, the fourth edge blind hole corresponds to the second edge blind hole, the half-hole also communicates with the third edge blind hole and the fourth edge blind hole adjacent to the third edge blind hole, and a third metal layer is provided in the third edge blind hole and the fourth edge blind hole, and the third metal layer is connected to the second metal layer.
8. The half-hole circuit board according to claim 7, wherein, It further includes: A second adhesive layer, located on the second conductive circuit layer; And A fourth conductive circuit layer, located on the second adhesive layer; Among them, at least one fifth edge blind hole and at least one sixth edge blind hole are formed in the edge of the circuit board half-hole board. Each of the fifth edge blind holes and each of the sixth edge blind holes penetrate through the second adhesive layer, and the bottom of each of the fifth edge blind holes and each of the sixth edge blind holes corresponds to the second conductive circuit layer. The fifth edge blind hole corresponds to the first edge blind hole, and the sixth edge blind hole corresponds to the second edge blind hole. The half-hole also communicates with the fifth edge blind hole and the sixth edge blind hole adjacent to the fifth edge blind hole. A fourth metal layer is provided in the fifth edge blind hole and the sixth edge blind hole, and the fourth metal layer is connected to the second metal layer.
9. The half-hole circuit board according to claim 8, wherein It further includes: A first solder mask layer, located on the third conductive circuit layer; And A second solder mask layer, located on the fourth conductive circuit layer.
10. The half-hole circuit board according to claim 6, characterized in that, At least one seventh blind hole and at least one eighth blind hole are formed in the circuit board half-hole board. Each of the seventh blind holes and each of the eighth blind holes penetrate through the base layer, and the bottom of each of the seventh blind holes and each of the eighth blind holes corresponds to the first conductive circuit layer. The half-hole also communicates with the seventh blind hole and the eighth blind hole adjacent to the seventh blind hole. The first edge blind hole, the seventh blind hole, the second edge blind hole, and the eighth blind hole are annularly distributed, and a first metal layer is provided in the seventh blind hole and the eighth blind hole.
Citation Information
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