Controllers with FPGA chips and their operation methods, rail transit equipment

Abstract

This invention discloses a controller with an FPGA chip and its operating method, as well as rail transit equipment. It relates to the field of rail transit on-board equipment technology. The controller with an FPGA chip includes: a DSP chip, an FPGA chip, a solid-state memory (SSD), and a dynamic memory (DRAM). The DSP chip and DRAM are communicatively connected, and the I / O pins of the DSP chip are electrically connected to the PROB pin of the FPGA chip. The SSD includes FLASH memory. The DSP chip and FPGA chip are electrically connected to the SSD via SPI or QSPI interfaces, respectively. The DSP chip also has a data input interface. The DSP chip receives programs through the data input interface and stores the programs in the DRAM, and also controls the potential of the PROB pin of the FPGA chip. The DSP chip writes the program from the DRAM into the SSD when the PROB pin of the FPGA chip is at a low potential; etc. This application enables remote updating of the FPGA program and decoupled startup of the FPGA and DSP.

Description

Technical Field

[0001] This invention relates to the field of rail transit vehicle-mounted equipment technology, and in particular to a controller with an FPGA chip, its operating method, and rail transit equipment. Background Technology

[0002] Currently, the configuration methods for controllers with FPGAs are generally divided into master mode and slave mode. In master mode, the FPGA acts as the master, with an external PROM or FLASH memory chip. Upon power-up, the FPGA actively reads the program from the PROM or FLASH and then performs automatic configuration. Programming and upgrading the FPGA requires a dedicated emulator via a JTAG interface, and a power-on reboot is necessary after configuration. The disadvantages of this master mode are: 1. It requires a dedicated emulator, which on-site after-sales personnel often lack; 2. Because the traction converter controller is installed under the vehicle body in a closed enclosure, upgrading the FPGA program is very inconvenient, or due to structural and space limitations, on-site upgrades are impossible, requiring the controller to be removed and upgraded in a specific environment, which is very cumbersome; 3. A power-on reboot is required after programming for the new program to load and run. In slave mode, the FPGA acts as the slave, eliminating the need for a JTAG emulator as in master mode, and allowing remote programming, avoiding the cumbersome steps of disassembling and upgrading the controller. In this mode, the DSP on the board is the primary processor. The FPGA program is transmitted to the DSP via the host computer. After receiving the program, the DSP first caches it in RAM, then adds verification information and stores it in external FLASH. Each time it powers on, the DSP reads the FPGA program from NAND FLASH and verifies it. If the verification is successful, the FPGA program is used to configure the FPGA. In this mode, the DSP is the core of the entire system, and the FPGA's program configuration timing and program upgrade logic are all implemented by the DSP's application program. The disadvantages of this mode are: 1. Over-reliance on the DSP; the FPGA can only start after the DSP has started normally; 2. FPGA data is stored in DSP-controlled FLASH. Each time the system starts, the DSP needs to move the data to memory and then convert the data into the appropriate format before writing it into the FPGA, resulting in many and cumbersome data transfer steps; 3. The entire system has a long startup time, and some peripheral circuits connected to the FPGA are in an abnormal operating state after power-on. Summary of the Invention

[0003] To overcome the above-mentioned defects of the prior art, this invention provides a controller with an FPGA chip and its operation method, as well as rail transit equipment. It solves the problems of needing specific equipment in master mode and being highly dependent on other control chips (DSP) in slave mode. It can realize remote FPGA program updates and decouple the FPGA and DSP startup.

[0004] The specific technical solution of this invention is as follows:

[0005] A controller with an FPGA chip, comprising:

[0006] The system includes a DSP chip, an FPGA chip, a solid-state memory (SSD), and a dynamic memory (DRAM). The DSP chip is communicatively connected to the DRAM, and the I / O pins of the DSP chip are electrically connected to the PROB pins of the FPGA chip. The SSD includes a FLASH memory. The DSP chip and the FPGA chip are electrically connected to the SSD via an SPI interface or a QSPI interface, respectively. The DSP chip also has a data input interface.

[0007] The DSP chip is used to receive a program through the data input interface and store the program in the dynamic memory, and is used to control the potential of the PROB pin of the FPGA chip; the DSP chip is used to write the program in the dynamic memory into the solid-state memory when the PROB pin of the FPGA chip is at a low potential; the FPGA chip is used to load the program from the solid-state memory and start it when the PROB pin of the FPGA chip is at a high potential.

[0008] Preferably, the I / O pins of the DSP chip are also electrically connected to the INIT_B pin and DONE pin of the FPGA chip;

[0009] The DSP chip is connected to the SPI bus of the solid-state memory via the SPI bus; the DSP chip, the FPGA chip, and the solid-state memory are connected in a daisy chain.

[0010] Preferably, the DSP chip is used to set the potential of the PROB pin of the FPGA chip to a high potential after the program in the dynamic memory is written into the solid-state memory.

[0011] Preferably, the FPGA chip sets the DONE pin to a high potential after loading the program from the solid-state memory and starting it.

[0012] A rail transit device, the rail transit device comprising: a rail transit traction converter, which includes a controller with an FPGA chip as described in any of the above.

[0013] A method for operating a controller with an FPGA chip, employing any of the controllers described above, the method comprising the following steps:

[0014] The DSP chip receives the program and stores the program in the dynamic memory;

[0015] After the program is stored in the dynamic memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to a low potential;

[0016] When the PROB pin of the FPGA chip is at a low potential, the DSP chip writes the program in the dynamic memory into the solid-state memory;

[0017] After the program is written to the solid-state memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to a high potential;

[0018] When the PROB pin of the FPGA chip is at a high potential, the FPGA chip loads the program from the solid-state memory and starts.

[0019] Preferably, when the potential of the PROB pin of the FPGA chip is low, the FPGA chip is in a reset state; when the potential of the PROB pin of the FPGA chip is high, the FPGA chip can be started.

[0020] Preferably, the method of operating the controller with the FPGA chip further includes the following steps:

[0021] Before the DSP chip receives the program, the DSP chip receives the update instruction from the host computer, feeds back the status to the host computer, and changes the update program flag bit to 1;

[0022] After the FPGA chip loads the program from the solid-state memory and starts up successfully, the FPGA chip changes the potential of the DONE pin to a high potential.

[0023] After the FPGA chip loads the program from the solid-state memory and starts up successfully, the DSP chip detects the potential of the DONE pin of the FPGA chip. If the potential of the DONE pin of the FPGA chip is high and the flag bit of the update program is 1, the DSP chip reads the version number of the program in the FPGA chip and outputs the version number.

[0024] Preferably, if the PROB pin of the FPGA chip is at a low potential and the flag bit of the update program is 1, then the DSP chip rewrites the program in the dynamic memory into the solid-state memory.

[0025] After the program is rewritten to the solid-state memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to a high potential. When the PROB pin of the FPGA chip is at a high potential, the FPGA chip loads the program from the solid-state memory and starts.

[0026] Preferably, when the DSP chip rewrites the program from the dynamic memory to the solid-state memory a preset number of times, the DSP chip outputs an error message.

[0027] Preferably, the method of operating the controller with the FPGA chip further includes the following steps:

[0028] When the DSP chip does not receive an update instruction from the host computer, the DSP chip detects the state of the DONE pin of the FPGA chip. If the state of the DONE pin is low, the DSP chip outputs information that the program is not stored in the solid-state memory.

[0029] If the DONE pin is at a high level, the DSP chip reads the version number of the program in the FPGA chip and outputs the version number information and / or a successful startup message.

[0030] The beneficial effects of this application are as follows:

[0031] Existing FPGA chips, operating in master mode, can only be upgraded via an emulator, not remotely. Remote upgrades require configuring the FPGA as a slave, necessitating an external DSP or MCU chip highly coupled to its startup. Each power-on cycle involves reading the program from FLASH, transferring it to RAM, and then programming it into the FPGA. This process increases data transmission risks, lengthens system startup time, and raises instability. This application combines these two approaches, leveraging the unique characteristics of both DSP and FPGA chips to decouple them, effectively mitigating the shortcomings of existing technologies. In other words, the DSP chip directly receives the program required for remote FPGA chip upgrades via its data input interface and stores it in dynamic memory. When the PROB pin of the FPGA chip is at a low potential, the DSP chip writes the program from the dynamic memory to solid-state memory. When the PROB pin of the FPGA chip is at a high potential, the FPGA chip can directly load the program from the external solid-state memory and start. Simultaneously, the DSP can also start its own application program. This eliminates the need for a dedicated emulator, significantly improving program upgrade efficiency, reducing upgrade costs, and shortening upgrade time. Secondly, the controller with the FPGA chip decouples the FPGA chip and DSP chip during startup, preventing startup timing from affecting the initial state of the system. Finally, this application can shorten the startup time of the controller with the FPGA chip and enhance system stability. In the prior art, when the FPGA chip adopts slave mode, the startup time is the sum of the DSP chip's boot startup, the DSP chip guiding the FPGA chip to start (including the DSP chip reading the program from flash to RAM, verification, and then writing the data in RAM to the FPGA chip), and the DSP chip's application startup. With the solution of this application, without updating the FPGA chip program, after the DSP chip's boot startup, the FPGA chip and the DSP chip's application startup can start simultaneously, thereby shortening the overall system startup time. Attached Figure Description

[0032] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of the invention in any way. Furthermore, the shapes and proportions of the components in the drawings are merely illustrative to aid in understanding the invention and do not specifically limit the shapes and proportions of the components. Those skilled in the art, guided by the teachings of this invention, can select various possible shapes and proportions to implement the invention according to specific circumstances.

[0033] Figure 1 This is a schematic diagram of the controller with an FPGA chip in an embodiment of the present invention.

[0034] Figure 2 This is a flowchart illustrating the steps of the operation method of the controller with an FPGA chip in an embodiment of the present invention.

[0035] Figure 3 This is a flowchart illustrating the operating principle of the DSP chip in this embodiment of the invention. Detailed Implementation

[0036] The details of the present invention can be more clearly understood by referring to the accompanying drawings and the description of specific embodiments. However, the specific embodiments of the present invention described herein are for illustrative purposes only and should not be construed as limiting the invention in any way. Under the teachings of this invention, those skilled in the art can conceive of any possible modifications based on the invention, and these should all be considered to fall within the scope of the invention.

[0037] To address the issues of requiring specific devices in master mode and being highly dependent on other control chips (DSPs) in slave mode, and to enable remote updates of the FPGA program while achieving decoupled startup of the FPGA and DSP, this application proposes a controller with an FPGA chip. Figure 1 This is a schematic diagram of the controller with an FPGA chip in an embodiment of the present invention, as shown below. Figure 1 As shown, a controller with an FPGA chip may include: a DSP chip, an FPGA chip, a solid-state memory, and a dynamic memory.

[0038] In this controller with an FPGA chip, the FPGA chip is configured in master mode. The DSP chip communicates with the dynamic memory (DRAM), for example, through a data bus and an address bus to achieve data transmission. The DRAM can be an SDRAM.

[0039] The solid-state memory is a FLASH memory. The DSP chip and FPGA chip are electrically connected to the solid-state memory via SPI or QSPI interfaces, respectively. The I / O pins of the DSP chip are electrically connected to the PROB pins of the FPGA chip.

[0040] The DSP chip also features a data input interface, allowing it to connect to a host computer via an RS232 serial bus. For example, the host computer can send the FPGA's required program to the DSP through the RS232 serial bus. The DSP chip receives the program, i.e., the program sent by the host computer to the FPGA, and stores it in dynamic memory. Simultaneously, the DSP chip can control the potential of the FPGA chip's PROB pin. The PROB pin of the FPGA chip can have a high potential (1) and a low potential (0).

[0041] In this application, the host computer can be the CPU of the control system or a system-level controller. Alternatively, the interface between the host computer and the DSP chip can also be a CAN bus or an Ethernet bus.

[0042] It should be noted that when the PROB pin of the FPGA chip is at a low level, the FPGA chip is in a reset state, and in this state, the FPGA chip cannot load programs from solid-state memory. When the PROB pin of the FPGA chip is at a high level, the FPGA chip initiates the loading of programs from external memory.

[0043] The DSP chip is used to write the program from the dynamic memory to the solid-state memory when the PROB pin of the FPGA chip is at a low level. After the program is written to the solid-state memory, the DSP chip controls the PROB pin of the FPGA chip to go high. The FPGA chip then loads the program from the solid-state memory and starts the program when the PROB pin of the FPGA chip is high.

[0044] In addition, the I / O pins of the DSP chip can also be electrically connected to the INIT_B and DONE pins of the FPGA chip. After the FPGA chip loads the program from the solid-state memory and starts up successfully, it changes the potential of the DONE pin to a high level. Status interaction between the DSP chip and the FPGA chip can be achieved through the INIT_B pin, allowing the DSP chip to read the configuration status of the FPGA chip.

[0045] The DSP chip is connected to the solid-state memory's SPI bus via its own SPI bus. Furthermore, the DSP chip, FPGA chip, and solid-state memory are connected in a daisy-chain configuration.

[0046] This application also proposes a method for operating a controller with an FPGA chip, which employs any of the aforementioned controllers with an FPGA chip. Figure 2 This is a flowchart illustrating the steps of the operation method of the controller with an FPGA chip in an embodiment of the present invention, as shown below. Figure 2As shown, the running method may include the following steps:

[0047] S101: The DSP chip receives the update command from the host computer, reports the status back to the host computer, and changes the update program flag to 1.

[0048] Figure 3 This is a flowchart illustrating the operating principle of the DSP chip in an embodiment of the present invention, as shown below. Figure 3 As shown, in this step, as a feasible approach, after a DSP chip reset or system reset, initialization can be performed first, restoring the update program flag (Flag) to 0 and the counter (count) to 0. Before receiving the program, the DSP chip first reads whether the host computer has an update command, for example, by reading the status of the RS232 serial bus to detect if there is an update command. If the host computer has an update command, the DSP chip sends information back to the host computer, waits and prepares to receive the program required by the FPGA, and changes the update program flag (Flag) to 1.

[0049] S102: The DSP chip receives the program and stores it in dynamic memory.

[0050] In this step, after receiving the feedback information, the host computer can use a terminal emulator, such as the Xmodem protocol, to transmit the binary program (bin file) generated by the FPGA development tools to the DSP via an RS232 serial port. The DSP chip then receives the program and stores it in its dynamic memory.

[0051] S103: After the program is stored in the dynamic memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to a low level.

[0052] like Figure 3 As shown, after the program is stored in the dynamic memory, the DSP chip sets the potential of the FPGA chip's PROB pin to a low level, such as 0. At this time, the FPGA chip enters a reset state. Alternatively, the counter count is incremented by 1.

[0053] S104: When the PROB pin of the FPGA chip is at a low level, the DSP chip writes the program in the dynamic memory into the solid-state memory.

[0054] In this step, when the PROB pin of the FPGA chip is at a low potential, the DSP chip converts the program in the dynamic memory into fixed-format data and writes it into the solid-state memory via the SPI bus.

[0055] S105: After the program is written to the solid-state memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to a high potential.

[0056] In this step, after the program is written to the solid-state memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to a high potential, that is, to 1. At this time, the FPGA chip becomes capable of starting up.

[0057] S106: When the PROB pin of the FPGA chip is at a high potential, the FPGA chip loads the program from the solid-state memory and starts.

[0058] In this step, such as Figure 3 As shown, when the PROB pin of the FPGA chip is at a high potential, the FPGA chip loads the program from the solid-state memory and starts.

[0059] S107: After the FPGA chip loads the program from the solid-state memory and starts up successfully, the FPGA chip changes the potential of the DONE pin to a high level. If the FPGA chip fails to load the program from the solid-state memory, the potential of the DONE pin remains low.

[0060] S108: After the FPGA chip loads the program from the solid-state memory and starts up successfully, the DSP chip detects the potential of the DONE pin of the FPGA chip. If the potential of the DONE pin of the FPGA chip is high and the program update flag is 1, the DSP chip reads the version number of the program in the FPGA chip and outputs the version number.

[0061] After step S106 is executed, a period of time is waited. The DSP chip detects the potential of the DONE pin of the FPGA chip. If the potential of the DONE pin of the FPGA chip is high and the update program flag is 1, the DSP chip reads the version number of the program in the FPGA chip and outputs the version number, for example, through an RS232 serial bus. At this point, it indicates that the FPGA chip has successfully loaded the program and started successfully.

[0062] If the PROB pin of the FPGA chip is low and the update program flag is 1, the DSP chip will rewrite the program from the dynamic memory to the solid-state memory. This indicates that the FPGA chip is experiencing a program loading failure or cannot start, requiring a rewrite of the program from the dynamic memory to the solid-state memory. After the program is rewritten to the solid-state memory, the DSP chip sets the PROB pin of the FPGA chip to a high level. If successful, the counter `count` is incremented by 1. When the PROB pin of the FPGA chip is high, the FPGA chip loads the program from the solid-state memory and starts.

[0063] This cycle repeats until the DSP chip rewrites the program from the dynamic memory to the solid-state memory a preset number of times, i.e., when the counter reaches the preset number, for example, three times. At this point, the DSP chip outputs an error message, for example, via an RS232 serial bus. This can be interpreted as the program sent by the host computer not being the program corresponding to the specific FPGA chip model.

[0064] S109: When the DSP chip does not receive an update command from the host computer, the DSP chip checks the state of the DONE pin of the FPGA chip. If the DONE pin is low, the DSP chip outputs information that no program is stored in the solid-state memory. If the DONE pin is high, the DSP chip reads the version number of the program in the FPGA chip and outputs the version number information and / or a successful startup message. This step can be performed selectively.

[0065] If the controller with the FPGA chip in this application does not require program updates, the DSP chip and the FPGA chip will start independently after power-on, which shortens the system startup time and increases system stability.

[0066] Existing FPGA chips, operating in master mode, can only be upgraded via an emulator, not remotely. Remote upgrades require configuring the FPGA as a slave, necessitating an external DSP or MCU chip highly coupled to its startup. Each power-on cycle involves reading the program from FLASH, transferring it to RAM, and then programming it into the FPGA. This process increases data transmission risks, lengthens system startup time, and raises instability. This application combines these two approaches, leveraging the unique characteristics of both DSP and FPGA chips to decouple them, effectively mitigating the shortcomings of existing technologies. In other words, the DSP chip directly receives the program required for remote FPGA chip upgrades via its data input interface and stores it in dynamic memory. When the PROB pin of the FPGA chip is at a low potential, the DSP chip writes the program from the dynamic memory to solid-state memory. When the PROB pin of the FPGA chip is at a high potential, the FPGA chip can directly load the program from the external solid-state memory and start. Simultaneously, the DSP can also start its own application program. This eliminates the need for a dedicated emulator, significantly improving program upgrade efficiency, reducing upgrade costs, and shortening upgrade time. Secondly, the controller with the FPGA chip decouples the FPGA chip and DSP chip during startup, preventing startup timing from affecting the initial state of the system. Finally, this application can shorten the startup time of the controller with the FPGA chip and enhance system stability. In the prior art, when the FPGA chip adopts slave mode, the startup time is the sum of the DSP chip's boot startup, the DSP chip guiding the FPGA chip to start (including the DSP chip reading the program from flash to RAM, verification, and then writing the data in RAM to the FPGA chip), and the DSP chip's application startup. With the solution of this application, without updating the FPGA chip program, after the DSP chip's boot startup, the FPGA chip and the DSP chip's application startup can start simultaneously, thereby shortening the overall system startup time.

[0067] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0068] Although this application has been described by way of examples, those skilled in the art will know that this application has many variations and modifications without departing from the spirit of this application, and it is intended that the appended claims cover such variations and modifications without departing from the spirit of this application.

Claims

1. A controller having an FPGA chip, characterized by, It includes: The system includes a DSP chip, an FPGA chip, a solid-state memory (SSD), and a dynamic memory (DRAM). The DSP chip is communicatively connected to the DRAM, and the I / O pins of the DSP chip are electrically connected to the PROB pins of the FPGA chip. The SSD includes a FLASH memory. The DSP chip and the FPGA chip are electrically connected to the SSD via an SPI interface or a QSPI interface, respectively. The DSP chip also has a data input interface. The DSP chip receives a program through the data input interface and stores the program in the dynamic memory. It also controls the potential of the PROB pin of the FPGA chip to reset and start the FPGA chip. When the PROB pin of the FPGA chip is at a low potential, the DSP chip writes the program from the dynamic memory into the solid-state memory. After the program is written into the solid-state memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to a high potential. The FPGA chip is configured in master mode. When the PROB pin of the FPGA chip is at a high potential, the FPGA chip loads the program from the solid-state memory and starts the program. When the program is not updated, the DSP chip and the FPGA chip can be decoupled and start independently and simultaneously.

2. The controller with FPGA chip according to claim 1, characterized in that, The I / O pins of the DSP chip are also electrically connected to the INIT_B and DONE pins of the FPGA chip. The DSP chip is connected to the SPI bus of the solid-state memory via the SPI bus; the DSP chip, the FPGA chip, and the solid-state memory are connected in a daisy chain.

3. The controller with FPGA chip according to claim 2, characterized in that, The FPGA chip is used to load the program from the solid-state memory and start it, and then set the DONE pin to a high potential.

4. A rail transport apparatus, characterized by, The rail transit equipment includes: a rail transit traction converter, which includes a controller with an FPGA chip as described in any one of claims 1 to 3.

5. A method for operating a controller with an FPGA chip as described in any one of claims 1 to 3, characterized in that, The operation method of the controller with the FPGA chip includes the following steps: The DSP chip receives the program and stores the program in the dynamic memory; After the program is stored in the dynamic memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to a low potential; When the PROB pin of the FPGA chip is at a low potential, the DSP chip writes the program in the dynamic memory into the solid-state memory; After the program is written to the solid-state memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to a high potential; When the PROB pin of the FPGA chip is at a high potential, the FPGA chip loads the program from the solid-state memory and starts.

6. The method for operating a controller with an FPGA chip according to claim 5, characterized in that, When the potential of the PROB pin of the FPGA chip is low, the FPGA chip is in a reset state; when the potential of the PROB pin of the FPGA chip is high, the FPGA chip can start up.

7. The method for operating a controller with an FPGA chip according to claim 5, characterized in that, The operation method of the controller with the FPGA chip further includes the following steps: Before the DSP chip receives the program, the DSP chip receives the update instruction from the host computer, feeds back the status to the host computer, and changes the update program flag bit to 1; After the FPGA chip loads the program from the solid-state memory and starts up successfully, the FPGA chip changes the potential of the DONE pin to a high potential. After the FPGA chip loads the program from the solid-state memory and starts up successfully, the DSP chip detects the potential of the DONE pin of the FPGA chip. If the potential of the DONE pin of the FPGA chip is high and the flag bit of the update program is 1, the DSP chip reads the version number of the program in the FPGA chip and outputs the version number.

8. The method for operating a controller with an FPGA chip according to claim 7, characterized in that, If the PROB pin of the FPGA chip is at a low potential and the flag bit of the update program is 1, then the DSP chip rewrites the program in the dynamic memory into the solid-state memory. After the program is rewritten to the solid-state memory, the DSP chip sets the potential of the PROB pin of the FPGA chip to a high potential. When the PROB pin of the FPGA chip is at a high potential, the FPGA chip loads the program from the solid-state memory and starts.

9. The method for operating a controller with an FPGA chip according to claim 8, characterized in that, When the number of times the DSP chip rewrites the program from the dynamic memory to the solid-state memory reaches a preset number, the DSP chip outputs an error message.

10. The method for operating a controller with an FPGA chip according to claim 8, characterized in that, The operation method of the controller with the FPGA chip further includes the following steps: When the DSP chip does not receive an update instruction from the host computer, the DSP chip detects the state of the DONE pin of the FPGA chip. If the state of the DONE pin is low, the DSP chip outputs information that the program is not stored in the solid-state memory. If the DONE pin is at a high level, the DSP chip reads the version number of the program in the FPGA chip and outputs the version number information and / or a successful startup message.

Images