Three-dimensional memory device and method of making the same

Abstract

The application provides a three-dimensional storage device and a manufacturing method thereof. The three-dimensional storage device comprises a semiconductor layer, a first stack structure on the semiconductor layer, a gate slit through the first stack structure, an insulating layer filling the gate slit, and a first conductive column in the insulating layer. An end of the first conductive column close to the semiconductor layer and the semiconductor layer comprise part of the insulating layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a three-dimensional memory device and a manufacturing method thereof. BACKGROUND

[0002] Three-dimensional memory device is a new type of flash memory, which solves the limitations of two-dimensional or planar flash memory by vertically stacking multiple layers of data storage units. Three-dimensional memory device has excellent precision, supports higher storage capacity in smaller space, low cost, low power consumption, and can fully meet many needs. However, three-dimensional memory device still faces many challenges. SUMMARY

[0003] To solve the problems in the related art, embodiments of the present application provide a three-dimensional memory device and a manufacturing method thereof.

[0004] Embodiments of the present application provide a three-dimensional memory device, comprising:

[0005] a semiconductor layer;

[0006] a first stack structure located on the semiconductor layer;

[0007] a gate line slit (GLS) penetrating the first stack structure;

[0008] an insulating layer filling the gate line slit, and

[0009] a first conductive column provided in the insulating layer, wherein an end of the first conductive column close to the semiconductor layer comprises part of the insulating layer.

[0010] In the above scheme, the first stack structure comprises a plurality of gate layers and dielectric layers arranged at intervals;

[0011] The first conductive column extends at least to a first plane; the first plane is a plane in which a surface of a first gate layer close to the semiconductor layer is located; the first gate layer is a gate layer in the first stack structure closest to the semiconductor layer.

[0012] In the above scheme, the three-dimensional memory device further comprises a gate dielectric layer, which is arranged between the insulating layer and the inner wall of the gate line slit; an end of the first conductive column close to the semiconductor layer comprises part of the insulating layer and part of the gate dielectric layer.

[0013] In the above scheme, the gate line slit extends into the semiconductor layer, and the opening size of the gate line slit in the semiconductor layer is smaller than the opening size of the gate line slit in the first stack structure.

[0014] In the above aspect, the three-dimensional memory device further comprises a barrier layer between the semiconductor layer and the first stack structure.

[0015] In the above aspect, the three-dimensional memory device further comprises a channel structure penetrating the first stack structure and extending into the semiconductor layer; the channel structure comprises a channel hole, and a barrier medium layer, a charge trapping layer, a tunneling medium layer and a channel layer arranged along the channel hole in sequence in a radial direction; the barrier medium layer, the charge trapping layer, the tunneling medium layer and the channel layer of the channel structure all penetrate the barrier layer; and the channel layer is electrically connected with the semiconductor layer.

[0016] In the above aspect, the channel layer of the channel structure extends into the semiconductor layer; and the part of the channel layer extending into the semiconductor layer is in contact with the semiconductor layer.

[0017] The embodiment of the present application further provides a three-dimensional memory device, comprising: a first semiconductor structure and a second semiconductor structure arranged in a stack; wherein the first semiconductor structure and the second semiconductor structure are connected together through bonding.

[0018] The first semiconductor structure comprises: a first substrate; a peripheral circuit on the first substrate;

[0019] The second semiconductor structure comprises: a first stack structure on the peripheral circuit of the bonding combination layer; a semiconductor layer on the first stack structure; a gate slit penetrating the first stack structure; an insulating layer filling the gate slit, and a first conductive column arranged in the insulating layer; and the part between the first conductive column close to the semiconductor layer and the semiconductor layer comprises part of the insulating layer.

[0020] In the above aspect, the first stack structure comprises a plurality of gate layers and dielectric layers arranged at intervals.

[0021] The first conductive column extends at least to a first plane; the first plane is a plane in which a surface of the first gate layer close to the semiconductor layer is located; and the first gate layer is a gate layer of the first stack structure closest to the semiconductor layer.

[0022] In the above aspect, the three-dimensional memory device further comprises a gate dielectric layer arranged between the insulating layer and the inner wall of the gate slit; and the part between the first conductive column close to the semiconductor layer and the semiconductor layer comprises part of the insulating layer and part of the gate dielectric layer.

[0023] In the above aspect, the three-dimensional memory device further comprises:

[0024] a source contact located in the semiconductor layer;

[0025] an electrical lead-through structure located on the semiconductor layer; the source contact is electrically connected with the electrical lead-through structure.

[0026] Another embodiment of the present application provides a method for manufacturing a three-dimensional memory device, comprising:

[0027] providing a base structure; the base structure comprises a source sacrificial layer and a second stack structure located above the source sacrificial layer;

[0028] forming a gate slit extending through the second stack structure;

[0029] filling an insulating layer into the gate slit;

[0030] forming a first conductive pillar in the insulating layer, the first conductive pillar comprises a portion of the insulating layer between an end of the first conductive pillar close to the source sacrificial layer and the source sacrificial layer;

[0031] removing the source sacrificial layer;

[0032] forming a semiconductor layer.

[0033] In the above scheme, the gate slit extends into the source sacrificial layer.

[0034] In the forming of the gate slit, an etching parameter with gradient change over time is adopted to etch the second stack structure and the source sacrificial layer, so that the opening size of the gate slit in the source sacrificial layer is smaller than the opening size of the gate slit in the second stack structure.

[0035] In the above scheme, the filling of the insulating layer into the gate slit comprises:

[0036] forming an initial insulating layer with a first height in the gate slit;

[0037] etching the initial insulating layer to form an insulating layer with a second height, wherein the first height is greater than the second height.

[0038] In the above scheme, the method further comprises:

[0039] forming a gate dielectric layer on the inner wall of the gate slit before the filling of the insulating layer into the gate slit; the first conductive pillar comprises a portion of the insulating layer and a portion of the gate dielectric layer between an end of the first conductive pillar close to the semiconductor layer and the source sacrificial layer.

[0040] In the above scheme, the method further comprises:

[0041] forming the source sacrificial layer on a second substrate;

[0042] forming the second stack structure on the source sacrificial layer, to obtain the base structure.

[0043] In the above scheme, the second stack structure comprises a plurality of spacer arranged gate sacrificial layers and dielectric layers.

[0044] The method further comprises:

[0045] Before forming the gate dielectric layer, the gate sacrificial layer is removed.

[0046] After forming the gate dielectric layer and before forming the filling insulating layer, a gate layer is formed at the position of the gate sacrificial layer, to obtain a first stack structure.

[0047] In the above scheme, the first conductive column extends at least to a first plane; the first plane is a plane in which a surface of a first gate layer close to the source sacrificial layer is located; the first gate layer is a gate layer closest to the source sacrificial layer among a plurality of gate layers.

[0048] In the above scheme, the method further comprises:

[0049] forming a peripheral circuit on a first substrate;

[0050] bonding the first substrate on which the peripheral circuit is formed and the second substrate on which the first conductive column is formed, to form a bonding combination layer;

[0051] removing the second substrate, to expose the source sacrificial layer.

[0052] In the above scheme, the method further comprises:

[0053] forming a source contact in the semiconductor layer;

[0054] forming an electrical lead-out structure on a second surface of the semiconductor layer; the source contact is electrically connected to the electrical lead-out structure; the first stack structure is located on a first surface of the semiconductor layer; the first surface and the second surface are opposite surfaces.

[0055] In the above scheme, the method further comprises:

[0056] forming a barrier layer on the source sacrificial layer before forming the second stack structure.

[0057] In the above scheme, the method further comprises:

[0058] forming a channel hole penetrating through the second stack structure, the barrier layer and extending into the source sacrificial layer;

[0059] forming a barrier dielectric layer, a charge trapping layer, a tunnel dielectric layer and a channel layer along the channel hole in sequence in a radial direction.

[0060] After removing the source sacrificial layer, remove the barrier dielectric layer, charge trapping layer, and tunneling dielectric layer corresponding to the channel hole portion located in the source sacrificial layer.

[0061] In the above scheme, forming the semiconductor layer includes:

[0062] A semiconductor material layer is formed on the surface of the barrier layer;

[0063] The semiconductor material layer is planarized to form the semiconductor layer.

[0064] This invention provides a three-dimensional storage device and its fabrication method. The three-dimensional storage device includes: a semiconductor layer; a first stacked structure located on the semiconductor layer; a gate gap penetrating the first stacked structure; an insulating layer filling the gate gap; and a first conductive pillar disposed in the insulating layer, wherein a portion of the insulating layer is included between the end of the first conductive pillar near the semiconductor layer and the semiconductor layer. In this invention, a floating conductive material (the first conductive pillar) is disposed in the gate gap to improve the anti-interference capability of the three-dimensional memory. Attached Figure Description

[0065] Figure 1 A cross-sectional schematic diagram of a three-dimensional memory provided in an embodiment of the present invention. Figure 1 ;

[0066] Figure 2 A cross-sectional schematic diagram of a three-dimensional memory provided in an embodiment of the present invention. Figure 2 ;

[0067] Figure 3 This is a schematic flowchart of a method for fabricating a three-dimensional memory according to an embodiment of the present invention;

[0068] Figures 4a-4r This is a cross-sectional schematic diagram illustrating the fabrication process of a three-dimensional memory provided in an embodiment of the present invention. Detailed Implementation

[0069] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0070] The application is described more by way of example in the following paragraphs and with reference to the accompanying drawings. Advantages and features of the application will become apparent from the following description of the application and from the claims. It is to be understood that the drawings are designed solely for purposes of illustration and are not intended to limit the scope of the application, for which reference should be made solely to the appended claims.

[0071] It is to be understood that the terms "on," "over," and "above," in the context of the present application, are to be interpreted in the broadest relative terms such that "on" not only means "on" something without intervening characteristics or layers (i.e., directly on something), but also includes "on" something with intervening characteristics or layers.

[0072] Further, spatially relative terms, such as "on," "over," "above," "up," "upper," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0073] In embodiments of the application, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Further, the substrate can comprise a variety of semiconductor materials, such as silicon, germanium, silicon carbide, silicon germanium, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0074] In embodiments of the application, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of an underlying or overlying structure, or can have a shape that is less than the underlying or overlying structure. Further, a layer can be a region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between a top surface and a bottom surface of a continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. A layer can include multiple sub-layers. For example, an interconnect layer can include one or more conductor and contact sub-layers (in which interconnect lines and / or via contacts are formed), and one or more dielectric sub-layers.

[0075] In embodiments of the application, the terms "first," "second," and the like, are used to distinguish between similar objects, and are not necessarily used to describe a particular sequential or chronological order.

[0076] It should be noted that the technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.

[0077] The embodiment of the present application provides a three-dimensional storage device, which comprises:

[0078] Based on the manufacturing method of the three-dimensional storage device, the embodiment of the present application further provides a three-dimensional storage device, which comprises:

[0079] A semiconductor layer;

[0080] A first stack structure located on the semiconductor layer;

[0081] A gate slit penetrating through the first stack structure;

[0082] An insulating layer filling the gate slit, and

[0083] A first conductive column arranged in the insulating layer, wherein one end of the first conductive column close to the semiconductor layer comprises part of the insulating layer.

[0084] In some embodiments, the first stack structure comprises a plurality of gate layers and dielectric layers arranged at intervals.

[0085] The first conductive column extends at least to a first plane; the first plane is a plane in which a surface of a first gate layer close to the semiconductor layer is located; the first gate layer is a gate layer closest to the semiconductor layer in the first stack structure.

[0086] In some embodiments, the three-dimensional storage device further comprises a gate dielectric layer arranged between the insulating layer and the inner wall of the gate slit; one end of the first conductive column close to the semiconductor layer comprises part of the insulating layer and part of the gate dielectric layer.

[0087] In some embodiments, the gate slit extends into the semiconductor layer, and the opening size of the gate slit in the semiconductor layer is smaller than the opening size of the gate slit in the first stack structure.

[0088] In some embodiments, the three-dimensional storage device further comprises a barrier layer located between the semiconductor layer and the first stack structure.

[0089] In some embodiments, the three-dimensional memory device further includes a channel structure extending through the first stack structure and into the semiconductor layer; the channel structure includes a channel hole, and a blocking dielectric layer, a charge trapping layer, a tunneling dielectric layer, and a channel layer disposed along the channel hole in a radial order; the blocking dielectric layer, the charge trapping layer, the tunneling dielectric layer, and the channel layer of the channel structure all extend through the blocking layer; and the channel layer is electrically connected with the semiconductor layer.

[0090] In some embodiments, the channel layer of the channel structure extends into the semiconductor layer; and the portion of the channel layer extending into the semiconductor layer is in contact with the semiconductor layer.

[0091] In some embodiments, the material of the first conductive pillar includes polysilicon.

[0092] In some embodiments, the material of the gate dielectric layer includes aluminum oxide.

[0093] Figure 1 A cross-sectional view of a three-dimensional memory device is provided for embodiments of the present application. As shown in Figure 1 The three-dimensional memory device 10 includes a semiconductor layer 203, which can include an electrically conductive material, such as polysilicon. In practical applications, the semiconductor layer 203 can serve as a common source layer.

[0094] As shown in Figure 1 The three-dimensional memory device 10 further includes a blocking layer 205 on the semiconductor layer 203. The blocking layer 205 can include any suitable material that is different from the material of the dielectric layer 2062 in the first stack structure 206.

[0095] As shown in Figure 1As shown, the three-dimensional storage device 10 also includes a first stacked structure 206 located on the barrier layer 205. The first stacked structure 206 includes a plurality of spaced-apart gate layers 2061 and dielectric layers 2062. In other words, except for the layers at the top or bottom of the first stacked structure 206, each gate layer 2061 may be adjacent to two dielectric layers 2062 on both sides, and each dielectric layer 2062 may be adjacent to two gate layers 2061 on both sides. The gate layers 2061 may include a conductive material, including but not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each gate layer 2061 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the gate layer 2061 may extend laterally as a word line and terminate at one or more stepped structures of the first stacked structure 206. The material of the dielectric layers 2062 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In practical applications, the gate layer 2061 and the dielectric layer 2062 may have the same thickness or different thicknesses. The number of pairs of gate layers 2061 and dielectric layers 2062 in the first stacked structure 206 (e.g., 32, 64, 96, 128, 160, 192, 224, 256 or more) determines the number of memory cells in the three-dimensional memory device 10. It should be understood that in some embodiments, the first stacked structure 206 may have a stack architecture (not shown) comprising multiple memory device stacks stacked on top of each other. The number of pairs of gate layers 2061 and dielectric layers 2062 in each memory device stack may be the same or different.

[0096] It should be noted that the first gate layer 2061-1 mentioned in the embodiments of the present invention is the gate layer closest to the semiconductor layer 203 among the several gate layers of the first stacked structure.

[0097] like Figure 1 As shown, the three-dimensional storage device 10 further includes a plurality of channel structures 207 extending through the first stacked structure 206 and into the semiconductor layer 203. The channel structure 207 includes: a channel via 2071 and a barrier dielectric layer 2072, a charge trapping layer 2073, a tunneling dielectric layer 2074, and a channel layer 2075 arranged radially along the channel via 2071; wherein, the barrier dielectric layer is used to block charge outflow from the storage layer, and the material can be silicon oxide (OX); the storage dielectric is used to trap and store charge, and the material can be silicon nitride (SiN); the tunneling dielectric layer is used to generate charge, and the material can be silicon oxide (OX); the channel layer material can be polycrystalline silicon. In some embodiments, the barrier dielectric layer 2072, the charge trapping layer 2073, the tunneling dielectric layer 2074, and the channel layer 2075 are referred to as an ONOP thin film.

[0098] It should be noted that in the embodiments of the present application, the blocking dielectric layer, the charge trapping layer, the tunneling dielectric layer and the channel layer of each channel structure 207 all penetrate the blocking layer 205; only the channel layer in each channel structure extends into the semiconductor layer 203. Thus, the channel layer 2071 can be conductively connected with the semiconductor layer 203.

[0099] As shown in FIG. 1, the three-dimensional memory device 10 further includes a plurality of gate slits 208 penetrating the first stack structure 206 and extending into the semiconductor layer 203; the inner walls (sides and bottoms) of the gate slits 208 are covered with a gate dielectric layer 209; the surfaces of part of the gate dielectric layer 209 are covered with an insulating layer 210; the insulating layer 210 is filled with a first conductive column 211. In practical applications, the gate dielectric layer 209 includes a high-k dielectric material, such as aluminum oxide (Al2O3). The insulating layer 210 is used for insulation and the material can include an insulating material, such as silicon oxide. Figure 1 Figure 1 It should be noted that in some embodiments, the gate slits 208 can also not extend into the semiconductor layer 203, but only stop at the bottom of the first stack structure 206, or extend into the blocking layer 205.

[0100] It should be noted that in the embodiments of the present application, the gate dielectric layer at the bottom of the gate slit 208 and the insulating layer at the bottom of the gate slit 208 are retained, and the conductive part in the gate slit 208, i.e., the first conductive column 211, is not used to provide electrical connection from the front surface of the three-dimensional memory device to the semiconductor layer, but is floatingly arranged in the gate slit 208, and plays a shielding and anti-interference role for the storage areas divided by the gate slit 208. Here, floating can be understood as that the first conductive column 211 is not electrically connected with other conductive devices in the three-dimensional memory device 10; at the same time, during the process of powering on the three-dimensional memory device 10, the first conductive column 211 is not applied with a potential.

[0101] In practical applications, the shape of the first conductive column 211 is not limited, and preferably, the shape of the first conductive column 211 can be a wall shape similar to the shape of the gate slit 208.

[0102] In some embodiments, the first conductive column 211 at least extends to a first plane; the first plane is a plane in which the surface of the first gate layer 2061-1 close to the semiconductor layer is located; the first gate layer 2061-1 is the gate layer in the first stack structure closest to the semiconductor layer. Here, the first plane is as shown in FIG. 1.

[0103] In some embodiments, the first conductive column 211 at least extends to a first plane; the first plane is a plane in which the surface of the first gate layer 2061-1 close to the semiconductor layer is located; the first gate layer 2061-1 is the gate layer in the first stack structure closest to the semiconductor layer. Here, the first plane is as shown in FIG. 1. Figure 1

[0104] ​​That is, in the embodiment of the present application, the first conductive column 211 filled in the insulating layer 210 is in a floating state, and when the projection of the first conductive column 211 on the plane parallel to the thickness direction of the second substrate can cover the projection of all the gate layers on the plane parallel to the thickness direction of the second substrate, a better shielding and anti-interference effect can be achieved.

[0105] The embodiment of the present application further provides a three-dimensional storage device, comprising: a first semiconductor structure and a second semiconductor structure which are arranged in a stack; wherein the first semiconductor structure and the second semiconductor structure are connected together through bonding;

[0106] The first semiconductor structure comprises: a first substrate; a peripheral circuit on the first substrate;

[0107] The second semiconductor structure comprises: a first stack structure on the bonding combination layer peripheral circuit; a semiconductor layer on the first stack structure; a gate slit penetrating through the first stack structure; an insulating layer filling the gate slit, and a first conductive column in the insulating layer, wherein the end of the first conductive column close to the semiconductor layer and the semiconductor layer comprise part of the insulating layer.

[0108] In some embodiments, the first stack structure comprises a plurality of gate layers and dielectric layers which are arranged at intervals.

[0109] The first conductive column extends at least to a first plane; the first plane is a plane in which the surface of the first gate layer close to the semiconductor layer is located; and the first gate layer is the gate layer in the first stack structure which is closest to the semiconductor layer.

[0110] In some embodiments, the three-dimensional storage device further comprises a gate dielectric layer which is arranged between the insulating layer and the inner wall of the gate slit; and the end of the first conductive column close to the semiconductor layer and the semiconductor layer comprise part of the insulating layer and part of the gate dielectric layer.

[0111] In some embodiments, the three-dimensional storage device further comprises:

[0112] A source contact in the semiconductor layer;

[0113] An electrical lead-out structure on the semiconductor layer; the source contact and the electrical lead-out structure are electrically connected. In some embodiments, the three-dimensional storage device further comprises a barrier layer between the semiconductor layer and the first stack structure.

[0114] In some embodiments, the three-dimensional storage device further includes a channel structure that penetrates the first stacked structure and extends into the semiconductor layer; the channel structure includes a channel hole and a barrier dielectric layer, a charge trapping layer, a tunneling dielectric layer, and a channel layer disposed radially along the channel hole; the barrier dielectric layer, the charge trapping layer, the tunneling dielectric layer, and the channel layer of the channel structure all penetrate the barrier layer; the channel layer is electrically connected to the semiconductor layer.

[0115] In some embodiments, the channel layer of the channel structure extends into the semiconductor layer; and the portion of the channel layer extending into the semiconductor layer contacts the semiconductor layer.

[0116] In some embodiments, the three-dimensional storage device further includes:

[0117] The source contact is located in the semiconductor layer;

[0118] An electrical lead-out structure located on the semiconductor layer; the source contact is electrically connected to the electrical lead-out structure.

[0119] Figure 2 This is a cross-sectional schematic diagram of a three-dimensional storage device provided in an embodiment of the present invention. In this embodiment, the three-dimensional storage device 10 is a bonded chip, and the three-dimensional storage device 10 includes a first semiconductor structure 100, a second semiconductor structure 200 stacked on the first semiconductor structure 100, and a bonding layer 300 located between the first semiconductor structure 100 and the second semiconductor structure 200.

[0120] like Figure 2 As shown, the first semiconductor structure 100 may include a first substrate 101 and peripheral circuitry 102 located on the first substrate. In practical applications, the first substrate 101 may include silicon (e.g., single-crystal silicon (c-Si)), silicon-germanium 100 (SiGe), gallium arsenide (GaAs), germanium (Ge), SOI, or any other suitable material.

[0121] In some embodiments, peripheral circuitry 102 is used to control and sense the three-dimensional storage device 10. Peripheral circuitry 102 can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to facilitate the operation of the three-dimensional storage device 10, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuitry 102 can include transistors formed on a first substrate 101, wherein all or part of the transistors are formed in the first substrate 101 (e.g., below the top surface of the first substrate 101) and / or directly on the substrate 101. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the transistor) can also be formed in the first substrate 101.

[0122] In some embodiments, the first semiconductor structure 100 of the three-dimensional storage device 10 further includes a first interconnect layer above the peripheral circuit 102. Figure 2 (Not shown in the diagram) to transmit electrical signals to and from peripheral circuit 102. The first interconnect layer may include multiple interconnects (also referred to herein as “contacts”, including lateral interconnects and vertical interconnect channel (VIA) contacts. As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as mid-stage (MEOL) interconnects and back-end (BEOL) interconnects. The first interconnect layer may also include interconnects and VIA contacts that may be formed in one or more interlayer dielectric (ILD) layers (also referred to as “intermetallic dielectric (IMD) layers”). That is, the first interconnect layer may include interconnects and VIA contacts in multiple ILD layers. The interconnects and VIA contacts in the first interconnect layer may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the first interconnect layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof.

[0123] like Figure 2As shown, the three-dimensional storage device 10 may further include connection contacts and a first bonding layer 103 above the interconnect layer and peripheral circuitry 102. The first bonding layer 103 may include a plurality of bonding contacts and a dielectric that electrically isolates the bonding contacts. The bonding contacts may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining areas of the first bonding layer 103 may be formed using a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts in the first bonding layer 103 and the surrounding dielectric may be used for hybrid bonding.

[0124] like Figure 2 As shown, the second semiconductor structure 200 of the three-dimensional storage device 10 may also include a second bonding layer 213 at the bonding layer 300 and above the first bonding layer 103 of the first semiconductor structure 100. The composition of the second bonding layer 213 is similar to that of the first bonding layer 103, and will not be described again here. The bonding contacts in the first bonding layer are in conductive contact with each other at the bonding layer 300.

[0125] The second semiconductor structure 200 can be bonded face-to-face to the top of the first semiconductor structure 100 at the bonding layer 300. In some embodiments, as a result of hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), the bonding layer 300 is disposed between the first bonding layer 103 and the second bonding layer 213. Hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding layer 300 is the location where the first bonding layer 103 and the second bonding layer 213 contact and bond. In practice, the bonding layer 300 can be a layer with a specific thickness, including the top surface of the first bonding layer 103 and the bottom surface of the second bonding layer 213.

[0126] In some embodiments, the second semiconductor structure 200 of the three-dimensional storage device 10 further includes a second interconnect layer above the second bonding layer 213. Figure 2 (Not shown in the image) to transmit electrical signals. The materials used to make the second interconnect layer are similar to those of the first interconnect layer, and will not be described again here.

[0127] In some embodiments, the three-dimensional storage device 10 is a three-dimensional NAND type storage device, wherein the storage cells are provided in the form of a NAND storage device string array. For example... Figure 2 As shown, the second semiconductor structure 200 of the three-dimensional storage device 10 may include an array of channel structures 207 used as a NAND storage device string array.

[0128] like Figure 2 As shown, the second semiconductor structure 200 of the three-dimensional storage device 10 includes a first stacked structure 206 located on the second bonding layer 213. In some embodiments, the first stacked structure 206 includes a plurality of spaced-apart gate layers 2061 and dielectric layers 2062. In other words, apart from the layers at the top or bottom of the first stacked structure 206, each gate layer 2061 may be adjacent to two dielectric layers 2062 on both sides, and each dielectric layer 2062 may be adjacent to two gate layers 2061 on both sides. The gate layer 2061 may include a conductive material, including but not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each gate layer 2061 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the gate layer 2061 may extend laterally as a word line and terminate at one or more stepped structures of the first stacked structure 206. The material of the dielectric layer 2062 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In practical applications, the gate layer 2061 and the dielectric layer 2062 may have the same thickness or different thicknesses. The number of pairs of gate layers 2061 and dielectric layers 2062 in the first stacked structure 206 (e.g., 32, 64, 96, 128, 160, 192, 224, 256 or more) determines the number of memory cells in the three-dimensional memory device 10. It should be understood that in some embodiments, the first stacked structure 206 may have a stack architecture (not shown) comprising multiple memory device stacks stacked on top of each other. The number of pairs of gate layers 2061 and dielectric layers 2062 in each memory device stack may be the same or different.

[0129] It should be noted that the first gate layer 2061-1 mentioned in the embodiments of the present invention is the gate layer closest to the semiconductor layer 203 among the several gate layers of the first stacked structure.

[0130] like Figure 2 As shown, the three-dimensional storage device 10 further includes a barrier layer 205 located between the first stacked structure 206 and the semiconductor layer 203. The barrier layer 205 may comprise any suitable material different from the material of the dielectric layer in the first stacked structure 206.

[0131] like Figure 2As shown, the second semiconductor structure 200 of the three-dimensional storage device 10 includes a plurality of channel structures 207 extending through the first stacked structure 206 and into the semiconductor layer 203. The channel structure includes: a channel via 2071 and a barrier dielectric layer 2072, a charge trapping layer 2073, a tunneling dielectric layer 2074, and a channel layer 2075 arranged radially along the channel via 2071; wherein the barrier dielectric layer is used to block charge outflow from the storage layer, and the material can be silicon oxide (OX); the storage dielectric is used to trap and store charge, and the material can be silicon nitride (SiN); the tunneling dielectric layer is used to generate charge, and the material can be silicon oxide (OX); the channel layer material can be polycrystalline silicon. In some embodiments, the barrier dielectric layer 2072, the charge trapping layer 2073, the tunneling dielectric layer 2074, and the channel layer 2075 are referred to as an ONOP thin film.

[0132] It should be noted that, in this embodiment of the invention, the barrier dielectric layer, charge trapping layer, tunneling dielectric layer, and channel layer of each channel structure 207 all penetrate the barrier layer 205; only the channel layer in each channel structure extends into the semiconductor layer 203. Thus, the channel layer 2071 can be electrically connected to the semiconductor layer 203.

[0133] like Figure 2 As shown, the second semiconductor structure 200 of the three-dimensional storage device 10 includes a plurality of gate gaps 208 that penetrate the first stacked structure 206 and extend into the semiconductor layer 203; the inner wall of the gate gap 208 ( Figure 2 A gate dielectric layer 209 is covered on the sides and top of the gate dielectric layer 209; an insulating layer 210 is covered on a portion of the surface of the gate dielectric layer 209; and a first conductive pillar 211 is filled in the insulating layer 210. In practical applications, the gate dielectric layer 209 comprises a high-k dielectric material, such as alumina. The insulating layer 210 is used for insulation, and the material may include insulating materials such as silicon oxide.

[0134] It should be noted that in some embodiments, the gate gap 208 may not extend into the semiconductor layer 203, but may only stop at the bottom of the first stacked structure 206, or extend into the barrier layer 205. It should also be noted that in this embodiment, the gate dielectric layer at the top of the gate gap 208 and the insulating layer at the top of the gate gap 208 are retained. The conductive portion in the gate gap 208, i.e., the first conductive post 211, is not used to provide an electrical connection from the front side of the three-dimensional storage device to the semiconductor layer, but is floating in the gate gap 208, serving as a shield and anti-interference measure for the various storage regions divided by the gate gap 208. Here, "floating" can be understood as the first conductive post 211 not being electrically connected to other conductive devices in the three-dimensional storage device 10; simultaneously, during the operation of the three-dimensional storage device 10, the first conductive post 211 is not subject to any applied potential.

[0135] In practical applications, the shape of the first conductive column 211 is not limited, and preferably, the shape of the first conductive column 211 can be the shape of a wall similar to the shape of the gate slit 208.

[0136] In some embodiments, the first conductive column 211 extends at least to a first plane; the first plane is a plane in which a surface of a first gate layer 2061-1 close to the semiconductor layer is located; the first gate layer 2061-1 is a gate layer closest to the semiconductor layer in the first stack structure. Here, the first plane is as shown in Figure 2

[0137] That is, in the embodiments of the present application, the first conductive column 211 filled in the insulating layer 210 is in a floating state, and when the projection of the first conductive column 211 on a plane parallel to the thickness direction of the second substrate can cover the projection of all the gate layers on the plane parallel to the thickness direction of the second substrate, a better shielding and anti-interference effect can be achieved.

[0138] As shown in Figure 3 The second semiconductor structure 200 of the three-dimensional storage device 10 includes a semiconductor layer 203 above the blocking layer 205. The material of the semiconductor layer 203 can include conductive materials, such as polysilicon.

[0139] As shown in Figure 3 The second semiconductor structure 200 of the three-dimensional storage device 10 includes a source contact 212 in the semiconductor layer 203. The material of the source contact 212 can include conductive materials.

[0140] As shown in Figures 4a-4r The three-dimensional storage device 10 further includes an electrical lead-out structure 400 for connecting with external devices.

[0141] The embodiments of the present application provide a three-dimensional storage device, which includes a semiconductor layer; a first stack structure above the semiconductor layer; a gate slit extending through the first stack structure and into the semiconductor layer; wherein the inner wall of the gate slit in the axial direction and the radial direction both include gate dielectric layers and insulating layers arranged in stacks; and a first conductive column filled in the insulating layer. In the embodiments of the present application, on the one hand, a floating conductive material is arranged in the gate slit to achieve the purpose of improving the anti-interference ability of the three-dimensional storage device; on the other hand, the gate dielectric layer at the bottom of the gate slit (the inner wall of the gate slit in the radial direction) is reserved, which avoids etching the bottom of the gate slit with a high aspect ratio and reduces the process difficulty.

[0142] The embodiments of the present application provide a three-dimensional storage device manufacturing method, Figure 3 ​A flowchart of a method for manufacturing a three-dimensional memory device is implemented by the present application. As shown in Figures 4a-4r The method comprises the following steps:

[0143] Step 301: providing a base structure; the base structure comprises a source electrode sacrificial layer, a second stack structure located above the source electrode sacrificial layer;

[0144] Step 302: forming a gate slit through the second stack structure;

[0145] Step 303: filling the gate slit with an insulating layer;

[0146] Step 304: forming a first conductive pillar in the insulating layer, the first conductive pillar comprising a portion of the insulating layer between one end of the source electrode sacrificial layer and the source electrode sacrificial layer;

[0147] Step 305: removing the source electrode sacrificial layer;

[0148] Step 306: forming a semiconductor layer. Figure 3 A cross-sectional view of a manufacturing process of a three-dimensional memory device according to an embodiment of the present application is shown below. The following describes the formation of a three-dimensional memory device according to the embodiment in conjunction with Figures 4a-4r and Figure 3 It should be noted that, Figures 4a-4r and Figures 4a-4d The operations shown in Figure 4a and Figure 4b are not exhaustive, and other operations can be performed before, after, or between any of the operations shown. In addition, some of these operations can be performed simultaneously, or in a different order than shown in Figure 4a and Figure 4b .

[0149] In step 301, referring to Figure 4b , the main purpose is to provide a base structure. The base structure comprises a source electrode sacrificial layer, a second stack structure, and a gate slit through the second stack structure.

[0150] In some embodiments, the method further comprises:

[0151] forming the source electrode sacrificial layer 203' on the second substrate 201;

[0152] forming the second stack structure 206' on the source electrode sacrificial layer 203', obtaining the base structure.

[0153] In practical applications, the second substrate 201 may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. Figure 4b As shown, a source sacrificial layer 203' is formed on a second substrate 201. The source sacrificial layer 203' may include any suitable sacrificial material, which may be subsequently removed, and a semiconductor layer 203 is formed at the removal site. In some embodiments, the source sacrificial layer 203' is sandwiched between a first stop layer 202 and a second stop layer 204. In subsequent processes, when the second substrate 201 is removed from the back side, the first stop layer 202 may act as a stop layer for grinding / etching, and based on this, the first stop layer 202 may include any suitable material different from the material of the second substrate 201, such as silicon nitride. Similarly, in subsequent processes, when the source sacrificial layer 203' is removed from the back side, the second stop layer 204 may act as an etch stop layer, and based on this, the second stop layer 204 may include any suitable material different from the material of the source sacrificial layer 203'. In subsequent processes, the first stop layer 202 is removed, and the second stop layer 204 is selectively removed.

[0154] In practical applications, the methods for forming the source sacrificial layer 203' include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0155] In some embodiments, the method further includes forming a barrier layer 205 on the source sacrificial layer 203' before forming the second stacked structure 206'.

[0156] In subsequent processes, after removing the source sacrificial layer 203', when removing the ONO film (barrier dielectric layer, charge trapping layer, tunneling dielectric layer) corresponding to the channel hole portion in the source sacrificial layer 203', the barrier layer can prevent the removal process from damaging the dielectric layer in the first stacked structure 206. Based on this, the barrier layer 205 can include any suitable material different from the material of the dielectric layer in the first stacked structure 206.

[0157] Next, as Figure 4cAs shown, a second stack structure 206' is formed. In some embodiments, the second stack structure 206' includes a plurality of spaced-apart gate sacrificial layers 2061' and dielectric layers 2062. In a specific embodiment, the gate sacrificial layers 2061' can be formed of silicon nitride (SiN), and the dielectric layers 2062 can be formed of silicon oxide (SiO2), so that the second stack structure 206' is a nitride-oxide (NO) stack. In a subsequent process, the gate sacrificial layers 2061' can be removed, and gate metal material is filled in the locations where the gate sacrificial layers 2061' are removed, forming gate layers whose material includes, for example, tungsten (W). The stack structure after the gate layer replacement in embodiments of the present application is referred to as the first stack structure 206. In practical applications, the manner of forming the gate sacrificial layers 2061' and the dielectric layers 2062 includes, but is not limited to, CVD, PVD, ALD, etc. Next, as shown, Figure 4c As shown, a staircase structure can be formed on at least one side of the second stack structure 206'. The staircase structure can be formed by performing a plurality of so-called "trim-etch" cycles on the second stack structure 206'. After that, as shown, Figure 4d As shown, insulating material is filled in the staircase structure.

[0158] In some embodiments, before the gate slit 208 is formed, the method further includes forming a channel structure 207; the step of forming the channel structure 207 includes: forming a channel hole 2071 that penetrates through the second stack structure 206', the barrier layer 205, and extends into the source sacrificial layer 203'; and sequentially forming, along the channel hole, a barrier dielectric layer 2072, a charge trapping layer 2073, a tunneling dielectric layer 2074, and a channel layer 2075. In practical applications, as shown, Figure 4e As shown, each channel hole 2071 is an opening that extends vertically through the second stack structure 206, the barrier layer, and stops in the source sacrificial layer 203'. In practical applications, the manner of forming the channel hole 2071 can include dry etching. As shown, Figure 4fThe blocking dielectric layer 2072, the charge trapping layer 2073, the tunneling dielectric layer 2074 and the channel layer 2075 are sequentially formed along the sidewall and the bottom surface of the channel hole in the order. The blocking dielectric layer 2072 is used to reduce the probability of charge movement in the memory cell to the gate of the memory cell, and the constituent material can include: oxide, oxynitride, dielectric with dielectric constant (k) greater than a preset threshold, etc., such as silicon oxide. The charge trapping layer 2073 is used to trap charges, and the constituent material can include: nitride, oxynitride, or silicon, etc., such as silicon nitride. The tunneling dielectric layer 2074 is used to make the charge tunnel between the channel region and the charge trapping layer under the action of an applied voltage, and the constituent material can include: oxide, or oxynitride, etc.; for example, silicon oxide. The channel layer 2075 can include: polysilicon and amorphous silicon; for example, polysilicon. In some embodiments, the blocking dielectric layer 2072, the charge trapping layer 2073, the tunneling dielectric layer 2074 and the channel layer 2075 can be formed by sequentially depositing a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer and a polysilicon layer ("ONOP" structure).

[0159] Next, in step 302, as shown, gate slits 208 are formed through the second stack structure 206' and extending into the source sacrificial layer. Each gate slit 208 is an opening extending vertically through the second stack structure 206', the blocking layer, and stopping in the source sacrificial layer 203'. In practical applications, the method of forming the gate slit 208 can include dry etching. Figure 4f

[0160] It should be noted that in some embodiments, the gate slit 208 can also not extend into the source sacrificial layer 203', but only stop at the bottom of the second stack structure 206', or extend into the blocking layer 205.

[0161] In some embodiments, the gate slit 208 extends into the source sacrificial layer 203'; when forming the gate slit 208, the second stack structure 206' and the source sacrificial layer 203' are etched using etching parameters with gradient changes over time, so that the opening size of the gate slit 208 in the source sacrificial layer 203' is smaller than the opening size of the gate slit 208 in the second stack structure 206'.

[0162] It can be understood that when the insulating material for forming the insulating layer is deposited on the sidewall of the gate slit 208 formed with the gate dielectric layer in the subsequent process, the closed state of the insulating material at the bottom of the gate slit 208 can be achieved.

[0163] After that, the replacement of the gate sacrificial layer to the gate layer can be performed through the gate slit 208.

[0164] ​In some embodiments, such as Figure 4f As shown, the method further includes removing the gate sacrificial layer 2061' before forming the gate dielectric layer 209. In practical applications, the gate sacrificial layer 2061' can be removed by wet etching.

[0165] Next, refer to Figure 4f The gate dielectric layer 209 is mainly formed. The gate dielectric layer 209 includes a high-k dielectric material, such as aluminum oxide.

[0166] In some embodiments, the method further includes:

[0167] Before filling the gate gap 208 with the insulating layer 210, a gate dielectric layer 209 is formed on the inner wall of the gate gap; the first conductive pillar 211 includes a portion of the insulating layer 210 and a portion of the gate dielectric layer 209 between one end of the first conductive pillar 211 near the semiconductor layer and the source sacrificial layer 203'.

[0168] In practical applications, such as Figures 4g-4h As shown, the gate dielectric layer 209 is recessed laterally, so that the gate dielectric layer 209 exists on the sidewalls and bottom of the gate gap 208. In practical applications, the gate dielectric layer 209 can be formed by methods including but not limited to CVD, PVD, ALD, etc.

[0169] It should be noted that, in this embodiment of the invention, the radial inner wall of the gate gap 208 needs to be retained. Figure 4g The gate dielectric layer 209 is located on the bottom of the gate slot 208. In subsequent processes, after removing the source sacrificial layer 203', when removing the ONO film (barrier dielectric layer, charge trapping layer, tunneling dielectric layer) corresponding to the channel via portion in the source sacrificial layer 203', the gate dielectric layer 209 on the radial inner wall of the gate slot 208 can prevent the insulating layer in the gate slot 208 from being etched by the removal process. At the same time, retaining the gate dielectric layer on the radial inner wall (bottom) of the gate slot can avoid bottom etching of the gate slot with a high aspect ratio, thereby greatly reducing the process difficulty and increasing the process window.

[0170] In some embodiments, after forming the gate dielectric layer 209, a gate layer 2061 is formed at the location of the gate sacrificial layer. In practical applications, such as... Figure 4g As shown, the gate layer 2061 (including the gate electrode and the adhesive layer) is deposited in the lateral recess through the gate gap 208. In practical applications, the gate layer 2061 can be formed by methods including but not limited to CVD, PVD, and ALD.

[0171] It should be noted that after the replacement of the gate layer, the gate sacrificial layer 2061' in the second stack structure 206' is replaced by the gate layer 2061, at this time, in order to make the description clear, the stack structure composed of the gate layer 2061 and the dielectric layer 2062 is called the first stack structure 206.

[0172] In step 303, referring to Figure 4h , an insulating layer 210 covering the gate dielectric layer 209 is mainly formed. The insulating layer 210 is used for insulation, and the material can include insulating materials such as silicon oxide.

[0173] In some embodiments, the formation of the insulating layer 210 covering the gate dielectric layer 209 includes:

[0174] An initial insulating layer with a first height H1 is formed in the gate gap 208;

[0175] The initial insulating layer is etched to form an insulating layer with a second height H2, wherein the first height is greater than the second height.

[0176] In practical applications, as mentioned earlier, the opening size of the gate gap 208 in the source sacrificial layer 203' is smaller than the opening size of the gate gap 208 in the first stack structure 206. The initial insulating layer is formed in the sidewall of the gate gap 208, and at this time, the insulating material at the bottom of the gate gap 208 presents a closed state as shown in Figure 4h Here, the first height H1 is the height between the closed insulating material and the bottom of the gate gap 208. The closed insulating material is the position of the exposed insulating material in the gate gap 208 closest to the bottom of the gate gap 208. In practical applications, the first height can refer to H1 shown in Figure 4i .

[0177] Next, as shown in Figure 4i , the initial insulating layer is etched to form an insulating layer 210 with a second height H2 smaller than the first height. Here, the second height H2 is the height between the etching stop position of the initial insulating layer and the bottom of the gate gap 208. In practical applications, the second height can refer to H2 shown in Figure 4j .

[0178] In practical applications, when etching the initial insulating layer, the gate dielectric layer 209 deposited on the top of the first stack structure 206 will also be etched to remove the gate dielectric layer 209 on the top of the first stack structure 206.

[0179] It can be understood that, in the embodiment of the present application, the first conductive column 211 filled in the insulating layer 210 is in a floating state, and when the first conductive column 211 extends at least to the first plane, the projection of the first conductive column 211 on the plane parallel to the thickness direction of the second substrate can cover the projection of all the gate layers on the plane parallel to the thickness direction of the second substrate, so that a better shielding and anti-interference effect can be achieved. Here, the first gate layer 2061-1 is the gate layer closest to the source sacrificial layer among the gate layers.

[0180] In step 304, referring to Figure 4k , the first conductive column 211 is mainly filled into the gate gap with the insulating layer. The first conductive column 211 is used to shield and anti-interference for the storage area divided by the gate gap; the first conductive material 211 can include a conductive material, such as polysilicon.

[0181] It should be noted that, in the embodiment of the present application, the gate dielectric layer closest to the bottom of the gate gap 208 and the insulating layer at the bottom of the gate gap 208 are reserved, and the conductive part in the gate gap 208, i.e. the first conductive column 211, is not used to provide electrical connection from the front of the three-dimensional storage device to the semiconductor layer, but is set in the gate gap 208 in a floating state, and is used to shield and anti-interference for the storage area divided by the gate gap 208.

[0182] In practical applications, the filled first conductive material is as shown in Figure 4k The filling method of the first conductive material includes but is not limited to CVD, PVD, ALD, etc.

[0183] Next, as shown in Figures 4a-4j , various connection contacts 214 are formed, including but not limited to channel contacts and word line contacts (gate contacts) and peripheral contacts, etc. Then a second bonding layer 213 is formed on the contacts. The method of forming the connection contacts and the second bonding layer 213 is relatively mature, and will not be described here.

[0184] Next, as shown in Figure 4kAs shown, in some embodiments, the method further includes forming the peripheral circuit 102 on the first substrate 101. In practical applications, the first substrate 101 can be a silicon substrate. As shown in FIG. k, a plurality of transistors are formed on the front side of the first substrate 101 using a plurality of processes, including but not limited to photolithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable process. In some embodiments, doped regions (not shown) are formed in the first substrate 101 by ion implantation and / or thermal diffusion, which are used as source regions and / or drain regions of the transistors, for example. In some embodiments, isolation regions (e.g., STI) are also formed in the first substrate 101 by wet etching and / or dry etching and thin film deposition. The transistors can be formed on the peripheral circuit 102.

[0185] It should be noted that Figures 4a-4j the steps shown in FIG. 1 Figure 4k The steps shown in FIG. 1 Figure 4l the steps shown in FIG. 1 Figure 4m The steps shown in FIG. 1 can be performed simultaneously, or can be performed in a certain order according to process needs.

[0186] Similarly, in FIG. 1 Figure 4n The various connection contacts 104 are formed in FIG. 1, and then the first bonding layer 103 is formed on the contacts. The way of forming the connection contacts and the first bonding layer is relatively mature, and will not be described here.

[0187] Next, the first substrate 101 and the second substrate 201 are bonded. In practical applications, the front side of the first substrate 101 and the front side of the second substrate 201 are bonded in a face-to-face manner, so that the storage array portion stack layer is stacked above the peripheral circuit. The way of bonding can include hybrid bonding. As shown in Figure 4n The second substrate 201 and the functional layers (such as the source sacrificial layer 203', the first stack structure 206, the channel structure 207, the gate gap 208, etc.) formed thereon are flipped upside down. The downward-facing second bonding layer is bonded with the upward-facing first bonding layer, that is, bonded in a face-to-face manner, thereby forming a bonding junction layer 300 between the first substrate 101 and the second substrate 201. In some embodiments, a processing process is applied to the bonding surface before bonding, such as plasma treatment, wet treatment, and / or heat treatment. After bonding, the bonding contacts in the first bonding layer and the bonding contacts in the second bonding layer are aligned with and contact each other.

[0188] Next, the second substrate 201, the first stop layer 202, the source sacrificial layer 203', and the second stop layer 204 are removed in sequence to expose an end portion of each of the plurality of channel structures 207.

[0189] Referring to Figure 4o , the second substrate 201 is removed to expose the source sacrificial layer 203'. The removal can be performed from the back side of the second substrate 201. In practical applications, the second substrate 201 can be removed using CMP, lapping, dry etching, and / or wet etching. In some embodiments, the second substrate 201 can be removed using CMP, which can automatically stop when the first stop layer 202 is reached. The first stop layer 202 can ensure that the second substrate 201 is completely removed without concern for thickness uniformity after thinning. The first stop layer 202 is removed after the second substrate 201 is removed.

[0190] In step 305, referring to Figures 4p-4q , the source sacrificial layer 203' is removed. In some embodiments, the removing the source sacrificial layer 203' includes removing the source sacrificial layer 203' using a wet etching process. In practical applications, the source sacrificial layer 203' can be incompletely removed using an appropriate etchant such as phosphoric acid and hydrofluoric acid until stopped by the second stop layer 204. The second stop layer 204 is selectively removed after the source sacrificial layer 203' is removed, and Figure 4p , the source sacrificial layer 203' and the second stop layer 204 are removed, and a surface of the barrier layer 205 is exposed.

[0191] Next, referring to Figure 4qAfter removing the source sacrificial layer 203', the blocking dielectric layer 2071, the charge trapping layer 2072 and the tunneling dielectric layer 2073 corresponding to the channel hole portion in the source sacrificial layer 203' are removed, i.e. only the channel layer 2075 is reserved. In some embodiments, multiple wet etching processes are performed in sequence to sequentially remove the blocking dielectric layer, the charge trapping layer and the tunneling dielectric layer corresponding to the channel hole portion in the source sacrificial layer 203'. In practical applications, an appropriate etchant such as phosphoric acid can be used to selectively remove the charge trapping layer including silicon nitride, and then an appropriate etchant such as hydrofluoric acid can be used to selectively remove the blocking dielectric layer and the tunneling dielectric layer including silicon oxide. At the same time, the etching of the blocking dielectric layer, the charge trapping layer and the tunneling dielectric layer can be controlled by controlling the etching time and / or etching rate, so that the etching does not affect the blocking dielectric layer, the charge trapping layer and the tunneling dielectric layer corresponding to the remaining part of the channel hole portion. In other embodiments, a patterned second stop layer 204 is used as an etching stop layer. When dry etching is performed, only the exposed blocking dielectric layer, the charge trapping layer and the tunneling dielectric layer are etched, and the etching stops as soon as the second stop layer 204 is etched, so that the etching does not affect the blocking dielectric layer, the charge trapping layer and the tunneling dielectric layer corresponding to the remaining part of the channel hole portion. After the dry etching is completed, the second stop layer 204 can be removed.

[0192] It can be understood that the method of removing the source sacrificial layer 203' and the blocking dielectric layer, the charge trapping layer and the tunneling dielectric layer corresponding to the channel hole portion in the source sacrificial layer 203' from the back can reduce manufacturing complexity and cost, and can increase yield. In addition, the method can also be well adapted to different numbers of stacked structures.

[0193] In step 306, referring to Figure 4r , the semiconductor layer 203 is mainly formed. The semiconductor layer 203 is formed at the position where the source sacrificial layer 203' is removed. The material of the semiconductor layer 203 can include conductive materials such as polysilicon. In some embodiments, the material for forming the semiconductor layer is deposited on the surface of the blocking layer 205; the deposited material is planarized to form the semiconductor layer 203.

[0194] In practical applications, as shown in ​ , a semiconductor material layer is formed on the surface of the blocking layer 205. The way of forming the semiconductor material layer includes but is not limited to CVD, physical PVD, ALD, etc.

[0195] Next, as shown in ​ , the semiconductor material layer is planarized to form the semiconductor layer 203. The planarization can be performed using CMP.

[0196] In subsequent manufacturing processes, source contacts 212 can also be formed.

[0197] In some embodiments, such as ​ As shown, the method further includes: forming a source contact 212 in the semiconductor layer 203; forming an electrical lead-out structure 400 on the second surface of the semiconductor layer 203; the source contact being electrically connected to the electrical lead-out structure 400; the first stacked structure 206 being located on the first surface of the semiconductor layer 203; the first surface and the second surface being opposite to each other. Here, the electrical lead-out structure 400 is used for connection to external devices.

[0198] It is understood that in this embodiment of the invention, the semiconductor layer is connected to the electrical lead structure through the source contact in the semiconductor layer 203, rather than through the conductive portion in the gate gap 208, i.e., the first conductive post 211. In this way, leakage current and parasitic capacitance between the word line and the source contact can be reduced, thereby improving the electrical performance of the three-dimensional storage device.

[0199] The present invention provides a method for fabricating a three-dimensional storage device, which includes a substrate structure comprising a source sacrificial layer and a second stacked structure above the source sacrificial layer; forming a gate gap penetrating the second stacked structure; filling the gate gap with an insulating layer; forming a first conductive pillar in the insulating layer, wherein a portion of the insulating layer is included between the end of the first conductive pillar near the source sacrificial layer and the source sacrificial layer; removing the source sacrificial layer; and forming a semiconductor layer. In this embodiment, on the one hand, floating conductive material is disposed in the gate gap to improve the anti-interference capability of the three-dimensional storage device; on the other hand, the gate dielectric layer at the bottom of the gate gap is retained, avoiding etching the bottom of the gate gap with a high aspect ratio and reducing the process difficulty.

[0200] It should be noted that the technical solutions described in the embodiments of the present invention can be combined arbitrarily without conflict.

[0201] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention.

Claims

1. A three-dimensional memory device comprising: The three-dimensional memory device comprises: a semiconductor layer; a first stack structure located on the semiconductor layer; a gate slit penetrating the first stack structure; an insulating layer filling the gate slit, and a first conductive column provided in the insulating layer, the first conductive column comprising part of the insulating layer between one end of the first conductive column close to the semiconductor layer and the semiconductor layer; a channel structure penetrating the first stack structure. 2.The three-dimensional memory device of claim 1, wherein, The first stack structure comprises a plurality of gate layers and dielectric layers arranged at intervals; the first conductive column extends at least to a first plane; the first plane is a plane in which a surface of a first gate layer close to the semiconductor layer is located; the first gate layer is a gate layer closest to the semiconductor layer in the first stack structure. 3.The three-dimensional storage apparatus of claim 1, wherein, The three-dimensional memory device further comprises a gate dielectric layer provided between the insulating layer and the inner wall of the gate slit; the first conductive column comprises part of the insulating layer and part of the gate dielectric layer between one end of the first conductive column close to the semiconductor layer and the semiconductor layer. 4.The three-dimensional storage apparatus of claim 1, wherein The gate slit extends into the semiconductor layer, and the opening size of the gate slit in the semiconductor layer is smaller than the opening size of the gate slit in the first stack structure. 5.The three-dimensional storage apparatus of claim 1, wherein, The three-dimensional memory device further comprises a blocking layer located between the semiconductor layer and the first stack structure. 6.The three-dimensional memory device of claim 5, wherein, The channel structure extends into the semiconductor layer; the channel structure comprises a channel hole, and a blocking dielectric layer, a charge trapping layer, a tunnel dielectric layer and a channel layer arranged radially in sequence along the channel hole; the blocking dielectric layer, the charge trapping layer, the tunnel dielectric layer and the channel layer of the channel structure all penetrate the blocking layer; the channel layer is electrically connected with the semiconductor layer. 7.The three-dimensional memory device of claim 6, wherein, The channel layer of the channel structure extends into the semiconductor layer; and the part of the channel layer extending into the semiconductor layer is in contact with the semiconductor layer.

8. A three-dimensional memory device, comprising: The three-dimensional memory device comprises: a first semiconductor structure and a second semiconductor structure arranged in a stack; wherein the first semiconductor structure and the second semiconductor structure are connected together by bonding to form a bonding junction layer; the first semiconductor structure comprises: a first substrate; a peripheral circuit located on the first substrate; the second semiconductor structure comprises: a first stack structure located on the peripheral circuit of the bonding junction layer; a semiconductor layer located on the first stack structure; a gate slit penetrating the first stack structure; an insulating layer filling the gate slit, and a first conductive column provided in the insulating layer, the first conductive column comprising part of the insulating layer between one end of the first conductive column close to the semiconductor layer and the semiconductor layer; a channel structure penetrating the first stack structure. 9.The three-dimensional memory device of claim 8, wherein, The first stack structure comprises a plurality of gate layers and dielectric layers arranged at intervals; the first conductive column extends at least to a first plane; the first plane is a plane in which a surface of a first gate layer close to the semiconductor layer is located; the first gate layer is a gate layer closest to the semiconductor layer in the first stack structure.

10. The three-dimensional storage arrangement of claim 8, wherein, The three-dimensional memory device further includes a gate dielectric layer disposed between the insulating layer and the inner wall of the gate slit; and the first conductive column includes part of the insulating layer and part of the gate dielectric layer between the end of the first conductive column close to the semiconductor layer and the semiconductor layer. 11.The three-dimensional memory device of claim 8, wherein, The three-dimensional memory device further includes: a source contact in the semiconductor layer; an electrical lead structure on the semiconductor layer; the source contact is electrically connected to the electrical lead structure.

12. A method for manufacturing a three-dimensional storage device, comprising: The method includes: providing a base structure; the base structure includes a source sacrificial layer and a second stack structure on the source sacrificial layer; forming a channel structure through the second stack structure; forming a gate slit through the second stack structure; filling the gate slit with an insulating layer; forming a first conductive column in the insulating layer, the first conductive column including part of the insulating layer between the end of the first conductive column close to the source sacrificial layer and the source sacrificial layer; removing the source sacrificial layer; forming a semiconductor layer.

13. The method of claim 12, wherein, The gate slit extends into the source sacrificial layer; when forming the gate slit, the second stack structure and the source sacrificial layer are etched using etching parameters that change with time in a gradient manner, so that the opening size of the gate slit in the source sacrificial layer is smaller than the opening size of the gate slit in the second stack structure.

14. The method of claim 13, wherein, The method further includes: forming an initial insulating layer with a first height in the gate slit; etching the initial insulating layer to form an insulating layer with a second height, wherein the first height is greater than the second height.

15. The method of claim 12, wherein, The method further includes: forming a gate dielectric layer on the inner wall of the gate slit before filling the gate slit with the insulating layer; the first conductive column includes part of the insulating layer and part of the gate dielectric layer between the end of the first conductive column close to the semiconductor layer and the source sacrificial layer.

16. The method of claim 15, wherein, The method further includes: forming the source sacrificial layer on a second substrate; forming the second stack structure on the source sacrificial layer to obtain the base structure.

17. The method of claim 16, wherein, The second stack structure includes a plurality of gate sacrificial layers and dielectric layers arranged at intervals; The method further includes: removing the gate sacrificial layer before forming the gate dielectric layer; forming a gate layer at the position of the gate sacrificial layer after forming the gate dielectric layer and before filling the insulating layer to obtain a first stack structure.

18. The method of claim 17, wherein, The first conductive column extends at least to a first plane; the first plane is a plane in which a surface of a first gate layer close to the source sacrificial layer is located; the first gate layer is a gate layer closest to the source sacrificial layer among a plurality of gate layers.

19. The method of claim 17, wherein, The method further includes: forming a peripheral circuit on a first substrate; bonding the first substrate on which the peripheral circuit is formed and the second substrate on which the first conductive column is formed to form a bonding layer; removing the second substrate to expose the source sacrificial layer.

20. The method of claim 19, wherein, The method further includes: forming a source contact in the semiconductor layer; An electrical lead-out structure is formed on a second surface of the semiconductor layer; the source contact is electrically connected with the electrical lead-out structure; the first stack structure is located on a first surface of the semiconductor layer; the first surface and the second surface are opposite surfaces.

21. The method of claim 17, wherein, The method further comprises: Before forming the second stack structure, a barrier layer is formed on the source sacrificial layer.

22. The method of claim 21, wherein, The method further comprises: A channel hole is formed through the second stack structure, the barrier layer, and extending to the source sacrificial layer; A barrier medium layer, a charge trapping layer, a tunneling medium layer, and a channel layer are sequentially formed along the channel hole in a radial direction; After removing the source sacrificial layer, the barrier medium layer, the charge trapping layer, and the tunneling medium layer corresponding to the channel hole part in the source sacrificial layer are removed.

23. The method of claim 21, wherein, The method further comprises: A semiconductor material layer is formed on the surface of the barrier layer; The semiconductor material layer is subjected to a planarization treatment to form the semiconductor layer.

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