Pulse signal capture circuit and method
By using a fast charging circuit and a slow charging circuit in the pulse signal capture circuit combined with the design of a comparator, the problems of high circuit complexity and failure rate in the prior art are solved, and the effective capture of pulse signals and system stability are achieved. promote.
Patent Information
- Application Number
- CN202110729420.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-06-29
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2041-06-29
AI Technical Summary
The existing pulse signal capture method requires a large number of circuit devices, resulting in large volume, high loss, high failure rate and difficulty in after-sales maintenance.
The fast charging circuit and slow charging circuit are combined with the design of the comparator, and pulse signals are generated in the comparator through voltage and voltage difference of different time constants, simplifying the circuit structure, reducing circuit devices, and improving system reliability and stability.
It realizes effective capture of pulse signals, improves the reliability and stability of the system, simplifies circuit design, reduces volume and losses, reduces failure rate and cost, and simplifies after-sales maintenance.
Smart Images
Figure CN115549653B_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of electronic circuits, and in particular, to a pulse signal capturing circuit and method. Background Art
[0002] At present, the most commonly used method for pulse capture is to first use discrete components (i.e., basic circuit components with a single function, such as resistors, capacitors, diodes, transistors, etc.) for detection and conversion, and then output to the post-processing circuit for pulse signal capture. However, this method requires more circuit components, resulting in large size, high loss, high failure rate, and difficult after-sales maintenance. Summary of the invention
[0003] The purpose of the present invention is to provide a pulse signal capture circuit and method, which can effectively capture pulse signals and improve the reliability and stability of the system. It has a simple structure and does not require too many circuit components. Therefore, it is not only easy to implement, but also has a small size, low loss, low failure rate, and simple after-sales maintenance.
[0004] According to a first embodiment of the present disclosure, a pulse signal capture circuit is provided, comprising a fast charging circuit, a slow charging circuit and a comparator, wherein: an input end of the fast charging circuit is connected to an input signal, an output end of the fast charging circuit is connected to a first input end of the comparator, an input end of the slow charging circuit is connected to the input signal, an output end of the slow charging circuit is connected to a second input end of the comparator, and an output end of the comparator outputs a pulse signal when an abnormality occurs in the input signal.
[0005] Optionally, the fast charging circuit includes a first resistor, a first capacitor and a second capacitor, wherein: one end of the first resistor is connected to the input signal and the other end is connected to the first input terminal of the comparator, the first capacitor is connected between the first input terminal and the second input terminal of the comparator, and one end of the second capacitor is connected to the second input terminal of the comparator and the other end is grounded.
[0006] Optionally, the slow charging circuit comprises a second resistor and the second capacitor, wherein the second resistor is connected between the input signal and the second input terminal of the comparator.
[0007] Optionally, when the input signal is an AC signal, the filtering frequencies of the fast charging circuit and the slow charging circuit are filtering frequencies that can ensure that the time constants of the fast charging circuit and the slow charging circuit are set after the input signal is output normally.
[0008] Optionally, a filtering frequency of the fast charging circuit and the slow charging circuit is at least 10 times a frequency of the input signal.
[0009] Optionally, the sensitivity of the pulse signal capturing circuit is adjusted by the difference in time constants between the fast charging circuit and the slow charging circuit.
[0010] Optionally, the sensitivity is positively correlated with the difference in the time constant.
[0011] Optionally, when the first input terminal of the comparator is a positive input terminal and the second input terminal of the comparator is a negative input terminal, the pulse signal output by the output terminal of the comparator is a positive pulse signal.
[0012] Optionally, when the first input terminal of the comparator is a negative input terminal and the second input terminal of the comparator is a positive input terminal, the pulse signal output by the output terminal of the comparator is a negative pulse signal.
[0013] According to a second embodiment of the present disclosure, a pulse signal capturing method is provided, comprising: charging a fast charging circuit and a slow charging circuit by an input signal; comparing the output voltages of the fast charging circuit and the slow charging circuit by a comparator and outputting a pulse signal when an abnormality occurs in the input signal.
[0014] Optionally, when the input signal is an AC signal, the filtering frequencies of the fast charging circuit and the slow charging circuit are filtering frequencies that can ensure that the time constants of the fast charging circuit and the slow charging circuit are set after the input signal is output normally.
[0015] Optionally, the filtering frequency of the fast charging circuit and the slow charging circuit is at least 10 times the frequency of the input signal.
[0016] Optionally, the sensitivity of the pulse signal capturing circuit is adjusted by the difference in time constants between the fast charging circuit and the slow charging circuit.
[0017] By adopting the above technical solution, since the charging time constants of the fast charging circuit and the slow charging circuit are different, a voltage difference can be generated between the first input terminal and the second input terminal of the comparator. After the voltage difference is compared and processed by the comparator, a pulse signal can be output at the output terminal of the comparator. Therefore, the pulse signal capture circuit according to the embodiment of the present disclosure can effectively capture both low-frequency pulse signals and high-frequency pulse signals, thereby improving the reliability and stability of the system. Moreover, the structure is simple and does not require too many circuit components. It is not only easy to implement, but also has a small size, low loss, low cost, low failure rate, and simple after-sales maintenance.
[0018] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:
[0020] Figure 1 It is a schematic block diagram of a pulse signal capturing circuit according to an embodiment of the present disclosure.
[0021] Figure 2 It is a schematic circuit diagram of a pulse signal capturing circuit according to an embodiment of the present disclosure.
[0022] Figure 3 is a schematic circuit diagram of a pulse signal capture circuit that outputs a positive pulse signal according to an embodiment of the present disclosure.
[0023] Figure 4 It is a schematic waveform diagram of the captured positive pulse signal.
[0024] Figure 5 is a schematic circuit diagram of a pulse signal capture circuit that outputs a negative-going pulse signal according to an embodiment of the present disclosure.
[0025] Figure 6 It is a schematic waveform diagram of the captured negative pulse signal.
[0026] Figure 7 4 is a circuit test input waveform diagram of the rising edge pulse signal capture circuit according to the embodiment of the present disclosure.
[0027] Figure 8 4 is a circuit test output waveform diagram of the rising edge pulse signal capture circuit according to the embodiment of the present disclosure.
[0028] Fig. 9 It is a flow chart of a pulse signal capturing method according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0029] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.
[0030] Figure 1 FIG. 1 is a schematic block diagram of a pulse signal capture circuit according to an embodiment of the present disclosure. Figure 1As shown, the pulse signal capture circuit includes a fast charging circuit 10, a slow charging circuit 20 and a comparator 30, wherein: the input end of the fast charging circuit 10 is connected to the input signal Vin, the output end of the fast charging circuit 10 is connected to the first input end 1 of the comparator 30, the input end of the slow charging circuit 20 is connected to the input signal Vin, the output end of the slow charging circuit 20 is connected to the second input end 2 of the comparator 30, and the output end Vo of the comparator 30 outputs a pulse signal when an abnormality occurs in the input signal.
[0031] The pulse signal capture circuit can be applied to the industrial field, the automotive field, etc., and can capture the pulse signal generated when the state changes such as arc drawing, key resetting, and the closing and closing of electrical devices.
[0032] The pulse signal outputted from the output terminal Vo of the comparator 30 can be directly sent to the interrupt port or capture port of the micro-controlling unit (MCU) for judgment, and then shutdown or other operations are executed according to system requirements.
[0033] The above-mentioned input signal abnormality refers to the presence of a signal that deviates from the original normal input signal trajectory in the normal input signal, for example, a pulse signal is superimposed on the original input signal.
[0034] By adopting the above technical solution, since the charging time constants of the fast charging circuit 10 and the slow charging circuit 20 are different, a voltage difference can be generated between the first input terminal 1 and the second input terminal 2 of the comparator 30. After the voltage difference is compared and processed by the comparator 30, a pulse signal can be output at the output terminal Vo of the comparator 30. Therefore, the pulse signal capture circuit according to the embodiment of the present disclosure can effectively capture both low-frequency pulse signals and high-frequency pulse signals, thereby improving the reliability and stability of the system. In addition, the structure is simple and does not require too many circuit components. It is not only easy to implement, but also small in size, low in loss, low in cost, low in failure rate, and simple in after-sales maintenance.
[0035] Figure 2 FIG. 1 is a schematic circuit diagram of a pulse signal capture circuit according to an embodiment of the present disclosure. Figure 2 As shown, the fast charging circuit 10 includes a first resistor R1, a first capacitor C1 and a second capacitor C2, wherein: one end of the first resistor R1 is connected to the input signal Vin, and the other end is connected to the first input terminal 1 of the comparator 30, the first capacitor C1 is connected between the first input terminal 1 and the second input terminal 2 of the comparator 30, and one end of the second capacitor C2 is connected to the second input terminal 2 of the comparator 30, and the other end is grounded. Figure 2 The fast charging circuit 10 shown is an RC charging circuit with a time constant T1 = R1 * ((C1 + C2) / (C1 * C2)).
[0036] Continue to refer Figure 2 The slow charging circuit 20 includes a second resistor R2 and a second capacitor C2, wherein the second resistor R2 is connected between the input signal Vin and the second input terminal 2 of the comparator 30. Figure 2 The slow charging circuit 20 shown is an RC charging circuit with a time constant T2 = R2 * C2.
[0037] By adopting the above technical solution, since the first resistor R1, the first capacitor C1, and the second capacitor C2 constitute a fast charging circuit 10, and the second resistor R2 and the second capacitor C2 constitute a slow charging circuit 20, since the charging time constants of the fast charging circuit 10 and the slow charging circuit 20 are different, they can generate a voltage difference between the first input terminal 1 and the second input terminal 2 of the comparator 30. After the voltage difference is compared and processed by the comparator 30, a pulse signal can be output at the output terminal Vo of the comparator 30.
[0038] Figure 3 It is a schematic circuit diagram of a pulse signal capture circuit (also called a rising edge pulse signal capture circuit) that outputs a positive pulse signal according to an embodiment of the present disclosure. Figure 3 and Figure 2 The difference is that the first input terminal 1 of the comparator 30 is the positive input terminal, and the second input terminal 2 of the comparator 30 is the negative input terminal. Then, the output terminal of the fast charging circuit 10 is connected to the positive input terminal of the comparator 30, and the output terminal of the slow charging circuit 20 is connected to the negative input terminal of the comparator 30. Therefore, at the same time point, the fast charging terminal voltage (that is, the voltage at the first input terminal 1 of the comparator 30) must be higher than the slow charging terminal voltage (that is, the voltage at the second input terminal 2 of the comparator 30), and the comparator 30 outputs a high level, that is, a positive pulse signal, thereby realizing the capture of the positive pulse signal. Figure 4 As shown in the schematic diagram of the captured forward pulse signal waveform, the output pulse of the comparator 30 can be synchronized with the input forward signal, that is, the comparator 30 can synchronously output the forward pulse signal, that is, synchronously capture the rising edge signal of the input signal Vin.
[0039] Figure 5 : is a schematic circuit diagram of a pulse signal capture circuit (also called a falling edge pulse signal capture circuit) that outputs a negative-going pulse signal according to an embodiment of the present disclosure. The principle of capturing a negative-going pulse signal is similar to that of capturing a positive-going pulse signal, that is, in order to achieve the capture of a negative-going pulse signal, the first input terminal 1 of the comparator 30 is a negative input terminal, and the second input terminal 2 of the comparator 30 is a positive input terminal, so that the pulse signal outputted from the output terminal of the comparator 30 is a low level, that is, a negative-going pulse signal, thereby achieving the capture of a negative-going pulse signal. Figure 6As shown in the schematic diagram of the captured negative pulse signal waveform, the output pulse of the comparator 30 can be synchronized with the input negative signal, that is, the comparator 30 can synchronously output the negative pulse signal, that is, synchronously capture the falling edge signal of the input signal Vin.
[0040] for Figure 4 and Figure 6 The phenomenon that the output lags behind the input shown in FIG. 1 is determined by the inherent characteristics of the comparator 30. Figure 5 Take the falling edge pulse capture shown as an example. When the rising edge signal of the input signal Vin comes, the fast charge voltage at the negative input of the comparator is higher than the slow charge voltage at the positive input of the comparator. The comparator outputs a low level. The input signal Vin remains high so that the comparator always outputs a low level. When the falling edge of the input signal Vin comes, the fast charge voltage at the negative input of the comparator changes quickly, causing the slow charge voltage at the positive input of the comparator to be higher than the fast charge voltage at the negative input of the comparator, so the comparator outputs a high level. That is, when the input signal Vin is high, the comparator outputs a low level, and when the input signal Vin is low, the comparator outputs a high level, and the waveform has a lag. The hysteresis phenomenon of the positive pulse signal capture is similar in principle.
[0041] In some embodiments, the sensitivity of the pulse signal capture circuit is adjusted by the difference in the time constants of the fast charging circuit 10 and the slow charging circuit 20. The sensitivity is positively correlated with the difference in the time constants. The greater the difference in the time constants, the higher the capture sensitivity. Therefore, by adjusting the time constants of the fast charging circuit 10 and the slow charging circuit 20, the sensitivity of the pulse signal capture circuit to the frequency can be changed to achieve the capture of pulses of different frequencies, and even narrow pulses with higher frequencies can be effectively captured, thereby improving the accuracy of capture detection, improving the reliability and stability of the system, and the circuit is simple, easy to implement, and has high circuit consistency, which can achieve standardized production and reduce design costs.
[0042] In some embodiments, when the input signal Vin is an AC signal, the filtering frequency of the fast charging circuit 10 and the slow charging circuit 20 is a filtering frequency that can ensure that the time constants of the fast charging circuit 10 and the slow charging circuit 20 are set after the input signal Vin is normally output. That is, the frequency of the input signal Vin also determines the parameter characteristics of the RC charging circuit, so it is necessary to ensure that the comparator action cannot be triggered when the input signal Vin is input, that is, the filtering of the RC charging circuit (that is, the fast charging circuit 10 and the slow charging circuit 20) cannot filter out the normal input signal waveform. For this reason, it can usually be required that the filtering frequency of the fast charging circuit 10 and the slow charging circuit 20 is at least 10 times the frequency of the input signal Vin, so that the time constants of the fast charging circuit 10 and the slow charging circuit 20 can be set after the input signal Vin is normally output to adjust the capture sensitivity. That is, by using the characteristic of the capacitor passing high frequencies and blocking low frequencies, the RC time constant is adjusted, so that the low-frequency signal is prevented from entering the comparator, so that the comparison action of the comparator cannot be triggered, but only the pulse signal can enter the comparator 30.
[0043] Figure 7 is a circuit test input waveform diagram of a rising edge pulse signal capture circuit according to an embodiment of the present disclosure, and Figure 8 This is a circuit test output waveform diagram of the rising edge pulse signal capture circuit according to the embodiment of the present disclosure. In order to implement this test, the comparator 30 uses LM393, the resistance value is selected as R1=R2=R3=1KΩ, the capacitance value is selected as C1=2nF, C2=3.3nF, then, the time constant T1 of the fast charging circuit 10 is T1=R1*((C1+C2) / (C1*C2))=1KΩ*((2nF+3.3nF) / (2nF*3.3nF))=0.8μs, the time constant T2 of the slow charging circuit 20 is T2=R2*C2=1KΩ*3.3nF=3.3μs, and the ratio of the time constants of the fast charging circuit 10 and the slow charging circuit 20 is T1 / T2=0.24. After actual circuit testing, pulses with a frequency of 1KHZ-100KHZ, an amplitude of 50mV, and a duty cycle of 1% can be captured.
[0044] Fig. 9 FIG. 1 is a flow chart of a pulse signal capturing method according to an embodiment of the present disclosure. Fig. 9 As shown, the method includes the following steps S91 to S92.
[0045] In step S91, the fast charging circuit and the slow charging circuit are charged by the input signal;
[0046] In step S92, the comparator compares the output voltages of the fast charging circuit and the slow charging circuit and outputs a pulse signal when an abnormality occurs in the input signal.
[0047] By adopting the above technical solution, since the charging time constants of the fast charging circuit and the slow charging circuit are different, a voltage difference can be generated between the two input terminals of the comparator. After the voltage difference is compared and processed by the comparator, a pulse signal can be output at the output terminal of the comparator. Therefore, the pulse signal capture method according to the embodiment of the present disclosure can effectively capture both low-frequency pulse signals and high-frequency pulse signals, thereby improving the reliability and stability of the system. Moreover, the structure is simple and does not require too many circuit devices. It is not only easy to implement, but also has a small size, low loss, low cost, low failure rate, and simple after-sales maintenance.
[0048] Optionally, when the input signal is an AC signal, the filtering frequencies of the fast charging circuit and the slow charging circuit are filtering frequencies that can ensure that the time constants of the fast charging circuit and the slow charging circuit are set after the input signal is output normally.
[0049] Optionally, the filtering frequency of the fast charging circuit and the slow charging circuit is at least 10 times the frequency of the input signal.
[0050] Optionally, the sensitivity of the pulse signal capturing circuit is adjusted by the difference in time constants between the fast charging circuit and the slow charging circuit.
[0051] Optionally, the sensitivity is directly correlated to the magnitude of the difference in time constants.
[0052] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings; however, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, a variety of simple modifications can be made to the technical solution of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.
[0053] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.
[0054] In addition, various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.
Claims
1. A pulse signal capture circuit, characterized in that: It includes a fast charging circuit, a slow charging circuit and a comparator, wherein: The input end of the fast charging circuit is connected to the input signal, the output end of the fast charging circuit is connected to the first input end of the comparator, the input end of the slow charging circuit is connected to the input signal, the output end of the slow charging circuit is connected to the second input end of the comparator, and the output end of the comparator outputs a pulse signal when an abnormality occurs in the input signal; The fast charging circuit and the slow charging circuit have different charging time constants, which results in a voltage difference between the first input terminal and the second input terminal of the comparator.
2. The pulse signal capturing circuit according to claim 1, characterized in that: The fast charging circuit comprises a first resistor, a first capacitor and a second capacitor, wherein: One end of the first resistor is connected to the input signal, and the other end is connected to the first input end of the comparator. The first capacitor is connected between the first input end and the second input end of the comparator. One end of the second capacitor is connected to the second input end of the comparator, and the other end is grounded.
3. The pulse signal capturing circuit according to claim 2, characterized in that: The slow charging circuit includes a second resistor and the second capacitor, wherein the second resistor is connected between the input signal and the second input terminal of the comparator.
4. The pulse signal capturing circuit according to any one of claims 1 to 3, characterized in that: When the input signal is an AC signal, the filtering frequencies of the fast charging circuit and the slow charging circuit are filtering frequencies that can ensure that the time constants of the fast charging circuit and the slow charging circuit are set after the input signal is normally output.
5. The pulse signal capturing circuit according to claim 4, characterized in that: The filtering frequency of the fast charging circuit and the slow charging circuit is at least 10 times the frequency of the input signal.
6. The pulse signal capturing circuit according to any one of claims 1 to 3, characterized in that: The sensitivity of the pulse signal capturing circuit is adjusted by the difference between the time constants of the fast charging circuit and the slow charging circuit.
7. The pulse signal capturing circuit according to claim 6, characterized in that: The sensitivity is positively correlated with the difference in the time constants.
8. The pulse signal capturing circuit according to any one of claims 1 to 3, characterized in that: In a case where the first input terminal of the comparator is a positive input terminal and the second input terminal of the comparator is a negative input terminal, the pulse signal outputted by the output terminal of the comparator is a positive pulse signal.
9. The pulse signal capturing circuit according to any one of claims 1 to 3, characterized in that: In a case where the first input terminal of the comparator is a negative input terminal and the second input terminal of the comparator is a positive input terminal, the pulse signal outputted by the output terminal of the comparator is a negative pulse signal.
10. A pulse signal capturing method, characterized in that: include: The fast charging circuit and the slow charging circuit are charged by an input signal, wherein the input end of the fast charging circuit is connected to the input signal, the output end of the fast charging circuit is connected to the first input end of the comparator, the input end of the slow charging circuit is connected to the input signal, and the output end of the slow charging circuit is connected to the second input end of the comparator; The comparator compares the output voltages of the fast charging circuit and the slow charging circuit and outputs a pulse signal when an abnormality occurs in the input signal; wherein, the fast charging circuit and the slow charging circuit have different charging time constants, thereby generating a voltage difference between the first input terminal and the second input terminal of the comparator.