A current source compensation circuit for a cascaded GaN current reduction sampling resistor

Abstract

The application discloses a kind of current source compensation circuits of cascade GaN reduces current sampling resistance, including current source module, current sampling chip and GaN cascade module, wherein, cascade module includes GaN power switch tube and power resistance;Current source module includes the first switching diode, the first triode, the first resistance and output device arranged in series, current source module further includes the second resistance, voltage reference source, one end of second resistance is connected with the cathode of first switching diode, the collector of first triode, the other end of second resistance, the cathode of voltage reference source is connected with the base of first triode, the anode of voltage reference source is connected with the connecting point between first resistance and output device;The output end of current source module is connected with the sampling pin of current sampling chip, and the output end of current sampling chip is connected with cascade module.The application reduces the resistance value of power resistance, reduces its power loss, improves the conversion efficiency of overall circuit.

Description

Technical Field

[0001] This invention relates to the field of semiconductor circuits, and more particularly to a cascaded GaN current source compensation circuit for reducing current sampling resistance. Background Technology

[0002] The control modes in energy storage power supplies, bidirectional inverters, inverters, DC-DC power supplies, and AC-DC power supplies are mostly current-driven. This requires sampling the current flowing through the power devices. The high efficiency of the power supply largely depends on the power devices. Due to the continuous updates in power semiconductor technology, the emergence of the third-generation semiconductor GaN has made it possible for power supplies to be efficient and small in size. However, for high-power power supplies, the power consumption of the series current sampling resistor of the cascaded GaN power transistors has become one of the obstacles to achieving efficient and green power supplies.

[0003] The current common practice is to connect a power resistor and a power switch in series. This power switch and power resistor are connected in series in the main power circuit. When the input voltage is low at 90V, the current flowing through the power switch and power resistor is very large, so the power loss in these two devices also increases accordingly. This also places very high demands on the rated power of the sampling resistor. Furthermore, the increased size of the sampling resistor will affect the conversion efficiency of the entire system, seriously hindering the design concept of high efficiency, green environmental protection, and high power density.

[0004] The above background information is provided only to assist in understanding the inventive concept and technical solution of this invention. It does not necessarily belong to the prior art of this patent application, nor does it necessarily provide technical teaching. In the absence of clear evidence that the above information was disclosed before the filing date of this patent application, the above background information should not be used to evaluate the novelty and inventiveness of this application. Summary of the Invention

[0005] The purpose of this invention is to provide a cascaded GaN current source compensation circuit that reduces the current sampling resistance, thereby improving the conversion efficiency of the overall circuit system.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A cascaded GaN current source compensation circuit for reducing current sampling resistance includes a current source module, a current sampling chip, and a GaN cascade module, wherein the GaN cascade module includes a GaN power switch and a power resistor connected in series in the main power circuit.

[0008] The current source module includes a first switching diode, a first transistor, a first resistor, and an output device, which are connected in series between its input and output terminals. The current source module also includes a second resistor and a voltage reference source. One end of the second resistor is connected to the negative terminal of the first switching diode and the collector of the first transistor. The other end of the second resistor and the cathode of the voltage reference source are both connected to the base of the first transistor. The anode of the voltage reference source is connected to the connection point between the first resistor and the output device.

[0009] The output terminal of the current source module is connected to the sampling pin of the current sampling chip for current compensation, and the output terminal of the current sampling chip is connected to the GaN cascade module.

[0010] Furthermore, following any one or a combination of the aforementioned technical solutions, the connection between the output terminal of the current sampling chip and the GaN cascade module includes:

[0011] The output terminal of the current sampling chip is connected to the gate of the GaN power switch in sequence through the second switching diode and the inductor, and is connected to the power resistor in sequence through the second switching diode, the third resistor and the second transistor. The output terminal of the current sampling chip is connected to the base of the second transistor through the fourth resistor. The emitter of the second transistor is connected to one end of the third resistor, and its collector is connected to the non-grounded end of the power resistor.

[0012] Furthermore, following any or a combination of the aforementioned technical solutions, a parallel branch of a fifth resistor and a first capacitor is provided between the output terminal of the current sampling chip and the GaN cascade module. One end of the parallel branch is connected to the output terminal of the current sampling chip, and the other end is connected to the positive terminal of the second switching diode. The negative terminal of the second switching diode is connected to the inductor and the third resistor.

[0013] Furthermore, following any or a combination of the aforementioned technical solutions, the sampling pin of the current sampling chip is connected to the non-grounded terminal of the power resistor via a sixth resistor, and connected to the grounded terminal of the power resistor via a second capacitor, wherein the capacitance of the second capacitor is less than the capacitance of the first capacitor.

[0014] Furthermore, based on any one or a combination of the aforementioned technical solutions, the first transistor is an NPN transistor, and the second transistor is a PNP transistor.

[0015] Furthermore, following any one or a combination of the aforementioned technical solutions, the output device is a resistor; or,

[0016] The output device is a switching diode, and its positive terminal is connected to the anode of the voltage reference source.

[0017] Furthermore, following any or a combination of the aforementioned technical solutions, the input terminal of the current source module is connected to the VCC terminal that powers the current sampling chip, and the output device is a switching diode, the positive terminal of which is connected to the anode of the voltage reference source.

[0018] The current sampling chip is configured to reduce its operating frequency to the operating frequency when the current source module with current compensation is added, after the current source module is added.

[0019] Furthermore, following any one or a combination of the aforementioned technical solutions, the input terminal of the current source module is connected to the VCC terminal that powers the current sampling chip, and the output device is a resistor, which is configured to adjust the operating frequency of the current sampling chip by adjusting the resistance value of the output device while keeping the feedback voltage of the sampling pin of the current sampling chip constant.

[0020] Furthermore, based on any or a combination of the aforementioned technical solutions, the cascaded GaN current source compensation circuit for reducing current sampling resistance further includes a rectifier circuit module and a series branch of voltage divider resistors. The rectifier circuit module is configured to convert the input AC power into DC power. One end of the series branch of voltage divider resistors is connected to the input terminal of the current source module, and the other end is connected to the rectifier circuit module and the main power circuit, respectively.

[0021] The output device is a resistor, and the multiple resistors in the series branch of the voltage divider resistor are configured to have consistent overcurrent protection points when inputting high-voltage AC and low-voltage AC.

[0022] Furthermore, following any one or a combination of the aforementioned technical solutions, the input terminal of the current source module is connected to the GATE node at the output terminal of the current sampling chip, so that the current source compensation circuit operates in continuous mode.

[0023] The beneficial effects of the technical solution provided by this invention are as follows: it can reduce the resistance value of the power resistor, reduce the power resistor loss, and thus improve the conversion efficiency of the overall circuit. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A schematic diagram of an overall system circuit including a current source compensation circuit is provided for an exemplary embodiment of the present invention;

[0026] Figure 2 for Figure 1 A schematic diagram of a local current source compensation circuit;

[0027] Figure 3 This is a schematic diagram of the simulation results of the sampling terminal voltage waveform without the current source compensation circuit.

[0028] Figure 4 A schematic diagram of the simulation results of the sampling terminal voltage waveform under the condition of the current source compensation circuit;

[0029] Figure 5 for Figure 2 A schematic diagram of the waveform simulation results of the output current at the sampling terminal after point A is connected to the GATE node;

[0030] Figure 6 To be Figure 5 A schematic diagram of the simulation result of a positive sawtooth wave with a plateau voltage obtained by adding the waveform of the waveform to the sampled current waveform of the power resistor.

[0031] The reference numerals in the figures include: 101-GaN power switch, 102-power resistor, 201-first switching diode, 202-first transistor, 203-first resistor, 204-output device, 205-second resistor, 206-voltage reference source, 301-second switching diode, 302-inductor, 303-third resistor, 304-fourth resistor, 305-fifth resistor, 306-second transistor, 307-first capacitor, 4-current sampling chip, 401-sixth resistor, and 402-second capacitor. Detailed Implementation

[0032] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0034] The emergence of third-generation semiconductors, especially cascaded GaN power devices, has replaced traditional MOSFETs to address power losses in power semiconductors, making it possible for energy storage power supplies to achieve high efficiency, environmental friendliness, and high power density. However, the power losses, high rated power, and large size of the power resistors connected in series with the power devices remain challenges. For the power switching transistors and power resistors connected in series in the main power circuit, when the input voltage is a low 90V, the current flowing through them is very large, resulting in significant power losses in these two devices. This places high demands on the rated power of the sampling resistor, and the size of the sampling resistor also increases accordingly. The purpose of this invention is to reduce the resistance value of the power resistor, i.e., the current sampling resistor, to achieve the technical effect of reducing its power losses and rated power.

[0035] In one embodiment of the present invention, a cascaded GaN current source compensation circuit for reducing current sampling resistance is provided, including a current source module, a current sampling chip 4, and a GaN cascade module, such as... Figure 2 As shown, the GaN cascade module includes a GaN power switch 101 and a power resistor 102 connected in series in the main power circuit;

[0036] The current source module includes a first switching diode 201, a first transistor 202, a first resistor 203, and an output device 204, which are connected in series between its input and output terminals. The current source module also includes a second resistor 205 and a voltage reference source 206, such as a TL431 voltage reference source. One end of the second resistor 205 is connected to the cathode of the first switching diode 201 and the collector of the first transistor 202. The other end of the second resistor 205 and the cathode of the voltage reference source 206 are both connected to the base of the first transistor 202. The first transistor 202 is specifically an NPN transistor. The anode of the voltage reference source 206 is connected to the connection point between the first resistor 203 and the output device 204. The reference pin of the voltage reference source 206 is connected to the connection point between the emitter of the first transistor 202 and the first resistor 203.

[0037] The output terminal of the current source module is connected to the sampling pin of the current sampling chip 4 for current compensation, and the output terminal of the current sampling chip 4 is connected to the GaN cascade module.

[0038] See Figure 2 The output terminal of the current sampling chip 4 is connected to the GaN cascade module, including:

[0039] The output terminal of the current sampling chip 4 is connected to the gate of the GaN power switch 101 in sequence through the second switching diode 301 and the inductor 302, and is connected to the power resistor 102 in sequence through the second switching diode 301, the third resistor 303 and the second transistor 306. The output terminal of the current sampling chip 4 is connected to the base of the second transistor 306 through the fourth resistor 304. The emitter of the second transistor 306 is connected to one end of the third resistor 303, and its collector is connected to the non-grounded end of the power resistor 102. The second transistor 306 is specifically a PNP transistor.

[0040] In one specific embodiment, a parallel branch of a fifth resistor 305 and a first capacitor 307 is provided between the output terminal of the current sampling chip 4 and the GaN cascade module. One end of the parallel branch is connected to the output terminal of the current sampling chip 4, and the other end is connected to the positive terminal of the second switching diode 301. The negative terminal of the second switching diode 301 is connected to the inductor 302 and the third resistor 303. The sampling pin of the current sampling chip 4 is connected to the non-grounded terminal of the power resistor 102 through a sixth resistor 401, and is connected to the grounded terminal of the power resistor 102 through a second capacitor 402, wherein the capacitance of the second capacitor 402 is smaller than the capacitance of the first capacitor.

[0041] The current source module compensates the current of the sampling pin (CS pin) of the current sampling chip 4, reducing the resistance of the power resistor 102 and its rated power, thereby reducing power loss and improving system conversion efficiency. Following the current source compensation circuit described above, the current sampling resistor (i.e....) can be reduced. Figure 2 The resistance of the power resistor 102 is reduced to 1 / 3 of its original value without the current source compensation circuit. The output current of the current source module is calculated using the following formula:

[0042] V ref =2.5V, R9 is the resistance value of the first resistor 203.

[0043] The magnitude of the compensation current can be defined by changing the resistance value of the first resistor 203; while the second resistor 205 provides a bias voltage to the first transistor 202 so that the first transistor 202 operates in the linear region.

[0044] For the output device 204, different devices have different functions. The following describes various embodiments in conjunction with different wiring methods of the input terminal of the current source module:

[0045] Example 1

[0046] The input terminal of the current source module, i.e., node A, is connected to the VCC terminal that powers the current sampling chip 4. Figure 2 The output device 204 at position Z3 is a switching diode, and its positive terminal is connected to the anode of the voltage reference source 206.

[0047] Reducing the resistance value of the current sampling resistor at the same operating frequency lowers its rated power, reduces power loss, and improves system conversion efficiency. For example... Figure 2 In the circuit, the switching diode is located at position Z3. At this point, the compensated current value is at its maximum. The current sampling chip 4 detects the highest potential at the CS pin and considers it to be under maximum load. Therefore, the current sampling chip 4 will increase its operating frequency to adapt to the current load. If a current source circuit with current compensation is added, the value of the power resistor 102 can be reduced, and the potential of the CS pin can be adjusted to match the sampling voltage of the original power resistor value. This allows the operating frequency of the current sampling chip 4 to be reduced to the operating frequency without the current source circuit. This reduces the power loss of the power resistor 102, lowers its rated power, and reduces its size, achieving miniaturization. Taking a 65W flyback circuit as an example, the peak current at a 90V input is:

[0048]

[0049] I mos_peak =2I P_avg =2.113A;

[0050] The peak power dissipated in power resistor 102 is:

[0051] Without adding a current source circuit for current compensation, the resistance of power resistor 102 is R. s =0.75Ω,

[0052] P loss =I mos_peak 2 ×R s =3.347W;

[0053] With the current source circuit for current compensation added in this embodiment, if the resistance of power resistor 102 is reduced to 1 / 3, its power consumption is:

[0054] The resistance of power resistor 102 after the resistance is reduced is R. s =0.25Ω,

[0055] P loss =I mos_peak 2 ×R s =1.116W;

[0056] The calculations above show that the peak power consumption of power resistor 102 is reduced to 1.116W. Therefore, a single 1.5W resistor can be used. However, with the original circuit design (a current source circuit without current compensation), three 1.5W resistors in parallel are required. To demonstrate the reduction in peak power consumption, a simulation of the current source compensation circuit can be performed using a 66W (22V / 3A) power supply from the MPS (Multi-Purpose Systems) HFC0300 control chip. The results are as follows... Figure 3 and Figure 4 As shown, Figure 3 This corresponds to the case where the CS pin is not equipped with a current compensation circuit. Curve ① is the voltage curve of the COMP pin of the current sampling chip 4, and curve ② is the voltage curve of the CS pin of the current sampling chip 4.

[0057] Figure 4 This corresponds to the case where a current compensation circuit is added to the CS pin. Curve ③ is the voltage curve of the COMP pin of the current sampling chip 4, and curve ④ is the voltage curve of the CS pin of the current sampling chip 4.

[0058] contrast Figure 3 and Figure 4 Simulation results of the voltage curve of the CS pin show that, in the feedback quantity V COMPUnder the condition of equality, V without compensation circuit CS The peak voltage is 575.30627mV, and the V with compensation circuit is... CS The peak voltage is 304.1388mV, where the peak voltage is defined as the difference between the high peak value and the low peak value.

[0059] With a fixed feedback amount, and without compensation for the CS pin:

[0060] The transformer's inductance L1 = 818 μH; R s =0.150Ω; V cs =0.5753V;

[0061] Then the transformer (see Figure 1 The energy stored in the transformer during one cycle of the GaN switch being turned on is:

[0062]

[0063] With a fixed feedback amount and compensation for the CS pin:

[0064] The transformer's inductance L1 = 818 μH; R s =0.080Ω; V cs =0.30413V;

[0065] Then the transformer (see Figure 1 The energy stored in the transformer during one cycle of the GaN switch being turned on is:

[0066]

[0067] Figure 1 This is merely a schematic diagram of the overall circuit architecture with a current source compensation circuit and should not be construed as limiting the scope of protection of this invention.

[0068] Comparing the above situations, it can be seen that the energy stored in the transformer in one cycle is almost equal, and the current flowing through the transformer and the GaN power switch 101 is equal. However, the resistance value Rs of the power resistor 102 is reduced by almost half, so the loss of the power resistor 102 is also reduced by almost half, thereby improving the overall efficiency of the power supply.

[0069] Example 2

[0070] Changing the operating frequency with a fixed feedback amount facilitates reverse engineering.

[0071] Replacing the component at Z3 in the current source compensation circuit of Example 1 with a resistor can change the operating frequency of the circuit. The principle is as follows:

[0072] Among them, V CS I represents the voltage at the CS pin of current sampling chip 4. out R7 represents the output current of the CS pin of current sampling chip 4, and R7 represents the resistance value of the sixth resistor 401. s R is the resistance value of power resistor 102. 12 Let Z3 be the resistance value. For conventional current-mode control integrated circuits (ICs), frequency adjustment is achieved not only through the feedback pin FB but also through the potential change of the current sampling pin CS. As can be seen from the above formula, for R... 12 Adjusting the size allows you to adjust V. CS Given a constant feedback voltage, the value of R can be adjusted. 12 This is to adjust the operating frequency.

[0073] In the usual design process, sometimes you encounter components that are already designed, such as the transformer inductance which is set to a fixed value. In such cases, you can only perform reverse design. Since the transformer inductance is determined, you can change the resistance R of the power resistor 102. s Determining the operating frequency is very limited and may result in R... s The resistance is very high, and R may also appear. s When the resistance is extremely small, if R s If the resistance value is large, power consumption issues may occur. If the resistor R... s If the current is too small, the sampled current signal may be weak and easily interfered with. Both of these situations can cause the transformer's operating state to become unbalanced. In this case, adding a current source compensation circuit can help by changing R. 12 The operating frequency is adjusted by changing the resistance value to optimize the transformer's operation.

[0074] Example 3

[0075] like Figure 2 As shown, the current source compensation circuit also includes a rectifier circuit module and a series branch of voltage divider resistors. The rectifier circuit module is configured to convert the input AC power into DC power, and the series branch of voltage divider resistors is equipped with R... 16 R 17 R 33 One end of the voltage divider resistor series branch ( Figure 2 Point B on the current source module ( ) and the input terminal of the current source module ( ) Figure 2 Connect point A on the circuit, and connect the other end of the circuit to the rectifier circuit module and the main power circuit respectively. Figure 2 The output device 204 at position Z3 is a resistor R. 12 .

[0076] This circuit architecture allows the power supply to maintain consistent overcurrent protection points under both high and low input voltage conditions. The principle is as follows: The circuit consists of R... 16 R 17 R 33 First switching diode 201, first transistor 202, second resistor 205, first resistor 203, R 12 Power resistor 102. The rectified high voltage passes through resistor R. 16 R 17 R 33 After voltage division, the voltage is applied to the current source compensation circuit. As the AC input voltage changes, the rectified voltage also changes, and the voltage applied to the current source compensation circuit changes accordingly: when the input voltage is low, R... 16 R 17 R 33 The voltage supplied to the current source compensation circuit by the voltage divider is low, and the compensation voltage to the CS pin of the current sampling chip 4 via the current compensation circuit is also low, resulting in a small compensation amount; when the input voltage is high, R 16 R 17 R 33 The voltage supplied to the current compensation circuit by the voltage divider is high, resulting in a high compensation voltage at the CS pin of the current sampling chip 4 via the current source compensation circuit. This leads to a large compensation amount. As the load increases, when the voltage at the CS pin of the current sampling chip 4 exceeds a certain limit, it enters a protection state. This can be achieved by adjusting R... 16 R 17 R 33 The size and compensation amount of the current source compensation circuit are adjusted to achieve consistency of the overcurrent protection point under high voltage and low voltage AC input.

[0077] Example 4

[0078] The input terminal of the current source module ( Figure 2 Point A on the current sampling chip 4 is connected to the GATE node at the output terminal. Figure 2 The GATE function in the circuit can change the operating mode of the circuit. The principle is as follows:

[0079] Figure 2 When node A and node GATE are connected, the gate drive pulse waveform becomes a sawtooth wave after passing through the current source compensation circuit. The waveform of the simulation circuit is as follows: Figure 5 The output current I of the current source compensation circuit can be seen from the figure. CS The peak value is 273.35672uA, and this waveform is an inverted sawtooth wave. The waveform of power resistor 102 is a positive sawtooth wave. Adding these two waveforms together forms a positive sawtooth wave with a plateau voltage. The simulation results are as follows. Figure 6 .

[0080] From the above V CSJudging from the waveform, the flyback circuit has entered CCM (continuous cycle mode), as shown below. Figure 3 As shown, without current source compensation for the CS pin, its current waveform is a sawtooth wave without a plateau voltage. In this case, the circuit operates in DCM (Discontinuous Computation Mode). That is, by reducing the sampling resistor and adding a current source compensation circuit, the circuit can transition from discontinuous mode to continuous mode. In continuous mode, due to the transformer's connection to the primary power switch t... off The energy is not completely released within a short time, so the conversion efficiency of the entire system is also high in this mode.

[0081] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0082] The above description is only a specific embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A cascaded GaN current source compensation circuit for reducing current sampling resistance, characterized in that, It includes a current source module, a current sampling chip (4) and a GaN cascade module, wherein the GaN cascade module includes a GaN power switch (101) and a power resistor (102) connected in series in the main power circuit; The current source module includes a first switching diode (201), a first transistor (202), a first resistor (203), and an output device (204) connected in series between its input and output terminals. The current source module also includes a second resistor (205) and a voltage reference source (206). One end of the second resistor (205) is connected to the negative terminal of the first switching diode (201) and the collector of the first transistor (202). The other end of the second resistor (205) and the cathode of the voltage reference source (206) are both connected to the base of the first transistor (202). The anode of the voltage reference source (206) is connected to the connection point between the first resistor (203) and the output device (204). The reference pin of the voltage reference source (206) is connected to the connection point between the first transistor (202) and the first resistor (203); The output terminal of the current source module is the output terminal of the output device (204), which is connected to the sampling pin of the current sampling chip (4) for current compensation, and the magnitude of the compensation current is defined by changing the resistance value of the first resistor (203); the output terminal of the current sampling chip (4) is connected to the GaN cascade module, including: the output terminal of the current sampling chip (4) is connected to the gate of the GaN power switch (101) in sequence through the second switching diode (301) and the inductor (302), and is connected to the power resistor (102) in sequence through the second switching diode (301), the third resistor (303) and the second transistor (306), and the output terminal of the current sampling chip (4) is connected to the base of the second transistor (306) through the fourth resistor (304), the emitter of the second transistor (306) is connected to one end of the third resistor (303), and its collector is connected to the non-grounded end of the power resistor (102); The input terminal of the current source module is the positive terminal of the first switching diode (201), which is connected to the VCC terminal that supplies power to the current sampling chip (4). The output device (204) is a resistor, which is configured to adjust the operating frequency of the current sampling chip (4) by adjusting the resistance value of the output device (204) when the feedback voltage of the sampling pin of the current sampling chip (4) remains unchanged; or, the output device (204) is a switching diode, whose positive terminal is connected to the anode of the voltage reference source (206), and the current sampling chip (4) is configured to control the operating frequency of the current sampling chip (4) to decrease to the operating frequency when the current source module without the current source module is added after the current source module with current compensation is added.

2. The cascaded GaN current source compensation circuit for reducing current sampling resistance according to claim 1, characterized in that, The output terminal of the current sampling chip (4) and the GaN cascade module are further provided with a parallel branch of a fifth resistor (305) and a first capacitor (307). One end of the parallel branch is connected to the output terminal of the current sampling chip (4), and the other end is connected to the positive terminal of the second switching diode (301). The negative terminal of the second switching diode (301) is connected to the inductor (302) and the third resistor (303).

3. The cascaded GaN current source compensation circuit for reducing current sampling resistance according to claim 2, characterized in that, The sampling pin of the current sampling chip (4) is connected to the non-grounded terminal of the power resistor (102) through the sixth resistor (401), and is connected to the grounded terminal of the power resistor (102) through the second capacitor (402), wherein the capacitance of the second capacitor (402) is less than the capacitance of the first capacitor.

4. The cascaded GaN current source compensation circuit for reducing current sampling resistance according to claim 1, characterized in that, The first transistor (202) is an NPN transistor, and the second transistor (306) is a PNP transistor.

5. A cascaded GaN current source compensation circuit for reducing current sampling resistance, characterized in that, It includes a current source module, a current sampling chip (4), a GaN cascade module, a rectifier circuit module and a series branch of voltage divider resistors, wherein the rectifier circuit module is configured to convert the input AC power into DC power, and the GaN cascade module includes a GaN power switch (101) and a power resistor (102) connected in series in the main power circuit. The current source module includes a first switching diode (201), a first transistor (202), a first resistor (203), and an output device (204) connected in series between its input and output terminals. The current source module also includes a second resistor (205) and a voltage reference source (206). One end of the second resistor (205) is connected to the negative terminal of the first switching diode (201) and the collector of the first transistor (202). The other end of the second resistor (205) and the cathode of the voltage reference source (206) are both connected to the base of the first transistor (202). The anode of the voltage reference source (206) is connected to the connection point between the first resistor (203) and the output device (204). The reference pin of the voltage reference source (206) is connected to the connection point between the first transistor (202) and the first resistor (203); The output terminal of the current source module is the output terminal of the output device (204), which is connected to the sampling pin of the current sampling chip (4) for current compensation, and the magnitude of the compensation current is defined by changing the resistance value of the first resistor (203); the output terminal of the current sampling chip (4) is connected to the GaN cascade module, including: the output terminal of the current sampling chip (4) is connected to the gate of the GaN power switch (101) in sequence through the second switching diode (301) and the inductor (302), and is connected to the power resistor (102) in sequence through the second switching diode (301), the third resistor (303) and the second transistor (306), and the output terminal of the current sampling chip (4) is connected to the base of the second transistor (306) through the fourth resistor (304), the emitter of the second transistor (306) is connected to one end of the third resistor (303), and its collector is connected to the non-grounded end of the power resistor (102); The input terminal of the current source module is the positive terminal of the first switching diode (201), which is connected to one end of the series branch of the voltage divider resistor. The other end of the series branch of the voltage divider resistor is connected to the rectifier circuit module and the main power circuit respectively. The output device (204) is a resistor, which is configured to adjust the operating frequency of the current sampling chip (4) by adjusting the resistance value of the output device (204) when the feedback voltage of the sampling pin of the current sampling chip (4) remains unchanged. The multiple resistors in the series branch of the voltage divider resistor are configured to have consistency of overcurrent protection points when inputting high voltage AC and low voltage AC.

6. A cascaded GaN current source compensation circuit for reducing current sampling resistance, characterized in that, It includes a current source module, a current sampling chip (4) and a GaN cascade module, wherein the GaN cascade module includes a GaN power switch (101) and a power resistor (102) connected in series in the main power circuit; The current source module includes a first switching diode (201), a first transistor (202), a first resistor (203), and an output device (204) connected in series between its input and output terminals. The current source module also includes a second resistor (205) and a voltage reference source (206). One end of the second resistor (205) is connected to the negative terminal of the first switching diode (201) and the collector of the first transistor (202). The other end of the second resistor (205) and the cathode of the voltage reference source (206) are both connected to the base of the first transistor (202). The anode of the voltage reference source (206) is connected to the connection point between the first resistor (203) and the output device (204). The reference pin of the voltage reference source (206) is connected to the connection point between the first transistor (202) and the first resistor (203); The output terminal of the current source module is the output terminal of the output device (204), which is connected to the sampling pin of the current sampling chip (4) for current compensation, and the magnitude of the compensation current is defined by changing the resistance value of the first resistor (203); the output terminal of the current sampling chip (4) is connected to the GaN cascade module, including: the output terminal of the current sampling chip (4) is connected to the gate of the GaN power switch (101) in sequence through the second switching diode (301) and the inductor (302), and is connected to the power resistor (102) in sequence through the second switching diode (301), the third resistor (303) and the second transistor (306), and the output terminal of the current sampling chip (4) is connected to the base of the second transistor (306) through the fourth resistor (304), the emitter of the second transistor (306) is connected to one end of the third resistor (303), and its collector is connected to the non-grounded end of the power resistor (102); The input terminal of the current source module is the positive terminal of the first switching diode (201), which is connected to the GATE node at the output terminal of the current sampling chip (4). The output device (204) is a resistor, which is configured to adjust the operating frequency of the current sampling chip (4) by adjusting the resistance value of the output device (204) when the feedback voltage of the sampling pin of the current sampling chip (4) remains unchanged; or, the output device (204) is a switching diode, whose positive terminal is connected to the anode of the voltage reference source (206), and the current sampling chip (4) is configured to control the operating frequency of the current sampling chip (4) to decrease to the operating frequency when the current source module without current compensation is added after the current source module is added.

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