A source-switched charge pump circuit with low current mismatch and wide matching range

Abstract

The present disclosure provides a source switch charge pump circuit with low current mismatch and wide matching range, comprising: a first bias circuit unit, a second bias circuit unit, a current injection circuit unit, and a charge pump core circuit. The charge pump core circuit comprises: an output current source charging branch and an output current source discharging branch. The output current source charging branch comprises a resistor enhancement structure formed based on a first operational amplifier OPA1 for voltage clamping, and the output current source discharging branch comprises a resistor enhancement structure formed based on a second operational amplifier OPA2 for voltage clamping, so that the final output current reduces the current mismatch while having a large matching output voltage range.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit technology, and in particular to a source switch charge pump circuit with low current mismatch and wide matching range. Background Art

[0002] Frequency synthesizers based on charge pump phase-locked loops are widely used in communication systems due to their excellent performance. The performance of frequency synthesizers is crucial to communication systems. Figure 1 This is a schematic diagram of a general-purpose charge pump phase-locked loop (PLL) frequency synthesizer. Spurious emissions are a critical factor in PLL frequency synthesizers. Excessive spurious emissions can introduce significant out-of-band noise into the frequency band, degrading the signal-to-noise ratio. Spurious emissions are primarily caused by the periodic variation of the voltage-controlled oscillator (VCO) control voltage, which modulates the output frequency. This periodic variation in control voltage is primarily due to non-idealities in the phase frequency detector (PFD) and charge pump (CP), particularly the charge pump.

[0003] Therefore, providing a more effective charge pump circuit to reduce the spurious signal of the frequency synthesizer, reduce the current mismatch, and widen the matching output voltage range is a technical issue that needs to be solved urgently. Summary of the Invention

[0004] Based on the above problems, the present disclosure provides a source switch charge pump circuit with low current mismatch and wide matching range, comprising: a first bias circuit unit, comprising: a first bias branch, for providing a first bias voltage V1 under the action of a first input current I1, and a second bias branch, for providing a second bias voltage V2 under the action of a second input current I2; a second bias circuit unit, comprising: a bias current generating circuit, connected to the current source unit, for generating a first bias current I1′ and a second bias current I2′ under the action of the first bias voltage V1 and the second bias voltage V2; a bias voltage generating circuit, connected to the bias current generating circuit, for generating a third bias voltage V3 and a fourth bias voltage V4 under the action of the first bias current I1′ and the second bias current I2′; a current injection circuit unit, comprising: a charging branch, connected to the bias voltage generating circuit, for generating a first bias voltage V3 and a second bias voltage V4 under the action of the third bias voltage V3 and the fourth bias voltage V 4, providing a third bias current I3 under the action of the first bias voltage V1 and the second bias voltage V2; a discharge branch, connected to the first bias circuit unit, for providing a fourth bias current I4 under the action of the first bias voltage V1 and the second bias voltage V2; a charge pump core circuit, including: an output current source charging branch, connected to the discharge branch, for amplifying and adjusting the fourth bias current I4 to obtain a charging current I4′; an output current source discharging branch, connected to the charging branch, for amplifying and adjusting the third bias current I3 to obtain a charging current I3′; the output current source charging branch includes a resistor enhancement structure formed based on the first operational amplifier OPA1 for voltage clamping, and the output current source discharging branch includes a resistor enhancement structure formed based on the second operational amplifier OPA2 for voltage clamping, so that the charging current I4′ is equal to the charging current I3′, so that the final output current reduces the current mismatch while having a large matching output voltage range.

[0005] According to an embodiment of the present disclosure, the first bias branch includes an eighth n-transistor MN8 and a first n-transistor MN1; the source of the first n-transistor MN1 is connected to the ground, the drain is connected to the source of the eighth n-transistor MN8, and the gate is connected to the gate of the eighth n-transistor MN8; the drain of the eighth n-transistor MN8 is connected to the gate.

[0006] According to an embodiment of the present disclosure, the second bias branch includes a second n-transistor MN2 and a ninth n-transistor MN9; wherein the source of the second n-transistor MN2 is connected to ground, the drain is connected to the source of the ninth n-transistor MN9, and the gate is connected to the drain of the ninth n-transistor MN9; and the gate of the ninth n-transistor MN9 is connected to the gates of the first n-transistor MN1 and the eighth n-transistor MN8.

[0007] According to an embodiment of the present disclosure, the bias voltage generating circuit includes a first p-transistor MP1, a second p-transistor MP2, a sixth p-transistor MP6, and a seventh p-transistor MP7; wherein the gates of the sixth p-transistor MP6 and the seventh p-transistor MP7 are respectively connected to the drain of the sixth p-transistor MP6, the sources of the sixth p-transistor MP6 and the seventh p-transistor MP7 are respectively connected to the drains of the first p-transistor MP1 and the second p-transistor MP2, the sources of the first p-transistor MP1 and the second p-transistor MP2 are connected to the power supply VDD; the gates of the first p-transistor MP1 and the second p-transistor MP2 are respectively connected to the drains of the sixth p-transistor MP6 and the seventh p-transistor MP7.

[0008] According to an embodiment of the present disclosure, the bias current generating circuit includes a third n-transistor MN3, a fourth n-transistor MN4, a tenth n-transistor MN10, and an eleventh n-transistor MN11; wherein the sources of the third n-transistor MN3 and the fourth n-transistor MN4 are connected to ground, the gates are connected to the gate of the second n-transistor MN2, and the drains are connected to the sources of the tenth n-transistor MN10 and the eleventh n-transistor MN11, respectively; the gates of the tenth n-transistor MN10 and the eleventh n-transistor MN11 are connected to the gate of the ninth n-transistor MN9, respectively, and the drains of the tenth n-transistor MN10 and the eleventh n-transistor MN11 are connected to the drains of the sixth p-transistor MP6 and the seventh p-transistor MP7, respectively.

[0009] According to an embodiment of the present disclosure, the charging branch includes a third p-transistor MP3 and an eighth p-transistor MP8; the gates of the third p-transistor MP3 and the eighth p-transistor MP8 are respectively connected to the gates of the second p-transistor MP2 and the seventh p-transistor MP7, the source of the third p-transistor MP3 is connected to the power supply VDD, and the source of the eighth p-transistor MP8 is connected to the drain of the third p-transistor MP3.

[0010] According to an embodiment of the present disclosure, the discharge branch includes a fifth n-transistor MN5 and a twelfth n-transistor MN12; wherein the gates of the fifth n-transistor MN5 and the twelfth n-transistor MN12 are respectively connected to the gates of the fourth n-transistor MN4 and the eleventh n-transistor MN11, the source of the fifth n-transistor MN5 is connected to ground, and the drain is connected to the source of the twelfth n-transistor MN12.

[0011] According to an embodiment of the present disclosure, the output current source charging branch includes a fourth p-transistor MP4, a fifth p-transistor MP5, a ninth p-transistor MP9, a tenth p-transistor MP10, an eleventh p-transistor MP11, a twelfth p-transistor MP12, and an operational amplifier OPA1; wherein the source of the fourth p-transistor MP4 is connected to the power supply VDD, the gate is connected to the ground, the drain is connected to the source of the ninth p-transistor MP9, the gate of the ninth p-transistor MP9 is connected to the gate of the eighth p-transistor MP8, the drain is connected to the source of the eleventh p-transistor MP11, the gate and drain of the eleventh p-transistor MP11 are connected and then connected. The positive terminal of the operational amplifier OPA1 is connected to the drain of the ninth p-transistor MP9, the negative terminal is connected to the drain of the tenth p-transistor MP10, the output terminal is connected to the gate of the twelfth p-transistor MP12, and the drain of the twelfth p-transistor MP12 is connected to the charge pump circuit output terminal Iout.

[0012] According to an embodiment of the present disclosure, the output current source discharge branch includes a sixth n-transistor MN6, a seventh n-transistor MN7, a thirteenth n-transistor MN13, a fourteenth n-transistor MN14, a fifteenth n-transistor MN15, a sixteenth n-transistor MN16, and an operational amplifier OPA2; wherein the gate of the sixth n-transistor MN6 is connected to the power supply VDD, the source is connected to the ground, and the drain is connected to the source of the thirteenth n-transistor MN13; the gate of the thirteenth n-transistor MN13 is connected to the gate of the twelfth n-transistor MN12; the drain of the thirteenth n-transistor MN13 is connected to the source of the fifteenth n-transistor MN15; and the fifteenth n-transistor MN15 is connected to the gate of the twelfth n-transistor MN12. The gate and drain of the operational amplifier OPA2 are connected to the drain of the eighth p-transistor MP8; the source of the seventh n-transistor MN7 is connected to the ground, the gate is connected to the signal DN, the drain is connected to the source of the fourteenth n-transistor MN14, the gate of the fourteenth n-transistor MN14 is connected to the gate of the thirteenth n-transistor MN13, and the drain is connected to the source of the sixteenth n-transistor MN16; the positive terminal of the operational amplifier OPA2 is connected to the drain of the thirteenth n-transistor MN13, the negative terminal is connected to the drain of the fourteenth n-transistor MN14, the output terminal is connected to the gate of the sixteenth n-transistor MN16, and the drain of the sixteenth n-transistor MN16 is connected to the output terminal Iout of the charge pump circuit.

[0013] Beneficial effects:

[0014] It can be seen from the above technical solutions that the disclosed low current mismatch and wide matching range source switch charge pump circuit has at least one or part of the following beneficial effects:

[0015] (1) Reduce the problem of upper and lower current mismatch caused by channel length modulation effect;

[0016] (2) The charge pump can have a large matching output voltage range while having low current mismatch. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of a frequency synthesizer based on a charge pump phase-locked loop.

[0018] Figure 2 The invention relates to a charge pump circuit structure in which a transistor feedback resistor is introduced in the prior art.

[0019] Figure 3 1 is a block diagram of an architecture of a source switch charge pump circuit with low current mismatch and wide matching range according to an embodiment of the present disclosure;

[0020] Figure 4 Schematic diagram of a source switch charge pump circuit with low current mismatch and wide matching range according to an embodiment of the present disclosure;

[0021] Figure 5 Schematic diagram of current matching simulation of a source switch charge pump circuit with low current mismatch and wide matching range according to an embodiment of the present disclosure.

[0022] Figure 6 Schematic diagram of calculating the equivalent output resistance of a source switch charge pump circuit with low current mismatch and wide matching range according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] The present disclosure provides a source switch charge pump circuit with low current mismatch and wide matching range, which can be applied to high-performance frequency synthesizers, so that the source switch charge pump has a large matching range while achieving low current mismatch, thereby reducing the output spurious of the charge pump phase-locked loop frequency synthesizer.

[0024] The non-idealities of the charge pump mainly include charge sharing, clock feedthrough, and current mismatch. In the process of implementing the present disclosure, the inventors found that there are many technologies currently used to mitigate the current mismatch characteristics of the charge pump. Figure 2Tsung-Hsien Lin et al. proposed a new source-switched charge pump (Lin TH, Ti CL, Liu YH. Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-N PLLs [J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2009, 56 (5): 877-885.). By introducing the resistance of parallel transistors in the charge pump to offset the influence of transistor channel length modulation, this structure has excellent current matching, but does not broaden the current matching range of the charge pump.

[0025] The existing source-switched charge pump structure can only compromise between current matching and output voltage range. The source-switched charge pump disclosed in the present invention introduces two operational amplifiers for voltage clamping on the basis of the traditional source-switched charge pump, and adds a common-source common-gate transistor at the source switch to further increase the output resistance, thereby achieving low current mismatch while having a larger matching range.

[0026] The disclosed source-switched charge pump circuit integrates two operational amplifiers (OPA1 and OPA2) for voltage clamping, building upon a traditional source-switched charge pump. This allows for precise replication of the output current source bias current and output current, mitigating the current mismatch between the upper and lower currents caused by channel length modulation. Furthermore, the addition of a cascode transistor at the source switch further increases the output resistance, enabling the charge pump to maintain a wide output voltage range while minimizing current mismatch.

[0027] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0028] In an embodiment of the present disclosure, a source switch charge pump circuit with low current mismatch and wide matching range is provided. Figure 3 and Figure 4 As shown, the charge pump circuit includes:

[0029] The first bias circuit unit 1 includes:

[0030] The first bias branch 101 is used to provide a first bias voltage V1 under the action of the first input current I1.

[0031] The second bias branch 102 is configured to provide a second bias voltage V2 under the action of the second input current I2;

[0032] The second bias circuit unit 2 includes:

[0033] a bias current generating circuit 202 connected to the current source unit, configured to generate a first bias current I1′ and a second bias current I2′ under the action of the first bias voltage V1 and the second bias voltage V2;

[0034] a bias voltage generating circuit 201 connected to the bias current generating circuit 202 and configured to generate a third bias voltage V3 and a fourth bias voltage V4 under the action of the first bias current I1′ and the second bias current I2′;

[0035] The current injection circuit unit 3 includes:

[0036] a charging branch 301 connected to the bias voltage generating circuit 201 and configured to provide a third bias current I3 under the action of the third bias voltage V3 and the fourth bias voltage V4;

[0037] a discharge branch 302 connected to the first bias circuit unit 1 and configured to provide a fourth bias current 14 under the action of the first bias voltage V1 and the second bias voltage V2;

[0038] The charge pump core circuit 4 includes:

[0039] an output current source charging branch 401 connected to the discharging branch 302 and configured to amplify and adjust the fourth bias current I4 to obtain a charging current I4′;

[0040] an output current source discharge branch 402 connected to the charging branch 301 and configured to amplify and adjust the third bias current I3 to obtain a charging current I3′;

[0041] The output current source charging branch 401 includes a resistance enhancement structure formed based on the first operational amplifier OPA1 for voltage clamping, and the output current source discharging branch 402 includes a resistance enhancement structure formed based on the second operational amplifier OPA2 for voltage clamping, so that the charging current I4′ and the charging current I3′ are equal, so that the final output current reduces the current mismatch while having a large matching output voltage range.

[0042] According to an embodiment of the present disclosure, the first bias branch includes an eighth n-transistor MN8 and a first n-transistor MN1; the source of the first n-transistor MN1 is connected to ground, the drain is connected to the source of the eighth n-transistor MN8, and the gate is connected to the gate of the eighth n-transistor MN8; the drain of the eighth n-transistor MN8 is connected to the gate. The second bias branch includes a second n-transistor MN2 and a ninth n-transistor MN9; the source of the second n-transistor MN2 is connected to ground, the drain is connected to the source of the ninth n-transistor MN9, and the gate is connected to the drain of the ninth n-transistor MN9; the gate of the ninth n-transistor MN9 is connected to the gates of the first n-transistor MN1 and the eighth n-transistor MN8.

[0043] According to an embodiment of the present disclosure, the bias voltage generating circuit 201 includes a first p-transistor MP1, a second p-transistor MP2, a sixth p-transistor MP6, and a seventh p-transistor MP7; wherein the gates of the sixth p-transistor MP6 and the seventh p-transistor MP7 are respectively connected to the drain of the sixth p-transistor MP6, the sources of the sixth p-transistor MP6 and the seventh p-transistor MP7 are respectively connected to the drains of the first p-transistor MP1 and the second p-transistor MP2, the sources of the first p-transistor MP1 and the second p-transistor MP2 are connected to the power supply VDD; the gates of the first p-transistor MP1 and the second p-transistor MP2 are respectively connected to the drains of the sixth p-transistor MP6 and the seventh p-transistor MP7.

[0044] According to an embodiment of the present disclosure, the bias current generating circuit 202 includes a third n-transistor MN3, a fourth n-transistor MN4, a tenth n-transistor MN10, and an eleventh n-transistor MN11. The sources of the third n-transistor MN3 and the fourth n-transistor MN4 are connected to ground, the gates are connected to the gate of the second n-transistor MN2, and the drains are connected to the sources of the tenth n-transistor MN10 and the eleventh n-transistor MN11, respectively. The gates of the tenth n-transistor MN10 and the eleventh n-transistor MN11 are connected to the gate of the ninth n-transistor MN9, respectively. The drains of the tenth n-transistor MN10 and the eleventh n-transistor MN11 are connected to the drains of the sixth p-transistor MP6 and the seventh p-transistor MP7, respectively.

[0045] According to an embodiment of the present disclosure, the charging branch 301 includes a third p-transistor MP3 and an eighth p-transistor MP8; wherein the gates of the third p-transistor MP3 and the eighth p-transistor MP8 are respectively connected to the gates of the second p-transistor MP2 and the seventh p-transistor MP7, the source of the third p-transistor MP3 is connected to the power supply VDD, and the source of the eighth p-transistor MP8 is connected to the drain of the third p-transistor MP3.

[0046] According to an embodiment of the present disclosure, the discharge branch 302 includes a fifth n-transistor MN5 and a twelfth n-transistor MN12; wherein the gates of the fifth n-transistor MN5 and the twelfth n-transistor MN12 are respectively connected to the gates of the fourth n-transistor MN4 and the eleventh n-transistor MN11, the source of the fifth n-transistor MN5 is connected to ground, and the drain is connected to the source of the twelfth n-transistor MN12.

[0047] According to an embodiment of the present disclosure, the output current source charging branch 401 includes a fourth p-transistor MP4, a fifth p-transistor MP5, a ninth p-transistor MP9, a tenth p-transistor MP10, an eleventh p-transistor MP11, a twelfth p-transistor MP12, and an operational amplifier OPA1; wherein the source of the fourth p-transistor MP4 is connected to the power supply VDD, the gate is connected to the ground, the drain is connected to the source of the ninth p-transistor MP9, the gate of the ninth p-transistor MP9 is connected to the gate of the eighth p-transistor MP8, the drain is connected to the source of the eleventh p-transistor MP11, and the gate and drain of the eleventh p-transistor MP11 are connected. The positive terminal of the operational amplifier OPA1 is connected to the drain of the ninth p-transistor MP9, the negative terminal is connected to the drain of the tenth p-transistor MP10, the output terminal is connected to the gate of the twelfth p-transistor MP12, and the drain of the twelfth p-transistor MP12 is connected to the charge pump circuit output terminal Iout.

[0048] According to an embodiment of the present disclosure, the output current source discharge branch 402 includes a sixth n-transistor MN6 , a seventh n-transistor MN7 , a thirteenth n-transistor MN13 , a fourteenth n-transistor MN14 , a fifteenth n-transistor MN15 , a sixteenth n-transistor MN16 and an operational amplifier OPA2 . Among them, the sixth n-transistor MN6 has a gate connected to the power supply VDD, a source connected to ground, and a drain connected to the source of the thirteenth n-transistor MN13. The gate of the thirteenth n-transistor MN13 is connected to the gate of the twelfth n-transistor MN12. The drain of the thirteenth n-transistor MN13 is connected to the source of the fifteenth n-transistor MN15. The gate and drain of the fifteenth n-transistor MN15 are connected and then connected to the drain of the eighth p-transistor MP8. The seventh n-transistor MN7 has a source connected to ground, a gate connected to the signal DN, a drain connected to the source of the fourteenth n-transistor MN14. The gate of the fourteenth n-transistor MN14 is connected to the gate of the thirteenth n-transistor MN13, and a drain connected to the source of the sixteenth n-transistor MN16. The positive terminal of the operational amplifier OPA2 is connected to the drain of the thirteenth n-transistor MN13, the negative terminal is connected to the drain of the fourteenth n-transistor MN14, the output terminal is connected to the gate of the sixteenth n-transistor MN16, and the drain of the sixteenth n-transistor MN16 is connected to the output terminal Iout of the charge pump circuit.

[0049] Combine Figures 1 to 4 As shown in the figure, the phase frequency detector (PFD) in the charge pump's pre-stage circuit compares the phase difference between the reference clock and the feedback clock to output control signals UP and DN, respectively, which determine whether the upper and lower current sources are conducted. To achieve a zero phase difference, the currents of the upper and lower current sources must be equal. Due to the channel length modulation effect and current mirror amplification, even if the reference currents are equal, the amplified currents are unequal. To address this unequal amplified current problem, the following specific method is provided.

[0050] like Figure 3 and Figure 4 As shown, the first bias circuit unit 1 provides bias voltages V1 and V2 to the second bias circuit unit 2, the discharge branch 302, and the output current source discharge branch 402. The second bias circuit unit 2 provides bias voltages V3 and V4 to the charging branch 301 and the output current source charging branch 401. The charging branch 301 in the current injection circuit unit 3 provides a bias current I3 to the output current source discharge branch 402; and the discharge branch 302 in the current injection circuit unit 3 provides a bias current I4 to the output current source charging branch 401. The currents in the charging branch 301 and the discharging branch 302 of the current injection circuit unit 3 are equal.

[0051] Furthermore, the output current source charging branch 401 incorporates a cascode structure, comprising a ninth p-transistor MP9 and a tenth p-transistor MP10. This cascode structure significantly increases the output resistance of the circuit comprised of the fifth p-transistor MP5, the tenth p-transistor MP10, and the twelfth p-transistor MP12, further reducing leakage current. Operational amplifier OPA1 voltage-clamps the first node N1 and the second node N2, accurately replicating the current flowing through the first node N1 and the second node N2. Consequently, I4′ = N × I4 (where N is a multiple, achieved by setting the width-to-length ratios of the fifth p-transistor MP5 and the tenth p-transistor MP10 to be N times that of the fourth p-transistor MP4 and the ninth p-transistor MP9, respectively). This reduces current mismatch caused by the channel length modulation effect.

[0052] Similarly, the output current source discharge branch 402 incorporates a cascode structure, including the thirteenth n-transistor MN13 and the fourteenth n-transistor MN14. This cascode structure significantly increases the output resistance of the circuit consisting of the seventh n-transistor MN7, the fourteenth n-transistor MN14, and the sixteenth n-transistor MN16, further reducing leakage current. Operational amplifier OPA2 voltage-clamps the third node N3 and the fourth node N4, accurately replicating the current flowing through the third node N3 and the fourth node N4. Therefore, I3′=N×I3 (where N is a multiple, which can be achieved by setting the width-to-length ratio of the seventh n-transistor MN7 and the fourteenth n-transistor MN14 to N times that of the sixth n-transistor MN6 and the thirteenth n-transistor MN13, respectively). This reduces the current mismatch caused by the channel length modulation effect.

[0053] Furthermore, due to the mirror image relationship between the charging branch 301 and the bias voltage generating circuit 201, I2′=I3, and due to the mirror image relationship between the discharging branch 302 and the bias current generating circuit 202, I2′=I4, and thus I3=I4. Furthermore, I3′=I4′. Figure 5 As shown, by calculating the relative mismatch of the upper and lower current sources using the formula (I3′-I4′) / I3′, it can be obtained that the relative mismatch of the upper and lower current sources is less than 1‰.

[0054] Furthermore, the switching signals UP and DN determine the on / off switching of the charging and discharging currents. That is, when UP is high, the charging current is zero. When UP is low, the charging current I4′ is N times the current I4 of the discharging branch 302. Similarly, when DN is low, the discharging current is zero. When DN is high, the discharging current I3′ is N times the current I3 of the charging branch 301.

[0055] According to an embodiment of the present disclosure, the first operational amplifier OPA1 adjusts the gate voltage of the twelfth p-transistor MP12 so that the drains of the ninth p-transistor MP9 and the tenth p-transistor MP10, ie, the first node N1 and the second node N2, have the same voltage.

[0056] According to an embodiment of the present disclosure, the second operational amplifier OPA2 adjusts the gate voltage of the sixteenth n-transistor MN16 so that the drains of the thirteenth n-transistor MN13 and the fourteenth n-transistor MN14, ie, the third node N3 and the fourth node N4, have the same voltage.

[0057] Because of the clamping effect of operational amplifiers OPA1 and OPA2, the charge pump can have a large matched output voltage range (0.15V-0.85V when the power supply voltage is 1V) while having a low current mismatch (less than one thousandth).

[0058] The following is the derivation process of the equivalent output resistance of the cascode circuit structure with operational amplifier feedback. Figure 6 As shown, it is assumed here that the body effect equivalent resistance of the seventh n transistor is r o7 , the transconductance of the fourteenth n-th transistor is g m14 , the body effect equivalent resistance is r o14 , the transconductance of the eighteenth n transistor is g m18 , the body effect equivalent resistance is r o18 , the gain of the operational amplifier is A. Looking from the drain of the fourteenth n transistor, the equivalent resistance of the fourteenth n transistor and the seventh n transistor is R S =[1+g m14 r o14 ]r o7 +r o14 Then, the output resistance seen from the drain of the eighteenth n-th transistor is R out =r o18 +(1+A)g m18 r o18 R S +R S It can be found that when an operational amplifier is added for voltage clamping, the output resistance of the circuit is expanded by about A times, so the circuit can have high current matching.

[0059] Similarly, the derivation of the equivalent resistance in the other part of the circuit is the same as the above method and will not be repeated here.

[0060] The embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that any implementations not depicted or described in the drawings or the main text of the specification are known to those skilled in the art and are not described in detail. Furthermore, the above definitions of the various elements and methods are not limited to the various specific structures, shapes, or methods described in the embodiments, and can be easily modified or replaced by those skilled in the art.

[0061] Based on the above description, those skilled in the art should have a clear understanding of the source switch charge pump circuit with low current mismatch and wide matching range disclosed in the present invention.

[0062] In summary, the present disclosure provides a source-switched charge pump circuit with low current mismatch and a wide matching range. This circuit, based on a conventional source-switched charge pump, introduces two operational amplifiers for voltage clamping, reducing the upper and lower current mismatch caused by the channel length modulation effect. Furthermore, the addition of cascode transistors at the source switch further increases the output resistance, enabling the charge pump to maintain a low current mismatch while maintaining a wide matching output voltage range.

[0063] It should also be noted that the above are different embodiments provided by the present disclosure. These embodiments are used to illustrate the technical content of the present disclosure and are not intended to limit the scope of protection of the present disclosure. A feature of one embodiment can be applied to other embodiments through appropriate modification, replacement, combination, or separation.

[0064] It should be noted that, herein, unless otherwise specified, “a” element is not limited to a single element, but may include one or more elements.

[0065] Furthermore, unless otherwise specified, ordinal numbers such as "first" and "second" are used herein solely to distinguish multiple components with the same name and do not imply a hierarchy, level, execution order, or process sequence between them. A "first" component and a "second" component may appear together in the same component or in different components. The presence of a component with a higher ordinal number does not necessarily imply the presence of the other component with a lower ordinal number.

[0066] In this document, unless otherwise specified, the so-called feature A "or" or "and / or" feature B means that A exists alone, B exists alone, or A and B exist at the same time; the so-called feature A "and" or "and" or "and" feature B means that A and B exist at the same time; the so-called "include", "comprise", "have" and "contain" mean including but not limited to these.

[0067] Furthermore, in this document, terms such as "upper," "lower," "left," "right," "front," "back," or "between" are used solely to describe the relative positions of multiple elements and can be interpreted to include translation, rotation, or mirroring. Furthermore, in this document, unless otherwise specified, "an element is on another element" or similar descriptions do not necessarily mean that the element contacts the other element.

[0068] Furthermore, unless specifically described or required to occur sequentially, the order of the steps is not limited to the order listed above and may be varied or rearranged based on desired design requirements. Furthermore, the above embodiments may be mixed and matched with each other or with other embodiments based on design and reliability considerations. That is, the technical features of different embodiments may be freely combined to form more embodiments.

[0069] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above are only specific embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A source switch charge pump circuit with low current mismatch and wide matching range, comprising: The first bias circuit unit (1) comprises: The first bias branch (101) is used to provide a first bias voltage V1 under the action of a first input current I1, A second bias branch (102) is used to provide a second bias voltage V2 under the action of a second input current I2; The second bias circuit unit (2) comprises: A bias current generating circuit (202), connected to the first bias circuit unit (1), for generating a first bias current I1′ and a second bias current I2′ under the action of the first bias voltage V1 and the second bias voltage V2; A bias voltage generating circuit (201) is connected to the bias current generating circuit (202) and is used to generate a third bias voltage V3 and a fourth bias voltage V4 under the action of the first bias current I1′ and the second bias current I2′; The current injection circuit unit (3) comprises: A charging branch (301), connected to the bias voltage generating circuit (201), for providing a third bias current I3 under the action of the third bias voltage V3 and the fourth bias voltage V4; A discharge branch (302), connected to the first bias circuit unit (1), for providing a fourth bias current I4 under the action of the first bias voltage V1 and the second bias voltage V2; The charge pump core circuit (4) includes: An output current source charging branch (401), connected to the discharge branch (302), is used to amplify and adjust the fourth bias current I4 to obtain a charging current I4′; An output current source discharge branch (402), connected to the charging branch (301), is used to amplify and adjust the third bias current I3 to obtain a charging current I3′; The output current source charging branch (401) includes a resistance enhancement structure formed based on the first operational amplifier OPA1 for voltage clamping, and the output current source discharging branch (402) includes a resistance enhancement structure formed based on the second operational amplifier OPA2 for voltage clamping, so that the charging current I4′ and the charging current I3′ are equal, so that the final output current reduces the current mismatch while having a large matching output voltage range.

2. The source-switched charge pump circuit with low current mismatch and wide matching range according to claim 1, wherein the first bias branch comprises an eighth n-transistor (MN8) and a first n-transistor (MN1); the source of the first n-transistor (MN1) is connected to ground, the drain is connected to the source of the eighth n-transistor (MN8), and the gate is connected to the gate of the eighth n-transistor (MN8); the drain of the eighth n-transistor (MN8) is connected to the gate.

3. The low current mismatch and wide matching range source switch charge pump circuit according to claim 2, wherein the second bias branch comprises a second n-transistor (MN2) and a ninth n-transistor (MN9); in, The source of the second n-transistor (MN2) is connected to the ground, the drain is connected to the source of the ninth n-transistor (MN9), and the gate is connected to the drain of the ninth n-transistor (MN9); the gate of the ninth n-transistor (MN9) is connected to the gates of the first n-transistor (MN1) and the eighth n-transistor (MN8).

4. The source switch charge pump circuit with low current mismatch and wide matching range according to claim 1, wherein the bias voltage generating circuit (201) comprises a first p-transistor (MP1), a second p-transistor (MP2), a sixth p-transistor (MP6) and a seventh p-transistor (MP7); in, The gates of the sixth p-transistor (MP6) and the seventh p-transistor (MP7) are respectively connected to the drain of the sixth p-transistor (MP6); the sources of the sixth p-transistor (MP6) and the seventh p-transistor (MP7) are respectively connected to the drains of the first p-transistor (MP1) and the second p-transistor (MP2); the sources of the first p-transistor (MP1) and the second p-transistor (MP2) are connected to the power supply VDD; the gates of the first p-transistor (MP1) and the second p-transistor (MP2) are respectively connected to the drains of the sixth p-transistor (MP6) and the seventh p-transistor (MP7).

5. The source switch charge pump circuit with low current mismatch and wide matching range according to claim 4, wherein the bias current generating circuit (202) comprises a third n-transistor (MN3), a fourth n-transistor (MN4), a tenth n-transistor (MN10) and an eleventh n-transistor (MN11); in, The sources of the third n-transistor (MN3) and the fourth n-transistor (MN4) are connected to the ground, the gates are connected to the gate of the second n-transistor (MN2), and the drains are connected to the sources of the tenth n-transistor (MN10) and the eleventh n-transistor (MN11); the gates of the tenth n-transistor (MN10) and the eleventh n-transistor (MN11) are connected to the gate of the ninth n-transistor (MN9), and the drains of the tenth n-transistor (MN10) and the eleventh n-transistor (MN11) are connected to the drains of the sixth p-transistor (MP6) and the seventh p-transistor (MP7), respectively.

6. The low current mismatch and wide matching range source switch charge pump circuit according to claim 4, wherein the charging branch (301) comprises a third p-transistor (MP3) and an eighth p-transistor (MP8); the gates of the third p-transistor (MP3) and the eighth p-transistor (MP8) are respectively connected to the gates of the second p-transistor (MP2) and the seventh p-transistor (MP7); the source of the third p-transistor (MP3) is connected to the power supply VDD; and the source of the eighth p-transistor (MP8) is connected to the drain of the third p-transistor (MP3).

7. The source switch charge pump circuit with low current mismatch and wide matching range according to claim 5, wherein the discharge branch (302) comprises a fifth n-transistor (MN5) and a twelfth n-transistor (MN12); in, The gates of the fifth n-transistor (MN5) and the twelfth n-transistor (MN12) are connected to the gates of the fourth n-transistor (MN4) and the eleventh n-transistor (MN11), respectively. The source of the fifth n-transistor (MN5) is connected to the ground, and the drain is connected to the source of the twelfth n-transistor (MN12).

8. The source switch charge pump circuit with low current mismatch and wide matching range according to claim 7, wherein the output current source charging branch (401) comprises a fourth p-transistor (MP4), a fifth p-transistor (MP5), a ninth p-transistor (MP9), a tenth p-transistor (MP10), an eleventh p-transistor (MP11), a twelfth p-transistor (MP12) and an operational amplifier OPA1; in, The source of the fourth p-transistor (MP4) is connected to the power supply VDD, the gate is connected to the ground, the drain is connected to the source of the ninth p-transistor (MP9), the gate of the ninth p-transistor (MP9) is connected to the gate of the eighth p-transistor (MP8), the drain is connected to the source of the eleventh p-transistor (MP11), the gate and drain of the eleventh p-transistor (MP11) are connected and then connected to the drain of the twelfth n-transistor (MN12); The gate of the fifth P-transistor (MP5) is connected to the signal UP, the source is connected to the power supply VDD, the drain is connected to the source of the tenth P-transistor (MP10), the gate of the tenth P-transistor (MP10) is connected to the gate of the ninth P-transistor (MP9), and the drain is connected to the source of the twelfth P-transistor (MP12); the positive terminal of the operational amplifier OPA1 is connected to the drain of the ninth P-transistor (MP9), the negative terminal is connected to the drain of the tenth P-transistor (MP10), the output terminal is connected to the gate of the twelfth P-transistor (MP12), and the drain of the twelfth P-transistor (MP12) is connected to the output terminal Iout of the charge pump circuit.

9. The low current mismatch and wide matching range source switch charge pump circuit according to claim 6, wherein the output current source discharge branch (402) comprises a sixth n-transistor (MN6), a seventh n-transistor (MN7), a thirteenth n-transistor (MN13), a fourteenth n-transistor (MN14), a fifteenth n-transistor (MN15), a sixteenth n-transistor (MN16) and an operational amplifier OPA2; in, The gate of the sixth n-transistor (MN6) is connected to the power supply VDD, the source is connected to the ground, and the drain is connected to the source of the thirteenth n-transistor (MN13). The gate of the thirteenth n-transistor (MN13) is connected to the gate of the twelfth n-transistor (MN12). The drain of the thirteenth n-transistor (MN13) is connected to the source of the fifteenth n-transistor (MN15). The gate and drain of the fifteenth n-transistor (MN15) are connected and then connected to the drain of the eighth p-transistor (MP8). The source of the seventh n-transistor (MN7) is connected to the ground, and the gate is connected to the signal DN. The operational amplifier OPA2 is connected to the source of the fourteenth n-transistor (MN14), the drain of the fourteenth n-transistor (MN14) is connected to the gate of the thirteenth n-transistor (MN13), the drain of the fourteenth n-transistor (MN14) is connected to the source of the sixteenth n-transistor (MN16), the positive terminal of the operational amplifier OPA2 is connected to the drain of the thirteenth n-transistor (MN13), the negative terminal is connected to the drain of the fourteenth n-transistor (MN14), the output terminal is connected to the gate of the sixteenth n-transistor (MN16), and the drain of the sixteenth n-transistor (MN16) is connected to the output terminal Iout of the charge pump circuit.

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