Motherboard, circuit board manufacturing method and circuit board

Abstract

The embodiments of the present application disclose a motherboard, a method for manufacturing a circuit board, and a circuit board. The motherboard includes at least one daughter board area, a protective layer, and a redundant material area. The daughter board area is provided with a test circuit, the protective layer covers the daughter board area, the redundant material area is connected to at least one side of the daughter board area, and the redundant material area is provided with at least two first test points. The first test points are electrically connected to the test circuit, which can improve the technical problems of low test accuracy and low pass rate in circuit testing of PCBA.

Description

Technical Field

[0001] The present application relates to the display field, and in particular to a motherboard, a method for manufacturing a circuit board, and a circuit board. Background Art

[0002] Printed Circuit Board (PCB) fabrication is performed on the printed circuit board (PCB) and electronic components are assembled onto it, resulting in a printed circuit board assembly (PCBA). To verify the reliability of the electronic components on the PCBA and to ensure the production yield of the fabrication plant, an in-circuit test (ICT) is required.

[0003] The implementation method of circuit testing is to use a test probe to connect the test point of the PCBA and the ICT equipment, and complete the test and ICT pass rate judgment by collecting the signals of each test point. In the process of research and practice of the prior art, the inventor of this application found that the surface of the existing PCBA is covered with a solder mask layer, and the solder mask layer is used to improve the antistatic ability of the PCBA. Since the test point is covered by the solder mask layer, the traditional measurement method of using a test probe to connect the test point of the PCBA is no longer applicable. In order to solve the above problem, the inventor tried to connect the test point to the gold finger of the binding area, press the flexible flat cable (Flexible Flat Cable, FFC) at the gold finger, thereby transferring the test point to the flexible flat cable, and then connect the test point of the flexible flat cable and the ICT equipment by using a test probe to complete the circuit test. However, since the binding area of ​​the PCBA is provided with multiple gold fingers, it is difficult for the flexible flat cable to be accurately pressed at the corresponding gold finger, resulting in technical problems of low test accuracy and low pass rate. Summary of the Invention

[0004] The embodiments of the present application provide a motherboard, a method for manufacturing a circuit board, and a circuit board, which can improve the technical problems of low test accuracy and low pass rate in circuit testing of PCBA.

[0005] An embodiment of the present application provides a motherboard, comprising:

[0006] at least one daughter board area, wherein the daughter board area is provided with a test circuit;

[0007] a protective layer, the protective layer covering the daughter board area; and

[0008] A redundant material area is connected to at least one side of the daughter board area. The redundant material area is provided with at least two first test points, and the first test points are electrically connected to the test circuit.

[0009] Under this structure, by electrically connecting the test circuit in the daughter board area to the first test point in the redundant material area, the test potential of the test circuit can be transferred to the redundant material area where no protective layer is set. The first test point will not be blocked by the protective layer. Therefore, the circuit test can still be implemented by connecting the test probe to the first test point and the ICT equipment, effectively improving the test accuracy and pass rate of the PCBA circuit test.

[0010] Optionally, in some embodiments of the present application, the redundant material area is further provided with at least two first test lines;

[0011] The daughter board area includes a binding area, and the binding area is provided with a plurality of gold fingers. The test circuit is electrically connected to the first test point through the gold fingers and the first test trace in sequence.

[0012] Under this structure, the test circuit is electrically connected to the first test point through the gold finger and the first test trace, thereby transferring the test point outside the daughter board area, so that the circuit test can be implemented by connecting the first test point and the ICT equipment with a test probe, effectively improving the test accuracy and pass rate of the PCBA circuit test.

[0013] Optionally, in some embodiments of the present application, the redundant material area is provided with a test area, the test area is connected to a side of the daughter board area close to the binding area, and the first test point and the first test trace are provided in the test area.

[0014] Under this structure, the test area is set close to the binding area. By concentrating the first test point and the first test line in the test area, it is beneficial to shorten the length of the first test line and effectively reduce the equivalent resistance between the first test point and the gold finger.

[0015] Optionally, in some embodiments of the present application, the motherboard includes at least one unit group, and the unit group includes two daughter board areas and two test areas;

[0016] In the unit group, the two test areas are arranged between the two sub-board areas, the two sub-board areas are arranged along a first direction, and the two test areas are arranged along a second direction, and the first direction and the second direction intersect.

[0017] Under this structure, the redundant material area between the two sub-board areas in the same unit group can be fully utilized, effectively improving the space utilization rate of the motherboard.

[0018] Optionally, in some embodiments of the present application, the motherboard includes at least two unit groups arranged along the first direction, and the distance between two adjacent unit groups is smaller than the distance between two sub-board areas in the unit group.

[0019] Under this structure, by reducing the distance between two adjacent unit groups, the area of ​​the redundant material area can be reduced, thereby avoiding material waste.

[0020] Optionally, in some embodiments of the present application, the first test trace includes a first sub-trace and a second sub-trace;

[0021] The first end of the first sub-route and the first end of the second sub-route are electrically connected, and the first end of the first sub-route and the first end of the second sub-route are electrically connected to the same first test point;

[0022] The second end of the first sub-route and the second end of the second sub-route are electrically connected, and the second end of the first sub-route and the second end of the second sub-route are electrically connected to the same gold finger.

[0023] Under this structure, the first sub-route and the second sub-route are connected in parallel, which is beneficial to reducing the equivalent resistance between the first test point and the gold finger. When the first sub-route or the second sub-route fails, it can also ensure normal conduction between the gold finger and the first test point, effectively improving reliability.

[0024] Optionally, in some embodiments of the present application, the test circuit includes at least two second test points and at least two second test lines, and the second test point is electrically connected to the first test point through the second test line, the gold finger, and the first test line in sequence.

[0025] Under this structure, the second test point is electrically connected to the first test point through the second test trace, the gold finger and the first test trace, thereby transferring the test point outside the daughter board area, so that circuit testing can be achieved by connecting the first test point and the ICT equipment with a test probe, effectively improving the test accuracy and pass rate of the PCBA circuit test.

[0026] Optionally, in some embodiments of the present application, the second test trace includes a third sub-trace and a fourth sub-trace;

[0027] The first end of the third sub-route is electrically connected to the first end of the fourth sub-route, and the first end of the third sub-route is electrically connected to the same second test point;

[0028] The second end of the third sub-route is electrically connected to the second end of the fourth sub-route, and the second end of the third sub-route is electrically connected to the same gold finger.

[0029] Under this structure, the third sub-route and the fourth sub-route are connected in parallel, which is beneficial to reducing the equivalent resistance between the second test point and the gold finger. When the third sub-route or the fourth sub-route fails, it can also ensure normal conduction between the gold finger and the second test point, effectively improving reliability.

[0030] Optionally, in some embodiments of the present application, one first test line connects at least two first test points.

[0031] Under this structure, when one of the first test points corresponding to one of the first test lines fails due to being blocked by foreign objects, the circuit test of this first test line can be performed through other first test points to ensure the normal transmission of the test signal and effectively improve reliability.

[0032] The present application also provides a method for manufacturing a circuit board, comprising:

[0033] Providing the above motherboard;

[0034] Performing an electrical test on the daughter board area through the first test point; and

[0035] The motherboard is cut to remove the redundant material area of ​​the motherboard and retain the daughterboard area, thereby obtaining the circuit board.

[0036] Under this setting, in the motherboard used, the test circuit in the daughterboard area is electrically connected to the first test point in the redundant material area, so that the test potential of the test circuit is transferred to the redundant material area where no protective layer is set, and the first test point will not be blocked by the protective layer. Therefore, the circuit test can still be realized by connecting the test probe to the first test point and the ICT equipment, effectively improving the test accuracy and pass rate of the PCBA circuit test.

[0037] The present application also provides a circuit board, comprising:

[0038] A binding area is provided on at least one side of the circuit board, and the binding area is provided with a plurality of gold fingers;

[0039] a test circuit, disposed on one side of the binding area, the test circuit being electrically connected to the corresponding gold finger; and

[0040] A protective layer covers the test circuit and exposes the binding area.

[0041] Under this structure, the circuit board is manufactured from the motherboard, and the yield rate of the circuit board is high.

[0042] The embodiment of the present application adopts a motherboard, a circuit board manufacturing method and a circuit board. By electrically connecting the test circuit in the daughter board area to the first test point in the redundant material area, the test potential of the test circuit can be transferred to the redundant material area where a protective layer is not set. The first test point will not be blocked by the protective layer. Therefore, the circuit test can still be implemented by connecting the first test point and the ICT equipment with a test probe, effectively improving the test accuracy and pass rate of the circuit test of the PCBA. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 This is a structural diagram of an existing PCBA;

[0045] Figure 2 It is a structural diagram of an improved PCBA;

[0046] Figure 3 This is a structural diagram of an existing motherboard;

[0047] Figure 4 This is a schematic structural diagram of the first motherboard provided in an embodiment of the present application;

[0048] Figure 5 yes Figure 4 Schematic diagram of the enlarged structure of the A1 region;

[0049] Figure 6 It is along Figure 5 Schematic diagram of the cross-sectional structure in the B1-B1 direction;

[0050] Figure 7 This is a schematic structural diagram of the second motherboard provided in an embodiment of the present application;

[0051] Figure 8 yes Figure 7 Schematic diagram of the enlarged structure of the A2 region;

[0052] Figure 9 It is along Figure 8 Schematic diagram of the cross-sectional structure in the B2-B2 direction;

[0053] Figure 10 It is a schematic diagram of the structure of the circuit board provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0055] Figure 1 The figure is a structural diagram of an existing PCBA 10. The PCBA 10 is provided with a solder resist layer 11. The solder resist layer 11 covers the surface of the PCBA 10 and is used to improve the antistatic ability of the PCBA 10. Figure 1 In the PCBA 10 shown, the PCBA 10 further has a test point 12 , and the solder mask layer 11 covers the test point 12 . Since the test point 12 is covered by the solder mask layer 11 , the traditional measurement method of using a test probe to connect the test point 12 of the PCBA 10 is no longer applicable.

[0056] Figure 2 This is a schematic diagram of the structure of an improved PCBA 10. A solder resist layer 11 is provided on the PCBA 10. The solder resist layer 11 covers the surface of the PCBA 10 and is used to improve the antistatic ability of the PCBA 10. Figure 2 In the illustrated PCBA 10, the PCBA 10 is further provided with in-plane test points 15 and a bonding area 13. The solder mask 11 covers the in-plane test points 15. The bonding area 13 is provided with multiple gold fingers 14. The in-plane test points 15 are electrically connected to corresponding gold fingers 14. To perform circuit testing on the PCBA 10, a flexible flat cable 20 can be provided. The flexible flat cable 20 is provided with out-of-plane test points 21. By pressing the flexible flat cable 20 onto the corresponding gold fingers 14, the in-plane test points 15 are electrically connected to the out-of-plane test points 21 of the flexible flat cable 20 through the gold fingers 14. A test probe is used to connect the out-of-plane test points 21 of the flexible flat cable 20 to the ICT equipment. By collecting signals from each out-of-plane test point 21, the test is completed and the ICT pass rate is determined.

[0057] but, Figure 2When the PCBA 10 shown is undergoing circuit testing, since the binding area 13 of the PCBA 10 is provided with multiple gold fingers 14, it is difficult for the flexible flat cable 20 to be accurately pressed onto the corresponding gold fingers 14. When the flexible flat cable 20 is not accurately pressed onto the corresponding gold fingers 14, misjudgment is likely to occur, which undoubtedly reduces the test accuracy. When the circuit test result is poor, in order to avoid misjudgment, the operator needs to repeat the circuit test, which undoubtedly increases the time cost and greatly reduces the pass rate of the circuit test.

[0058] Figure 3 This is a schematic structural diagram of an existing motherboard 30. Figure 1 and Figure 2 The motherboard corresponding to the PCBA 10 shown is as follows Figure 3 As shown, a motherboard 30 includes multiple PCBs 31. A fabrication plant assembles electronic components on the PCBs 31 to produce a PCBA 10. A redundant material area 32 is provided between two adjacent PCBs 31. This redundant material area 32 is relatively wide and underutilized, which undoubtedly leads to material waste.

[0059] The present invention provides a motherboard, a method for manufacturing a circuit board, and a circuit board. Detailed descriptions are provided below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments.

[0060] See also Figure 4 An embodiment of the present application provides a motherboard 100, including at least one daughter board area Sub, a protective layer 170 and a redundant material area R. The daughter board area Sub is provided with a test circuit TC, the protective layer 170 covers the daughter board area Sub, the redundant material area R is connected to at least one side of the daughter board area Sub, and the redundant material area R is provided with at least two first test points TP1, and the first test points TP1 are electrically connected to the test circuit TC.

[0061] In an embodiment of the present application, by electrically connecting the test circuit TC of the sub-board area Sub to the first test point TP1 of the redundant material area R, the test potential of the test circuit TC can be transferred to the redundant material area R where the protective layer 170 is not set. The first test point TP1 will not be blocked by the protective layer 170. Therefore, the circuit test can still be implemented by connecting the first test point TP1 and the ICT equipment with a test probe, thereby effectively improving the test accuracy and pass rate of the circuit test of the PCBA.

[0062] Specifically, such as Figure 4As shown, the redundant material area R is further provided with at least two first test traces TL1, which are electrically connected to the first test point TP1. The test circuit TC is electrically connected to the first test point TP1 via the first test point TP1. The sub-board area Sub includes a binding area BA, which is provided with a plurality of gold fingers GF. The test circuit TC is electrically connected to the gold fingers GF, so that the test circuit TC is electrically connected to the first test point TP1 via the gold fingers GF and the first test traces TL1.

[0063] Under this structure, the test circuit TC is electrically connected to the first test point TP1 through the gold finger GF and the first test trace TL1, thereby transferring the test point to outside the sub-board area Sub, so that circuit testing can be implemented by connecting the first test point TP1 and the ICT equipment using a test probe, effectively improving the test accuracy and pass rate of the PCBA circuit test.

[0064] Specifically, such as Figure 4 As shown, the redundant material area R is provided with a test area TA, which is connected to a side of the sub-board area Sub close to the binding area BA, and the first test point TP1 and the first test trace TL1 are provided in the test area TA.

[0065] Under this structure, the test area TA is set close to the binding area BA. By concentrating the first test point TP1 and the first test line TL1 in the test area TA, it is beneficial to shorten the length of the first test line TL1 and effectively reduce the equivalent resistance between the first test point TP1 and the gold finger GF.

[0066] Specifically, such as Figure 4 As shown, motherboard 100 includes at least one unit group UA, which includes two sub-board areas Sub and two test areas TA. Within a unit group UA, two test areas TA are located between two sub-board areas Sub. The two sub-board areas Sub are arranged along a first direction Y, and the two test areas TA are arranged along a second direction X, with the first direction Y and the second direction X intersecting. In this embodiment, the first direction Y and the second direction X are perpendicular. However, depending on the actual situation, the first direction Y and the second direction X can intersect at other angles, and this is not a strict limitation.

[0067] In this structure, the redundant material area R between the two sub-board areas Sub in the same unit group UA can be fully utilized, thereby effectively improving the space utilization of the motherboard 100.

[0068] Specifically, the motherboard 100 includes at least two unit groups UA arranged along the first direction Y, and a distance D1 between two adjacent unit groups UA is smaller than a distance D2 between two sub-board areas Sub in the unit group UA.

[0069] Under this structure, by reducing the distance between two adjacent unit groups UA, the area of ​​the redundant material region R can be reduced, thereby avoiding material waste.

[0070] Specifically, such as Figure 4-Figure 6 As shown, at least one of the first test traces TL1 includes a first sub-trace TL11 and a second sub-trace TL12. For example, a portion of the first test traces TL1 includes the first sub-trace TL11 and the second sub-trace TL12, or each first test trace TL1 includes the first sub-trace TL11 and the second sub-trace TL12, which is not limited here. In one of the first test traces TL1, the first end of the first sub-trace TL11 is electrically connected to the first end of the second sub-trace TL12, and the first end of the first sub-trace TL11 and the first end of the second sub-trace TL12 are electrically connected to the same first test point TP1; the second end of the first sub-trace TL11 is electrically connected to the second end of the second sub-trace TL12, and the second end of the first sub-trace TL11 and the second end of the second sub-trace TL12 are electrically connected to the same gold finger GF.

[0071] Under this structure, the first sub-route TL11 and the second sub-route TL12 are connected in parallel, which is beneficial to reducing the equivalent resistance between the first test point TP1 and the gold finger GF. When the first sub-route TL11 or the second sub-route TL12 fails, it can also ensure that the gold finger GF and the first test point TP1 can be normally connected, effectively improving reliability.

[0072] Specifically, such as Figure 6 As shown, motherboard 100 includes a substrate 110, a first conductive layer 120, a first insulating layer 130, a second conductive layer 140, a second insulating layer 150, and a third conductive layer 160. The first conductive layer 120 is provided on the substrate 110. The first insulating layer 130 covers the first conductive layer 120 and the substrate 110. The second conductive layer 140 is provided on the first insulating layer 130. The second insulating layer 150 covers the second conductive layer 140 and the first insulating layer 130. The third conductive layer 160 is provided on the second insulating layer 150. A protective layer 170 covers the third conductive layer 160 and the second insulating layer 150.

[0073] In the embodiment of the present application, the first sub-trace TL11 and the second sub-trace TL12 are provided on different conductive layers, and their projections on the substrate 110 at least partially overlap, effectively reducing wiring space. Of course, depending on actual circumstances, the first sub-trace TL11 and the second sub-trace TL12 can be provided on the same conductive layer, and this is not intended to be a limitation.

[0074] Specifically, such as Figure 6As shown, the first sub-trace TL11 is provided in the first conductive layer 120, the second sub-trace TL12 is provided in the second conductive layer 140, and the gold finger GF and the first test point TP1 are provided in the third conductive layer 160. Specifically, the first insulating layer 130 is provided with a first via 131 and a second via 132. The first end of the first sub-trace TL11 and the first end of the second sub-trace TL12 are electrically connected through the first via 131, and the second end of the first sub-trace TL11 and the second end of the second sub-trace TL12 are electrically connected through the second via 132. The second insulating layer 150 is provided with a third via 151 and a fourth via 152. The first end of the first sub-trace TL11 and the first test point TP1 are electrically connected through the third via 151, and the second end of the first sub-trace TL11 and the gold finger GF are electrically connected through the fourth via 152.

[0075] Specifically, such as Figure 4 As shown, the test circuit TC includes at least two second test points TP2 and at least two second test traces TL2 , and the second test traces TL2 are electrically connected to the second test points TP2 and the gold fingers GF.

[0076] Under this structure, the second test point TP2 is electrically connected to the first test point TP1 through the second test trace TL2, the gold finger GF and the first test trace TL1, thereby transferring the test point to outside the sub-board area Sub, so as to facilitate circuit testing by connecting the first test point TP1 and the ICT equipment with a test probe, effectively improving the test accuracy and pass rate of the PCBA circuit test.

[0077] Specifically, such as Figure 4-Figure 6 As shown, at least one of the second test traces TL2 includes a third sub-trace TL21 and a fourth sub-trace TL22. For example, some of the second test traces TL2 include the third sub-trace TL21 and the fourth sub-trace TL22, or each second test trace TL2 includes the third sub-trace TL21 and the fourth sub-trace TL22, which is not limited here. In one of the second test traces TL2, the first end of the third sub-trace TL21 and the first end of the fourth sub-trace TL22 are electrically connected, and the first end of the third sub-trace TL21 and the first end of the fourth sub-trace TL22 are electrically connected to the same second test point TP2; the second end of the third sub-trace TL21 and the second end of the fourth sub-trace TL22 are electrically connected, and the second end of the third sub-trace TL21 and the second end of the fourth sub-trace TL22 are electrically connected to the same gold finger GF.

[0078] Under this structure, the third sub-route TL21 and the fourth sub-route TL22 are connected in parallel, which is beneficial to reducing the equivalent resistance between the second test point TP2 and the gold finger GF. When the third sub-route TL21 or the fourth sub-route TL22 fails, it can also ensure that the gold finger GF and the second test point TP2 can be normally connected, effectively improving reliability.

[0079] In the embodiment of the present application, the third sub-trace TL21 and the fourth sub-trace TL22 are provided on different conductive layers, and their projections on the substrate 110 at least partially overlap, effectively reducing wiring space. Of course, depending on actual circumstances, the third sub-trace TL21 and the fourth sub-trace TL22 can be provided on the same conductive layer, and this is not intended to be a limitation.

[0080] Specifically, such as Figure 6 As shown, the third sub-trace TL21 is provided in the first conductive layer 120, the second test point TP2 and the fourth sub-trace TL22 are provided in the second conductive layer 140, and the second test point TP2 is connected to the first end of the fourth sub-trace TL22. The first insulating layer 130 is provided with a fifth via 133 and a sixth via 134. The first end of the third sub-trace TL21 and the first end of the fourth sub-trace TL22 are electrically connected via the fifth via 133, and the second end of the third sub-trace TL21 and the second end of the fourth sub-trace TL22 are electrically connected via the sixth via 134. The second insulating layer 150 is provided with a seventh via 153. The second end of the third sub-trace TL21 and the gold finger GF are electrically connected via the seventh via 153.

[0081] Specifically, such as Figure 7-Figure 9 As shown, a first test trace TL1 connects at least two first test points TP1. In this structure, if one of the first test points TP1 corresponding to one of the first test traces TL1 fails due to being blocked by a foreign object, circuit testing of the first test trace TL1 can be performed through other first test points TP1, ensuring normal transmission of test signals and effectively improving reliability.

[0082] The present invention also provides a method for manufacturing a circuit board, including:

[0083] Step B11, providing the motherboard 100;

[0084] Step B21, performing electrical testing on the sub-board area Sub through the first test point TP1; and

[0085] Step B31 : cutting the motherboard 100 to remove the redundant material area R of the motherboard 100 and retain the sub-board area Sub, thereby obtaining the circuit board 200 .

[0086] In the motherboard 100 used in the above step B11, the test circuit TC of the daughter board area Sub is electrically connected to the first test point TP1 of the redundant material area R, so that the test potential of the test circuit TC is transferred to the redundant material area R where the protective layer 170 is not set. The first test point TP1 will not be blocked by the protective layer 170. Therefore, the circuit test can still be implemented by connecting the first test point TP1 and the ICT equipment with a test probe, effectively improving the test accuracy and pass rate of the circuit test of the PCBA.

[0087] See also Figure 10 This application also provides a circuit board 200 comprising a bonding area BA, a test circuit TC, and a protective layer 170. The bonding area BA is provided on at least one side of the circuit board 200 and is provided with a plurality of gold fingers GF. The test circuit TC is provided on one side of the bonding area BA and is electrically connected to corresponding gold fingers GF. The protective layer 170 covers the test circuit TC, leaving the bonding area BA exposed. With this structure, the circuit board 200 is manufactured from the motherboard 100 described above, and the yield rate of the circuit board 200 is high.

[0088] It should be noted that the circuit board 200 corresponds to the daughter board area Sub of the motherboard 100. Therefore, the specific structure of the circuit board 200 is the same as that of the daughter board area Sub, and the structure of the circuit board 200 will not be repeated here.

[0089] The above is a detailed introduction to a motherboard, a circuit board manufacturing method, and a circuit board provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present application.

Claims

1. A motherboard, characterized in that: include: at least one daughter board area, wherein the daughter board area is provided with a test circuit; protective layer; as well as a redundant material area, the redundant material area being connected to at least one side of the daughter board area, the redundant material area being provided with at least two first test points and at least two first test traces, the first test points being electrically connected to the test circuit; Wherein, the protective layer covers the sub-board area and stops at the redundant material area; The daughter board area includes a binding area, the binding area is provided with a plurality of gold fingers, and the test circuit is electrically connected to the first test point through the gold fingers and the first test trace in sequence; The motherboard includes a substrate, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer, wherein the first conductive layer is provided on the substrate, the first insulating layer covers the first conductive layer and the substrate, the second conductive layer is provided on the first insulating layer, the second insulating layer covers the second conductive layer and the first insulating layer, the third conductive layer is provided on the second insulating layer, and the protective layer covers the third conductive layer and the second insulating layer; The first test trace includes a first sub-trace and a second sub-trace, and the first sub-trace and the second sub-trace are located in different conductive layers; The first end of the first sub-route and the first end of the second sub-route are electrically connected, and the first end of the first sub-route and the first end of the second sub-route are electrically connected to the same first test point; The second end of the first sub-route and the second end of the second sub-route are electrically connected, and the second end of the first sub-route and the second end of the second sub-route are electrically connected to the same gold finger.

2. The motherboard according to claim 1, wherein: The redundant material area is provided with a test area, the test area is connected to a side of the daughter board area close to the binding area, and the first test point and the first test trace are provided in the test area.

3. The motherboard according to claim 2, wherein: The motherboard includes at least one unit group, and the unit group includes two daughter board areas and two test areas; In the unit group, the two test areas are arranged between the two sub-board areas, the two sub-board areas are arranged along a first direction, and the two test areas are arranged along a second direction, and the first direction and the second direction intersect.

4. The motherboard according to claim 3, wherein: The motherboard includes at least two unit groups arranged along the first direction, and the distance between two adjacent unit groups is smaller than the distance between two daughter board areas in the unit group.

5. The motherboard according to claim 1, wherein: The test circuit includes at least two second test points and at least two second test lines. The second test point is electrically connected to the first test point through the second test line, the gold finger, and the first test line in sequence.

6. The motherboard according to claim 5, wherein: The second test routing includes a third sub-routing and a fourth sub-routing; The first end of the third sub-route is electrically connected to the first end of the fourth sub-route, and the first end of the third sub-route is electrically connected to the same second test point; The second end of the third sub-route is electrically connected to the second end of the fourth sub-route, and the second end of the third sub-route is electrically connected to the same gold finger.

7. The motherboard according to any one of claims 1 to 6, wherein: One first test line connects at least two of the first test points.

8. A method for manufacturing a circuit board, characterized in that: include: Providing a motherboard according to any one of claims 1 to 7; Performing electrical testing on the daughter board area through the first test point; as well as The motherboard is cut to remove the redundant material area of ​​the motherboard and retain the daughterboard area, thereby obtaining the circuit board.

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