High-speed interface testing apparatus, system, and method of testing a high-speed interface

Abstract

This invention relates to a high-speed interface testing device, system, and method, and pertains to the field of integrated circuit testing technology. The device includes: a chip under test (DUT) interface, an external chip interface, a first resistor board, a second resistor board, a first SMA interface, a second SMA interface, a signal integrity test board, and a PSSL board. Among the three interconnected 0-ohm resistors, the first interconnected 0-ohm resistor is connected to the PSSL board, the second interconnected 0-ohm resistor is connected to the external chip interface, and the third interconnected 0-ohm resistor is connected to both the first and second SMA interfaces. A first SI board is connected to both the first and second SMA interfaces. The DUT interface is used to connect to the high-speed interface chip. This three-loop configuration allows for efficient determination of different test items required for high-speed interface chip testing during the programming process, providing a multi-functional and multi-parameter efficient testing method for high-speed interfaces.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, and in particular to a high-speed interface testing device, system, and method for testing high-speed interfaces. Background Technology

[0002] High-speed interfaces are used not only in personal computers, servers, and communication equipment, but also in digital consumer electronics, medical devices, broadcasting equipment, semiconductor manufacturing and testing equipment, and many other electronic devices and applications. Furthermore, with technological advancements and evolution, high-speed interfaces are often integrated with multiple types of functions.

[0003] To ensure the performance of high-speed interfaces, related technologies typically use integrated circuit automatic test equipment (ATE) testing systems to test high-speed interfaces.

[0004] However, traditional ATE testing cannot meet all test requirements for high-speed interfaces that are compatible with multiple test schemes. Therefore, how to provide a design method for an ATE test board for a high-speed interface has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies, thereby providing a high-speed interface testing device, system, and method, offering a multi-functional, multi-parameter, and efficient testing approach for high-speed interfaces. The technical solution is as follows:

[0006] On the one hand, a high-speed interface testing device is provided, which includes a chip under test interface, an external chip interface, a first resistor board, a second resistor board, a first SMA (SubMiniature version A) interface, a second SMA interface, a signal integrity (SI) board, and a PSSL board (please provide the full name of PSSL).

[0007] The first and second resistance plates are each equipped with three interconnected 0-ohm resistors.

[0008] Among the three interconnected 0-ohm resistors, the first interconnected 0-ohm resistor is connected to the PSSL board, the second interconnected 0-ohm resistor is connected to the external chip interface, and the third interconnected 0-ohm resistor is connected to the first SMA interface and the second SMA interface. The first SI board is connected to the first SMA interface and the second SMA interface respectively.

[0009] The interface of the chip under test is used to connect to a high-speed interface chip.

[0010] The external chip interface is used to connect to external chips, which are used to assist in the testing of high-speed interface chips.

[0011] On the other hand, a high-speed interface testing system is provided, which includes a test bench, a computer device, and a high-speed interface testing apparatus as described above. The test bench and the high-speed interface testing apparatus are communicatively connected, and the test bench is equipped with the computer device.

[0012] On the other hand, a testing method for a high-speed interface is provided, which is applied to a computer device within the high-speed interface testing system described above. The method includes:

[0013] Identify the chip under test (DUT) connected to the high-speed interface testing device, as well as the corresponding external chip;

[0014] In response to receiving the signal indicating that the chip under test has been installed and the signal indicating that the external chip has been installed, a programming and decomposition program is generated.

[0015] Configure the burning and decomposition program, and control the test machine and high-speed interface test device to start the test process;

[0016] Read the programming bytes corresponding to the programming decomposition program;

[0017] Based on the byte programming results corresponding to the programmed bytes, the test results corresponding to the chip under test are determined. The test items in the byte programming results are determined by the chip under test, the PSSL board, and the external chip.

[0018] The beneficial effects of the technical solution provided by this invention include at least the following:

[0019] In the device used to test the chip under test, three sets of 0Ω resistors connected to the first and second resistor boards form a three-way circuit connection. During the test, the chip under test forms an external loop with the test bench, a direct connection is formed between the chip under test and the external chip, and a verification loop is formed through the SMA interface and the SI board. During the high-speed interface programming test, the test parameters can be determined through the direct connection between the PSSL board, the chip under test, and the external chip, and the verification results are confirmed by the SI board. Through the three-way circuit setting, different test items for high-speed interface chip testing can be efficiently determined during the programming process, providing a multi-functional and multi-parameter efficient testing method for high-speed interfaces. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 The diagram shows a structural block diagram of a high-speed interface testing apparatus provided in an exemplary embodiment of this application.

[0022] Figure 2 A schematic diagram of a high-speed interface testing system provided in an exemplary embodiment of this application is shown.

[0023] Figure 3 The illustration shows a flowchart of a high-speed interface testing method provided in an exemplary embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0025] Figure 1 This invention provides a structural block diagram of a high-speed interface testing apparatus according to an exemplary embodiment of the present application. Please refer to [the diagram]. Figure 1 The device includes a chip under test (DUT) interface 110, an external chip interface 120, a first resistor board 130, a second resistor board 140, a first SMA interface 150, a second SMA interface 160, an SI board 170, and a PSSL board 180. The first and second resistor boards each have three interconnected 0-ohm resistors. Of these three interconnected 0-ohm resistors, the first interconnected 0-ohm resistor is connected to the PSSL board, the second interconnected 0-ohm resistor is connected to the external chip interface, and the third interconnected 0-ohm resistor is connected to both the first and second SMA interfaces. The first SI board is connected to both the first and second SMA interfaces. The DUT interface is used to connect to a high-speed interface chip, and the external chip interface is used to connect to an external chip, which is used to assist in the testing of the high-speed interface chip.

[0026] Optionally, the high-speed interface testing device shown in this application is applied to the final stage of the high-speed interface production process, that is, to test whether the product can be shipped through high-speed interface chip testing. Please refer to... Figure 1The chip under test (DUT) interface is used to connect to a high-speed interface chip, which is then tested to determine if it has any faults. The external chip interface is used to connect to a functional chip being tested. In this embodiment, the DUT and the external chip are of corresponding types. In one example, the DUT is implemented as an Ethernet chip, exemplarily Ethernet chip CXXXXX8, and the external chip is implemented as the corresponding chip CXXXXX08.

[0027] The operating parameters of the Ethernet chip CXXXXX8 are as follows:

[0028] External reference clock: 25MHz

[0029] 1-channel RGMII: 125MHz DDR

[0030] 4-way 5Gbps Serdes: 20dB

[0031] 4-way 1.25Gbps Serdes: 20dB

[0032] 8 Ethernet ports: External 60-meter Cat5e network cable loopback.

[0033] The external chip CXXXXX08 features an eight-port gigabit Ethernet PHY, an integrated eight-channel independent 10M / 100M / 1000M Ethernet transceiver, and support for two QSGMII interface connections to MACs.

[0034] In the embodiments of this application, by means of... Figure 1 The electrical connection relationship shown indicates that in the high-speed interface test device, the three interconnected 0-ohm resistors correspond to three circuits.

[0035] The first interconnected resistors are connected to the PSSL board, forming the first loop. During testing, the PSSL board is used to perform main parameter tests. In one example, when the PSSL board is implemented as a V93000 test system board and the chip under test is implemented as an Ethernet chip CXXXXX8, the PSSL board's test items include at least one of the following: OS test, XTAL, DC, BSCAN, CHAN, STUCK, and TRANS parameter test items.

[0036] Combination Figure 1 The high-speed interface testing device shown. Figure 2 This illustration shows a schematic diagram of a high-speed interface testing system provided in an exemplary embodiment of this application. Please refer to [the diagram]. Figure 2 The device includes, for example Figure 1 The high-speed interface testing device 210 and the testing machine 220 shown are equipped with computer equipment 221.

[0037] This computer device has the functions of data processing, data reception, and data transmission. Combined with... Figure 1 The high-speed interface testing device shown has a second circuit consisting of a test bench, a 0-ohm resistor, an external chip, and the chip under test (DUT) connected to each other. This circuit is used to test the auxiliary parameters corresponding to the DUT. In one example, when the PSSL board is implemented as a V93000 test system board and the DUT is implemented as an Ethernet chip CXXXXX8, the auxiliary parameter test items include at least one of the following: IRC, PRC, PGM, OTC, FRC, INIT, 5G-RPBS, and 1P25G_PRBS.

[0038] Please refer to Figure 1 In this embodiment, the third interconnected 0-ohm resistor forms a loop with the first SMA interface, the second SMA interface, and the SI board, which is used to verify the signal integrity and content of the parameters obtained from the second loop test.

[0039] In this embodiment, the high-speed interface testing device selects a high-speed board (Meg6), achieves impedance matching by adjusting line width, line spacing, and interlayer reference, optimizes signal quality by using curved traces and equal length processing, optimizes the wiring length based on simulation results, and finally meets the simulation requirements.

[0040] In summary, the apparatus and system provided in this application, in the device for testing the chip under test, form a three-way circuit by connecting three sets of 0Ω resistors correspondingly on the first and second resistor boards. This allows the chip under test to form an external circuit with the testing machine during testing, a direct connection between the chip under test and the external chip, and a verification circuit through the SMA interface and SI board. During the high-speed interface programming test, the test parameters can be determined through the direct connection between the PSSL board and the chip under test and the external chip, and the verification results can be confirmed by the SI board. The three-way circuit setup enables efficient determination of different test items for high-speed interface chip testing during the programming process, providing a multi-functional and multi-parameter efficient testing method for high-speed interfaces.

[0041] Figure 3 This application illustrates a flowchart of a high-speed interface testing method provided in an exemplary embodiment, demonstrating how this method can be applied to applications such as... Figure 2 Taking the computer equipment within the high-speed interface testing system shown as an example, the method includes:

[0042] Step 301: Identify the chip under test connected to the high-speed interface testing device, and the external chip corresponding to the chip under test.

[0043] This process involves configuring the chip under test (DUT) and the external chip for the corresponding system. As mentioned earlier, when the DUT is implemented as CXXXXX8, the external chip is implemented as CXXXXX08.

[0044] Step 302: In response to receiving the signal indicating that the chip under test has been installed and the signal indicating that the external chip has been installed, a programming and decomposition program is generated.

[0045] In this embodiment of the application, after confirming that both the chip under test and the external chip are installed, the test program in the computer device can be started to perform the test. During the test, it is necessary to generate a programming decomposition program, that is, to generate a programming list based on the configuration information of the chip and the test machine.

[0046] Step 303: Configure the burning and decomposition program, and control the test machine and high-speed interface test device to start the test process.

[0047] This process involves configuring and executing the programming and decomposition program described in step 302. In this embodiment, the process further includes determining the pin address corresponding to the chip under test and generating the programming and decomposition program based on the pin address.

[0048] Step 304: Read the burning bytes corresponding to the burning and decomposition program.

[0049] After the programming and decomposition process is executed, the computer device will read the programming results of the chip under test.

[0050] Step 305: Based on the byte programming result corresponding to the programmed bytes, determine the test result corresponding to the chip under test. The test items in the byte programming result are determined by the chip under test, the PSSL board, and the external chip.

[0051] In this embodiment, the process of determining the test result includes determining the number of bits to be programmed and determining the programmed content. Optionally, the computer device determines the number of bits corresponding to the programmed bytes; in response to the number of bits being consistent with the preset number of bits, it determines the content of the bytes corresponding to the programmed bytes; in response to the byte content being consistent with the preset byte content, it determines that the chip under test has passed the test.

[0052] In this embodiment, if a single programming attempt fails, a reprogramming process is executed. Specifically, if the number of bytes is inconsistent with the preset number of bytes, or if the byte content is inconsistent with the preset byte content, a reprogramming procedure is executed; if the number of reprogramming attempts reaches a threshold, the chip under test is determined to have failed the test.

[0053] In this embodiment of the application, when multiple high-speed interface chips on a production line are tested in turn, the sequential testing of the chips to be tested is achieved by modifying the rolling code part of the programming file in the programming program.

[0054] In summary, the method provided in this application embodiment, in the device for testing the chip under test, uses three sets of 0Ω resistors connected to the first and second resistor boards to form a three-way circuit connection. This allows the chip under test to form an external circuit with the testing machine during testing, a direct connection between the chip under test and the external chip, and a verification circuit through the SMA interface and SI board. During the high-speed interface programming test, the test parameters can be determined through the direct connection between the PSSL board and the chip under test and the external chip, and the verification results can be confirmed by the SI board. The three-way circuit setup enables efficient determination of different test items for high-speed interface chip testing during the programming process, providing a multi-functional and multi-parameter efficient testing method for high-speed interfaces.

[0055] The above are merely optional embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-speed interface testing device, characterized in that, The device includes a chip under test interface, an external chip interface, a first resistor board, a second resistor board, a first SMA interface, a second SMA interface, an SI board, and a PSSL board. The first resistor plate and the second resistor plate are each provided with three interconnected 0-ohm resistors; Among the three interconnected 0-ohm resistors, the first interconnected 0-ohm resistor is connected to the PSSL board, the second interconnected 0-ohm resistor is connected to the external chip interface, and the third interconnected 0-ohm resistor is connected to the first SMA interface and the second SMA interface. The SI board is connected to the first SMA interface and the second SMA interface respectively. The interface of the chip under test is used to connect with a high-speed interface chip; The external chip interface is used to connect to an external chip, and the external chip is used to assist in the testing of the high-speed interface chip; Among them, the three interconnected 0-ohm resistors correspond to three loops. The first interconnected resistors are connected to the PSSL board to form the first loop. The test instrument, the second interconnected 0-ohm resistors, the external chip, and the chip under test form the second loop. The third interconnected 0-ohm resistors, the first SMA interface, the second SMA interface, and the SI board form a loop.

2. A high-speed interface testing system, characterized in that, The high-speed interface testing system includes a testing machine and the high-speed interface testing device as described in claim 1; The test bench and the high-speed interface test device are communicatively connected, and the test bench is equipped with computer equipment.

3. A testing method for a high-speed interface, characterized in that, The method is applied to a computer device within the high-speed interface testing system as described in claim 2, and the method includes: Identify the chip under test (DUT) connected to the high-speed interface testing device, and the external chip corresponding to the DUT; In response to receiving the signal indicating that the chip under test has been installed and the signal indicating that the external chip has been installed, a programming and decomposition program is generated. Configure the burning and decomposition program, and control the test machine and the high-speed interface test device to start the test process; Read the programming bytes corresponding to the programming decomposition program; Based on the byte programming results corresponding to the programmed bytes, the test results corresponding to the chip under test are determined. The test items in the byte programming results are determined by the chip under test, the PSSL board, and the external chip.

4. The testing method for high-speed interfaces according to claim 3, characterized in that, The step of determining the test result corresponding to the chip under test based on the byte programming result corresponding to the programmed byte includes: Determine the number of bytes corresponding to the programmed bytes; In response to the fact that the number of bytes is consistent with the preset number of bytes, the byte content corresponding to the burned bytes is determined; If the byte content matches the preset byte content, the chip under test is determined to have passed the test.

5. The testing method for high-speed interfaces according to claim 4, characterized in that, The method further includes: In response to a discrepancy between the number of bytes and the preset number of bytes, or a discrepancy between the byte content and the preset byte content, a burn-in procedure is executed. When the number of times the burn-in procedure is executed reaches a threshold, it is determined that the chip under test has failed the test.

6. The testing method for high-speed interfaces according to claim 3, characterized in that, The configuration burning and decomposition program includes: Determine the pin address corresponding to the chip under test; The programming and decomposition program is generated based on the pin address.

7. The testing method for high-speed interfaces according to claim 3, characterized in that, The method further includes: In the burning and decomposition process, the rolling code portion corresponding to the burning file is modified.

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