Circuit diagram inspection method and device, computer device and storage medium

Abstract

The application relates to a circuit diagram checking method and device, computer equipment, a storage medium and a computer program product. The method comprises the following steps: obtaining a target net list of a circuit to be checked, the target net list comprising a connection relationship between each pin of the circuit to be checked; simulating the circuit to be checked based on the target net list; if the simulation determines that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit unit, no special element is arranged between two connected external pins of the circuit to be checked. The method can avoid errors in a circuit layout converted from a circuit schematic diagram.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a circuit diagram checking method and device, computer equipment, a storage medium and a computer program product. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor structure in electronic devices such as computers. DRAM includes a peripheral circuit and a plurality of memory cells, and the reading and writing of data by each memory cell is controlled by the peripheral circuit. SUMMARY

[0003] The present application provides a circuit diagram checking method and device, computer equipment, a computer readable storage medium and a computer program product.

[0004] In a first aspect, the present application provides a circuit diagram checking method. The method comprises:

[0005] obtaining a target netlist of a circuit to be checked, the target netlist comprising connection relationships between pins of the circuit to be checked;

[0006] simulating the circuit to be checked based on the target netlist;

[0007] if the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit unit, then no special element is set between two connected external pins of the circuit to be checked.

[0008] In one of the embodiments, the simulating the circuit to be checked based on the target netlist comprises:

[0009] inputting the target netlist into simulation software;

[0010] obtaining a simulation result obtained by the simulation software simulating the circuit to be checked;

[0011] determining whether the number of external pins of the circuit to be checked is the same as the number of pins of the connected internal circuit unit according to the simulation result.

[0012] In one of the embodiments, the determining whether the number of external pins of the circuit to be checked is the same as the number of pins of the connected internal circuit unit according to the simulation result comprises:

[0013] if the simulation exits and an error of pin number mismatch occurs, then it is determined that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit unit;

[0014] If the simulation is completed, it is determined that the number of external pins of the circuit to be checked is the same as the number of pins of the connected internal circuit unit.

[0015] In one embodiment, the method further comprises:

[0016] If the simulation determines that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit unit, it is determined that a pin combination of a special element is not set, the pin combination being two connected external pins in the circuit to be checked.

[0017] In one embodiment, the determination of the pin combination of the special element not being set comprises:

[0018] The external pins of the circuit to be checked and the pins of the connected internal circuit unit are obtained from the target netlist respectively;

[0019] The external pins of the circuit to be checked and the pins of the connected internal circuit unit are compared to determine the different pins in the external pins of the circuit to be checked and the pins of the connected internal circuit unit, and the pin combination is obtained.

[0020] In one embodiment, the method further comprises:

[0021] A special element is set between the two external pins in the determined pin combination, and an updated circuit schematic diagram is obtained.

[0022] In one embodiment, the method further comprises:

[0023] The circuit schematic diagram is converted into a circuit layout.

[0024] In one embodiment, the target netlist of the circuit to be checked is obtained, comprising:

[0025] The circuit to be checked is determined;

[0026] The netlist of the determined circuit to be checked is obtained, and the target netlist is obtained.

[0027] In one embodiment, the circuit to be checked is determined, comprising:

[0028] The target circuit input by the user is received, and the circuit to be checked is obtained.

[0029] In one embodiment, the circuit to be checked is determined, comprising:

[0030] The non-target circuit input by the user is received;

[0031] The non-target circuit is deleted from the total circuit, and the circuit to be checked is obtained.

[0032] In one of the embodiments, the method further comprises:

[0033] If the simulation determines that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit units, it is determined that no special element is arranged between the two connected external pins of the circuit to be checked.

[0034] In a second aspect, the present application further provides a circuit diagram checking device. The device comprises:

[0035] The acquisition module is configured to acquire a target netlist of a circuit to be checked, the target netlist comprising connection relationships between pins of the circuit to be checked;

[0036] The simulation module is configured to simulate the circuit to be checked based on the target netlist;

[0037] The determination module is configured to determine that no special element is arranged between the two connected external pins of the circuit to be checked, if the simulation determines that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit units.

[0038] In a third aspect, the present application further provides a computer device. The computer device comprises a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0039] acquiring a target netlist of a circuit to be checked, the target netlist comprising connection relationships between pins of the circuit to be checked;

[0040] simulating the circuit to be checked based on the target netlist;

[0041] If the simulation determines that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit units, it is determined that no special element is arranged between the two connected external pins of the circuit to be checked.

[0042] In a fourth aspect, the present application further provides a computer readable storage medium. The computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the following steps:

[0043] acquiring a target netlist of a circuit to be checked, the target netlist comprising connection relationships between pins of the circuit to be checked;

[0044] simulating the circuit to be checked based on the target netlist;

[0045] If the simulation determines that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit units, it is determined that no special element is arranged between the two connected external pins of the circuit to be checked.

[0046] In a fifth aspect, the present application provides a computer program product. The computer program product comprises a computer program which, when executed by a processor, implements the following steps:

[0047] obtaining a target netlist of the circuit to be checked, the target netlist comprising connection relationships between pins of the circuit to be checked;

[0048] performing simulation on the circuit to be checked based on the target netlist;

[0049] if the simulation determines that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit unit, no special element is arranged between the two connected external pins of the circuit to be checked.

[0050] The circuit diagram checking method, device, computer device, storage medium and computer program product described above, by obtaining a target netlist of the circuit to be checked, the target netlist comprising connection relationships between pins of the circuit to be checked, thereby performing simulation on the circuit to be checked based on the target netlist. For a feedthrough net, if no special circuit marking element brknetM4 is arranged between the two wires of the feedthrough net, the number of pins of the feedthrough net is externally recognized as two, but internally recognized as only one, that is, the number of external pins of the feedthrough net is different from the number of pins of the internal circuit unit. Therefore, if the simulation determines that the number of external pins of the circuit to be checked is different from the number of pins of the internal circuit unit, no special element is arranged between the two connected external pins of the circuit to be checked, thereby performing simulation on the netlist of the circuit to be checked, and according to the simulation result, it can be determined whether the two wires of the feedthrough net are connected through the special circuit marking element brknetM4. The whole process is simple and convenient, which can quickly check the feedthrough net, avoid misusing parasitic RC cells or directly connecting between the two wires of the feedthrough net, and further avoid errors in the circuit layout converted from the circuit schematic diagram. In this way, problems can be found in the early design stage, which is conducive to timely processing of problems and minimizing losses caused by problems. BRIEF DESCRIPTION OF DRAWINGS

[0051] Figure 1 An application environment diagram of the circuit diagram checking method in one embodiment;

[0052] Figure 2 A circuit schematic diagram of part of the circuit in one embodiment;

[0053] Figure 3 For one embodiment Figure 2 Corresponding circuit layout;

[0054] Figure 4 For one embodiment

[0055] Figure 5 For one embodiment

[0056] Figure 6 For one embodiment

[0057] Figure 7 For one embodiment Figure 2 Corresponding external circuit layout;

[0058] Figure 8 For one embodiment

[0059] Figure 9 For one embodiment

[0060] Figure 10 For one embodiment

[0061] Figure 11 For one embodiment

[0062] Figure 12 For one embodiment

[0063] Explanation of reference numerals:

[0064] 102, terminal, 104, server;

[0065] 211, first connecting line, 212, second connecting line, 213, third connecting line, 214, fourth connecting line;

[0066] 220, brknetM4;

[0067] 230, parasitic RC cell;

[0068] 240, special mark layer;

[0069] 251, first pin, 252, second pin, 253, third pin, 254, fourth pin;

[0070] 260, equivalent connecting line;

[0071] 271, Pin 5; 272, Pin 6; 273, Pin 7; 274, Pin 8. Detailed Implementation

[0072] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0073] The circuit diagram inspection method provided in this application embodiment can be applied to, for example... Figure 1 The application environment shown is illustrated. Terminal 102 is communicatively connected to server 104. Server 104 stores various component models required for circuit design. Terminal 102 retrieves the circuit schematic of DRAM from server 104 to convert the circuit schematic into a circuit layout for DRAM production. Server 104 can be located locally on terminal 102, such as integrated with terminal 102, or it can be located remotely. Specifically, terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, and tablets. Server 104 can be implemented using a standalone server or a server cluster consisting of multiple servers.

[0074] In DRAM design, some circuits contain feedthrough nets. A feedthrough net consists of two interconnected lines (nets) with different markings, which are connected by a special circuit marking element called brknetM4.

[0075] However, designers may mistakenly use parasitic RC cells or connect them directly between two lines in a feedthrough net, causing errors in the circuit layout converted from the schematic.

[0076] like Figure 2 In the circuit shown, two feedthrough nets are designed: the first feedthrough net has two connections, namely the first connection 211 and the second connection 212, which are connected by a special circuit marking element brknetM4 220; the second feedthrough net has two connections, namely the third connection 213 and the fourth connection 214, which are connected by a parasitic RC cell 230.

[0077] BrknetM4 is a special marker layer (break net) for the fourth metal layer (M4). If brknetM4 is used in the circuit schematic, when converting the schematic to a circuit layout, the corresponding layout location of brknetM4 will have separate pins connected to the two lines of the feedthrough net. Figure 2 For example, the first connection 211 and the second connection 212 are connected using a special circuit marking element, brknetM4 220, which is converted into a circuit layout as follows: Figure 3 As shown, a special marking layer 240 is provided between the first connection 211 and the second connection 212. The special marking layer 240 is connected to the first end of the first connection 211 and the first end of the second connection 212. The second end of the first connection 211 is designated as the first pin 251 of the circuit, and the second end of the second connection 212 is designated as the second pin 252 of the circuit. That is, the first pin 251, the first connection 211, the special marking layer 240, the second connection 212, and the second pin 252 are connected in sequence. In this way, due to the presence of the special marking layer 240, the first connection 211 and the second connection 212 will be identified as two separate connections.

[0078] A parasitic RC cell is a circuit element that marks parasitic resistance and capacitance information. It can simulate the capacitance and resistance information of interconnects for simulation, improving the accuracy of simulation results. If a parasitic RC cell is used in the circuit schematic, the corresponding layout location of the parasitic RC cell will be recognized as a connection line when the schematic is converted to a circuit layout. Figure 2 For example, the third connection 213 and the fourth connection 214 are connected using a parasitic RC cell 230, which can be converted into a circuit layout as follows: Figure 3 As shown, the third connection 213 and the fourth connection 214 are connected by an equivalent connection 260. Although there are three connections in total—the third connection 213, the fourth connection 214, and the connection corresponding to the parasitic RC cell 230—the circuit layout will recognize multiple sequentially connected connections as a single connection. Therefore, the third connection 213, the fourth connection 214, and the connection corresponding to the parasitic RC cell 230 are converted into the equivalent connection 260. At this time, there is only one connection (equivalent connection 260) in the circuit layout, which is the same as a direct connection. However, the circuit schematic has two connections with different markings (the third connection 213 and the fourth connection 214), which will cause an error when comparing the circuit layout with the circuit schematic.

[0079] In order to avoid the error of the circuit layout converted from the circuit schematic, a special circuit marking element brknetM4 is usually added between the two lines of the feedthrough net, that is, the two lines of the feedthrough net are connected through the brknetM4. However, when designing the DRAM circuit, there may be a case that a parasitic RC cell is misused or the two lines of the feedthrough net are directly connected, that is, the special circuit marking element brknetM4 is not added between the two lines of the feedthrough net, thereby causing the error of the circuit layout converted from the circuit schematic.

[0080] In the related art, after the circuit layout is converted from the circuit schematic, the circuit layout is compared with the circuit schematic to find problems. However, this can only find problems in the later stage of design, which may cause unnecessary loss.

[0081] To solve the above problems, embodiments of the present application provide a circuit diagram checking method, device, computer equipment, storage medium and computer program product, which simulates the connection relationship between pins in the circuit netlist. The number of pins of the feedthrough net is externally identified as two, but if the special circuit marking element brknetM4 is not set between the two lines of the feedthrough net, the two lines of the feedthrough net will be defaulted as one line, causing the number of pins to be internally identified as only one. Therefore, whether the number of external pins of the feedthrough net in the simulation result is the same as the number of pins of the internal circuit unit can determine whether the two lines of the feedthrough net are connected through the special circuit marking element brknetM4. The whole process is simple and convenient, which can quickly check the feedthrough net, avoid misusing the parasitic RC cell or directly connecting the two lines of the feedthrough net, and further avoid the error of the circuit layout converted from the circuit schematic. In this way, problems can be found in the early stage of design, which is beneficial to timely processing of the problems and reduces the loss caused by the problems as much as possible.

[0082] In one embodiment, as shown in Figure 4 , a circuit diagram checking method is provided. Taking the terminal in Figure 1 as an example, the method includes the following steps:

[0083] Step 402, obtaining a target netlist of a circuit to be checked.

[0084] The to-be-inspected circuit is a circuit to be inspected in the DRAM circuit. For example, the DRAM circuit includes an address decoding circuit, an amplification circuit, a data buffer circuit, a power supply circuit, and the like, and the to-be-inspected circuit can be the amplification circuit, the data buffer circuit, or the power supply circuit.

[0085] The netlist is a standard static parasitic parameter (Standard Parasitic Format netlist, for short: SPF) information table. By obtaining the netlist, the external pins of the circuit, the internal circuit units, the external pins of the circuit units, and the connection relationship between the pins can be obtained from the netlist. Therefore, the target netlist includes the connection relationship between the pins of the to-be-inspected circuit.

[0086] The pin is a wire leading out from the internal circuit to connect with the external circuit, that is, the interface of the circuit. The external pin of the to-be-inspected circuit is the interface of the to-be-inspected circuit connected with the external circuit, and the external pin of the circuit unit is the interface of the circuit unit connected with the external circuit.

[0087] For example, the to-be-inspected circuit is internally provided with a circuit unit A, a circuit unit B, a circuit unit C, and a circuit unit D, the output end of the circuit unit A and the output end of the circuit unit B are respectively connected with the input end of the circuit unit C, and the circuit unit D is independently provided from the circuit unit A, the circuit unit B, and the circuit unit C. At this time, the input end of the circuit unit A, the input end of the circuit unit B, and the input end of the circuit unit D are three input ends of the to-be-inspected circuit, and the output end of the circuit unit C and the output end of the circuit unit D are two output ends of the to-be-inspected circuit. In this way, the external pin of the to-be-inspected circuit includes three input ends and two output ends of the to-be-inspected circuit, and the pin of the internal circuit unit includes the input end and the output end of the circuit unit A, the input end and the output end of the circuit unit B, the input end and the output end of the circuit unit C, and the input end and the output end of the circuit unit D.

[0088] Optionally, the terminal receives the circuit identification input by the user, and according to the circuit identification, the software program is called to obtain the netlist of the to-be-inspected circuit, that is, the target netlist.

[0089] In step 404, the to-be-inspected circuit is simulated based on the target netlist.

[0090] The simulation is to simulate the operation of the circuit. During the simulation process, the connection between the pins is checked first, and when a problem is found, an error is reported in time. By checking the simulation result, it can be determined whether the external pin of the to-be-inspected circuit and the pin of the internal circuit unit are one-to-one corresponding in the early stage, and whether the two connection lines of the feedthrough net are connected through the special circuit marker element brknetM4.

[0091] Step 406: If the simulation determines that the number of external pins of the circuit under test is different from the number of pins of the connected internal circuit units, no special element is set between the two connected external pins of the circuit under test.

[0092] Optionally, if the simulation determines that the number of external pins of the circuit under test is the same as the number of pins of the connected internal circuit units, a special element is set between the two connected external pins of the circuit under test.

[0093] The number of external pins of the circuit under test is the number of all pins of the circuit under test connected to external circuits. The number of pins of the internal circuit units connected by the external pins of the circuit under test is the number of all pins of the internal circuit units connected to the external pins of the circuit under test, and does not include the number of pins connected between the internal circuit units.

[0094] Still taking the example that the circuit under test is internally provided with circuit unit A, circuit unit B, circuit unit C, and circuit unit D, the external pins of the circuit under test include three input terminals and two output terminals of the circuit under test, and the number is five. Under normal circumstances, the pins of the internal circuit units connected by the external pins of the circuit under test include the input terminal of circuit unit A, the input terminal of circuit unit B, the input terminal of circuit unit D, the output terminal of circuit unit C, and the output terminal of circuit unit D, and the number is also five. The output terminal of circuit unit A, the output terminal of circuit unit B, and the input terminal of circuit unit C belong to the pins connected between the internal circuit units, and are not included in the number of pins of the internal circuit units connected by the external pins of the circuit under test.

[0095] If circuit unit D is a feedthrough net, and parasitic RC cell is used inside circuit unit D or is directly connected, circuit unit D will be determined as a wire in the circuit layout, and only one of the input terminal and the output terminal of circuit unit D will be identified when the netlist is obtained, and the number of pins of circuit unit D is only one. However, the number of external pins corresponding to the circuit under test is two, so the simulation result will appear an error, and the error content is that the external pins of the circuit under test do not correspond to the pins of the internal circuit units one by one, and according to the error content, it can be determined that no special circuit marker element brknetM4 is added inside circuit unit D.

[0096] If the circuit unit D is a feedthrough net, and a special circuit marking element brknetM4 is used inside the circuit unit D, the circuit unit D will be identified with two wires in the circuit layout, connecting the input and output of the circuit unit D, and the input and output of the circuit unit D will be identified when the netlist is obtained, and the number of pins of the circuit unit D is two. Meanwhile, the number of external pins of the to-be-checked circuit is also two, so the simulation result will show a pass or success message, according to which it can be determined that the external pins of the to-be-checked circuit correspond to the pins of the internal circuit unit one by one, and it is further determined that the special circuit marking element brknetM4 is added inside the circuit unit D.

[0097] Optionally, the terminal controls the running of the simulation software according to the information in the target netlist, so as to simulate the to-be-checked circuit.

[0098] In the above circuit diagram checking method, the target netlist of the to-be-checked circuit is obtained, the target netlist includes the connection relationship between each pin of the to-be-checked circuit, and the to-be-checked circuit is simulated based on the target netlist. For the feedthrough net with two wires connected to each other, if no special circuit marking element brknetM4 is set between the two wires of the feedthrough net, the number of pins of the feedthrough net is two from the outside, but only one from the inside, that is, the number of external pins of the feedthrough net is different from the number of pins of the internal circuit unit. Therefore, if the simulation determines that the number of external pins of the to-be-checked circuit is different from the number of pins of the internal circuit unit, it is determined that no special element is set between the two external pins of the to-be-checked circuit, and the to-be-checked circuit is simulated through the netlist of the to-be-checked circuit, and according to the simulation result, it can be determined whether the two wires of the feedthrough net are connected through the special circuit marking element brknetM4. The whole process is simple and convenient, and the feedthrough net can be quickly checked, and the parasitic RC cell or direct connection between the two wires of the feedthrough net is avoided, and the error of the circuit layout converted from the circuit schematic diagram is avoided. In this way, the problem is found in the early stage of design, which is conducive to timely processing of the problem and reduces the loss caused by the problem as much as possible.

[0099] In one embodiment, as shown in FIG. 4, step 402 includes: Figure 5

[0100] Step 502, determining a to-be-checked circuit.

[0101] ​Optionally, the terminal is provided with an input module, such as a mouse, a keyboard, a knob, a touch screen, etc., and the user can input the circuit of his own choice through the input module. After receiving the circuit of the user's choice, the terminal can determine the circuit to be checked according to the circuit of the user's choice.

[0102] Further, the terminal is also provided with an output module, such as a display screen, etc., and the user can obtain all the circuits of the DRAM through the output module so as to select the circuit therefrom.

[0103] Step 504: obtaining the netlist of the determined circuit to be checked to obtain a target netlist.

[0104] Optionally, the terminal extracts the corresponding netlist according to the determined circuit to be checked, thereby obtaining the target netlist. Specifically, the extraction of the netlist can be performed through the parameter-dependent lookup (ADL) interface provided by the virtuoso software.

[0105] In the above embodiment, the circuit to be checked is first determined, and then the netlist of the determined circuit to be checked is extracted by using the software tool, thereby obtaining the target netlist of the circuit of the user's choice for checking the circuit of the user's choice.

[0106] In one embodiment, step 502 includes: receiving the target circuit input by the user to obtain the circuit to be checked.

[0107] Optionally, the terminal receives the name of the target circuit and takes the circuit corresponding to the name as the circuit to be checked.

[0108] In another embodiment, step 502 includes: receiving the non-target circuit input by the user; and deleting the non-target circuit from the total circuit to obtain the circuit to be checked.

[0109] Optionally, the terminal is provided with a storage, such as a hard disk, etc., and the entire DRAM circuit can be pre-stored. After receiving the name of the non-target circuit, the non-target circuit in the total circuit of the DRAM is deleted according to the name, and the remaining circuit is the circuit to be checked.

[0110] In the above embodiment, the circuit input by the user can be the target circuit corresponding to the circuit to be checked, or the non-target circuit corresponding to the circuit other than the circuit to be checked. If the number of the circuit to be checked is small, the target circuit is inputted to directly obtain the circuit to be checked, so as to quickly extract the netlist of the circuit to be checked. If the number of the circuit to be checked is large, the non-target circuit is inputted, so that the number of the circuit input by the user is small, thereby facilitating the use of the user.

[0111] In one embodiment, as shown in FIG. 4A, step 404 includes: Figure 6

[0112] Step 602: inputting the target netlist into the simulation software.​

[0113] Optionally, the simulation software is provided with an input interface, which can be a script, etc. The terminal calls the target netlist through the input interface to run the simulation software based on the target netlist to simulate the operation of the circuit to be checked.

[0114] In step 604, a simulation result obtained by the simulation software simulating the circuit to be checked is acquired.

[0115] The simulation result is the content output by the simulation software when the simulation software stops running. Whether the simulation is completed or not, the simulation software will output the simulation result when it stops running. If a problem is found during the running, the simulation software will stop running and report an error. If the running is completed, the simulation software will stop running and output a message that the simulation is completed or successful. As can be seen, the simulation result can indicate whether the simulation is completed and the reason why the simulation is not completed. The simulation result of the circuit to be checked is acquired, so that whether the simulation is completed and the reason why the simulation is not completed can be determined, and then whether the number of external pins of the circuit to be checked is the same as the number of pins of the internal circuit unit connected thereto can be determined.

[0116] Optionally, the simulation software is provided with an output interface, and the terminal acquires the simulation result through the output interface.

[0117] In step 606, whether the number of external pins of the circuit to be checked is the same as the number of pins of the internal circuit unit connected thereto is determined according to the simulation result.

[0118] Optionally, the connection between each pin is checked during the simulation. If the number of external pins of the circuit to be checked is different from the number of pins of the internal circuit unit connected thereto, the simulation is exited and an error of pin number mismatch is reported. If the number of external pins of the circuit to be checked is the same as the number of pins of the internal circuit unit connected thereto, the following process can be smoothly entered. Therefore, if the simulation is exited and the error of pin number mismatch is reported, it is determined that the number of external pins of the circuit to be checked is different from the number of pins of the internal circuit unit connected thereto. If the simulation is completed or the error of the following process is reported, it is determined that the number of external pins of the circuit to be checked is the same as the number of pins of the internal circuit unit connected thereto.

[0119] Still taking the Figure 2 as an example, the two ends of the first feedthrough net are the first pin 251 and the second pin 252, and a special circuit marking element brknetM4 220 is used between the first pin 251 and the second pin 252. The two ends of the second feedthrough net are the third pin 253 and the fourth pin 254, and a parasitic RC cell 230 is used between the third pin 253 and the fourth pin 254.

[0120] AsFigure 7 As shown, two feedthrough nets constitute the to-be-checked circuit. The to-be-checked circuit includes four external pins, i.e., a fifth pin 271 connected with the first pin 251, a sixth pin 272 connected with the second pin 252, a seventh pin 273 connected with the third pin 253, and an eighth pin 274 connected with the fourth pin 254.

[0121] Simulation is performed on the to-be-checked circuit constituted by the two feedthrough nets, and it is found that the external pins of the to-be-checked circuit are the fifth pin 271, the sixth pin 272, the seventh pin 273, and the eighth pin 274, and the number of the external pins is four. Since the special circuit marking element brknetM4 220 is used between the first pin 251 and the second pin 252, both the first pin 251 and the second pin 252 can be recognized by the simulation software. However, the parasitic RC cell 230 is used between the third pin 253 and the fourth pin 254, and the simulation software can only recognize the third pin 253, and mistakenly considers that the fourth pin 254 is the same pin as the third pin 253. In summary, the simulation obtains the pins of the internal circuit unit as the first pin 251, the second pin 252, and the third pin 253, and the number of the pins is three. It can be seen that the number of the external pins of the to-be-checked circuit is different from the number of the pins of the connected internal circuit unit, and thus the two connecting lines of the feedthrough net are not connected by the special circuit marking element brknetM4, specifically, the second feedthrough net.

[0122] In the above embodiment, the target netlist is input into the simulation software, so that the simulation software simulates the to-be-checked circuit. The simulation result obtained by the simulation software simulating the to-be-checked circuit is acquired, and according to the simulation result, it is determined whether the number of the external pins of the to-be-checked circuit is the same as the number of the pins of the connected internal circuit unit, and then it is determined whether the two connecting lines of the feedthrough net are connected by the special circuit marking element brknetM4. The whole process is simple and convenient, and the feedthrough net can be quickly checked, and the two connecting lines of the feedthrough net are prevented from being mistakenly connected by the parasitic RC cell or directly connected, and thus the error of the circuit layout converted from the circuit schematic diagram is avoided.

[0123] In one embodiment, the method further includes: if the simulation determines that the number of the external pins of the to-be-checked circuit is different from the number of the pins of the connected internal circuit unit, determining that the pin combination of the special element is not set, and the pin combination is two connected external pins in the to-be-checked circuit.

[0124] Wherein, the pin combination is feedthrough net, and the special element is brknetM4.

[0125] In the above embodiment, if the simulation determines that the number of external pins of the to-be-inspected circuit is different from the number of pins of the connected internal circuit unit, it is determined that there is a feedthrough net in the to-be-inspected circuit that does not use brknetM4. The feedthrough net that does not use brknetM4 is found, and brknetM4 is added in the found feedthrough net, so as to optimize the circuit schematic diagram and avoid errors in the circuit layout converted from the circuit schematic diagram. In this way, the problem is found in the early stage of design, which is conducive to timely processing of the problem and reduces the loss caused by the problem as much as possible.

[0126] In one embodiment, as shown in Figure 8 , the pin combination without the special element is determined, including:

[0127] Step 802, respectively acquiring the external pins of the to-be-inspected circuit and the pins of the connected internal circuit unit from the target netlist.

[0128] Optionally, the target netlist includes the connection relationship between each pin of the to-be-inspected circuit. The terminal can obtain each external pin of the to-be-inspected circuit and the pin of the internal circuit unit connected to the external pin according to the target netlist. For example, the external pins of the to-be-inspected circuit are the fifth pin 271, the sixth pin 272, the seventh pin 273 and the eighth pin 274, which are sequentially listed in the left column of Figure 7 , and the pins of the internal circuit unit are the first pin 251, the second pin 252 and the third pin 253, which are sequentially listed in the right column of Figure 9 . Wherein, the two pins in the same row of the left and right columns correspond to each other. Figure 9

[0129] Step 804, comparing the external pins of the to-be-inspected circuit with the pins of the connected internal circuit unit, determining the different pins in the external pins of the to-be-inspected circuit and the pins of the connected internal circuit unit, and obtaining the pin combination.

[0130] As shown in Figure 9 , the pins in the left and right columns are compared row by row. The pins in the first row, the second row and the third row on the left and right sides are one-to-one corresponding. The fourth row on the right is empty. The eighth pin 274 in the fourth row on the left does not have a corresponding pin. The different pins in the external pins of the to-be-inspected circuit and the pins of the connected internal circuit unit are obtained, that is, the eighth pin 274. Then, the feedthrough net that does not use brknetM4 is obtained, that is, the second feedthrough net.

[0131] ​In the above embodiment, the external pins of the to-be-checked circuit and the pins of the connected internal circuit units are obtained from the target netlist respectively, and the external pins of the to-be-checked circuit are compared with the pins of the connected internal circuit units, so that different pins in the external pins of the to-be-checked circuit and the pins of the connected internal circuit units are obtained, and the feedthrough net not using brknetM4 is determined.

[0132] In one embodiment, the method further comprises: setting a special element between two external pins in the determined pin combination to obtain an updated circuit schematic diagram.

[0133] In the above embodiment, the brknetM4 is added in the feedthrough net not using brknetM4 to update the circuit schematic diagram, so as to avoid errors in the circuit layout converted from the circuit schematic diagram.

[0134] In one embodiment, the method further comprises: converting the circuit schematic diagram into a circuit layout.

[0135] In the above embodiment, the circuit schematic diagram is converted into a circuit layout to produce a product.

[0136] In one embodiment, as shown in Figure 10 , a circuit diagram checking method is provided to specifically illustrate the method shown in Figure 4 , comprising the following steps:

[0137] Step 1001, determining a to-be-checked circuit.

[0138] Step 1002, obtaining a netlist of the determined to-be-checked circuit to obtain a target netlist.

[0139] Step 1003, inputting the target netlist into simulation software.

[0140] Step 1004, obtaining a simulation result obtained by the simulation software simulating the to-be-checked circuit.

[0141] Step 1005, determining whether the number of external pins of the to-be-checked circuit is the same as the number of pins of the connected internal circuit units according to the simulation result.

[0142] Step 1006, if the number of external pins of the to-be-checked circuit is the same as the number of pins of the internal circuit units, it is determined that a special element is arranged between two connected external pins of the to-be-checked circuit.

[0143] Step 1007, if the number of external pins of the to-be-checked circuit is different from the number of pins of the connected internal circuit units, it is determined that no special element is arranged between two connected external pins of the to-be-checked circuit.

[0144] Step 1008, obtaining the external pin of the to-be-checked circuit and the pin of the connected internal circuit unit from the target netlist respectively.

[0145] Step 1009, comparing the external pin of the to-be-checked circuit with the pin of the connected internal circuit unit, determining the different pins in the external pin of the to-be-checked circuit and the pin of the connected internal circuit unit, obtaining the pin combination without the special element, and the pin combination is two connected external pins in the to-be-checked circuit.

[0146] Step 1010, setting a special element between the two external pins in the determined pin combination, obtaining an updated circuit schematic diagram.

[0147] Step 1011, converting the circuit schematic diagram into a circuit layout.

[0148] Wherein, the steps 1008 to 1010 are executed in sequence after the step 1007, and the step 1011 is executed after the step 1006 or the step 1010.

[0149] It should be understood that, although each step in the flowchart involved in each embodiment as described above is displayed in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise stated herein, there is no strict order limitation for the execution of these steps, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart involved in each embodiment as described above can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be alternately executed with at least part of other steps or steps or stages in other steps.

[0150] Based on the same inventive concept, the embodiments of the present application also provide a circuit diagram checking device for implementing the above-mentioned circuit diagram checking method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more circuit diagram checking device embodiments provided below can refer to the limitations of the circuit diagram checking method in the above text, which will not be repeated here.

[0151] In one embodiment, as shown in Figure 11 A circuit diagram checking device 1100 is provided, comprising: an acquisition module 1101, a simulation module 1102 and a determination module 1103, wherein:

[0152] The acquisition module 1101 is configured to acquire a target netlist of a to-be-checked circuit, the target netlist comprising a connection relationship between each pin of the to-be-checked circuit.

[0153] The simulation module 1102 is configured to simulate the to-be-inspected circuit based on the target netlist.

[0154] The determination module 1103 is configured to determine that no special element is arranged between two connected external pins of the to-be-inspected circuit when the simulation determines that the number of external pins of the to-be-inspected circuit is different from the number of pins of the connected internal circuit unit.

[0155] In an embodiment, the simulation module 1102 includes a simulation unit, a result acquisition unit, and a number determination unit. The simulation unit is configured to input the target netlist into simulation software. The result acquisition unit is configured to acquire a simulation result obtained by the simulation software simulating the to-be-inspected circuit. The number determination unit is configured to determine, according to the simulation result, whether the number of external pins of the to-be-inspected circuit is the same as the number of pins of the connected internal circuit unit.

[0156] In an embodiment, the number determination unit is configured to determine that the number of external pins of the to-be-inspected circuit is different from the number of pins of the connected internal circuit unit if the simulation exits and an error of pin number mismatch occurs, and determine that the number of external pins of the to-be-inspected circuit is the same as the number of pins of the connected internal circuit unit if the simulation is completed.

[0157] In an embodiment, the determination module 1103 is further configured to determine, if the simulation determines that the number of external pins of the to-be-inspected circuit is different from the number of pins of the connected internal circuit unit, a pin combination in which no special element is arranged, the pin combination being two connected external pins of the to-be-inspected circuit.

[0158] In an embodiment, the determination module 1103 includes a pin acquisition unit and a pin comparison unit. The pin acquisition unit is configured to acquire the external pins of the to-be-inspected circuit and the pins of the connected internal circuit unit from the target netlist respectively. The pin comparison unit is configured to compare the external pins of the to-be-inspected circuit with the pins of the connected internal circuit unit, determine different pins in the external pins of the to-be-inspected circuit and the pins of the connected internal circuit unit, and obtain the pin combination.

[0159] In an embodiment, the apparatus further includes an updating module. The updating module is configured to arrange a special element between the two external pins in the determined pin combination, and obtain an updated circuit schematic diagram.

[0160] In an embodiment, the apparatus further includes a conversion module. The conversion module is configured to convert the circuit schematic diagram into a circuit layout.

[0161] In an embodiment, the acquisition module 1101 includes a circuit determination unit and a netlist acquisition unit. The circuit determination unit is configured to determine the to-be-inspected circuit. The netlist acquisition unit is configured to acquire a netlist of the determined to-be-inspected circuit, and obtain the target netlist.

[0162] In one embodiment, the circuit determination unit is used to receive a target circuit input by a user and obtain the circuit to be inspected.

[0163] In one embodiment, the circuit determination unit is used to receive non-target circuits input by the user; remove non-target circuits from the total circuit to obtain the circuit to be inspected.

[0164] In one embodiment, the determining module 1103 is further configured to determine that a special element is provided between two connected external pins of the circuit under test when the simulation determines that the number of external pins of the circuit under test is the same as the number of pins of the connected internal circuit units.

[0165] Each module in the aforementioned circuit diagram checking device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0166] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 12 As shown, the computer device includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When executed by the processor, the computer program implements a circuit diagram checking method. The display unit is used to form a visually visible image and can be a display screen, projection device, or virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0167] Those skilled in the art will understand that Figure 12The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0168] In one embodiment, a computer device is provided, comprising a memory and a processor, the memory storing a computer program, and the processor implementing the following steps when executing the computer program: obtaining a target netlist of a circuit to be checked, the target netlist comprising connection relationships between pins of the circuit to be checked; simulating the circuit to be checked based on the target netlist; and if the simulation determines that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit unit, then no special element is arranged between two connected external pins of the circuit to be checked.

[0169] In one embodiment, the processor further implements the following steps when executing the computer program: inputting the target netlist into simulation software; obtaining simulation results obtained by the simulation software simulating the circuit to be checked; and determining whether the number of external pins of the circuit to be checked is the same as the number of pins of the connected internal circuit unit according to the simulation results.

[0170] In one embodiment, the processor further implements the following steps when executing the computer program: if the simulation exits and an error of pin number mismatch occurs, then determining that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit unit; and if the simulation is completed, then determining that the number of external pins of the circuit to be checked is the same as the number of pins of the connected internal circuit unit.

[0171] In one embodiment, the processor further implements the following steps when executing the computer program: if the simulation determines that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit unit, then determining a pin combination in which no special element is arranged, the pin combination being two connected external pins of the circuit to be checked.

[0172] In one embodiment, the processor further implements the following steps when executing the computer program: obtaining the external pins of the circuit to be checked and the pins of the connected internal circuit unit from the target netlist respectively; comparing the external pins of the circuit to be checked with the pins of the connected internal circuit unit to determine different pins in the external pins of the circuit to be checked and the pins of the connected internal circuit unit, and obtaining the pin combination.

[0173] In one embodiment, the processor further implements the following steps when executing the computer program: arranging a special element between the two external pins in the determined pin combination, and obtaining an updated circuit schematic diagram.

[0174] In one embodiment, the processor, when executing the computer program, also implements the following step: converting the circuit schematic diagram into a circuit layout.

[0175] In one embodiment, the processor, when executing the computer program, also implements the following step: determining the circuit to be checked; obtaining a netlist of the determined circuit to be checked to obtain a target netlist.

[0176] In one embodiment, the processor, when executing the computer program, also implements the following step: receiving a target circuit input by a user to obtain the circuit to be checked.

[0177] In one embodiment, the processor, when executing the computer program, also implements the following step: receiving a non-target circuit input by a user; deleting the non-target circuit from the total circuit to obtain the circuit to be checked.

[0178] In one embodiment, the processor, when executing the computer program, also implements the following step: if the simulation determines that the number of external pins of the circuit to be checked is the same as the number of pins of the connected internal circuit unit, a special element is arranged between the two connected external pins of the circuit to be checked.

[0179] In one embodiment, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program. The computer program, when executed by a processor, implements the following steps: obtaining a target netlist of a circuit to be checked, the target netlist including the connection relationship between each pin of the circuit to be checked; based on the target netlist, simulating the circuit to be checked; and if the simulation determines that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit unit, no special element is arranged between the two connected external pins of the circuit to be checked.

[0180] In one embodiment, the computer program, when executed by the processor, also implements the following steps: inputting the target netlist into simulation software; obtaining a simulation result obtained by the simulation software simulating the circuit to be checked; and determining whether the number of external pins of the circuit to be checked is the same as the number of pins of the connected internal circuit unit according to the simulation result.

[0181] In one embodiment, the computer program, when executed by the processor, also implements the following steps: if the simulation exits and an error of pin number mismatch occurs, it is determined that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit unit; and if the simulation is completed, it is determined that the number of external pins of the circuit to be checked is the same as the number of pins of the connected internal circuit unit.

[0182] In one embodiment, the computer program, when executed by the processor, also implements the following steps: if the simulation determines that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit unit, a pin combination in which no special element is arranged is determined, and the pin combination is the two connected external pins of the circuit to be checked.

[0183] In one embodiment, the computer program, when executed by the processor, further implements the following steps: obtaining external pins of the to-be-checked circuit and pins of the connected internal circuit unit from the target netlist respectively; comparing the external pins of the to-be-checked circuit with the pins of the connected internal circuit unit, determining different pins among the external pins of the to-be-checked circuit and the pins of the connected internal circuit unit, and obtaining the pin combination.

[0184] In one embodiment, the computer program, when executed by the processor, further implements the following steps: setting a special element between two external pins in the determined pin combination, and obtaining an updated circuit schematic diagram.

[0185] In one embodiment, the computer program, when executed by the processor, further implements the following steps: converting the circuit schematic diagram into a circuit layout.

[0186] In one embodiment, the computer program, when executed by the processor, further implements the following steps: determining the to-be-checked circuit; and obtaining a netlist of the determined to-be-checked circuit, and obtaining the target netlist.

[0187] In one embodiment, the computer program, when executed by the processor, further implements the following steps: receiving a target circuit input by a user, and obtaining the to-be-checked circuit.

[0188] In one embodiment, the computer program, when executed by the processor, further implements the following steps: receiving a non-target circuit input by a user; and deleting the non-target circuit from the total circuit, and obtaining the to-be-checked circuit.

[0189] In one embodiment, the computer program, when executed by the processor, further implements the following steps: if the simulation determines that the number of external pins of the to-be-checked circuit is the same as the number of pins of the connected internal circuit unit, then a special element is arranged between two connected external pins of the to-be-checked circuit.

[0190] In one embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, implements the following steps: obtaining a target netlist of a to-be-checked circuit, the target netlist comprising connection relationships among pins of the to-be-checked circuit; simulating the to-be-checked circuit based on the target netlist; and if the simulation determines that the number of external pins of the to-be-checked circuit is different from the number of pins of the connected internal circuit unit, then no special element is arranged between two connected external pins of the to-be-checked circuit.

[0191] In one embodiment, the computer program, when executed by the processor, further implements the following steps: inputting the target netlist into simulation software; obtaining a simulation result obtained by the simulation software simulating the to-be-checked circuit; and determining whether the number of external pins of the to-be-checked circuit is the same as the number of pins of the connected internal circuit unit according to the simulation result.

[0192] In one embodiment, the computer program, when executed by the processor, further implements the following steps: if the simulation exits and an error of pin number mismatch occurs, determining that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit unit; and if the simulation is completed, determining that the number of external pins of the circuit to be checked is the same as the number of pins of the connected internal circuit unit.

[0193] In one embodiment, the computer program, when executed by the processor, further implements the following steps: if the simulation determines that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit unit, determining that the pin combination of the special element is not set, the pin combination being two connected external pins in the circuit to be checked.

[0194] In one embodiment, the computer program, when executed by the processor, further implements the following steps: obtaining the external pins of the circuit to be checked and the pins of the connected internal circuit unit from the target netlist respectively; comparing the external pins of the circuit to be checked with the pins of the connected internal circuit unit to determine the different pins in the external pins of the circuit to be checked and the pins of the connected internal circuit unit, and obtaining the pin combination.

[0195] In one embodiment, the computer program, when executed by the processor, further implements the following steps: setting a special element between the two external pins in the determined pin combination to obtain an updated circuit schematic diagram.

[0196] In one embodiment, the computer program, when executed by the processor, further implements the following steps: converting the circuit schematic diagram into a circuit layout.

[0197] In one embodiment, the computer program, when executed by the processor, further implements the following steps: determining the circuit to be checked; obtaining the netlist of the determined circuit to be checked to obtain a target netlist.

[0198] In one embodiment, the computer program, when executed by the processor, further implements the following steps: receiving a target circuit input by a user to obtain the circuit to be checked.

[0199] In one embodiment, the computer program, when executed by the processor, further implements the following steps: receiving a non-target circuit input by a user; and deleting the non-target circuit from the total circuit to obtain the circuit to be checked.

[0200] In one embodiment, the computer program, when executed by the processor, further implements the following steps: if the simulation determines that the number of external pins of the circuit to be checked is the same as the number of pins of the connected internal circuit unit, a special element is set between two connected external pins of the circuit to be checked.

[0201] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of the country and region.

[0202] It can be understood by those skilled in the art that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing related hardware through a computer program, and the computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments of each method. In the embodiments provided in the present application, any reference to memory, database or other medium can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (Read-Only Memory, ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetic variable memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric memory (Ferroelectric Random Access Memory, FRAM), phase change memory (Phase Change Memory, PCM), graphene memory, etc. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, etc. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0203] The technical features of the above embodiments can be combined in any way. In order to make the description simple, not all possible combinations of the technical features in the above embodiments are described, but as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0204] The above-described embodiments are merely illustrative of several embodiments of the present application, and the description is relatively specific and detailed, but should not be understood as a limitation on the scope of the patent. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A circuit diagram inspection method characterized by, The method comprises: acquiring a target netlist of a circuit to be checked, the target netlist comprising connection relationships between pins of the circuit to be checked; performing simulation on the circuit to be checked based on the target netlist; if the simulation determines that the number of external pins of the circuit to be checked is different from the number of pins of connected internal circuit units, then no special element is arranged between two connected external pins of the circuit to be checked, the special element being a special circuit marking element brknetM4, and it is further determined whether two wires of a feedthrough net are connected through the special circuit marking element brknetM4.

2. The method of claim 1, wherein, The simulation on the circuit to be checked based on the target netlist comprises: inputting the target netlist into simulation software; acquiring simulation results obtained by the simulation software performing simulation on the circuit to be checked; determining whether the number of external pins of the circuit to be checked is the same as the number of pins of connected internal circuit units according to the simulation results.

3. The method of claim 2, wherein, The determination of whether the number of external pins of the circuit to be checked is the same as the number of pins of connected internal circuit units according to the simulation results comprises: if simulation exits and an error of pin number mismatch occurs, then it is determined that the number of external pins of the circuit to be checked is different from the number of pins of connected internal circuit units; if simulation is completed, then it is determined that the number of external pins of the circuit to be checked is the same as the number of pins of connected internal circuit units.

4. The method according to any one of claims 1 to 3, characterized in that, The method further comprises: if the simulation determines that the number of external pins of the circuit to be checked is different from the number of pins of connected internal circuit units, then a pin combination without a special element is determined, the pin combination being two connected external pins in the circuit to be checked.

5. The method of claim 4, wherein, The determination of the pin combination without a special element comprises: respectively acquiring external pins of the circuit to be checked and pins of connected internal circuit units from the target netlist; comparing the external pins of the circuit to be checked with the pins of connected internal circuit units to determine different pins in the external pins of the circuit to be checked and the pins of connected internal circuit units, and obtaining the pin combination.

6. The method of claim 4, wherein, The method further comprises: arranging a special element between two external pins in the determined pin combination, to obtain an updated circuit schematic diagram.

7. The method of claim 6, wherein, The method further comprises: converting the circuit schematic diagram into a circuit layout.

8. The method according to any one of claims 1 to 3, characterized in that, The acquisition of the target netlist of the circuit to be checked comprises: determining a circuit to be checked; acquiring a netlist of the determined circuit to be checked, to obtain the target netlist.

9. The method of claim 8, wherein, The determination of the circuit to be checked comprises: receiving a target circuit input by a user, to obtain the circuit to be checked.

10. The method of claim 8, wherein, The determination of the circuit to be checked comprises: receiving a non-target circuit input by a user; deleting the non-target circuit from a total circuit, to obtain the circuit to be checked.

11. The method according to any one of claims 1 to 3, characterized in that, The method further comprises: if the simulation determines that the number of external pins of the circuit to be checked is the same as the number of pins of connected internal circuit units, then the special element is arranged between two connected external pins of the circuit to be checked.

12. A circuit diagram inspection apparatus characterized by comprising: The device comprises: An acquisition module is configured to acquire a target netlist of a circuit to be checked, the target netlist comprising connection relationships between pins of the circuit to be checked; An emulation module is configured to emulate the circuit to be checked based on the target netlist; A determination module is configured to determine that no special element is arranged between two connected external pins of the circuit to be checked when emulation determines that the number of external pins of the circuit to be checked is different from the number of pins of connected internal circuit units, the special element being a special circuit marker element brknetM4, and further determine whether two wires of a feedthrough net are connected through the special circuit marker element brknetM4.

13. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 11.

14. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 11.

15. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 11.

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