A method for adjacency layout of multi-core chips
By using a multi-core chip adjacency layout method, the inter-core interconnection structure was optimized, solving the problems of wire congestion and long latency in multi-core chips, and realizing low-power and small-area chip design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BLUE OCEAN SMART SYST (NANJING) LTD
- Filing Date
- 2022-11-11
- Publication Date
- 2026-05-26
AI Technical Summary
Multi-core chips have numerous interconnections between cores, resulting in complex structures, which leads to problems such as wire congestion, long latency, high power consumption, increased area, and deteriorated timing.
A multi-core chip adjacency layout method is adopted, which optimizes the inter-core interconnection structure by grouping signal lines, changing topology, adding decoding logic and buffers, low-power units, and combining hierarchical physical implementation.
It achieves an adjacency layout, reduces inter-core interconnect congestion, lowers power consumption and area, optimizes timing, and shortens physical implementation time.
Smart Images
Figure CN115659899B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design, and more particularly to a method for adjacency layout of multi-core chips. Background Technology
[0002] With the rise of modern high-performance computing chips, multi-core chip design has become widely used. Once the chip's logic function design is complete, the physical implementation begins. A good physical implementation starts with a good layout. The main goals of physical layout are: small area, good timing, reduced interconnect length, reduced congestion, and reduced voltage drop. However, a large number of interconnects between multiple cores at the top layer often cause wiring congestion, increasing wiring length and leading to greater latency. Furthermore, buffers and inverters on the lines also consume significant area and power. The more cores there are, the more complex the signal lines become, and the more severe the problems become.
[0003] There are three common physical placement methods for chips: non-adjacent placement, adjacent placement, and hybrid placement. Non-adjacent placement is characterized by channels between cores, typically used for signal line routing and connections between cores. Adjacent placement is characterized by cores being adjacent to each other without any channels in between. Hybrid placement combines elements of both modes. The choice of physical placement depends on the core's logic design; a logic design that doesn't adequately consider physical implementation will lead to implementation difficulties and reduced chip performance. Summary of the Invention
[0004] The technical problem that this invention aims to solve is that in existing chip design technology, multi-core chips have a large number of interconnects between cores and a complex structure; during the chip physical implementation process, wire congestion is often encountered; in advanced processes, the latency of the wires accounts for a high proportion, and the longer and denser the wires, the more obvious the parasitic effects become, which leads to a series of problems such as increased power consumption, increased area, worse timing, and increased consumption of computing resources.
[0005] To address the above problems, this invention provides a method for adjacency layout of multi-core chips, comprising the following steps:
[0006] S1 analyzes the input and output port signal lines of each single core and groups them according to functional design and topology;
[0007] S2 makes topological changes to the internal and top-level connections of a single core and adds decoding logic;
[0008] S3 adds buffers and low-power units based on constraints including timing and low power consumption.
[0009] S4 implements an adjacency layout and a hierarchical physical implementation method.
[0010] In step S1, the signal lines are divided into four groups: common signal, dedicated signal, feedthrough signal, and original signal.
[0011] In step S2, for the common signal in the M×N multi-core matrix structure, it is split into M paths at the top level, with each path's single core sharing a single signal;
[0012] For dedicated signals, each bit of the signal in each channel is split into N bits, and an AND gate is added to each bit of the signal. The other input of the AND gate comes from the newly added decoding logic, which is used to decode the core number, generate an enable signal, and control the correct propagation of the signal. In addition to expanding the input port to N bits, dedicated signals also need to establish N output ports to enable the propagation of signals to other cores.
[0013] For feedthrough signals, each signal already has a pair of input and output ports. When performing topology transformation, a new pair of input and output ports are added and directly connected, with their physical location opposite to the original ports. The newly added reverse feedthrough output port of the first core of each row is connected to the original feedthrough input port of the first core of the next row, and the original output port of the tail core is connected to its own newly added reverse feedthrough input port.
[0014] For the original signal, the original design needs to ensure direct connection between different cores and meet the requirements of adjacency layout.
[0015] In step S3, the method for inserting buffers is to insert one buffer at each of the signal line input and output ports, and according to timing constraints, insert several evenly distributed buffers or inverters in the middle section of the signal line; the method for designing low-power units is that, during the physical implementation of the core, the corresponding low-power units can be automatically inserted using EDA tools through the UPF unified power format low-power constraint file, or the expected low-power units can be directly inserted in the modified design code.
[0016] In step S4, the hierarchical physical implementation method is to first complete the physical implementation of a single core and generate the physical design file of the core, including: netlist, LEF layout switching format file, ETM timing model and other files. In the top-level physical implementation, the physical design file of the core is reused to reduce the memory usage and running time of EDA tools.
[0017] Preferably, the logic code for each single core is completely identical.
[0018] Preferably, the topological changes of each single core in step S2 are completely consistent and do not affect the original logical functions.
[0019] Preferably, the number of cores is multiple, the shape of a single core is rectangular, and the multiple cores are arranged in a matrix; after the adjacency layout, the multiple cores form a rectangle.
[0020] The beneficial effects of adopting the above technical solution are as follows:
[0021] Compared with existing technologies, this invention eliminates most inter-core connections by transforming the topology of single cores and top-level signal lines, achieving the effect of adjacent layout. This reduces congestion of inter-core connections and the corresponding area, power consumption, and timing overhead. Since the transformed cores can be directly instantiated and reused multiple times, the physical implementation time is reduced. The more cores there are, the more physical implementation time is saved. Attached Figure Description
[0022] Figure 1 This is a flowchart of the multi-core chip adjacency layout method of the present invention;
[0023] Figure 2 This is a schematic diagram of a typical port type for a single core.
[0024] Figure 3 This is a schematic diagram of the common signal topology transformation of a multi-core matrix;
[0025] Figure 4 A schematic diagram of dedicated signal topology transformation for multi-core matrices;
[0026] Figure 5 This is a schematic diagram of the feedthrough signal topology transformation for a multi-core matrix.
[0027] Figure 6 This is a schematic diagram of the buffer insertion method;
[0028] Figure 7 This is a schematic diagram of the physical implementation. Detailed Implementation
[0029] The technical solution of this patent will be further explained below with reference to specific embodiments, and the following terms will be used:
[0030] Multi-core matrix: A matrix formed by concatenating multiple core adjacency layouts;
[0031] Top layer: The logical layer outside the multi-core matrix;
[0032] Core number: Core_ <row> _ <column>row is the row number of the core matrix; column is the column number of the core matrix, both starting from 0; x is any number, for example, the core in the top left corner is numbered Core_0_0, Core_x_0 refers to all cores in the first column; Core_0_x refers to all cores in the first row.
[0033] Example 1
[0034] according to Figures 1 to 7 As shown, this embodiment provides a method for adjacency layout of multi-core chips, including the following steps:
[0035] Step 1: Signal line grouping. Analyze the input and output port signal lines of each single core, and group them according to functional design and topology. Divide the signal lines into four groups: common signals, dedicated signals, feedthrough signals, and original signals.
[0036] Due to the diversity of chip design, the core signal lines are first classified according to their topology, and different measures are taken for different topologies, such as... Figure 2 The image shows a typical port type for a core. The left side represents the input, the right side represents the output, the box represents the core boundary, the cloud represents the core's internal logic, and CLK_IN is the clock input. In typical designs, there are only input ports, and different cores share the same clock signal.
[0037] DFT_IN / OUT are test signals, such as test mode signals, scan inputs, and output signals. In multi-core designs, they are generally controlled independently, meaning each core has its own dedicated test signal.
[0038] POWER_IN / OUT are power consumption control signals, such as shutdown signals. They can have input and output ports, and the power consumption control signals of multiple cores can be connected in series.
[0039] DATA_IN / OUT are data input / output signals, which are determined according to the characteristics of the design itself and need to meet the requirements of adjacency layout.
[0040] The following four lists represent common signal line topology types, with the actual signal names from the typical designs described above included in the lists:
[0041] Common signal list = [CLK_IN],
[0042] Dedicated signal list = [DFT_IN],
[0043] Feedthrough signal list = [POWER_IN, POWER_OUT],
[0044] Original signal list = [DATA_IN, DATA_OUT].
[0045] Step 2, topology change: Perform topology changes on the internal and top-level connections of the single core, and add decoding logic;
[0046] For the common signal of the MxN multi-core matrix structure, Figure 3 Taking a 2x3 multi-core matrix as an example, the common signal is clk_in, which is the core clock signal. At the top level, the clock signal is split into two paths. In Core_x_0, a new clock signal is added, represented by a dashed line. The original design's one path is represented by a solid line. The output port and input port of the dashed line are at the same height, so that it can interface with the data signal of Core_x_1. For the multi-core matrix with modified clock signals, the clock signal is distributed to all cores, and the topology of the clock signals inside all cores is completely consistent.
[0047] For dedicated signals, such as Figure 4 As shown, since each core requires an independent signal, each bit of signal is split into 3. In Core_x_0, 3 bits of signal are input, and each bit is added with an AND gate. The other input of the AND gate comes from the newly added decoding logic as an enable signal. The newly added decoding logic is represented by a dashed cloud box. Its function is to decode the core number and determine that the signal in the N bits that is consistent with the core code can be passed into the core. In addition to expanding the input port to 3 bits, the dedicated signal also needs to establish 3 output ports to realize the propagation of the signal to other cores.
[0048] For feedthrough signals, such as Figure 5 As shown, each signal already has a pair of input / output ports represented by solid lines, namely a feedthrough input port and a feedthrough output port. The cores in each row are connected in series. During topology transformation, a new pair of input / output ports represented by dashed lines is added, with their physical location opposite to the original ports. The newly added reverse feedthrough output port of the first core in each row is connected to the original feedthrough input port of the first core in the next row, and the original output port of the last core is connected to its own newly added reverse feedthrough input port. For core Core_0_0, the output port of this signal is connected to the input port of core Core_0_1, and core Core_0... The output port of signal _1 is connected to the input port of core_0_2. The output port of signal _1 is connected to the newly added reverse feedthrough input port of core_0_2. The newly added reverse feedthrough output port of core_0_2 is connected to the newly added reverse feedthrough input port of core_0_1. The reverse feedthrough output port of core_0_1 is connected to the reverse feedthrough input port of core_0_0. The reverse feedthrough output port of core_0_0 is connected to the input port of core_1_0, and so on, so that the signal can pass through all cores.
[0049] For the original signal, the original design needs to ensure direct connection between different cores and meet the requirements of adjacency layout.
[0050] Step 3: Insert buffers and low-power units. Based on the constraints, including timing and low power requirements, add buffers and low-power units.
[0051] In physical implementation, line delay is affected by parasitic parameters, so a single metal wire cannot be used to run through all cores. Therefore, appropriate buffer units need to be inserted at suitable locations on the line. This method inserts a buffer at each of the input and output ports, such as... Figure 6 As shown, in the middle section of the line, four evenly distributed buffers are inserted based on the timing prediction or actual results.
[0052] For low-power designs, during the physical implementation of the core, the corresponding low-power units can be automatically inserted using EDA tools through the UPF unified power format low-power constraint file. Alternatively, the expected low-power units can be directly inserted into the modified design code.
[0053] Step 4, Physical Implementation: Implement adjacency layout and hierarchical physical implementation methods;
[0054] Since the port positions of adjacent cores correspond, these signal lines are physically connected after removing the channels from the core matrix, achieving an adjacency layout. To maximize the benefits of this method, a hierarchical physical implementation method is needed. For example... Figure 7 As shown, the physical implementation of a single core is completed first, generating the physical design files for that core, including netlist, LEF layout switching format file, ETM timing model, etc. During the top-level physical implementation, the physical design files of that core are reused to reduce the memory usage and runtime of EDA tools.
[0055] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.< / column> < / row>
Claims
1. A method for adjacency layout of multi-core chips, characterized in that, Includes the following steps: S1 signal line grouping: Analyze the input and output port signal lines of each single core and group them according to functional design and topology; S2 topology changes, which modify the topology of the internal and top-level connections of a single core and add decoding logic; S3 inserts buffers and low-power units, adding buffers and low-power units according to constraints including timing and low power consumption. S4 physical implementation, which implements adjacency layout and hierarchical physical implementation methods.
2. The method for multi-core chip adjacency layout as described in claim 1, characterized in that, In step S1, the signal lines are divided into four groups: common signal, dedicated signal, feedthrough signal, and original signal.
3. The method for multi-core chip adjacency layout as described in claim 2, characterized in that, The topology change in step S2 is as follows: For the common signal in the M×N multi-core matrix structure, it is split into M paths at the top level, and each path's single core shares a signal; For dedicated signals, each bit of signal in each channel is split into N bits, and an AND gate is added to each bit of signal. The other input of the AND gate comes from the newly added decoding logic. In addition to expanding the input port to N bits, dedicated signals also need to establish N output ports to enable the propagation of signals to other cores. For feedthrough signals, each signal already has a pair of input and output ports. When performing topology transformation, a new pair of input and output ports are added and directly connected, with their physical location opposite to the original ports. The newly added reverse feedthrough output port of the first core of each row is connected to the original feedthrough input port of the first core of the next row, and the original output port of the tail core is connected to its own newly added reverse feedthrough input port. For the original signal, the original design needs to ensure direct connection between different cores and meet the requirements of adjacency layout.
4. The method for multi-core chip adjacency layout as described in claim 1, characterized in that, In step S3, the method for inserting buffers is to insert one buffer at each of the input and output ports of the signal line, and according to timing constraints, insert several evenly distributed buffers or inverters in the middle section of the signal line.
5. The method for multi-core chip adjacency layout as described in claim 1, characterized in that, In step S3, the method for designing low-power units is to automatically insert the corresponding low-power units using EDA tools during the physical implementation of the core through a UPF unified power format low-power constraint file.
6. The method for multi-core chip adjacency layout as described in claim 1, characterized in that, In step S3, the method for designing low-power units is to directly insert the expected low-power units into the modified design code.
7. The method for multi-core chip adjacency layout as described in claim 1, characterized in that, In step S4, the hierarchical physical implementation method is to first complete the physical implementation of a single core and generate the physical design file of that core. In the top-level physical implementation, the physical design file of that core is reused to reduce the memory usage and running time of the EDA tool.
8. The method for multi-core chip adjacency layout as described in claim 7, characterized in that, The physical design documents include: netlist, LEF layout switching format file, and ETM timing model.
9. The method for multi-core chip adjacency layout as described in claim 1, characterized in that, The logic code for each single core is completely identical.
10. The method for multi-core chip adjacency layout as described in claim 1, characterized in that, In step S2, the topology changes of each single core are completely consistent and do not affect the original logical functions.
11. The method for multi-core chip adjacency layout as described in claim 1, characterized in that, The decoding logic added in step 2 is used to decode the core number, generate an enable signal, and control the correct propagation of the signal.
12. The method for multi-core chip adjacency layout as described in claim 1, characterized in that, The number of cores is complex, and the shape of a single core is rectangular. Multiple cores are arranged in a matrix; after adjacency layout, multiple cores form a rectangle.