Protection circuit, output unit, source driver and display device

Abstract

The embodiment of the present application provides a protection circuit, an output unit, a source driver and a display device. The protection circuit includes a level conversion unit and a voltage maintaining unit. The level conversion unit is used to receive a first polarity reversal signal of a first voltage domain and a second polarity reversal signal of the first voltage domain, convert the first polarity reversal signal of the first voltage domain into a first polarity reversal signal of the second voltage domain and then output it; the polarity of the first polarity reversal signal of the first voltage domain and the second polarity reversal signal of the first voltage domain are opposite; the absolute value of the voltage of the first voltage domain is less than the absolute value of the voltage of the second voltage domain; the voltage maintaining unit is connected to the level conversion unit to maintain the voltage of the first polarity reversal signal of the second voltage domain. The protection circuit provided by the embodiment of the present application can avoid physical damage caused by the disordered high driving voltage loaded on the output switch unit if the power supply of the first voltage domain is turned off first.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a protection circuit, an output unit, a source driver and a display device. Background Art

[0002] For driving the display panel, in order to prevent polarization of the crystal material, the source driver should alternately provide positive and negative voltages.

[0003] As the resolution of display panels continues to increase, the operating speed of the source driver also increases. In order to increase the driving speed, more advanced processes need to be used in the design of the source driver to improve the response speed of the source driver. However, as the process level increases, the voltage resistance of the source driver decreases.

[0004] The source driver generally requires two supply voltages, LV (Low supply Voltage) and HV (High supply Voltage), which are provided by the LV power supply and the HV power supply, respectively. The LV power supply is used to provide voltage to the control signal, and the control signal includes a polarity reversal signal POL. The HV power supply is used to provide voltage to the buffer and the output switch unit. When the two power supplies are turned off, if the LV power supply is turned off first, the polarity reversal signal LV POL cannot be determined, which may cause the polarity reversal signal HV POL obtained by level conversion to be disordered, resulting in a disordered high drive voltage being loaded on the device driven by the HV power supply (such as the output switch unit), so that the device loaded on the HV power supply (such as the output switch unit) exceeds the highest withstand voltage value that can be tolerated, resulting in physical damage to the device loaded on the HV power supply (such as the output switch unit). Summary of the invention

[0005] In view of the shortcomings of the existing methods, the present application proposes a protection circuit, an output unit, a source driver and a display device to solve the technical problem in the prior art that if the LV power supply is turned off first, the polarity reversal signal LV POL cannot be determined, which may cause the polarity reversal signal HV POL obtained by level conversion to be disordered, resulting in the disordered high driving voltage being loaded on the device driven by the HV power supply (such as the output switch unit), which may cause physical damage.

[0006] In a first aspect, an embodiment of the present application provides a protection circuit applied to an output unit of a source driver, wherein the output unit includes a switch logic unit and an output switch unit, and the protection circuit includes:

[0007] The level conversion unit is configured to be electrically connected to the output switch unit through the switch logic unit, and is used to receive a first polarity inversion signal of the first voltage domain and a second polarity inversion signal of the first voltage domain in a first stage, and convert the first polarity inversion signal of the first voltage domain into a first polarity inversion signal of the second voltage domain; the first polarity inversion signal of the first voltage domain and the second polarity inversion signal of the first voltage domain have opposite polarities; the absolute value of the voltage of the first voltage domain is less than the absolute value of the voltage of the second voltage domain; the first polarity inversion signal of the second voltage domain is configured to be converted into a control signal through the switch logic unit and output to the output switch unit;

[0008] The voltage maintaining unit is connected to the level conversion unit and is used to form a loop with the level conversion unit in the second stage to maintain the voltage of the first polarity inversion signal of the second voltage domain.

[0009] In a possible implementation, the level conversion unit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor;

[0010] The first electrode of the first transistor is connected to the first electrode of the second transistor and is connected to the first voltage terminal;

[0011] The second electrode of the first transistor is respectively connected to the control electrode of the second transistor, the voltage maintaining unit and the first electrode of the third transistor;

[0012] The second electrode of the second transistor is respectively connected to the control electrode of the first transistor, the voltage maintaining unit and the first electrode of the fourth transistor, and is used to output a first polarity inversion signal of the second voltage domain;

[0013] The second electrode of the third transistor, the second electrode of the fourth transistor and the voltage maintaining unit are connected to the second voltage terminal;

[0014] The control electrode of the third transistor receives a first polarity inversion signal of the first voltage domain, and the control electrode of the fourth transistor receives a second polarity inversion signal of the first voltage domain.

[0015] In a possible implementation, the voltage maintaining unit includes: a fifth transistor and a sixth transistor;

[0016] A first electrode of the fifth transistor is connected to the first electrode of the third transistor, a second electrode of the fifth transistor is connected to the second electrode of the third transistor, and a control electrode of the fifth transistor is connected to the first electrode of the fourth transistor;

[0017] A first electrode of the sixth transistor is connected to the first electrode of the fourth transistor, a second electrode of the sixth transistor is connected to the second electrode of the fourth transistor, and a control electrode of the sixth transistor is connected to the first electrode of the third transistor.

[0018] In a possible implementation, the first transistor and the second transistor are both P-type transistors;

[0019] The third transistor, the fourth transistor, the fifth transistor and the sixth transistor are all N-type transistors.

[0020] In a possible implementation, the level conversion unit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor;

[0021] The first electrode of the first transistor, the first electrode of the second transistor and the voltage maintaining unit are connected, and are connected to the third voltage terminal;

[0022] The second electrode of the first transistor is respectively connected to the voltage maintaining unit, the control electrode of the fourth transistor and the first electrode of the third transistor;

[0023] The control electrode of the first transistor receives a first polarity inversion signal of the first voltage domain, and the control electrode of the second transistor receives a second polarity inversion signal of the first voltage domain;

[0024] The second electrode of the second transistor is respectively connected to the voltage maintaining unit, the control electrode of the third transistor and the first electrode of the fourth transistor, and is used to output a first polarity inversion signal of the second voltage domain;

[0025] The second electrode of the third transistor is connected to the second electrode of the fourth transistor and is also connected to the fourth voltage terminal.

[0026] In a possible implementation, the voltage maintaining unit includes: a fifth transistor and a sixth transistor;

[0027] A first electrode of the fifth transistor is connected to the first electrode of the first transistor, a second electrode of the fifth transistor is connected to the second electrode of the first transistor, and a control electrode of the fifth transistor is connected to the second electrode of the second transistor;

[0028] A first electrode of the sixth transistor is connected to the first electrode of the second transistor, a second electrode of the sixth transistor is connected to the second electrode of the second transistor, and a control electrode of the sixth transistor is connected to the second electrode of the first transistor.

[0029] In a possible implementation, the first transistor, the second transistor, the fifth transistor and the sixth transistor are all P-type transistors;

[0030] The third transistor and the fourth transistor are both N-type transistors.

[0031] In a second aspect, an embodiment of the present application provides an output unit applied to a source driver, and the output unit includes a protection circuit as described in any one of the first aspects.

[0032] In a possible implementation, it further includes: a first buffer unit, a second buffer unit, a switch logic unit, and an output switch unit;

[0033] The output end of the first buffer unit is electrically connected to the first input end of the output switch unit, and is used to receive an input positive input signal and output a positive driving signal to the output switch unit;

[0034] The output end of the second buffer unit is electrically connected to the second input end of the output switch unit, and is used to receive an input negative input signal and output a negative driving signal to the output switch unit;

[0035] The output end of the protection circuit is electrically connected to the control end of the switch logic unit, and is used to output the first polarity reversal signal of the second voltage domain to the control end of the switch logic unit;

[0036] The output end of the switch logic unit is electrically connected to the output switch unit, and is used to convert the first polarity inversion signal of the second voltage domain into a control signal and output it to the output switch unit;

[0037] The output switch unit is configured to be electrically connected to the display panel and is used to output a positive driving signal or a negative driving signal to the display panel according to the control signal.

[0038] In a third aspect, an embodiment of the present application provides a source driver, comprising any output unit as in the second aspect.

[0039] In a fourth aspect, an embodiment of the present application provides a display device, comprising a display panel and a source driver as in the third aspect; an output end of the source driver is electrically connected to the display panel.

[0040] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:

[0041] The protection circuit provided by the embodiment of the present application is applied to the output unit of the source driver, and the protection circuit includes a level conversion unit and a voltage maintenance unit. In the first stage, that is, if both power supplies are normally powered, the first polarity reversal signal LV_POL of the first voltage domain is converted into the first polarity reversal signal HV_POL of the second voltage domain through the level conversion unit, and the first polarity reversal signal HV_POL is configured to be converted into a control signal HV_CTRL and output to the output switch unit. In the second stage, that is, if the power supply (LV power supply) of the first voltage domain is turned off first, the voltage of the first polarity reversal signal HV_POL of the second voltage domain can be maintained by forming a loop through the voltage maintenance unit and the level conversion unit, which plays a latching role, so that the output switch unit is still driven based on the polarity information of the original polarity reversal signal, so that the driving voltage range of the output switch unit remains unchanged, which can avoid that if the power supply (LV power supply) of the first voltage domain is turned off first, the polarity reversal signal HV POL obtained by the level conversion may be disordered, thereby causing the disordered high driving voltage to be loaded on the output switch unit and cause physical damage. The protection circuit provided in the embodiment of the present application is independent of the order in which the power is turned off, and can prevent physical damage caused by the disordered high driving voltage being loaded on the output switch unit.

[0042] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0044] Figure 1 It is a structural schematic diagram of an output unit in the prior art;

[0045] Figure 2 A schematic diagram of the structure of a protection circuit provided in an embodiment of the present application;

[0046] Figure 3a A circuit schematic diagram of a protection circuit provided in an embodiment of the present application;

[0047] Figure 3b A circuit schematic diagram of another protection circuit provided in an embodiment of the present application;

[0048] Figure 4a for Figure 3a Timing diagram of the protection circuit;

[0049] Figure 4b for Figure 3b Timing diagram of the protection circuit;

[0050] Figure 5 A schematic diagram of the structure of an output unit provided in an embodiment of the present application.

[0051] Reference numerals:

[0052] 10-protection circuit, 11-level conversion unit, 12-voltage maintenance unit; 20-first buffer unit, 30-second buffer unit, 40-switch logic unit, 50-output switch unit;

[0053] 100 - output unit, 200 - source driver, 300 - display panel. DETAILED DESCRIPTION

[0054] The present application is described in detail below, and examples of embodiments of the present application are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar components or components with the same or similar functions. In addition, if the detailed description of the known technology is unnecessary for the features of the present application shown, it will be omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limiting the present application.

[0055] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with those in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as here.

[0056] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0057] The inventor of the present application has conducted research and found that in order to increase the driving speed, a more advanced process needs to be used in the design of the source driver to increase the response speed of the source driver. However, as the process level increases, the voltage resistance of the source driver decreases.

[0058] For example, we need to use a more advanced process to design a source driver with an output of 10V, but the process only provides devices with a withstand voltage of 5V (that is, the withstand voltage of the source driver is 5V). In order to solve this contradiction, the following structure will be used to obtain a source driver with an output of 10V, such as Figure 1 As shown, the source driver includes an output unit, which includes a positive buffer unit, a negative buffer unit, an output switch unit, a switch logic unit and a level conversion unit.

[0059] Specifically, the output switch unit receives the input positive drive signal PMV (+5V) and negative drive signal NMV (-5V), and the positive drive signal PMV (+5V) and the negative drive signal NMV (-5V) come from the positive and negative buffer units, respectively. The output switch unit outputs OUTPUT_1 and OUTPUT_2 to pixel 1 and pixel 2. The control signal HV_CTRL received by the output switch unit is derived from the polarity reversal signal LV_POL. That is, the polarity reversal signal LV_POL outputs the control signal HV_CTRL through the level conversion unit and the switch logic unit. The control signal HV_CTRL controls the output switch unit to control the allocation of the input end and the output end of the output switch unit. For example, the control signal HV_CTRL controls the output switch unit so that the output end OUTPUT_1 outputs the positive drive signal PMV, or controls the output switch unit so that the output end OUTPUT_1 outputs the negative drive signal NMV.

[0060] For example, the output switch unit uses a device with a maximum driving voltage of 5V, that is, the withstand voltage of the output switch unit is 5V, assuming the following:

[0061] When the polarity inversion signal LV_POL=0, OUTPUT_1=PMV (+5V) and OUTPUT_2=NMV (-5V).

[0062] When the polarity inversion signal LV_POL=1, OUTPUT_1=NMV (-5V) and OUTPUT_2=PMV (+5V).

[0063] Therefore, the output of the output switch unit can be controlled by the polarity inversion signal LV_POL, so that a driving voltage with a voltage difference of 10V can be obtained to drive the pixels of the display panel.

[0064] However, if the LV power supply is turned off first, since the polarity reversal signal LV_POL cannot be determined, the polarity reversal signal HV POL obtained by the level conversion unit may be disordered, which may cause the control signal HV_CTRL output by the switch logic unit to be disordered, which may cause a disordered high driving voltage to be loaded on the output switch unit, which may cause the output switch unit to exceed the highest withstand voltage value it can withstand, causing physical damage to the output switch unit, and then causing damage to the source driver.

[0065] For example, when the polarity reversal signal LV_POL=0, the output switch unit receives PMV (+5V), OUTPUT_1=PMV (+5V); when the polarity reversal signal LV_POL=1, the output switch unit receives NMV (-5V), OUTPUT_1=NMV (-5V); when the polarity reversal signal LV_POL=0, the two power supplies are turned off. If the LV power supply is turned off first, LV_POL cannot be determined, resulting in HV_POL may be disordered, thereby causing the control signal HV_CTRL output by the switch logic unit to be disordered, and NMV (-5V) may be loaded on the output switch unit. Since OUTPUT_1=PMV (+5V) before, the voltage difference loaded on the output switch unit may become 10V, which exceeds the maximum withstand voltage value of 5V that the output switch unit can withstand, causing physical damage to the output switch unit.

[0066] The present application provides a protection circuit, an output unit, a source driver and a display device, aiming to solve the above technical problems in the prior art.

[0067] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments.

[0068] The embodiment of the present application provides a protection circuit 10, which is applied to an output unit of a source driver, wherein the output unit includes a switch logic unit and an output switch unit, such as Figure 2 As shown, the protection circuit 10 includes a level conversion unit 11 and a voltage maintaining unit 12 .

[0069] The level conversion unit 11 is configured to be electrically connected to the output switch unit through the switch logic unit, and is used to receive the first polarity inversion signal LV_POL of the first voltage domain and the second polarity inversion signal LV_POL_B of the first voltage domain in the first stage, and convert the first polarity inversion signal LV_POL of the first voltage domain into the first polarity inversion signal HV_POL of the second voltage domain; the polarities of the first polarity inversion signal LV_POL of the first voltage domain and the second polarity inversion signal LV_POL_B of the first voltage domain are opposite; the absolute value of the voltage of the first voltage domain is less than the absolute value of the voltage of the second voltage domain; the first polarity inversion signal of the second voltage domain is configured to be converted into the control signal HV_CTRL through the switch logic unit and output to the output switch unit.

[0070] The voltage maintaining unit 12 is connected to the level converting unit 11 and is used to form a loop with the level converting unit in the second stage to maintain the voltage of the first polarity inversion signal HV_POL of the second voltage domain.

[0071] The protection circuit provided in the embodiment of the present application is applied to the output unit of the source driver, and the protection circuit includes a level conversion unit 11 and a voltage maintaining unit 12. In the first stage, that is, if both power supplies are normally powered, the first polarity reversal signal LV_POL of the first voltage domain is converted into the first polarity reversal signal HV_POL of the second voltage domain through the level conversion unit 11, and the first polarity reversal signal HV_POL is configured to be converted into a control signal HV_CTRL and output to the output switch unit. In the second stage, that is, if the power supply (LV power supply) of the first voltage domain is turned off first, the voltage maintaining unit 12 forms a loop with the level conversion unit 11, and the voltage of the first polarity reversal signal HV_POL of the second voltage domain can be maintained, which plays a latching role, so that the output switch unit is still driven based on the polarity information of the original polarity reversal signal, and the driving voltage range of the output switch unit remains unchanged, which can avoid the polarity reversal signal HV POL obtained by level conversion from being disordered due to the power supply (LV power supply) of the first voltage domain being turned off first, thereby causing the disordered high driving voltage to be loaded on the output switch unit and causing physical damage. The protection circuit provided in the embodiment of the present application is independent of the order in which the power is turned off, and can prevent physical damage caused by the disordered high driving voltage being loaded on the output switch unit.

[0072] In some embodiments, Figure 3a As shown, the level conversion unit 11 includes: a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4;

[0073] A first electrode of the first transistor T1 is connected to a first electrode of the second transistor T2 and is connected to a first voltage terminal VDDA;

[0074] The second electrode of the first transistor T1 is respectively connected to the control electrode of the second transistor T2, the voltage maintaining unit 12 and the first electrode of the third transistor T3;

[0075] The second electrode of the second transistor T2 is respectively connected to the control electrode of the first transistor T1, the voltage maintaining unit 12 and the first electrode of the fourth transistor T4, and the second electrode of the second transistor T2 is used to output the first polarity reversal signal HV_POL of the second voltage domain;

[0076] The second electrode of the third transistor T3 and the second electrode of the fourth transistor T4 are connected to the voltage maintaining unit 12 and are also connected to the second voltage terminal GND;

[0077] The control electrode of the third transistor T3 receives the first polarity inversion signal LV_POL of the first voltage domain, and the control electrode of the fourth transistor T4 receives the second polarity inversion signal LV_POL_B of the first voltage domain.

[0078] In some embodiments, Figure 3a As shown, the voltage maintaining unit 12 includes: a fifth transistor T5 and a sixth transistor T6;

[0079] A first electrode of the fifth transistor T5 is connected to a first electrode of the third transistor T3, a second electrode of the fifth transistor T5 is connected to a second electrode of the third transistor T3, and a control electrode of the fifth transistor T5 is connected to a second electrode of the second transistor T2 and a first electrode of the fourth transistor T4 respectively;

[0080] A first electrode of the sixth transistor T6 is connected to a first electrode of the fourth transistor T4 , a second electrode of the sixth transistor T6 is connected to a second electrode of the fourth transistor T4 , and a control electrode of the sixth transistor T6 is connected to a second electrode of the first transistor T1 and a first electrode of the third transistor T3 .

[0081] In some embodiments, Figure 3a As shown, the first transistor T1 and the second transistor T2 are both P-type transistors; the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are all N-type transistors.

[0082] In a specific example, Figure 3a As shown, the first electrode of the first transistor T1 is connected to the first electrode of the second transistor T2, and is connected to the first voltage terminal VDDA;

[0083] The second electrode of the first transistor T1 is respectively connected to the control electrode of the second transistor T2, the first electrode of the fifth transistor T5, the control electrode of the sixth transistor T6 and the first electrode of the third transistor T3;

[0084] The second electrode of the second transistor T2 is respectively connected to the control electrode of the first transistor T1, the control electrode of the fifth transistor T5, the first electrode of the sixth transistor T6 and the first electrode of the fourth transistor T4, and the second electrode of the second transistor T2 is used to output the first polarity reversal signal HV_POL of the second voltage domain;

[0085] The second electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5 and the second electrode of the sixth transistor T6 are connected and connected to the second voltage terminal GND;

[0086] The control electrode of the third transistor T3 receives the first polarity inversion signal LV_POL of the first voltage domain, and the control electrode of the fourth transistor T4 receives the second polarity inversion signal LV_POL_B of the first voltage domain.

[0087] Reference Figure 3a and Figure 4a As shown, the working principle of the protection circuit 10 is introduced. In this example, LV_POL is a high-low level alternating signal, the high level voltage of LV_POL is the voltage of the third voltage terminal VDDD, the low level voltage of LV_POL is the voltage of the second voltage terminal GND, and the voltage of LV_POL is provided by the power supply of the first voltage domain (LV power supply). The voltage of the first voltage terminal VDDA is provided by the power supply of the second voltage domain (HV power supply). Figure 3a In the embodiment, the polarities of the first polarity inversion signal HV_POL of the second voltage domain and the second polarity inversion signal HV_POL_B of the second voltage domain are opposite. For ease of description, in the following description, VDDD is used to represent the voltage of the third voltage terminal VDDD, GND is used to represent the voltage of the second voltage terminal GND, and VDDA is used to represent the voltage of the first voltage terminal VDDA.

[0088] 1. If both power supplies are operating normally, that is, the first stage (such as Figure 4a During the interval t1), the first polarity inversion signal LV_POL of the first voltage domain is converted into the first polarity inversion signal HV_POL of the second voltage domain by the level conversion unit 11 and then outputted.

[0089] Specifically, if both power supplies are powered normally, when LV_POL is a high-level voltage VDDD, LV_POL_B is a low-level voltage GND, the third transistor T3 is turned on, the fourth transistor T4 is turned off, HV_POL_B is connected to the second voltage terminal GND through the third transistor T3, HV_POL_B is a low-level voltage GND, so that the second transistor T2 is turned on, so that HV_POL is connected to the first voltage terminal VDDA, and HV_POL is a high-level voltage VDDA. When LV_POL is a low-level voltage GND, LV_POL_B is a high-level voltage VDDD, the third transistor T3 is turned off, the fourth transistor T4 is turned on, HV_POL is connected to the second voltage terminal GND through the fourth transistor T4, and HV_POL is a low-level voltage GND. Therefore, when both power supplies are powered normally, LV_POL (high-level voltage VDDD and low-level voltage GND) becomes HV_POL (high-level voltage VDDA and low-level voltage GND) after level conversion. VDDA is greater than VDDD. For example, if the voltage of VDDD is 1V, the voltage of GND is 0V, and the voltage of VDDA is 5V (positive 5V). This example is only used to explain that VDDA is greater than VDDD. In practice, VDDD, GND, and VDDA can be set according to actual conditions, and this application does not limit them.

[0090] 2. If the power supply of the first voltage domain (LV power supply) is turned off first, and the power supply of the second voltage domain (HV power supply) is turned off later, that is, the second stage (such as Figure 4a The voltage maintaining unit 12 can maintain the voltage of the first polarity inversion signal HV_POL of the second voltage domain (eg Figure 4a The dotted circle in the middle acts as a latch.

[0091] Specifically, if the power supply of the first voltage domain (LV power supply) is turned off first, and the power supply of the second voltage domain (HV power supply) is turned off later, the third transistor T3 and the fourth transistor T4 are both turned off, and the first transistor T1, the second transistor T2, the fifth transistor T5 and the sixth transistor T6 form a latch, which can keep the loop of the protection circuit, thereby maintaining the voltage output by HV_POL, that is, realizing the latching function.

[0092] Specifically, the latch principle is: HV_POL is a high-level voltage VDDA, so that the first transistor T1 is turned off and the fifth transistor T5 is turned on, so that HV_POL_B is a low-level voltage GND, so that the sixth transistor T6 is turned off and the second transistor T2 is turned on, so that HV_POL is still a high-level voltage VDDA, which plays a role in maintaining the voltage of HV_POL and realizing the latch function.

[0093] In some embodiments, Figure 3bAs shown, the level conversion unit 11 includes: a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4;

[0094] The first electrode of the first transistor T1, the first electrode of the second transistor T2 and the voltage maintaining unit 12 are connected to the third voltage terminal VDDD;

[0095] The second electrode of the first transistor T1 is respectively connected to the voltage maintaining unit 12, the control electrode of the fourth transistor T4 and the first electrode of the third transistor T3;

[0096] The control electrode of the first transistor T1 receives a first polarity inversion signal LV_POL of the first voltage domain, and the control electrode of the second transistor T2 receives a second polarity inversion signal LV_POL_B of the first voltage domain;

[0097] The second electrode of the second transistor T2 is respectively connected to the voltage maintaining unit 12, the control electrode of the third transistor T3 and the first electrode of the fourth transistor T4, and the second electrode of the second transistor T2 is used to output the first polarity reversal signal HV_POL of the second voltage domain;

[0098] The second electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4 and is also connected to the fourth voltage terminal VDDN.

[0099] In some embodiments, Figure 3b As shown, the voltage maintaining unit 12 includes: a fifth transistor T5 and a sixth transistor T6;

[0100] A first electrode of the fifth transistor T5 is connected to the first electrode of the first transistor T1, a second electrode of the fifth transistor T5 is connected to the second electrode of the first transistor T1, and a control electrode of the fifth transistor T5 is respectively connected to the second electrode of the second transistor T2 and the first electrode of the fourth transistor T4;

[0101] The first electrode of the sixth transistor T6 is connected to the first electrode of the second transistor T2, the second electrode of the sixth transistor T6 is connected to the second electrode of the second transistor T2, and the control electrode of the sixth transistor T6 is respectively connected to the second electrode of the first transistor T1 and the first electrode of the third transistor T3.

[0102] In some embodiments, Figure 3b As shown, the first transistor T1 , the second transistor T2 , the fifth transistor T5 and the sixth transistor T6 are all P-type transistors; the third transistor T3 and the fourth transistor T4 are all N-type transistors.

[0103] In a specific example, Figure 3bAs shown, the first electrode of the first transistor T1, the first electrode of the second transistor T2, the first electrode of the fifth transistor T5 and the first electrode of the sixth transistor T6 are connected and connected to the third voltage terminal VDDD;

[0104] The second electrode of the first transistor T1 is respectively connected to the second electrode of the fifth transistor T5, the control electrode of the sixth transistor T6, the control electrode of the fourth transistor T4 and the first electrode of the third transistor T3;

[0105] The control electrode of the first transistor T1 receives a first polarity inversion signal LV_POL of the first voltage domain, and the control electrode of the second transistor T2 receives a second polarity inversion signal LV_POL_B of the first voltage domain;

[0106] The second electrode of the second transistor T2 is respectively connected to the second electrode of the sixth transistor T6, the control electrode of the fifth transistor T5, the control electrode of the third transistor T3 and the first electrode of the fourth transistor T4, and the second electrode of the second transistor T2 is used to output the first polarity inversion signal HV_POL of the second voltage domain;

[0107] The second electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4 and is also connected to the fourth voltage terminal VDDN.

[0108] Reference Figure 3b and Figure 4b As shown, the working principle of the protection circuit 10 is introduced. In this example, LV_POL is a high-low level alternating signal, the high level voltage of LV_POL is the voltage of the third voltage terminal VDDD, the low level voltage of LV_POL is the voltage of the second voltage terminal GND, and the voltage of LV_POL is provided by the power supply of the first voltage domain (LV power supply). The voltage of the fourth voltage terminal VDDN is provided by the power supply of the second voltage domain (HV power supply). Figure 3b In the embodiment, the polarities of the first polarity inversion signal HV_POL of the second voltage domain and the second polarity inversion signal HV_POL_B of the second voltage domain are opposite. For ease of description, in the following description, VDDD is used to represent the voltage of the third voltage terminal VDDD, GND is used to represent the voltage of the second voltage terminal GND, and VDDN is used to represent the voltage of the fourth voltage terminal VDDN.

[0109] 1. If both power supplies are operating normally, that is, the first stage (such as Figure 4b During the interval t1), the first polarity inversion signal LV_POL of the first voltage domain is converted into the first polarity inversion signal HV_POL of the second voltage domain by the level conversion unit 11 and then outputted.

[0110] Specifically, if both power supplies are powered normally, when LV_POL is a high-level voltage VDDD, LV_POL_B is a low-level voltage GND, the first transistor T1 is turned off, the second transistor T2 is turned on, HV_POL is connected to the third voltage terminal VDDD through the second transistor T2, and HV_POL is a high-level voltage VDDD. When LV_POL is a low-level voltage GND, LV_POL_B is a high-level voltage VDDD, the first transistor T1 is turned on, the second transistor T2 is turned off, HV_POL_B is connected to the third voltage terminal VDDD through the first transistor T1, HV_POL_B is a high-level voltage VDDD, so that the fourth transistor T4 is turned on, so that HV_POL is connected to the fourth voltage terminal VDDN, and HV_POL is a low-level voltage VDDN. Thus, when both power supplies are powered normally, LV_POL (high level voltage VDDD and low level voltage GND) becomes HV_POL (high level voltage VDDD and low level voltage VDDN) after level conversion. VDDN is less than GND. For example, if the voltage of VDDD is 1V, the voltage of GND is 0V, and the voltage of VDDN is -5V (negative 5V). This example is only used as an explanation that VDDN is less than GND. In practice, VDDD, GND, and VDDN can be set according to actual conditions, and this application does not limit it.

[0111] 2. If the power supply of the first voltage domain (LV power supply) is turned off first, and the power supply of the second voltage domain (HV power supply) is turned off later, that is, the second stage (such as Figure 4b The voltage maintaining unit 12 can maintain the voltage of the first polarity inversion signal HV_POL of the second voltage domain (eg Figure 4b The dotted circle in the middle acts as a latch.

[0112] Specifically, if the power supply of the first voltage domain (LV power supply) is turned off first and the power supply of the second voltage domain (HV power supply) is turned off later, the first transistor T1 and the second transistor T2 are both turned off, and the fifth transistor T5, the sixth transistor T6, the third transistor T3 and the fourth transistor T4 form a latch, which can keep the loop of the protection circuit, thereby maintaining the voltage output by HV_POL, that is, realizing the latching function.

[0113] Specifically, the latch principle is: HV_POL is a low-level voltage VDDN, so that the third transistor T3 is turned off and the fifth transistor T5 is turned on, so that HV_POL_B is a high-level voltage VDDD, so that the sixth transistor T6 is turned off and the fourth transistor T4 is turned on, so that HV_POL is still a low-level voltage VDDN, which plays a role in maintaining the voltage of HV_POL and realizing the latch function.

[0114] It should be noted that Figure 3a and Figure 3b The high and low levels of the first polarity inversion signal LV_POL in the first voltage domain in the LV_POL are defined to be logically opposite. For example, Figure 3a In the example, if the high voltage VDDD of LV_POL is defined as logic "1" and the low voltage GND is defined as logic "0", then Figure 3b The high level voltage VDDD of the first polarity inversion signal LV_POL of the first voltage domain in the circuit is defined as logic "0", and the low level voltage GND is defined as logic "1". Figure 4a and Figure 4b Both show the case where the LV power supply is turned off when the first polarity inversion signal LV_POL is logic "1".

[0115] Based on the same inventive concept, an embodiment of the present application provides an output unit 100 applied to a source driver 200 . The output unit 100 includes a protection circuit 10 provided in any of the above embodiments.

[0116] The output unit 100 provided in the embodiment of the present application has the same inventive concept and the same beneficial effects as the previous embodiments. The contents not shown in detail in the output unit 100 can be referred to the previous embodiments and will not be repeated here.

[0117] In some embodiments, the output unit 100 further includes: a first buffer unit 20, a second buffer unit 30, a switch logic unit 40 and an output switch unit 50;

[0118] The output end of the first buffer unit 20 is electrically connected to the first input end of the output switch unit 50, and is used to receive the input positive input signal and output the positive driving signal PMV to the output switch unit 50;

[0119] The output end of the second buffer unit 30 is electrically connected to the second input end of the output switch unit 50, and is used to receive the input negative input signal and output the negative driving signal NMV to the output switch unit 50;

[0120] The output end of the protection circuit 10 is electrically connected to the control end of the switch logic unit 40, and is used to output the first polarity reversal signal HV_POL of the second voltage domain to the control end of the switch logic unit 40;

[0121] The output end of the switch logic unit 40 is electrically connected to the output switch unit 50 , and is used to convert the first polarity inversion signal HV_POL of the second voltage domain into a control signal HV_CTRL to the output switch unit 50 .

[0122] The output switch unit 50 is configured to be electrically connected to the display panel, and is used to output the positive driving signal PMV or the negative driving signal NMV to the display panel 300 according to the control signal HV_CTRL.

[0123] The output unit 100 provided in the embodiment of the present application can avoid the possibility that the polarity reversal signal HV_POL may be disordered due to the power supply of the first voltage domain being turned off first, resulting in the disordered high driving voltage (positive driving signal PMV and negative driving signal NMV) being loaded on the output switch unit 50 and causing physical damage. Moreover, the output unit 100 provided in the embodiment of the present application is independent of the order in which the power supply is turned off, and can prevent physical damage caused by the disordered high driving voltage being loaded on the output switch unit 50.

[0124] Based on the same inventive concept, Figure 5 As shown, an embodiment of the present application provides a source driver 200, including an output unit 100 provided in any of the above embodiments.

[0125] The source driver provided in the embodiment of the present application has the same inventive concept and the same beneficial effects as the previous embodiments. The contents not shown in detail in the source driver can be referred to the previous embodiments and will not be repeated here.

[0126] Based on the same inventive concept, Figure 5 As shown, an embodiment of the present application provides a display device, including a display panel 300 and a source driver 200 provided in any of the above embodiments; an output end of the source driver 200 is electrically connected to the display panel 300 .

[0127] The display device provided in the embodiment of the present application has the same inventive concept and the same beneficial effects as the previous embodiments. The contents not shown in detail in the display device can be referred to the previous embodiments and will not be repeated here.

[0128] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0129] The protection circuit provided in the embodiment of the present application is applied to the output unit of the source driver, and the protection circuit includes a level conversion unit 11 and a voltage maintaining unit 12. In the first stage, that is, if both power supplies are normally powered, the first polarity reversal signal LV_POL of the first voltage domain is converted into the first polarity reversal signal HV_POL of the second voltage domain through the level conversion unit 11, and the first polarity reversal signal HV_POL is configured to be converted into a control signal HV_CTRL and output to the output switch unit. In the second stage, that is, if the power supply (LV power supply) of the first voltage domain is turned off first, the voltage maintaining unit 12 forms a loop with the level conversion unit 11, and the voltage of the first polarity reversal signal HV_POL of the second voltage domain can be maintained, which plays a latching role, so that the output switch unit is still driven based on the polarity information of the original polarity reversal signal, and the driving voltage range of the output switch unit remains unchanged, which can avoid the polarity reversal signal HV POL obtained by level conversion from being disordered due to the power supply (LV power supply) of the first voltage domain being turned off first, thereby causing the disordered high driving voltage to be loaded on the output switch unit and causing physical damage. The protection circuit provided in the embodiment of the present application is independent of the order in which the power is turned off, and can prevent physical damage caused by the disordered high driving voltage being loaded on the output switch unit.

[0130] It will be appreciated by those skilled in the art that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Furthermore, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

[0131] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0132] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0133] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0134] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0135] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0136] The above description is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A protection circuit, characterized in that: An output unit applied to a source driver, the output unit comprising a switch logic unit and an output switch unit, the protection circuit comprising: The level conversion unit is configured to be electrically connected to the output switch unit through the switch logic unit, and is used to receive a first polarity inversion signal of the first voltage domain and a second polarity inversion signal of the first voltage domain in a first stage, and convert the first polarity inversion signal of the first voltage domain into a first polarity inversion signal of the second voltage domain; the first polarity inversion signal of the first voltage domain and the second polarity inversion signal of the first voltage domain have opposite polarities; the absolute value of the voltage of the first voltage domain is less than the absolute value of the voltage of the second voltage domain; the first polarity inversion signal of the second voltage domain is configured to be converted into a control signal through the switch logic unit and output to the output switch unit; a voltage maintaining unit connected to the level conversion unit and configured to form a loop with the level conversion unit to maintain the voltage of the first polarity inversion signal of the second voltage domain in the second phase; The level conversion unit includes: a first transistor, a second transistor, a third transistor and a fourth transistor; the voltage maintenance unit includes: a fifth transistor and a sixth transistor; The first electrode of the first transistor is connected to the first electrode of the second transistor and to the first voltage terminal; the second electrode of the first transistor is respectively connected to the control electrode of the second transistor, the first electrode of the fifth transistor, the control electrode of the sixth transistor and the first electrode of the third transistor; the second electrode of the second transistor is respectively connected to the control electrode of the first transistor, the control electrode of the fifth transistor, the first electrode of the sixth transistor and the first electrode of the fourth transistor, and is used to output the first polarity inversion signal of the second voltage domain; the second electrode of the third transistor, the second electrode of the fourth transistor, the second electrode of the fifth transistor and the second electrode of the sixth transistor are connected to the second voltage terminal; or, the first electrode of the first transistor, the first electrode of the second transistor, the first electrode of the fifth transistor and the first electrode of the sixth transistor are connected to the third voltage terminal; the second electrode of the first transistor is respectively connected to the second electrode of the fifth transistor, the control electrode of the sixth transistor, the control electrode of the fourth transistor and the first electrode of the third transistor; the second electrode of the second transistor is respectively connected to the control electrode of the fifth transistor, the second electrode of the sixth transistor, the control electrode of the third transistor and the first electrode of the fourth transistor, and is used to output the first polarity inversion signal of the second voltage domain; the second electrode of the third transistor is connected to the second electrode of the fourth transistor and is connected to the fourth voltage terminal.

2. The protection circuit according to claim 1, characterized in that: The control electrode of the third transistor receives a first polarity inversion signal of the first voltage domain, and the control electrode of the fourth transistor receives a second polarity inversion signal of the first voltage domain.

3. The protection circuit according to claim 2, characterized in that: The first transistor and the second transistor are both P-type transistors; The third transistor, the fourth transistor, the fifth transistor and the sixth transistor are all N-type transistors.

4. The protection circuit according to claim 1, characterized in that: The control electrode of the first transistor receives a first polarity inversion signal of a first voltage domain, and the control electrode of the second transistor receives a second polarity inversion signal of the first voltage domain.

5. The protection circuit according to claim 4, characterized in that: The first transistor, the second transistor, the fifth transistor and the sixth transistor are all P-type transistors; The third transistor and the fourth transistor are both N-type transistors.

6. An output unit, characterized in that: Applied to a source driver, the output unit comprises the protection circuit as claimed in any one of claims 1 to 5.

7. The output unit according to claim 6, characterized in that: Also includes: A first buffer unit, a second buffer unit, a switch logic unit and an output switch unit; The output end of the first buffer unit is electrically connected to the first input end of the output switch unit, and is used to receive an input positive input signal and output a positive driving signal to the output switch unit; The output end of the second buffer unit is electrically connected to the second input end of the output switch unit, and is used to receive an input negative input signal and output a negative driving signal to the output switch unit; The output end of the protection circuit is electrically connected to the control end of the switch logic unit, and is used to output the first polarity inversion signal of the second voltage domain to the control end of the switch logic unit; The output end of the switch logic unit is electrically connected to the output switch unit, and is used to convert the first polarity inversion signal of the second voltage domain into a control signal and output it to the output switch unit; The output switch unit is configured to be electrically connected to the display panel, and is used to output the positive driving signal or the negative driving signal to the display panel according to the control signal.

8. A source driver, characterized in that: Comprising the output unit as claimed in any one of claims 6 to 7.

9. A display device, characterized in that: comprising a display panel and a source driver as claimed in claim 8; The output end of the source driver is electrically connected to the display panel.

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