Defect detection using process window refinement

Abstract

This application relates to performing optical inspection to detect potential defects within integrated circuit devices using process window refinement defect detection, and performing a first electron-based inspection on a portion of the potential defects to identify primary actual defects. A process window of manufacturing parameter settings used to manufacture the integrated circuit devices is identified, and the integrated circuit devices manufactured by using the manufacturing parameter settings within the process window have less than a threshold number of the primary actual defects. To identify additional actual defects, a second electron-based inspection is performed that is limited to selected ones of the potential defects in the integrated circuit devices manufactured by using the manufacturing parameter settings within the process window and not inspected in the first electron-based inspection.

Description

TECHNICAL FIELD

[0001] This application relates to integrated circuit design and manufacturing, and more particularly to systems and processes that identify defects within integrated circuit devices. BACKGROUND

[0002] When designing integrated circuit devices (ICs), engineers typically first generate a design, which is then modeled using computer simulations. The simulations help the designers understand where defects can occur during production of the devices. However, despite how many simulations are performed, actual test devices and finished products are eventually produced. These produced / manufactured actual physical devices are often inspected and electronically tested to identify actual or potential defects. SUMMARY

[0003] Some systems and methods herein perform optical inspection to detect potential defects within an integrated circuit device, and perform a first electron-based inspection of less than all of the potential defects to identify major actual defects. Such systems and methods identify a process window of settings of manufacturing parameters used to manufacture the integrated circuit device. The integrated circuit devices manufactured by using the manufacturing parameter settings within the process window have less than a threshold number of the major actual defects. To identify additional actual defects, these systems and methods perform a second electron-based inspection limited to selected ones of the potential defects in the integrated circuit devices manufactured by using the manufacturing parameter settings within the process window but not inspected in the first electron-based inspection.

[0004] Other systems and methods herein manufacture an integrated circuit device to include components formed into patterns. The manufacturing of the integrated circuit device uses different manufacturing parameters for the patterns in different devices in the integrated circuit device, and each pattern is formed multiple times in different ways by using the different manufacturing parameters. These systems and methods perform optical inspection to detect potential defects in the integrated circuit device, and perform a first electron-based inspection of less than all of the potential defects to identify major actual defects. Such systems and methods identify a process window of settings of manufacturing parameters, where the patterns manufactured by using the manufacturing parameter settings outside the process window have at least a threshold number of the major actual defects, and the patterns manufactured by using the manufacturing parameter settings within the process window have less than the threshold number of the major actual defects. To identify additional actual defects, the systems and methods perform a second electron-based inspection limited to ones of the patterns that satisfy all of the following conditions: have the potential defects; were not inspected in the first electron-based inspection; and are patterns manufactured by using the manufacturing parameter settings within the process window.

[0005] A system herein can include a processor, an optical inspection tool operatively coupled with the processor, and an electronic-based inspection tool operatively coupled with the processor. The optical inspection tool is to optically inspect potential defects within an integrated circuit device. The integrated circuit device has components formed into patterns. The integrated circuit device is formed by using different manufacturing parameters for the patterns on different regions in the integrated circuit device. The electronic-based inspection tool is to perform a first electronic-based inspection on some of the potential defects to identify primary actual defects. The processor is to identify a process window including manufacturing parameter settings. The patterns that are manufactured by using the manufacturing parameter settings within the process window have less than a threshold number of the primary actual defects. The electronic-based inspection tool is to identify additional actual defects by performing a second electronic-based inspection on some of the patterns that satisfy all of the following conditions: have the potential defects; are not inspected in the first electronic-based inspection; and are patterns manufactured by using the manufacturing parameter settings within the process window. BRIEF DESCRIPTION OF DRAWINGS

[0006] Embodiments herein will be better understood with reference to the following detailed description together with the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0007] Figure 1 Flow diagrams showing processes performed by embodiments herein;

[0008] Figure 2 Conceptual diagrams showing operations performed by systems and methods herein;

[0009] Figure 3 and Figure 4 Flow diagrams conceptually showing process windows and interactions of systems and methods herein;

[0010] Figure 5 Schematic diagrams showing systems implementing processes shown in Figures 1-4 Figures; and

[0011] Figure 6 Schematic diagrams showing hardware systems in accordance with embodiments herein. DETAILED DESCRIPTION

[0012] As noted above, regardless of how many simulations are performed, ultimately actual test devices and finished products are produced. These actual physical devices produced / manufactured are typically inspected and electronically tested to identify actual or potential defects. The additional information generated by such testing can be used by IC designers to possibly modify the design to reduce the number of defects and to make the overall operation of the device more efficient. Such inspection and testing can be performed on finished devices or partially completed devices (e.g., in-process inspection / testing). Thus, in-process inspection increases yield during integrated circuit device manufacturing.

[0013] Process window qualification (PWQ) is a type of semiconductor inspection. In PWQ, actual physical integrated circuit devices (e.g., wafers, substrates, etc.) are manufactured using different focus and exposure parameters for different devices (e.g., different chips, different circuits, different components) on them to provide different examples of possible manufacturing conditions, where the focus and / or exposure can be different. Changing the focus and exposure can change the shape, size, and impurity concentration of various components.

[0014] These different focus / exposure settings are sometimes referred to as "modulations." Such devices are sometimes referred to as focus-exposure modulation integrated circuit devices, as different components (of potentially the same design) are manufactured on the same surface (e.g., wafer, layer, etc.) using different focus and exposure settings, resulting in components of the same design being manufactured differently within the same integrated circuit device.

[0015] Thus, as part of the integrated circuit design process, focus-exposure modulation integrated circuit devices are used. Defects are identified in the focus-exposure modulation integrated circuit devices to allow an acceptable range of focus and exposure settings (to achieve a particular yield, cost, manufacturing speed, and other production goals) to be established, finding a so-called acceptable focus-exposure "process window." Devices manufactured using focus and exposure settings within this process window will typically have the desired yield, cost, etc., while devices manufactured using focus and exposure manufacturing parameter settings outside of this process window will typically not.

[0016] More specifically, the focus-exposure modulation integrated circuit devices are first inspected using optical inspection tools, such as bright field inspection (BFI) tools. Such optical inspection tools produce optical images of the integrated circuit devices having light and dark areas, which are typically referred to as "hot spots." Hot spots can indicate potential defects, such as crush, bridging, line end shortening, etc., where components (conductor and insulator shapes) within the focus-exposure modulation integrated circuit devices deviate from the corresponding semiconductor design.

[0017] Defects (hotspots) detected by optical (BFI) are divided into "bins" (categories) by using a process that classifies defects by type of manufacturing error (e.g., short, open, missing shape, extra shape, etc.). Each bin or category of optically detected defects has a design structure or shape (sometimes referred to herein simply as "pattern") that is unique with respect to the patterns of components categorized into other bins. Thus, each bin contains a single pattern that potentially causes an error that will prevent an integrated circuit from functioning as designed (resulting in a yield loss). Although each bin contains a single pattern, each bin can contain hotspots formed by using different combinations of focus and exposure settings applied to the pattern of the bin due to different focus and exposure settings applied to different locations of the focus-exposure modulation integrated circuit device.

[0018] To determine whether the potential defect pattern of a bin actually causes a yield loss (e.g., whether the hotspot is an actual defect), an electronic (non-optical) based inspection is performed, such as a scanning electron microscopy (SEM) inspection. The electronic based inspection is expensive in terms of equipment utilization and time. Thus, a very small percentage (e.g., less than 5% or even less than 1%) of hotspots are subjected to the electronic based inspection. Therefore, various sampling strategies (using randomness and / or logic) are used to determine which hotspots need the electronic based inspection, which can result in limited inspection of focus and exposure settings for certain bins. This can result in certain bins (certain patterns) not being subjected to any electronic based inspection.

[0019] As a result of the (somewhat random and infrequent) electronic based sampling, some representative defects for each bin can be identified at different focus / exposure settings. This time consuming process inspects how the structure responds to changes in lithography parameters (focus / exposure), and this allows determination of process window limits. Specifically, various targets (e.g., yield, cost, performance, manufacturing speed, and other production targets) are used to determine which focus and exposure parameters will meet the target and which will not. Those focus and exposure parameters within the process window will meet the target, while those outside the process window will not.

[0020] To increase sensitivity, a second iteration can be performed only on one or more sites (e.g., defective patterns / shapes) identified by the electron-based inspection, and such currently known defects are sometimes referred to as "areas of interest." The areas of interest are sites or patterns that the integrated circuit designers want to view in more detail because the number or percentage of defects within that site is abnormally high, or because such defects are deemed to have a disproportionate impact on the operation of the integrated circuit. In this additional iteration, some of the patterns (sites) are selected to undergo additional electron-based inspection, thereby providing more data for these selected patterns. The additional SEM iteration of this process helps refine the boundaries of the process window by performing more SEM inspection on a smaller number of sites, thereby providing more testing detail.

[0021] In one example, over 100,000 optical inspection hotspots can result in less than 1,000 electron-based confirmed defects. In addition, such a process can identify over 10,000 patterns (sites) that can cause defects in integrated circuit components, and can provide defect rates for each pattern, as well as various statistical analyses, etc. This allows further refinement of the process window to focus the review on higher sample rates or hit rates at specific defect levels.

[0022] As Figure 1 As shown in the flowchart of item 100, the methods herein fabricate a focus-exposure modulation integrated circuit device (IC) to include components formed as patterns. The fabrication of the focus-exposure modulation integrated circuit device in item 100 uses different fabrication parameters (e.g., exposure and focus) for the patterns on different areas of the integrated circuit device, and each pattern is formed differently by using the different fabrication parameters multiple times. In item 102, these methods optically detect (e.g., by using bright field inspection (BFI)) potential defects within the entire (all) focus-exposure modulation integrated circuit device. Again, these potential defects are commonly referred to as "hotspots."

[0023] In item 104, the optically (BFI) detected potential defects are divided into "sites" (classified) by a process that classifies defects by type of error. Each site or each class of optically detected defects has a pattern that is unique relative to other optically detected defect sites. Thus, each site contains a single pattern, and each site can contain hotspots formed by using different combinations of focus and exposure settings applied to the pattern of the site.

[0024] In item 106, various sampling strategies are used (by using randomness and / or logic) to determine which hotspots need electron-based inspection, potentially using information from the substation process. Then, in item 108, these methods perform a first electron-based inspection (e.g., a scanning electron microscope (SEM) inspection) on a fraction (e.g., less than 5% or even less than 1%) of the potential defects, and the first electron-based inspection identifies the primary actual defects.

[0025] In item 110, such methods identify a process window. The process window is a range of manufacturing parameter settings. When manufactured using settings outside the process window, the patterns will have at least a threshold number of the primary actual defects resulting from the first electron-based inspection. However, the patterns manufactured using settings within the process window have less than the threshold number of the primary actual defects resulting from the first electron-based inspection. The threshold number (threshold manufacturing parameter setting) used to define the bounds of the process window can be limited to an integer, and can be set to 1, to require that the patterns manufactured using settings within the process window have no primary actual defects, and that the patterns manufactured using settings outside the process window have at least one primary actual defect. Alternatively, higher threshold numbers and non-integers can be used, depending on different technologies and manufacturing goals.

[0026] In a subsequent step (e.g., 122), the methods herein perform a second electron-based inspection. In preparing such additional electron-based inspection, in item 112, the methods can rank the patterns based on the occurrence of the primary actual defects within each of the patterns. This allows the methods to select the most frequently defective patterns in item 114 to create a high-occurrence defect pattern group of the most common defect patterns (based on the ranking previously in item 112).

[0027] In further preparing such additional electron-based inspection, in item 116, the methods can rank the primary actual defects based on their occurrence. In item 118, the methods then create a high-occurrence defect group of the most common primary actual defects (based on the ranking in item 116). In item 120, the methods then identify the patterns that have the primary actual defects in the high-occurrence defect group, and identify this group as a high-defect pattern group.

[0028] To identify additional actual defects, in item 122, these methods perform a second electron-based inspection (e.g., again the same scanning electron microscope (SEM) inspection) limited to some of the patterns that meet all of the following conditions: they have potential defects in item 102; they were missed or not inspected in the first electron-based inspection in item 108; and the integrated circuit device has patterns that were manufactured by using manufacturing parameter settings within the process window identified in item 110.

[0029] In some embodiments, the second electron-based inspection (within the process window) is only potentially performed on patterns that match some of the patterns in the high-occurrence-defect pattern group, or only potentially performed on patterns that match some of the patterns in the high-defect pattern group. In other embodiments, the second electron-based inspection in item 122 (on items manufactured by using settings within the process window) is only potentially performed on potential defects in the potential defects in component patterns that match component patterns manufactured by using the manufacturing parameter settings outside the process window and exhibiting the primary actual defect. In further embodiments, the second electron-based inspection in item 122 is only potentially performed on potential defects in the potential defects in component patterns that match component patterns manufactured by using the manufacturing parameter settings outside the process window and were not inspected in the first electron-based inspection.

[0030] In item 124, the methods herein can modify the process window by changing the manufacturing parameter settings so that the additional actual defects are also outside the process window.

[0031] Figure 2 A conceptual diagram showing how a process can be performed by the systems and methods herein. More specifically, Figure 2 shows that in item 140, the systems and methods herein establish an initial process window using the process shown in items 100-110 in the flowchart. Figure 1 In item 140, the systems and methods herein perform a first iteration of SEM review based on hotspots shown in the BFI scan.

[0032] In item 142, the systems and methods herein classify (bin) various patterns based on the location of each hotspot within the overall focus-exposure modulation integrated circuit device. This process in item 142 can enable hotspot location adjustment (e.g., "fuzziness") based on the distance of the hotspot from the center (or other reference point) of the focus-exposure modulation integrated circuit device (x / y offset location of each different hotspot). In addition, in item 142, various bin details (e.g., manufacturing parameters of the hotspot, type of shape, size of shape, relative hotspot location, etc.) can be retained for later analysis. Item 142 also shows that a region of interest can be established for additional SEM iterations by setting a higher sampling rate or hit rate on certain defects.

[0033] In item 144, the systems and methods herein search the patterns that produce hotspots to identify patterns within the process window that should receive additional inspection. Thus, item 144 can rank the patterns based on which patterns most often produce hotspots or based on which hotspots most often produce SEM-detectable defects. For example, item 144 can identify which patterns should receive additional inspection based on the hit rate, which is the rate at which a hotspot-producing pattern also produces a SEM-detectable defect. This evaluation can take into account lithography condition dependencies, which can include the focus and exposure, as well as other parameter settings.

[0034] This allows the systems and methods herein to perform "process window-aware" pattern analysis in item 146. In one example, the process in item 146 can perform additional SEM inspection on hotspots in patterns that exhibit the primary actual defects that match the patterns manufactured using the manufacturing parameter settings outside the process window (manufactured using the manufacturing parameter settings within the process window). In another example, the process in item 146 can perform additional SEM inspection on hotspots in patterns that match the patterns manufactured using the manufacturing parameter settings outside the process window (manufactured using the manufacturing parameter settings within the process window) that were not inspected in the first electronic-based inspection.

[0035] In item 148, the systems and methods herein determine which patterns within the process window will actually receive the additional round of SEM review based on risk factors of the patterns identified as candidates for additional SEM inspection in item 144. Some of the risk factors can include how close a pattern is to the edge of the process window; whether the hit rate of a given pattern is higher compared to other patterns; expected relative performance loss if a particular pattern has a defect, etc.

[0036] Thus, if a hotspot within the process window is selected by the process window aware pattern analysis 146 and deemed large enough of a risk in item 148, then that hotspot will be subjected to additional SEM review by the systems and methods herein in item 150. From this additional SEM review, the systems and methods herein identify additional defects that are solely within the process window, as shown in item 152.

[0037] Figure 3 and Figure 4 A flowchart showing the above is shown in which a process performs additional SEM inspection on hotspots in patterns manufactured using the manufacturing parameter settings within the process window. In particular, in item 146, a process performs additional SEM inspection on hotspots in patterns manufactured using the manufacturing parameter settings within the process window. In item 148, the process determines whether the hotspots have previously been subjected to SEM inspection. In item 150, the process subjects the hotspots to additional SEM inspection if the hotspots have not previously been subjected to SEM inspection. Figure 3 In item 148, the process determines whether the hotspots have previously been subjected to SEM inspection. In item 150, the process subjects the hotspots to additional SEM inspection if the hotspots have not previously been subjected to SEM inspection. Figure 4 In item 148, the process determines whether the hotspots have previously been subjected to SEM inspection. In item 150, the process subjects the hotspots to additional SEM inspection if the hotspots have not previously been subjected to SEM inspection.

[0038] Thus, Figure 3 A conceptual example is shown in which a process window 162 is represented as a two-dimensional matrix 160 of focus-exposure parameters for a particular pattern (e.g., main pattern A 164). In particular, the process window 162 is simply those focus-exposure parameters for the main pattern A 164 that do not result in SEM detected defects. For ease of understanding, the focus-exposure parameters of the matrix that are outside of the process window 162 are represented in Figure 3 In item 148, the process determines whether the hotspots have previously been subjected to SEM inspection. In item 150, the process subjects the hotspots to additional SEM inspection if the hotspots have not previously been subjected to SEM inspection.

[0039] In item 148, the process determines whether the hotspots have previously been subjected to SEM inspection. In item 150, the process subjects the hotspots to additional SEM inspection if the hotspots have not previously been subjected to SEM inspection. Figure 3In the example of FIG. 1, item 166 points to a focus-exposure parameter for main pattern A 164 that is outside of process window 162 and produces a hotspot and a SEM defect. Item 168 points to two different focus-exposure parameters for the same main pattern A 164 that are within process window 162 and both produce hotspots, but the initial SEM (items 108 and 140 described above) did not select either of these hotspots for further analysis. Thus, the process and system herein perform a second iteration of SEM inspection (extra SEM) on the hotspots associated with item 168 that are within process window 162.

[0040] Differently, in the example of FIG. 2, Figure 4 The display is also shown as a conceptual example of process window 172 within a two-dimensional matrix 170 of focus-exposure parameters for a particular pattern (e.g., main pattern B 174). Specifically, process window 172 is simply those focus-exposure parameters for main pattern B 174 that do not result in SEM-detected defects. As with Figure 3 For ease of understanding, in the example of FIG. 3, Figure 4 In the example of FIG. 3, the focus-exposure parameters of the matrix that are outside of process window 172 are represented by shading. Thus, the darker upper and lower rows in matrix 170 are focus-exposure parameters for main pattern B 174 that result in SEM-detected defects, and the other rows in matrix 170 are focus-exposure parameters for the same main pattern B 174 that do not result in SEM-detected defects.

[0041] In the example of FIG. 4, Figure 4 In the example of FIG. 4, item 176 indicates that the initial SEM (items 108 and 140 described above) did not inspect main pattern B. Item 178 points to a focus-exposure parameter for main pattern B 174 that is within process window 172 and produces a hotspot. Thus, the process and system herein perform a second iteration of SEM inspection (extra SEM) on the hotspot associated with item 178 that is within process window 172.

[0042] The above shows that the process herein provides an efficient method to identify SEM review sites for defect discovery after BFI scan and first round of SEM review during process window qualification. This identifies design system defects by using process window aware pattern analysis to select BFI (bright field inspection) defects for SEM review. Specifically, this process performs BFI and first SEM review during process window qualification, applies pattern classification to the BFI defects, merges with existing SEM confirmed defects, performs pattern search to get hit rate on each design, and uses the process window aware pattern analysis to select the most severe BFI defects for further SEM review.

[0043] Figure 5One implementation of the system of this document (of many possible implementations) can include, among other components, a processor 190 (a computer or system of networked computers), an optical inspection tool 192 (e.g., a bright field inspection (BFI) tool) operatively connected with the processor 190, an electron-based inspection tool 194 (e.g., a scanning electron microscope (SEM)) operatively connected with the processor 190, and an integrated circuit manufacturing facility 196 (e.g., a photolithography machine, a mask production machine, an assembly device, a packaging machine, a transport device, etc.). The manufacturing facility 196 is to manufacture focus-exposure modulation integrated circuit devices and other devices, potentially controlled by the processor 190, and provide such focus-exposure modulation integrated circuit devices to the optical inspection tool 192 and the electron-based inspection tool 194.

[0044] The optical inspection tool 192 is to optically inspect the focus-exposure modulation integrated circuit devices for potential defects. In addition, the focus-exposure modulation integrated circuit devices have components formed as patterns because the manufacturing facility is to form the focus-exposure modulation integrated circuit devices using different manufacturing parameters for the patterns on different areas of the integrated circuit devices. The electron-based inspection tool 194 is to perform a first electron-based inspection of some of the potential defects to identify major actual defects.

[0045] The processor 190 is to identify a process window of different manufacturing parameter settings. The patterns manufactured using the manufacturing parameter settings within the process window have less than a threshold number of the major actual defects resulting from the first electron-based inspection.

[0046] The electron-based inspection tool 194 is also to identify additional actual defects by performing a second electron-based inspection of some of the patterns that satisfy all of the following conditions: have the potential defects; were not inspected in the first electron-based inspection; and are within the process window. The electron-based inspection tool 194 is to perform the second electron-based inspection within the process window of the patterns of the patterns that have the major actual defects outside the process window. The electron-based inspection tool 194 is also to perform the second electron-based inspection within the process window of the patterns of the patterns that were not inspected in the first electron-based inspection within or outside the process window.

[0047] The processor 190 is also to rank the patterns based on an occurrence rate of the patterns having the major actual defects and establish a high occurrence rate defect pattern group of most common defect patterns based on the ranking. The electron-based inspection tool 194 is also to perform a second electron-based inspection within the process window of the high occurrence rate defect pattern group.

[0048] The processor 190 is also used to rank the main actual defects based on the occurrence rates, to establish a high occurrence defect group of the most common main actual defects based on the ranking, and to identify patterns in which the main actual defects in the high occurrence defect group occur as a high defect pattern group. The electron-based inspection tool 194 is used to perform the second electron-based inspection on the high defect pattern group within the process window.

[0049] Figure 6 A representative hardware environment (i.e., computing system) for implementing the aforementioned systems, methods, and computer program products described above is shown in FIG. 10. This schematic drawing illustrates a hardware configuration of an information processing / computing system in accordance with the embodiments herein. The system includes at least one processor or central processing unit (CPU) 900. The CPU 900 is interconnected with various devices such as a random access memory (RAM) 904, read-only memory (ROM) 906, and an input / output (I / O) adapter 908 through a system bus 902. The I / O adapter 908 can connect to peripheral devices, such as a disk unit 910 and a tape drive 912, or other program storage devices that are readable by the system. The system can read the inventive instructions on the program storage devices and follow these instructions to perform the methods of the embodiments herein. The system also includes a user interface adapter 918 that connects a keyboard 914, a mouse 916, a speaker 920, a microphone 922, and / or other user interface devices such as a touch screen device (not shown) with the bus 902 to gather user input. Furthermore, a communication adapter 924 connects the bus 902 with a data processing network 926, and a display adapter 928 connects the bus 902 with a display device 930, which can be implemented as an output device such as a monitor, a printer, or a transmitter.

[0050] The flow and block diagrams in the drawings show architectural, functional, and operational aspects of devices and methods according to various embodiments. In this regard, each block in the flow or block diagrams can represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession can in fact be executed substantially concurrently or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. Also, it is noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by dedicated hardware-based systems that perform the specified functions or actions, or combinations of dedicated hardware and computer instructions.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the above-described embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0052] In addition to illustrating the methods and functions of the present embodiments at various stages, the respective drawings also illustrate the logic of the methods implemented in whole or in part by one or more apparatuses and structures. Such apparatuses and structures are configured to implement (i.e., include one or more components, such as resistors, capacitors, transistors, etc., that are connected to carry out the execution of processes) the above-described methods. In other words, one or more computer hardware apparatuses can be created that are configured to implement the methods and processes described herein with reference to the drawings and their respective descriptions.

[0053] The embodiments herein can be used in a variety of electronic applications, including but not limited to advanced sensors, memory / data storage, semiconductors, microprocessors, and other applications. The resulting apparatuses and structures can be distributed in original wafer form (i.e., as a single wafer having a plurality of unpackaged chips), as die, or in packaged form. In the latter case, the chip is typically encased in a single chip package (e.g., a plastic carrier having pins that are affixed to a motherboard or other higher level carrier) or a multi-chip package (e.g., a ceramic carrier having single or double side interconnections or embedded interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer

[0054] The description of the present embodiments is not intended to be exhaustive or to be limited to the precise form disclosed and many modifications and changes are possible without departing from the scope and spirit of the present embodiments. The present embodiments are chosen and described and their disclosure is made to best explain the principles of the present embodiments and their best mode of practice presently known, and to enable others skilled in the art to best make and use them and various embodiments having appropriate modifications in the

[0055] While the forgoing detailed description has set forth various embodiments of the application, modifications and variations can be made to the described embodiments by those of ordinary skill in the art without departing from the spirit or scope of the application. For example, it will be understood that the elements of the various embodiments can be combined in any suitable manner without departing from the spirit or scope of the application. Further, it will be understood that elements of the various embodiments can be combined in any suitable manner without departing from the spirit or scope of the application. Accordingly, the claims are not to be limited to the precise details of the described embodiments.

Claims

1. A method for testing an integrated circuit, characterized by, comprises: performing optical inspection to detect potential defects within integrated circuit devices; performing a first electron-based inspection on a portion of the potential defects to identify major actual defects; identifying a process window comprising settings of manufacturing parameters used to manufacture the integrated circuit devices, wherein the integrated circuit devices manufactured by using the manufacturing parameter settings within the process window have less than a threshold number of the major actual defects; and performing a second electron-based inspection for identifying additional actual defects, the inspection being limited to selected ones of the potential defects in the integrated circuit devices manufactured by using the manufacturing parameter settings within the process window that were not inspected in the first electron-based inspection.

2. The method of claim 1, wherein, The integrated circuit devices comprise components formed into patterns, wherein the method further comprises: ranking the patterns based on a frequency of occurrence of the patterns having the major actual defects; and establishing a high frequency defect pattern group of most common defect patterns based on the ranking, and wherein the second electron-based inspection is performed on the integrated circuit devices having patterns matching the patterns of the high frequency defect pattern group.

3. The method of claim 1, wherein, The integrated circuit devices comprise components formed into patterns, wherein the method further comprises: ranking the major actual defects based on a frequency of occurrence; and establishing a high frequency defect group of most common major actual defects based on the ranking; and identifying as a high defect pattern group the patterns of the patterns in which the major actual defects of the high frequency defect group occur, wherein the second electron-based inspection is performed on the integrated circuit devices having patterns matching the patterns of the high defect pattern group.

4. The method of claim 1, wherein, The manufacturing parameters comprise exposure and focus.

5. The method of claim 1, wherein, The optical inspection comprises bright field inspection, and the first electron-based inspection and the second electron-based inspection comprise scanning electron microscope inspection.

6. A method for testing an integrated circuit, characterized by, comprises: manufacturing integrated circuit devices to comprise components formed into patterns, wherein the manufacturing of the integrated circuit devices uses different manufacturing parameters for the patterns on different ones of the integrated circuit devices, and wherein each pattern is formed multiple times in different ways by using the different manufacturing parameters; performing optical inspection to detect potential defects in the integrated circuit devices; performing a first electron-based inspection on a portion of the potential defects to identify major actual defects; identifying a process window comprising settings of manufacturing parameters, wherein patterns of the patterns manufactured by using the manufacturing parameter settings outside the process window have at least a threshold number of the major actual defects, and wherein patterns of the patterns manufactured by using the manufacturing parameter settings within the process window have less than the threshold number of the major actual defects; and performing a second electron-based inspection for identifying additional actual defects, the inspection being limited to ones of the patterns that satisfy all of the following conditions: have the potential defects; were not inspected in the first electron-based inspection; and are patterns manufactured by using the manufacturing parameter settings within the process window.

7. The method of claim 6, wherein, further comprises: ranking the patterns based on a frequency of occurrence of the patterns having the major actual defects; and ranking the patterns based on a frequency of occurrence of the patterns having the major actual defects; and based on the ranking, a high-occurrence defect pattern group of most common defect patterns is established, wherein the second electron-based inspection is performed on the patterns matching the patterns of the high-occurrence defect pattern group.

8. The method of claim 6, wherein, Further comprising: ranking the primary actual defects based on occurrence; and based on the ranking, a high-occurrence defect group of most common primary actual defects is established; and identifying as a high-defect pattern group the patterns of the high-occurrence defect group in which the primary actual defects occur, wherein the second electron-based inspection is performed on the patterns matching the patterns of the high-defect pattern group.

9. The method of claim 6, wherein, The manufacturing parameters include exposure and focus.

10. The method of claim 6, wherein, The optical inspection includes bright field inspection, and the first and second electron-based inspections include scanning electron microscope inspection.

11. A system for testing an integrated circuit, characterized by Comprising: a processor; an optical inspection tool operatively coupled with the processor; and an electron-based inspection tool operatively coupled with the processor, wherein the optical inspection tool is to optically inspect potential defects in an integrated circuit device, wherein the integrated circuit device has components formed as patterns, wherein the integrated circuit device is formed by using different manufacturing parameters for the patterns on different devices in the integrated circuit device, wherein the electron-based inspection tool is to perform a first electron-based inspection on some of the potential defects to identify primary actual defects, wherein the processor is to identify a process window including settings of manufacturing parameters, wherein the patterns manufactured by using the manufacturing parameter settings within the process window have less than a threshold number of the primary actual defects, and wherein the electron-based inspection tool is to identify additional actual defects by performing a second electron-based inspection on some of the patterns that satisfy all of the following conditions: have the potential defects; were not inspected in the first electron-based inspection; and are patterns manufactured by using the manufacturing parameter settings within the process window.

12. The system of claim 11, wherein, The processor is to: rank the patterns based on occurrence of the patterns having the primary actual defects; and based on the ranking, establish a high-occurrence defect pattern group of most common defect patterns, and wherein the electron-based inspection tool is to perform the second electron-based inspection on the patterns matching the patterns of the high-occurrence defect pattern group.

13. The system of claim 11, wherein, The processor is to: rank the primary actual defects based on occurrence; and based on the ranking, establish a high-occurrence defect group of most common primary actual defects; and identify as a high-defect pattern group the patterns of the high-occurrence defect group in which the primary actual defects occur, and wherein the electron-based inspection tool is to perform the second electron-based inspection on the patterns matching the patterns of the high-defect pattern group.

14. The system of claim 11, wherein, The optical inspection tool includes bright field inspection, and wherein the electron-based inspection tool includes scanning electron microscopy.

Images